Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device that is formed with a small number of processes and has a withstand voltage structure that can stably secure a predetermined withstand voltage, and a manufacturing method thereof.SOLUTION: A withstand voltage structure arranged in an edge termination region 2 is a spatially modulated JTE structure that is a combination of a JTE structure and an FLR structure. All FLRs 31 that make up the FLR structure are surrounded by the innermost p-- type region 32 that makes up the JTE structure. The innermost FLR 31 is placed across these regions at a position overlapping the boundary between a p+ type extending portion 22a of an active region 1 and the innermost p-- type region 32 constituting the JTE structure. The FLR 31 is formed at the same time as the p++ type contact region 15 of the active region 1 and has substantially the same impurity concentration as the p++ type contact region 15. An n+ type channel stopper region 33 is formed at the same time as an n+ type source region 14 of the active region 1 and has substantially the same impurity concentration as the n+ type source region 14.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device. [Background technology]

[0002] The breakdown voltage structure of a power semiconductor device is composed of multiple p-type regions selectively provided in the surface region of an n-type drift region exposed on the front surface of a semiconductor substrate in an edge termination region between an active region and an end of the semiconductor substrate (semiconductor chip).When the semiconductor material of a power semiconductor device is silicon carbide (SiC), which has a maximum electric field strength one order of magnitude greater than that of silicon (Si), a multi-zone junction termination extension (JTE) structure, a spatially modulated JTE structure, or a field limiting ring (FLR) structure are mainly arranged as the breakdown voltage structure.

[0003] The multi-zone JTE structure is a structure in which three or more p-type regions (hereinafter referred to as JTE regions) are concentrically arranged around the periphery of an active region so that the impurity concentration decreases as the JTE region is positioned further away from the inside (the active region (center of the semiconductor chip: chip center) side) to the outside (the edge of the semiconductor substrate (chip edge) side).Since the electric field strength tends to decrease as it moves away from the active region to the outside, the multi-zone JTE structure stably ensures a specified breakdown voltage based on the impurity concentration distribution by lowering the impurity concentration in the JTE region positioned further away from the active region in accordance with this tendency of electric field strength distribution.

[0004] The spatially modulated JTE structure is an improved JTE structure, which consists of two adjacent JTE regions (when it consists of only one JTE region, it is called one JTE region and its outer n -A spatial modulation region having an impurity concentration distribution spatially equivalent to the intermediate impurity concentration between the two regions (a first region and a second region) is placed between the first region and the second region, and the impurity concentration distribution of the entire JTE structure gradually decreases toward the outside. The spatial modulation region is composed of two small regions on either side of the region, each of which has approximately the same impurity concentration as the adjacent regions, which are alternately arranged in a predetermined pattern. The spatial impurity concentration distribution of the entire spatial modulation region is determined by the width and impurity concentration ratio of the two small regions.

[0005] The spatially modulated JTE structure can more stably ensure a predetermined breakdown voltage compared to a general JTE structure that does not have a spatially modulated region. The FLR structure is a structure in which a plurality of p-type regions (FLR) having the same impurity concentration are arranged concentrically around the active region. In the FLR structure, the electric field is dispersed by the plurality of p-type regions arranged apart from each other to ensure a predetermined breakdown voltage. In this way, a predetermined breakdown voltage structure is arranged in the edge termination region to reduce or disperse the electric field in the edge termination region, thereby improving the breakdown voltage of the edge termination region and improving the breakdown voltage of the entire semiconductor device. The structure of a conventional silicon carbide semiconductor device will be described.

[0006] Fig. 19 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. The conventional silicon carbide semiconductor device 110 shown in Fig. 19 is a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS type field effect transistor having an insulated gate (MOS gate) having a three-layer structure of metal-oxide film-semiconductor) having a trench gate structure with a double-zone spatially modulated JTE structure 130 in an edge termination region 102 of a semiconductor substrate (semiconductor chip) 140 made of silicon carbide. The edge termination region 102 surrounds the periphery of an active region 101 through which the main current of the MOSFET flows.

[0007] The semiconductor substrate 140 is made of silicon carbide. + On the starting substrate 111 -The silicon carbide layers 142, 143 which become the p-type drift region 112 and the p-type base region 113 are epitaxially grown in sequence. A portion of the p-type silicon carbide layer 143 in the edge termination region 102 is removed by etching, and a step 124 is formed on the front surface of the semiconductor substrate 140. The front surface of the semiconductor substrate 140 is recessed toward the drain electrode 125 at a second surface 140b on the outer side (the end side of the semiconductor substrate 140) than at a first surface 140a on the chip center (the center of the semiconductor substrate 140) side, with the step 124 as a boundary.

[0008] Due to this step 124, the p-type silicon carbide layer 143 remains in a mesa shape in the center of the front surface (the main surface on the p-type silicon carbide layer 143 side) of the semiconductor substrate 140. The first and second surfaces 140a and 140b of the front surface of the semiconductor substrate 140 are the p-type silicon carbide layer 143 and the n-type silicon carbide layer 143, respectively. - In the central portion 101a of the active region 101, the p-type base region 113 of each unit cell of the MOSFET, the n-type silicon carbide layer 142 are formed on the front surface side of the semiconductor substrate 140. + type source region 114 and p ++ A MOS gate including a contact region 115, a trench 116, a gate insulating film 117 and a gate electrode 118 is provided.

[0009] In the peripheral portion 101b of the active region 101, a surface region of the first surface 140a of the front surface of the semiconductor substrate 140 is provided with p + The p-type base extension 122a, the p-type base extension 113a and the p-type ++ A contact extension 115a is optionally provided. + The p-type base extension 122a, the p-type base extension 113a and the p-type ++ The contact extensions 115a are arranged on the outermost p-type contacts constituting a unit cell in the central portion 101a of the active region 101. + The p-type region 122, the p-type base region 113 and the outermost p ++ It is an extension of the mold contact region 115 and surrounds the central portion 101 a of the active region 101 .

[0010] p + The p-type base extension 122a, the p-type base extension 113a and the p-type++ The contact extension 115a reaches a third surface (a mesa edge of a step) 140c that connects the first surface 140a and the second surface 140b on the front surface of the semiconductor substrate 140. Reference numerals 121 and 122 denote p-type contacts for reducing the electric field applied to the gate insulating film 117 on the bottom surface of the trench 116. + The reference numeral 123 denotes a p type region provided in a surface region of the third surface 140c of the front surface of the semiconductor substrate 140. + The reference numerals 119, 120, 125, and 133 denote an interlayer insulating film, a source electrode, a drain electrode, and an n-type region, respectively. + The channel stopper region is a type channel stopper region.

[0011] In the edge termination region 102, a surface region of the second surface 140b of the front surface of the semiconductor substrate 140 is - The silicon carbide layer 142 is provided with a plurality of p - A mold region 131 and a plurality of p -- A mold region 132 is selectively provided. - A spatial modulation JTE structure having a spatial modulation region 130b formed by a type region 131 and a plurality of p -- The spatial modulation JTE structure having the spatial modulation region 130d formed by the mold region 132 constitutes a double-zone spatial modulation JTE structure 130. - Type region 131 and multiple p -- The mold regions 132 are spaced apart from one another and concentrically arranged around the periphery of the active region 101 .

[0012] The innermost p - Type region 131 is p + Adjacent to the mold extension 122a. -- The type region 132 is p + Adjacent to the mold extension 122a, the outermost p - All adjacent p - Located between the mold regions 131. The innermost p -- p outside type region 132 -- The type region 132 is p - All adjacent p --Between the type regions 132 - The drift region 112 is located in the - Type region 131 and the innermost p -- The type region 132 is p + It is fixed to the potential of the source electrode 120 via the mold extension 122a.

[0013] The innermost p - The innermost p -- The outermost p of the mold region 132 - The outer portion (hereinafter referred to as JTE region) 130c of the mold region 131 constitutes a double zone JTE structure. - Type region 131 and the innermost p -- The part of the mold region 132 between the JTE regions 130a and 130c constitutes the spatial modulation region 130b between the JTE regions 130a and 130c. -- p outside type region 132 -- A type region 132 and n - The type drift region 112 and the spatial modulation region 130d are formed adjacent to the outside of the JTE region 130c.

[0014] Conventional silicon carbide semiconductor devices have a double-zone JTE structure (p - p in the type domain and outside -- Proposals have been made for a double-zone spatially modulated JTE structure in which a double-zone JTE structure has an FLR inside a double-zone JTE structure (a structure in which a gate insulating layer and a gate insulating layer are concentrically arranged adjacent to each other surrounding an active region) and a double-zone spatially modulated JTE structure in which an FLR is provided inside a double-zone JTE structure (see, for example, Patent Documents 1 and 2 below). By combining a double-zone JTE structure with an FLR, Patent Document 1 below reduces the impurity concentration dependency of the reverse breakdown voltage and increases the margin in the manufacturing process. Patent Document 2 below reduces the number of steps in forming the breakdown voltage structure, thereby reducing the adverse effects of process variations on the breakdown voltage structure.

[0015] Another breakdown voltage structure of a conventional silicon carbide semiconductor device is a p-type resurf layer that uniforms the electric field near the front surface of the semiconductor substrate, and a p-type field plate that is fixed to the potential of the field plate and disposed inside the resurf layer. + A type edge termination layer and a plurality of p-type junctions arranged inside and outside the resurf layer and concentrically surrounding the edge termination layer. + A breakdown voltage structure composed of a type FLR and a MOSFET has been proposed (see, for example, Patent Documents 3 and 4 below). Patent Document 3 below discloses the number, width, and spacing of the FLR. Patent Documents 3 and 4 below disclose the impurity concentrations of the RESURF layer, edge termination layer, and FLR. [Prior art documents] [Patent documents]

[0016] [Patent Document 1] JP 2012-195519 A [Patent Document 2] Patent No. 6672764 [Patent Document 3] Patent No. 3708057 [Patent Document 4] Patent No. 5827020 Summary of the Invention [Problem to be solved by the invention]

[0017] However, in the conventional double-zone spatially modulated JTE structure 130 (see FIG. 19 ), in order to adjust the spatial impurity concentration distribution of the entire double-zone spatially modulated JTE structure 130, a plurality of p-type regions with different impurity concentrations (p-type regions in FIG. 19 ) are used. - Type region 131 and p -- The multiple ion implantations for forming the p-type region (p ++ type contact region 115 and p + This needs to be carried out in a separate process from the ion implantation for forming the mold regions 121 to 123. This increases the number of processes, which leads to increased costs.

[0018] A general JTE structure and a spatially modulated JTE structure (not shown) also require multiple ion implantations to form multiple p-type regions with different impurity concentrations, and therefore have the same problems as the conventional double-zone spatially modulated JTE structure 130. A general FLR structure (not shown) can be formed with a single ion implantation, and the number of processes can be reduced, but the area of ​​the voltage-resistant structure needs to be large to stably secure a predetermined voltage-resistant structure. For this reason, when expensive silicon carbide is used as the semiconductor material, the wafer price becomes high, which is a major factor in increasing costs.

[0019] In order to solve the problems associated with the conventional techniques described above, an object of the present invention is to provide a silicon carbide semiconductor device having a voltage withstanding structure that is formed with a small number of steps and can stably ensure a predetermined voltage withstand voltage, and a method for manufacturing the silicon carbide semiconductor device. [Means for solving the problem]

[0020] In order to solve the above-mentioned problems and achieve the object of the present invention, a silicon carbide semiconductor device according to the present invention has the following features. A semiconductor substrate made of silicon carbide is provided with an active region and a termination region surrounding the periphery of the active region. A first conductivity type region is provided inside the semiconductor substrate spanning from the active region to the termination region. A second conductivity type region is provided in the active region between a first main surface of the semiconductor substrate and the first conductivity type region. A semiconductor element having a pn junction between the first conductivity type region and the second conductivity type region is provided in a central portion of the active region. A second conductivity type peripheral region is provided on the periphery of the active region. The second conductivity type peripheral region surrounds the periphery of the central portion of the active region.

[0021] A first electrode of the semiconductor element is provided on a first main surface of the semiconductor substrate and is electrically connected to the second conductivity type region and the second conductivity type peripheral region. A second electrode of the semiconductor element is provided on a second main surface of the semiconductor substrate and is electrically connected to the first conductivity type region. A plurality of second conductivity type FLRs are selectively provided in the termination region between the first main surface of the semiconductor substrate and the first conductivity type region, spaced apart from each other. The plurality of FLRs concentrically surround the active region to form an FLR structure. A plurality of second conductivity type low concentration regions are selectively provided in the termination region between the first main surface of the semiconductor substrate and the first conductivity type region, spaced apart from each other.

[0022] The plurality of second-conductivity-type low-concentration regions concentrically surround the active region to form a JTE structure. The second-conductivity-type low-concentration regions have a lower impurity concentration than the FLR. A first second-conductivity-type low-concentration region that is the innermost of the plurality of second-conductivity-type low-concentration regions is adjacent to the outside of the second-conductivity-type peripheral region and extends from the boundary with the second-conductivity-type peripheral region to the outside of the FLR. A second second-conductivity-type low-concentration region, excluding the first second-conductivity-type low-concentration region, of the plurality of second-conductivity-type low-concentration regions is disposed outside the FLR. A first FLR that is the innermost of the plurality of FLRs is disposed across the second-conductivity-type peripheral region and the first second-conductivity-type low-concentration region.

[0023] In addition, in the silicon carbide semiconductor device according to the present invention, a depth of the FLR is shallower than a depth of the second conductivity type low concentration region.

[0024] In addition, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the FLR has an impurity concentration higher than that of the second conductivity type outer peripheral region.

[0025] In the silicon carbide semiconductor device according to the present invention, the impurity concentration of the FLR is 1×10 18 / cm 3 More than 1×1021 / cm 3 The present invention is characterized in that:

[0026] In the silicon carbide semiconductor device according to the present invention, a dose of the second conductivity type low concentration region is 5.5×10 12 / cm 2 More than 2.1×10 13 / cm 2 The present invention is characterized in that:

[0027] In the silicon carbide semiconductor device according to the present invention, in the above-described invention, the interval between adjacent FLRs becomes wider with increasing distance from the active region, and the spreading dimension of the interval between adjacent FLRs is not less than 0.1 μm and not more than 2.5 μm.

[0028] In addition, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the spreading dimension of the space between the FLRs adjacent to each other is not less than 0.2 μm and not more than 1.0 μm.

[0029] Furthermore, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the semiconductor element includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a gate insulating film, and a gate electrode. The first semiconductor region is selectively provided between a first main surface of the semiconductor substrate and the second conductivity type region. The second semiconductor region is selectively provided between the first main surface of the semiconductor substrate and the second conductivity type region. The second semiconductor region has a higher impurity concentration than the second conductivity type region.

[0030] The gate insulating film is provided in contact with a region of the second conductive type region between the first semiconductor region and the first conductive type region. The gate electrode is provided on the opposite side of the second conductive type region with the gate insulating film interposed therebetween. The first electrode is electrically connected to the second conductive type region via the first semiconductor region and the second semiconductor region. The FLR has an impurity concentration that is the same as the impurity concentration of the second semiconductor region.

[0031] In order to solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a silicon carbide semiconductor device according to the present invention is a method for manufacturing a silicon carbide semiconductor device including a semiconductor substrate made of silicon carbide, an active region in which a semiconductor element having a pn junction between a first conductivity type region and a second conductivity type region is provided in a central portion, and a termination region surrounding the active region, and has the following features: A first step of forming a first conductivity type semiconductor layer to become the first conductivity type region on a starting substrate made of silicon carbide is performed. A second step of forming a second conductivity type semiconductor layer to become the second conductivity type region on the first conductivity type semiconductor layer in the active region is performed. A third step of selectively forming a first semiconductor region of a first conductivity type in a surface region of the second conductivity type semiconductor layer is performed. A fourth step of selectively forming a second semiconductor region of a second conductivity type in the surface region of the second conductivity type semiconductor layer is performed.

[0032] A fifth step is performed to form a second-conductivity-type peripheral region on the outer periphery of the active region so as to surround the periphery of the central portion of the active region. A sixth step is performed to selectively form a plurality of second-conductivity-type FLRs arranged apart from one another in the surface region of the first-conductivity-type semiconductor layer in the termination region, the FLRs concentrically surrounding the periphery of the active region to form an FLR structure. A seventh step is performed to selectively form a plurality of second-conductivity-type low-concentration regions having an impurity concentration lower than that of the FLRs, the FLRs arranged apart from one another in the surface region of the first-conductivity-type semiconductor layer in the termination region, the JTE structure being concentrically surrounding the periphery of the active region. An eighth step is performed to form a first electrode of the semiconductor element on a first main surface of the semiconductor substrate, the first electrode being electrically connected to the second-conductivity-type region and the second-conductivity-type peripheral region.

[0033] A ninth step is performed to form a second electrode of the semiconductor element on the second main surface of the semiconductor substrate, the second electrode being electrically connected to the first conductivity type region. In the seventh step, a first second conductivity type low concentration region that is the innermost one of the plurality of second conductivity type low concentration regions is disposed adjacent to the second conductivity type peripheral region. Formation area and the second conductive type peripheral region is disposed adjacent to the outer periphery of the first conductive type. Formation area From the boundary of the FLR Formation area A second low concentration region of the second conductivity type, other than the first low concentration region of the second conductivity type, is disposed outside the FLR. Formation area In the sixth step, a first FLR that is the innermost of the plurality of FLRs is disposed outside the second conductive type peripheral region. Formation area and the first second conductivity type low concentration region Formation area The fourth step and the sixth step are carried out simultaneously.

[0034] In order to solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a silicon carbide semiconductor device according to the present invention is a method for manufacturing a silicon carbide semiconductor device including a semiconductor substrate made of silicon carbide, an active region in which a semiconductor element having a pn junction between a first conductivity type region and a second conductivity type region is provided in a central portion, and a termination region surrounding the active region, and has the following features: A first step of forming a first conductivity type semiconductor layer to become the first conductivity type region on a starting substrate made of silicon carbide is performed. A second step of forming a second conductivity type semiconductor layer to become the second conductivity type region on the first conductivity type semiconductor layer in the active region is performed. A third step of selectively forming a first semiconductor region of a first conductivity type in a surface region of the second conductivity type semiconductor layer is performed. A fourth step of selectively forming a second semiconductor region of a second conductivity type in the surface region of the second conductivity type semiconductor layer is performed.

[0035] A fifth step is performed to form a second-conductivity-type peripheral region on the outer periphery of the active region so as to surround the periphery of the central portion of the active region. A sixth step is performed to selectively form a plurality of second-conductivity-type FLRs arranged at a distance from each other in the surface region of the first-conductivity-type semiconductor layer in the termination region, the FLRs concentrically surrounding the periphery of the active region to form an FLR structure. A seventh step is performed to selectively form a plurality of second-conductivity-type low-concentration regions having an impurity concentration lower than that of the FLRs, the FLRs arranged at a distance from each other in the surface region of the first-conductivity-type semiconductor layer in the termination region, the JTE structure being concentrically surrounding the periphery of the active region. An eighth step is performed to form a gate insulating film in contact with a region of the second-conductivity-type region between the first semiconductor region and the first-conductivity-type region. A ninth step is performed to form a gate electrode on the opposite side of the second-conductivity-type region with the gate insulating film interposed therebetween.

[0036] A tenth step is performed in which a second conductivity type impurity is introduced into a region of the second conductivity type region between the first semiconductor region and the first conductivity type region to adjust a gate threshold voltage. An eleventh step is performed in which a first electrode of the semiconductor element is formed on a first main surface of the semiconductor substrate, the first electrode being electrically connected to the second conductivity type region and the second conductivity type peripheral region. A twelfth step is performed in which a second electrode of the semiconductor element is formed on a second main surface of the semiconductor substrate, the second electrode being electrically connected to the first conductivity type region. In the seventh step, a thirteenth step is performed in which a first conductivity type low concentration region having a first conductivity type impurity concentration that is the same as the second conductivity type impurity concentration of the second conductivity type low concentration region is selectively formed in a surface region of the first conductivity type semiconductor layer in the termination region.

[0037] A second conductive type impurity is introduced into the entire surface region of the first conductive type semiconductor layer in the termination region, thereby forming the first conductive type low concentration region. Formation area The second conductive type low concentration region is formed in the portion other than the first conductive type low concentration region. Formation area and a fourteenth step of lowering the first conductivity type impurity concentration of the second conductivity type peripheral region. Formation area and the second conductive type peripheral region is disposed adjacent to the outer periphery of the first conductive type. Formation areaFrom the boundary of the FLR Formation area A second low concentration region of the second conductivity type, other than the first low concentration region of the second conductivity type, is disposed outside the FLR. Formation area In the sixth step, a first FLR that is the innermost of the plurality of FLRs is disposed outside the second conductive type peripheral region. Formation area and the first second conductivity type low concentration region Formation area The above-mentioned 10th Step and step 14 are carried out simultaneously.

[0038] According to the above-mentioned invention, it is possible to suppress the fluctuation of the breakdown voltage characteristic of the spatially modulated JTE structure, which is a combination of the JTE structure and the FLR structure arranged in the edge termination region. In addition, by adjusting the width and arrangement of the FLR structure constituting the spatially modulated JTE structure, the spatially modulated JTE structure can be formed simultaneously with any part of the active region, so that the number of masks and the number of ion implantation steps for forming the spatially modulated JTE structure can be reduced, thereby shortening the manufacturing lead time. Effect of the Invention

[0039] ADVANTAGE OF THE DRAWINGS The present invention relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device, and is advantageous in that it is possible to provide a silicon carbide semiconductor device having a breakdown voltage structure that is formed through a small number of steps and can stably ensure a predetermined breakdown voltage. [Brief description of the drawings]

[0040] [Figure 1] 1 is a plan view showing a layout of a semiconductor device according to a first embodiment as viewed from the front surface side of a semiconductor substrate. [Diagram 2] 2 is a cross-sectional view showing a cross-sectional structure taken along line AA' in FIG. [Diagram 3] 1 is a cross-sectional view showing a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment. [Figure 4] 1 is a cross-sectional view showing a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment. [Diagram 5] 1 is a cross-sectional view showing a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment. [Figure 6] 1 is a cross-sectional view showing a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment. [Figure 7] FIG. 11 is a cross-sectional view showing a state during the manufacture of a silicon carbide semiconductor device according to a second embodiment. [Figure 8] FIG. 11 is a cross-sectional view showing a state during the manufacture of a silicon carbide semiconductor device according to a second embodiment. [Figure 9] FIG. 11 is a cross-sectional view showing a state during the manufacture of a silicon carbide semiconductor device according to a second embodiment. [Figure 10] FIG. 11 is a cross-sectional view showing a state during the manufacture of a silicon carbide semiconductor device according to a second embodiment. [Figure 11] FIG. 1 is a cross-sectional view showing an example of a spatially modulated JTE structure of an experimental example. [Figure 12] 11 is a table showing simulation conditions and judgment results of an experimental example. [Figure 13] FIG. 13 is a characteristic diagram showing the relationship between the dose and the breakdown voltage of the JTE structure constituting the spatially modulated JTE structure of the experimental example. [Figure 14] FIG. 13 is a characteristic diagram showing the relationship between the dose and the breakdown voltage of the JTE structure constituting the spatially modulated JTE structure of the experimental example. [Figure 15] FIG. 13 is a characteristic diagram showing the relationship between the dose and the breakdown voltage of the JTE structure constituting the spatially modulated JTE structure of the experimental example. [Figure 16] FIG. 13 is a characteristic diagram showing the relationship between the spreading dimension and the breakdown voltage of the FLR structure constituting the spatially modulated JTE structure of the experimental example. [Figure 17] FIG. 13 is a characteristic diagram showing the relationship between the arrangement of FLRs constituting the spatially modulated JTE structure of the experimental example and the breakdown voltage. [Figure 18] FIG. 11 is a characteristic diagram showing the relationship between the arrangement of FLRs constituting the spatial modulation JTE structure of the embodiment and the breakdown voltage. [Figure 19] FIG. 1 is a cross-sectional view showing a structure of a conventional silicon carbide semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0041] Preferred embodiments of the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, in a layer or region prefixed with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - attached to n or p respectively mean that the impurity concentration is higher and lower than that of a layer or region not prefixed with n or p. In the following description of the embodiments and the accompanying drawings, the same reference numerals are attached to similar configurations, and duplicated explanations are omitted. "Approximately the same" or "equivalent" means that the same is the same within a range of ±5% including an allowable error due to process variations.

[0042] (Embodiment 1) The structure of a silicon carbide semiconductor device according to a first embodiment will be described. Fig. 1 is a plan view showing a layout of the semiconductor device according to the first embodiment as viewed from the front surface side of the semiconductor substrate. Fig. 2 is a cross-sectional view showing a cross-sectional structure along the cutting line A-A' in Fig. 1. The silicon carbide semiconductor device 10 according to the first embodiment shown in Figs. 1 and 2 is a vertical MOSFET having a trench gate structure (element structure) in an active region 1 of a semiconductor substrate (semiconductor chip) 40 made of silicon carbide (SiC), and has a spatially modulated JTE structure 30 formed by combining a JTE structure and an FLR structure as a breakdown voltage structure in an edge termination region 2.

[0043] The active region 1 is a region through which a main current (drift current) flows when the MOSFET is in an on-state, and a plurality of unit cells (semiconductor elements) of the MOSFET having the same structure are arranged adjacent to each other in a central portion 1a. The active region 1 has a substantially rectangular planar shape and is arranged substantially in the center of the semiconductor substrate 40. Specifically, the active region 1 is a region through which a main current (drift current) flows when the MOSFET is in an on-state. + The mold extension 22a and the JTE structure (the innermost p --The edge termination region 2 is an inner portion from the boundary with the active region 1 (chip end). The edge termination region 2 is a region between the active region 1 and the end (chip end) of the semiconductor substrate 40, and surrounds the periphery of the active region 1 in a substantially rectangular shape. The spatially modulated JTE structure 30 disposed in the edge termination region 2 will be described later.

[0044] The semiconductor substrate 40 is + The n-type drain region (first conductivity type region) 11 is made of silicon carbide. + On the front surface of the starting substrate 41, - The silicon carbide layers (first and second conductivity type semiconductor layers) 42, 43 that become the n-type drift region (first conductivity type region) 12 and the p-type base region (second conductivity type region) 13 are epitaxially grown in sequence. The main surface of the semiconductor substrate 40 on the p-type silicon carbide layer 43 side is the front surface, and the n-type base region (second conductivity type region) 13 is the n-type base region (second conductivity type region) 14. + The main surface (n + The back surface of the semiconductor substrate 40 is the back surface of the starting substrate 41. In the central portion 1a of the active region 1, the p-type base region 13 and the n-type + type source region (first semiconductor region) 14, p ++ A MOS gate including a type contact region (second semiconductor region) 15, a trench 16, a gate insulating film 17 and a gate electrode 18 is provided.

[0045] n + The starting substrate 41 is n + The n-type drain region 11. - The drift region 12 is an n - The first and second p-type silicon carbide layers 42 are + The first and second regions 21 and 22, the n-type current diffusion region (not shown), the FLR 31 and p -- This is the part excluding the mold region 32. - The drift region 12 is a first, second + Type regions 21, 22, FLR31 and p -- Type region 32 and n + The p-type base region 13 is formed between the n-type starting substrate 41 and the active region 1, and extends from the active region 1 to the chip end. +type source region 14 and p ++ The portion excluding the contact region 15 and the first surface (to be described later) of the front surface of the semiconductor substrate 40 and the n - It is provided between the mold drift region 12.

[0046] n + type source region 14 and p ++ The n-type contact regions 15 are selectively provided between the front surface of the semiconductor substrate 40 and the p-type base region 13. + type source region 14 and p ++ The p-type contact region 15 is in contact with the p-type base region 13 and is exposed on the front surface of the semiconductor substrate 40. The exposure on the front surface of the semiconductor substrate 40 means that the contact region 15 is in contact with a source electrode (first electrode) 20 (described later) through a contact hole in an interlayer insulating film 19 (described later). ++ The p-type contact region 15 may not be provided. ++ In place of the p-type contact region 15, the p-type base region 13 is exposed on the front surface of the semiconductor substrate 40.

[0047] In the active region 1, - An n-type current diffusion region (not shown), which is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers, may be provided between the n-type drift region 12 and the p-type base region 13. The n-type current diffusion region is provided between the adjacent trenches 16 and is located at a position closer to the n-type current diffusion region than the bottom surface of the trenches 16. + The first and second p + The n-type regions 21 and 22 are located closer to the bottom of the trench 16 than the n-type regions 21 and 22. + The first and second p-type drain regions 11 and 12 are disposed at a deep position. + The mold regions 21 and 22 have the function of reducing the electric field applied to the bottom surface of the trench 16 .

[0048] 1st p. + The first p-type region 21 is provided apart from the p-type base region 13 and faces the bottom surface of the trench 16 in the depth direction Z. +The mold region 21 has a source electrode (first electrode) in a portion not shown. 20 The second p + The mold region 22 is formed between the adjacent trenches 16. + The trench 16 is provided apart from the p-type region 21 and the trench 16 and is in contact with the p-type base region 13. The trench 16 is + The n-type source region 14 and the p-type base region 13 are connected to each other. - The n-type current diffusion region 12 (or the n-type current diffusion region, if provided) is reached.

[0049] The trenches 16 extend, for example, in a stripe shape in a first direction X parallel to the front surface of the semiconductor substrate 40. + Type source region 14, p ++ Type contact region 15 and second p + The mold region 22 extends linearly in the first direction X parallel to the trench 16. ++ The contact regions 15 may be scattered in the first direction X. Gate electrodes 18 are provided inside the trenches 16 via gate insulating films 17. All the gate electrodes 18 are electrically connected to each other via a gate runner (gate wiring layer: not shown).

[0050] The interlayer insulating film 19 is provided on the entire front surface of the semiconductor substrate 40, and covers the gate electrode 18. The source electrode 20 is provided on substantially the entire front surface of the semiconductor substrate 40 in the active region 1. The source electrode 20 is formed on an n-type semiconductor substrate 40 exposed through a contact hole in the interlayer insulating film 19. + type source region 14 and p ++ The p-type contact region 15 is in contact with the p-type base region 13, + type source region 14 and p ++ The drain electrode ( Second The back surface (n + The back surface of the starting substrate 41 is provided on the entire surface of the substrate. + Type drain region 11(n +The mold is electrically connected to a starting substrate 41).

[0051] On the front surface of the semiconductor substrate 40, for example, the p-type silicon carbide layer 43 is removed over the entire edge termination region 2, thereby forming a step 24 in which the outer (end (chip end) side of the semiconductor substrate 40) portion (second surface) 40b is lowered (recessed) toward the drain electrode 25 than the inner (center (chip center) side of the semiconductor substrate 40) portion (first surface) 40a. Inside this step 24, the p-type silicon carbide layer 43 remains in a mesa (trapezoid) shape. Outside the step 24, the n - The surface (exposed surface) of the type silicon carbide layer 42 becomes the second surface 40b of the front surface of the semiconductor substrate 40.

[0052] The active region 1 and the edge termination region 2 are isolated from each other by a portion 40c (mesa edge of step 24: hereinafter referred to as the third surface) of the front surface of the semiconductor substrate 40 that connects the first surface 40a and the second surface 40b. The active region 1 is the portion inside the step 24, and has the first surface 40a of the semiconductor substrate 40. The edge termination region 2 is the portion outside the step 24, and has second and third surfaces 40b, 40c of the semiconductor substrate 40. At the outer periphery 1b of the active region 1, a surface region of the first surface 40a of the front surface of the semiconductor substrate 40 is provided with p + The p-type base extension 22a, the p-type base extension 13a and the p ++ A p-type region (second conductivity type outer peripheral region) made of the p-type contact extension 15a is provided.

[0053] p + The p-type base extension 22a, the p-type base extension 13a and the p ++ The contact extension 15a surrounds the periphery of the central portion 1a of the active region 1 in a substantially rectangular shape, and extends outward from the central portion 1a of the active region 1 to reach the third surface 40c of the front surface of the semiconductor substrate 40. + The mold extension 22a is the second p + It is an extension of the mold region 22. + The mold extension 22a reaches a position deeper on the drain electrode 25 side than the second surface 40b of the front surface of the semiconductor substrate 40. +The mold extension portion 22a extends outward beyond the step 24 and surrounds the boundary between the second surface 40b and the third surface 40c on the front surface of the semiconductor substrate 40 over the entire periphery.

[0054] The p-type base extension 13a is an extension of the p-type base region 13. The p-type base extension 13a is disposed between the first surface 40a of the front surface of the semiconductor substrate 40 and the p + It is provided between the mold extension portion 22a. ++ The outermost p-type contact extension 15a ++ The contact region 15 is an extension of the contact region 15. ++ The p-type contact extension 15a is provided between a first surface 40a on the front surface of the semiconductor substrate 40 and the p-type base extension 13a. ++ The contact extension 15a contacts the source electrode 20, and + The p-type base extension 22a and the p-type base extension 13a are p ++ The potential is fixed to the potential of the source electrode 20 via the contact extension 15a.

[0055] p + The p-type base extension 22a, the p-type base extension 13a and the p ++ The contact extension 15a has a function of making the electric field uniform in the plane of the first surface 40a of the front surface of the semiconductor substrate 40 in the outer periphery 1b of the active region 1. + The p-type base extension 22a, the p-type base extension 13a and the p ++ The n-type contact extension 15a is connected to the edge termination region 2 when the MOSFET is turned off. - The hole current generated in the drift region 12 and flowing toward the active region 1 is called p ++ This region is for drawing out the source electrode 20 from the type contact extension 15a, and has the function of suppressing hole current concentration in the edge termination region 2 upon avalanche breakdown.

[0056] p + The p-type base extension 22a, the p-type base extension 13a and the p ++ The p-type contact extending portion 15a is overlapped with the p-type contact extending portion 15b along the third surface 40c of the front surface of the semiconductor substrate 40. + type area (hereinafter p+ A step region 23 is provided. + The step region 23 is p -- The p-type region 32 is formed by ion implantation at the same time, and extends from the active region 1 to the outside beyond the step 24, and is exposed on the second and third faces 40b and 40c. The exposure on the second and third faces 40b and 40c means that the p-type region 32 is in contact with the interlayer insulating film 19 on the second and third faces 40b and 40c. + The p-type step region 23 ++ The portion overlapping the contact extension 15a is indicated by a dashed line. + The overlapping portions of the p-type base extension 22a and the p-type base extension 13a are indicated by solid lines (the same applies to FIG. 11).

[0057] p + The step region 23 completely surrounds the boundary between the second surface 40b and the third surface 40c of the front surface of the semiconductor substrate 40. + The impurity concentration of the step region 23 is p + The p-type step region 23 is formed so as to overlap the p-type region in the peripheral portion 1b of the active region 1. -- Since it is formed simultaneously with the p-type region 32, it has a higher impurity concentration than p-type base region 13, which has the lowest impurity concentration among the multiple p-type regions in the peripheral portion 1b of active region 1. An interlayer insulating film 19 extends from active region 1 to edge termination region 2 so as to cover the front surface (first to third faces 40a to 40c) of semiconductor substrate 40. In peripheral portion 1b of active region 1 and edge termination region 2, a field oxide film may be provided between the front surface of semiconductor substrate 40 and interlayer insulating film 19.

[0058] The structure of the spatially modulated JTE structure 30 will be described. The spatially modulated JTE structure 30 is composed of a JTE region 30b and spatially modulated regions 30a and 30c (see FIG. 2), and has the function of alleviating the electric field on the front surface side of the semiconductor substrate 40 to maintain a breakdown voltage. The spatial p-type impurity concentration distribution throughout the spatially modulated JTE structure 30 gradually decreases toward the outside. The breakdown voltage is the limit voltage at which the MOSFET does not malfunction or break down. Specifically, the spatially modulated JTE structure 30 is composed of multiple p ++ The FLR structure consists of a FLR-type region 31 and multiple p-- type area 32 and - and a spatially modulated JTE structure consisting of a type drift region 12.

[0059] Multiple FLR31 and multiple p -- The n-type region (second conductivity type low concentration region) 32 is an n-type region in a surface region of the second surface 40b of the front surface of the semiconductor substrate 40. - The FLR 31 and the p-type silicon carbide layer 42 are selectively provided inside the p-type silicon carbide layer 42 and exposed to the second surface 40b. -- type area 32 Each is shown with a different hatching. -- The breakdown voltage of the edge termination region 2 is adjusted by adjusting the impurity concentration, width, and arrangement of the mold region. The multiple FLRs 31 have approximately the same width (width in the normal direction) and are arranged concentrically around the active region 1, spaced apart from one another. Approximately the same width means that the width is the same within a range that includes tolerances due to process variations. The innermost (chip center side) FLR (first FLR) 31 may be wider than the other FLRs 31.

[0060] The dimension of the FLR structure is preferably, for example, about 0.1 μm or more and 2.5 μm or less. -- Although the breakdown voltage of the edge termination region 2 varies due to the variation in the dose of the dopant in the dopant region 32 (see FIGS. 13 to 15), by keeping the extension dimension of the FLR structure within the above range, -- It is possible to stably ensure a predetermined breakdown voltage of the edge termination region 2 within the range of variation in the dose of the mold region 32. -- The dose variation in the type region 32 is p -- This is due to the variation in the amount of ions implanted in the ion implantation for forming the mold region 32, or the variation in the activation rate of the implanted impurities, or the variation in both.

[0061] Preferably, the FLR structure has a spreading dimension of, for example, about 0.2 μm or more and 1.0 μm or less. --The minimum breakdown voltage of the edge termination region 2 can be increased within the range of variation in the dose of the type region 32. The extension dimension of the FLR structure is the distance d between the adjacent FLRs 31. n and a distance d between the adjacent FLRs 31 that share the outer FLRs 31 among the adjacent FLRs 31. n+1 The difference between and (=d n+1 -d n ) (see FIG. 11). The spreading dimension is uniform within the FLR structure, and the interval between adjacent FLRs 31 increases by a predetermined spreading dimension toward the outside.

[0062] FLR31 has a p + It terminates at a position shallower than the mold extension portion 22a (p + The innermost FLR 31 is shallower than the mold extension 22a. + The mold extension 22a and the innermost p -- The p-type region (first second-conductivity-type low-concentration region) 32 is disposed at a position overlapping the boundary between these regions. + The outer end of the mold extension 22a is indicated by a broken line (similar to FIG. 11). Even if the arrangement of the FLRs 31 is shifted outward, for example, by about 1 μm, due to a misalignment during the alignment of an ion implantation mask for forming the FLRs 31, the innermost FLRs 31 will not be damaged. + The mold extension 22a and the innermost p -- It is preferable to set the width of the innermost FLR 31 so that the innermost FLR 31 is disposed across the mold region 32. + Adjacent to the outside of the step region 23 or + It may be located so as to overlap the outer edge of the mold step region 23 .

[0063] FLR31 has a p -- It terminates at a position shallower than the mold region 32 (p -- (The depth is shallower than that of the type region 32.) As a result, as will be described later, all FLRs 31 are --The FLR 31 is surrounded by a p-type region 32. The end of the FLR 31 on the drain electrode 25 side is a p -- By being surrounded by the p-type region 32, the electric field concentration at the end of the FLR 31 on the drain electrode 25 side is alleviated, and the breakdown voltage of the edge termination region 2 can be improved. All the FLRs 31 have approximately the same impurity concentration. + Mold extensions 22a and p + The impurity concentration is higher than that of the step region 23 .

[0064] For example, all FLR31 ++ The p-type contact region 15 is formed at the same time. ++ The impurity concentration of the FLR 31 may be substantially the same as that of the p-type contact region 15. + By making the impurity concentration of the FLR31 higher than that of the active region, the breakdown voltage of the edge termination region 2 becomes higher than that of the active region 1, and avalanche breakdown is less likely to occur in the edge termination region 2. For example, the impurity concentration of the FLR31 is 1×10 18 / cm 3 More than 1×10 21 / cm 3 By setting the impurity concentration of the FLR 31 within the above range, the FLR 31 can function as an FLR structure without being completely depleted even when a high electric field is applied.

[0065] Multiple p -- The p-type regions 32 are arranged concentrically around the active region 1 and spaced apart from each other. -- The spacing between the mold regions 32 becomes wider toward the outside. -- The innermost p-type region 32 terminates at a position deeper than the FLR 31 on the drain electrode 25 side. -- The type region 32 is p + It is adjacent to the outside of the mold extension portion 22a, extends outward beyond the outermost FLR 31, and surrounds all the FLRs 31. -- The type regions 32 are located between all the adjacent FLRs 31. -- Within mold region 32, an FLR structure is provided.

[0066] p -- The p-type region 32 is a p-type region (p + Mold extension part 22a, p-type base extension part 13a, p ++ Type contact extensions 15a and p + The impurity concentration is lower than that of the step region 23. -- The mold region 32 has approximately the same impurity concentration, for example, 10 17 / cm 3 It is about the first half. -- The target dose of the mold region 32 is, for example, 5.5×10 12 / cm 2 More than 2.1×10 13 / cm 2 It is preferable that the thickness is about the same as or less than the above (see Figures 13 to 15). -- The target dose of the mold region 32 is p -- This is the design value of the dose of ion implantation for forming the mold region 32 .

[0067] p -- The target dose of the mold region 32 changes due to the accumulation of positive charges at the interface between the passivation film (polyimide protective film) covering the front surface of the semiconductor substrate 40 in the edge termination region 2 during high temperature operation and the oxide film (single layer of the interlayer insulating film 19, or a laminated film of the field oxide film and the interlayer insulating film 19) underneath. Therefore, the dose is appropriately set according to the amount of the anticipated accumulated charge. -- The dose variation in the type region 32 is p -- The dose of the mold region 32 should be within ±20% of the target dose. -- By keeping the variation in the dose of the mold region 32 within the above range, the predetermined withstand voltage of the edge termination region 2 can be stably ensured.

[0068] All FLR31 and innermost p -- The type region 32 is p + The p-type base extension 22a, the p-type base extension 13a and the p ++ The p-type contact extension 15a is electrically connected to the source electrode 20. --The innermost p -- Except for the mold region 32, the FLR 31 is disposed on the outer side. -- Between the drain electrode 25 side and the n-type region 32, - The type drift region 12 extends to the second surface 40b of the front surface of the semiconductor substrate 40. This allows all adjacent p -- Between the type regions 32 - A mold drift region 12 is located.

[0069] FLR31 and p -- The dose, width and arrangement of each of the doped regions 32 ensure a predetermined breakdown voltage of the edge termination region 2. -- The spatial modulation region 30a is formed by alternately and repeatedly adjoining the portions of the mold region 32 between the adjacent FLRs 31 in the normal direction. -- The JTE region 30b is formed adjacent to the spatial modulation region 30a at a portion of the mold region 32 outside the outermost FLR 31. -- p outside type region 32 -- A type region 32 and n - The spatial modulation region 30c is adjacent to the outer side of the JTE region 30b and alternately repeats in the normal direction.

[0070] In the surface region of the second surface 40b of the front surface of the semiconductor substrate 40, n - The n-type silicon carbide layer 42 is + A type channel stopper region 33 is optionally provided. + The channel stopper region 33 is provided outside the spatially modulated JTE structure 30, separated from the spatially modulated JTE structure 30, and exposed at the chip edge. + The type channel stopper region 33 and the outermost p -- Between the drain electrode 25 side and the n-type region 32, - The n-type drift region 12 extends. + The type channel stopper region 33 and the outermost p -- The spacing between adjacent p --longer than the spacing between the mold regions 32. + The type channel stopper region 33 is, for example, an n + The impurity concentration may be substantially the same as that of the source region 14 .

[0071] The operation of the silicon carbide semiconductor device 10 according to the first embodiment will be described. When a voltage equal to or greater than the gate threshold voltage is applied to the gate electrode 18 while a positive voltage (forward voltage) with respect to the source electrode 20 is applied to the drain electrode 25, a channel (n-type inversion layer) is formed in the portion of the p-type base region 13 along the trench 16. + Type drain region 11 to n - The n-type inversion layer is formed along the sidewall of the trench 16 inside the p-type base region 13. + A current flows toward the type source region 14, and the MOSFET (silicon carbide semiconductor device 10) turns on.

[0072] On the other hand, when a forward voltage is applied between the source and drain, and a voltage less than the gate threshold voltage is applied to the gate electrode 18, the first and second p + The p-type regions 21 and 22 and the p-type base region 13 and the n - The MOSFET maintains the off state by reverse-biasing the pn junction with the type drift region 12. At this time, a depletion layer spreads from the pn junction, and the electric field applied to the bottom surface of the trench 16 located on the source electrode 20 side of the pn junction is relaxed.

[0073] Furthermore, when the MOSFET is turned off, the depletion layer extending from the pn junction in the active region 1 is connected to each p-type region and n-type region of the spatially modulated JTE structure 30 formed to surround the active region 1. - Edge termination region 2 extends laterally outward (toward the chip end) due to the pn junction with active region 12. The depletion layer extends outward through edge termination region 2, ensuring a predetermined breakdown voltage based on the dielectric breakdown field strength of silicon carbide and the depletion layer width (width in the normal direction from active region 1 to the chip end).

[0074] Next, a method for manufacturing the silicon carbide semiconductor device 10 according to the first embodiment will be described. Figures 3 to 6 are cross-sectional views showing a state during the manufacturing process of the silicon carbide semiconductor device according to the first embodiment. Figures 3 to 6 show only the outer peripheral portion 1b and edge termination region 2 (see Figure 2) of the active region 1 of one chip region 50a, and the central portion 1a of the active region 1 will be described with reference to Figure 2. The chip region 50a is a region that will become a semiconductor chip (semiconductor substrate 40) after dicing (cutting) of the semiconductor wafer 50, and a plurality of chip regions 50a are formed in a matrix shape surrounded by, for example, lattice-shaped dicing lines (cutting lines) 50b in the central portion of the semiconductor wafer 50.

[0075] First, as shown in Figure 3, + The starting substrate 41 is + A mold starting wafer 51 is prepared. Next, n + On the front surface of the starting mold wafer 51, n - n-type drift region 12 - Next, an n-type silicon carbide layer 42 is epitaxially grown in the central portion 1a of the active region 1 by photolithography and ion implantation of p-type impurities. - The first p-type silicon carbide layer 42 has a surface region. + Mold region 21 and second p + The lower portions of the mold regions 22 are selectively formed. + At the same time as forming the lower part of the type region 22, the outer periphery 1b of the active region 1 is - The surface region of the silicon carbide layer 42 is + The lower portion 52 of the mold extension 22a is formed.

[0076] Next, page 1 + Mold region 21 and second p + After removing the ion implantation mask (not shown) used to form the lower part of the mold region 22, n - On the silicon carbide layer 42, - By epitaxially growing the silicon carbide layer to increase its thickness, -The silicon carbide layer 42 is then formed to the thickness of the product (silicon carbide semiconductor device 10). Next, the n-type silicon carbide layer 42 is formed in the central portion 1a of the active region 1 by photolithography and ion implantation of p-type impurities. - The thickened portion 42a of the silicon carbide layer 42 is then subjected to a second p + The upper part of the mold region 22 is formed. + The upper and lower parts of the mold area 22 are connected to form a second p + A mold area 22 is formed.

[0077] 2nd p. + At the same time as forming the upper part of the type region 22, the outer periphery 1b of the active region 1 is - The surface region of the thickened portion 42a of the silicon carbide layer 42 To p + The upper portion 53 of the mold extension portion 22a is formed. + The upper part 53 and the lower part 52 of the mold extension part 22a are connected to each other, + The mold extension 22a is formed. Next, - A p-type silicon carbide layer 43 that becomes the p-type base region 13 is epitaxially grown on the surface of the n-type silicon carbide layer 42. + On the front surface of the starting wafer 51, - A semiconductor wafer 50 is completed in which silicon carbide layers 42, 43 which become p-type drift region 12 and p-type base region 13 are epitaxially grown in sequence.

[0078] When forming an n-type current spreading region, n + On the front surface of the starting wafer 51, - After forming the n-type silicon carbide layer 42, - Before epitaxial growth to increase the thickness of the n-type silicon carbide layer 42, the n-type silicon carbide layer 42 is doped with n-type impurities over the entire active region 1 by photolithography and ion implantation of n-type impurities. - The lower portion of the n-type current diffusion region is formed in the surface region of the n-type silicon carbide layer 42. - After increasing the thickness of the silicon carbide layer 42, - The thickened portion 42a of the silicon carbide layer 42 is doped with n-type GaN over the entire active region 1. -The upper part of the n-type current diffusion region may be formed in the surface region of the type silicon carbide layer 42 so as to be connected to the lower part of the n-type current diffusion region.

[0079] 4, the edge termination region 2 of the p-type silicon carbide layer 43 is removed by photolithography and etching to leave the p-type silicon carbide layer 43 only in the active region 1. As a result, the front surface of the semiconductor wafer 50 has an outer portion (second surface 40b) which is larger than the inner portion (first surface 40a). + A lowered (recessed) step 24 is formed on the mold starting wafer 51 side, and the edge termination region 2 is formed on the second surface 40b of the front surface of the semiconductor wafer 50. - The n-type silicon carbide layer 42 is exposed on the second surface 40b of the front surface of the semiconductor wafer 50 in the edge termination region 2. - A surface region of the silicon carbide layer 42 may be removed slightly.

[0080] Next, the etching mask (not shown) used for partially removing the p-type silicon carbide layer 43 is removed. Next, a set of steps including photolithography, ion implantation of impurities, and removal of the ion implantation mask (not shown) is repeated under different conditions to form n ions in the p-type silicon carbide layer 43 in the active region 1 in the surface region of the front surface (the main surface on the p-type silicon carbide layer 43 side) of the semiconductor wafer 50. + Type source region 14, p ++ Type contact region 15, p ++ Type contact extensions 15a and p + The step region 23 is selectively formed, and the n-type step region 2 is selectively formed in the edge termination region 2. - The spatially modulated JTE structure 30 and the n-type silicon carbide layer 42 are formed in the + A type channel stopper region 33 is selectively formed.

[0081] In this case, for example, n + At the same time as the formation of the type source region 14, the surface region (n - The n-type silicon carbide layer 42 is formed in a surface region thereof so as to extend across the ends of the adjacent chip regions 50a. +As shown in FIG. 5, a plurality of p-type channel stopper regions 33 are selectively formed in the surface region of the second surface 40b of the front surface of the semiconductor wafer 50. -- The p-type region 32 is selectively formed. Then, as shown in FIG. ++ Type contact region 15 and p ++ At the same time as forming the type contact extension 15a, the innermost p -- A plurality of FLRs 31 may be selectively formed inside the mold region 32 .

[0082] FLR31, p -- Type regions 32 and n + The order in which the n-type channel stopper regions 33 are formed can be changed. - The first and second p-type silicon carbide layers 42 + type region 21,22, p + Mold extension part 22a, FLR31, p -- Type regions 32 and n + A type channel stopper region 33 and an n + The remaining non-ion-implanted portion between the starting wafer 51 and the n - The n-type drift region 12 is formed in the p-type silicon carbide layer 43. + Type source region 14, p ++ Type contact region 15 and p ++ Type contact extension 15a and n - The non-ion-implanted portions remaining between the p-type silicon carbide layer 42 and the p-type base region 13 and the p-type base extension 13a are formed.

[0083] Next, the ion-implanted impurities are activated by heat treatment. Next, trenches 16, gate insulating film 17, gate electrode 18, interlayer insulating film 19, source electrode 20, drain electrode 25, and passivation film (polyimide protective film: not shown) are formed by a general method. Since the passivation film may be pulled by the dicing blade and peeled off, the portion of the passivation film above the dicing line 50b is removed before dicing. Thereafter, the semiconductor wafer 50 is diced along the dicing line 50b to separate the chip region 50a into individual semiconductor chips (semiconductor substrate 40), thereby completing the silicon carbide semiconductor device 10 of FIGS. 1 and 2.

[0084] As described above, according to the first embodiment, the breakdown voltage structure disposed in the edge termination region is a spatially modulated JTE structure that is a combination of a JTE structure and an FLR structure. All the FLRs that make up the FLR structure are arranged in the innermost p -- The innermost FLR of the FLR structure is surrounded by p + The innermost p that constitutes the mold extension and JTE structure -- The edge termination region is disposed at a position overlapping the boundary with the mold region, spanning these regions. This makes it possible to suppress fluctuations in the withstand voltage characteristics of the spatially modulated JTE structure, and therefore ensure a predetermined withstand voltage in a stable manner.

[0085] Furthermore, according to the first embodiment, by adjusting the width and arrangement of the FLR structures constituting the spatially modulated JTE structure, the spatially modulated JTE structure can be formed simultaneously with any part of the active region, so that the number of masks and the number of ion implantation steps can be reduced, and the manufacturing lead time can be shortened. Since the conventional structure (see FIG. 19) uses 18 masks, according to the first embodiment, it is possible to reduce the time by about 0.5% for each reduction in the number of masks. For this reason, for example, it is possible to form the FLR structure at the p of the active region. ++ The n-type contact region is formed at the same time as the n-type contact region. + The n-type channel stopper region is +By forming the masks simultaneously with the source region, the number of masks can be reduced by two in total, enabling the manufacturing lead time to be shortened by approximately 10%.

[0086] Moreover, according to the first embodiment, the edge termination region is arranged with a spatially modulated JTE structure that is a combination of a JTE structure and an FLR structure, so that the width (area of ​​the edge termination region) of the edge termination region can be narrower than that of the conventional structure. This allows the chip size to be reduced, and therefore the cost to be reduced. Moreover, according to the first embodiment, a predetermined breakdown voltage is stably secured in the edge termination region, so that avalanche breakdown is less likely to occur in the edge termination region. This allows the avalanche breakdown capacity to be determined by the breakdown voltage of the active region, and thus improves reliability.

[0087] (Embodiment 2) Next, a method for manufacturing a silicon carbide semiconductor device according to the second embodiment will be described. Figures 7 to 10 are cross-sectional views showing a state during the manufacturing of a silicon carbide semiconductor device according to the second embodiment. Figures 7 to 10 show only the outer peripheral portion 1b and edge termination region 2 (see Figure 2) of an active region 1 of one chip region 50a, and the central portion 1a of the active region 1 will be described with reference to Figure 2. The silicon carbide semiconductor device 10 shown in Figures 1 and 2 is produced (manufactured) by the method for manufacturing a silicon carbide semiconductor device according to the second embodiment. The arrangement of the chip region 50a and dicing lines 50b of the semiconductor wafer 50 is the same as in the first embodiment.

[0088] The method for manufacturing a silicon carbide semiconductor device according to the second embodiment includes the steps of: forming a JTE structure (p -- The method of forming the mold region 32) is different from the method of manufacturing the silicon carbide semiconductor device 10 according to the first embodiment (see FIGS. 3 to 6). Specifically, in the second embodiment, first, as shown in FIG. + On the front surface of the starting wafer 51 - From the epitaxial growth of the silicon carbide layer 42, + Mold region 21 and second p + Formation of the lower part of the mold region 22, n- epitaxial growth to increase the thickness of the second p-type silicon carbide layer 42; + The upper part of the mold region 22 is then formed.

[0089] Next, photolithography and ion implantation of n-type impurities are performed to form n-type GaN in edge termination region 2. - In the portion 42a of the silicon carbide layer 42 where the thickness is increased, the p -- In the portion other than the region where the n-type region 32 is formed, an n-type region (first conductivity type low concentration region) 61 is formed. -- Between the forming region of the mold region 32 and the outermost p -- An n-type region 61 is formed in the outer portion of the region where the n-type region 32 is formed. The n-type impurity concentration of the n-type region 61 is set to the p -- The p-type impurity concentration is substantially the same as that of the n-type region 32. The n-type region 61 may be formed, for example, at the same time as an n-type current diffusion region (not shown) of the active region 1, etc.

[0090] Next, as shown in FIG. 8, similarly to the first embodiment, n - After the p-type silicon carbide layer 43 is formed on the n-type silicon carbide layer 42, a portion of the edge termination region 2 of the p-type silicon carbide layer 43 is removed to form a n-type silicon carbide layer 43 on the front surface of the semiconductor wafer 50, the n-type silicon carbide layer 43 being closer to the n-type silicon carbide layer 42 than the inner first surface 40a. + The second surface 40b of the mold starting wafer 51 is lowered toward the outer side. - 9, the surface region (n - The n-type region 61 is converted to p-type by ion implantation of p-type impurities into the entire surface region of the silicon carbide layer 42, thereby lowering the n-type impurity concentration in the n-type region 61.

[0091] As a result, the surface area of ​​the second surface 40b of the front surface of the semiconductor wafer 50 (n - The surface region of the n-type silicon carbide layer 42 (except for the n-type region 61) is inverted to p-type, and the p-type of the spatially modulated JTE structure 30 is -- The adjacent p --Between the n-type regions 32, the n-type regions 61 are turned into p-type regions to have a lower n-type impurity concentration than the n-type regions 61. - A first conductivity type low concentration region 62 is disposed. - The impurity concentration of the n-type region 62 is - The impurity concentration of the drift region 12 (=7.4×10 16 / cm 3 It is better to have approximately the same - The impurity concentration may be up to about 10 times higher than that of the type drift region 12 .

[0092] This p -- The ion implantation of p-type impurities into the entire surface region of the second face 40b of the front surface of the semiconductor wafer 50 to form the base region 32 may be performed, for example, by utilizing an etching mask used in the etching to remove the portion of the edge termination region 2 of the p-type silicon carbide layer 43. Alternatively, the ion implantation of p-type impurities into the entire surface region of the second face 40b of the front surface of the semiconductor wafer 50 may be performed without using a mask, by utilizing a channel implanter for adjusting the gate threshold voltage, which implants p-type impurities into the channel portion of the active region 1 (an n-type inversion layer formed inside the p-type base region 13 when the MOSFET is on).

[0093] Next, as shown in FIG. 10, similarly to the first embodiment, n + At the same time as forming the n-type source region 14 + The p-type channel stopper region 33 is selectively formed. ++ Type contact region 15 and p ++ By forming the FLR 31 at the same time as the formation of the type contact extension 15a, the spatial modulation JTE structure 30 is formed as in the first embodiment (see FIG. 6). -- type area 32, n + It is possible to reverse the order of forming n-type channel stopper region 33 and n-type region 61. Thereafter, the steps following heat treatment for impurity activation are performed in order to complete silicon carbide semiconductor device 10 of FIGS.

[0094] As described above, according to the second embodiment, it is possible to obtain the same effect as that of the first embodiment. Also, according to the second embodiment, the JTE structure (p -- The edge termination region (type region) is formed by ion-implanting p-type impurities into the entire edge termination region using an n-type region that can be formed simultaneously with the ion implantation to form each portion of the active region, and by using a mask used in another process to lower the impurity concentration in the n-type region. The portion of the edge termination region excluding the n-type region becomes the JTE structure that constitutes the spatially modulated JTE structure. This allows the number of masks required to form the spatially modulated JTE structure to be further reduced.

[0095] (Experimental Example) The breakdown voltage of the edge termination region 2 in which the spatially modulated JTE structure 30 (see FIG. 2) is arranged was examined. FIG. 11 is a cross-sectional view showing an example of the spatially modulated JTE structure of an experimental example. FIG. 12 is a table showing the simulation conditions and the judgment results of the experimental example. FIGS. 13 to 15 are characteristic diagrams showing the relationship between the dose amount and the breakdown voltage of the JTE structure constituting the spatially modulated JTE structure of the experimental example. FIG. 16 is a characteristic diagram showing the relationship between the extension dimension and the breakdown voltage of the FLR structure constituting the spatially modulated JTE structure of the experimental example. FIGS. 17 and 18 are characteristic diagrams showing the relationship between the arrangement of the FLR constituting the spatially modulated JTE structure of the experimental example and the working example and the breakdown voltage, respectively.

[0096] 12 shows the results of simulating the breakdown voltage of the edge termination region 2 under a number of simulation conditions (hereinafter, set conditions 1 to 3) in which the number, width and arrangement interval of the FLRs 31 constituting the spatially modulated JTE structure 30 (see FIG. 2) of the above-mentioned first embodiment are variously changed. Set conditions 1 to 3 are set in order to confirm the influence of the number, width (width in the normal direction) and arrangement interval of the FLRs 31 on the breakdown voltage of the edge termination region 2. + The mold extension 22a and the innermost p -- There is no FLR 31 that spans the mold region 32, and all the FLRs 31 are + The mold extension 22a and the innermost p -- The condition was that the mold region 32 was disposed outside the boundary.

[0097] The widths of the FLRs 31 in the setting conditions 1 to 3 are 1 μm, 1.5 μm, and 2 μm, respectively. The setting conditions 1 to 3 include four simulation conditions with different numbers of FLRs 31 (4, 6, 8, and 10. Note that the setting condition 3 has 9 FLRs because it is not possible to arrange 10 FLRs 31). The width of the edge termination region 2 (p + The mold extension 22a and the innermost p -- The length from the boundary with the mold region 32 to the edge of the semiconductor substrate 40) w0, the spatial modulation region 30c, and n + The same simulation conditions were used for the type channel stopper region 33 under the set conditions 1 to 3. Specifically, the conditions are as follows: The width w0 of the edge termination region 2 was set to 150 μm.

[0098] 5p -- A spatial modulation JTE structure having a spatial modulation region 30c was constructed in the mold region 32. -- The widths (widths in the normal direction) w1 to w5 of the mold region 32 were set to 40 μm, 4.6 μm, 1.6 μm, 2.2 μm, and 2.5 μm from the inside, respectively. The width (=30 μm) of the spatial modulation region 30c was fixed, and the widths of adjacent p -- The intervals w11 to w14 between the mold regions 32 were set to 1.5 μm, 1.8 μm, 1.8 μm, and 4 μm from the inside, respectively. -- Type region 32 and n + The distance w15 between the n-type channel stopper region 33 and the n-type channel stopper region 33 was set to 20 μm. + The width w16 of the mold channel stopper region 33 was set to 20 μm.

[0099] The innermost p -- The width w1 (=40 μm) of the mold region 32 is fixed, and the width of the JTE region 30b is set to about 10 μm for each simulation condition according to the number of FLRs 31. + The distance d0 between the mold extension 22a and the innermost FLR 31 and the extension dimension of the FLR structure (=d n+1 -d n, n is a positive number (n≧1), and the maximum value of n=the number of FLRs 31−1) was set. FIG. 11 shows a cross-sectional structure when the number of FLRs 31 is set to four. FIG. 12 shows four simulation conditions for each of setting conditions 1 to 3. In FIG. 12, "structure name" is a name for distinguishing the simulation conditions.

[0100] In FIG. 12, the "SMJTE" in the "structure name" refers to multiple p -- This means that the spatial modulation JTE structure has a spatial modulation region 30c formed by a mold region 32. The "Ring (m), m is a positive number (m≧1)" in the "structure name" refers to the innermost p -- This means that the number of FLRs 31 arranged inside the mold region 32 is m. Therefore, when the "structure name" is, for example, "SMJTE+Ring(4)", multiple p -- The spatially modulated JTE structure has a spatially modulated region 30c formed by a type region 32, and the innermost p -- This means that the structure has four FLRs 31 arranged inside a mold region 32.

[0101] "Minimum withstand voltage" means p -- This is the minimum withstand voltage of edge termination region 2 that can be obtained within the range of the target dose amount of mold region 32 ±20%. Whether or not the predetermined withstand voltage of edge termination region 2 has been obtained based on this minimum withstand voltage of edge termination region 2 is indicated in "Judgment". A judgment of "○" is when the "minimum withstand voltage" is 1550V or more, the difference from the withstand voltage of about 1600V of edge termination region 102 in the conventional example being within 5%, for example. A judgment of "△" is when the "minimum withstand voltage" is 1500V or more, which is a predetermined withstand voltage including a safety margin of edge termination region 2 (maximum applied voltage 80%, safety margin 20%), and a judgment of "×" is when the "minimum withstand voltage" is less than 1500V.

[0102] Experimental example setting conditions 1 to 3 --The results of simulating the breakdown voltage of edge termination region 2 versus the dose of type region 32 are shown in Figures 13 to 15, respectively. For set conditions 1 to 3, simulations were performed under four simulation conditions (set conditions 1 to 3: SMJTE+Ring(4), SMJTE+Ring(6) and SMJTE+Ring(8), set conditions 1 and 2: SMJTE+Ring(10), set condition 3: SMJTE+Ring(9)). The horizontal axis of Figures 13 to 15 indicates the innermost p -- The dose in the mold region 32 (SMJTE1 dose) is plotted on the vertical axis, and the breakdown voltage BVdss in the edge termination region 2 is plotted on the vertical axis.

[0103] 13 to 15 show the results of simulation of a conventional silicon carbide semiconductor device 110 (hereinafter, referred to as the conventional example: see FIG. 19) having a double-zone spatially modulated JTE structure 130 (2-zone SMJTE). -- The conditions of the mold region 132 (number and impurity concentration) are the same as those of the experimental example p -- The conditions are the same as those of the mold region 32, and the innermost p -- The innermost spatial modulation region 130b is disposed inside the mold region 132. - In the conventional example, the horizontal axis of Figs. -- The vertical axis represents the dose in the mold region 132 , and the vertical axis represents the breakdown voltage BVdss of the edge termination region 2 .

[0104] The vertical dashed lines in Figures 13 to 15 indicate the p-type region with the lower impurity concentration (the p-type region in the experimental example) out of the two p-type regions with different impurity concentrations that constitute the innermost spatial modulation region of the spatial modulation JTE structure. -- Type region 32, conventional p -- Standard (target) dose (1.2×10 13 / cm 2 The horizontal axis of Figures 13 to 15 is the innermost p -- The variation in the target dose of the mold regions 32 and 132 is shown. --The target variation in dose of the mold regions 32, 132 is due to variations in the implantation dose, or variations in the activation rate of the implanted impurities, or both.

[0105] 13 and 14, it was confirmed that in the embodiment, the greater the number of FLRs 31, the more stably a predetermined breakdown voltage can be ensured in edge termination region 2. For example, by increasing the number of FLRs 31 to eight or more, the breakdown voltage can be made to be approximately the same as that of edge termination region 102 in the conventional example. On the other hand, the result shown in FIG. 15 indicates that as the width of FLR 31 increases, the extension dimension (=d n+1 -d n It was confirmed that, due to the narrowing of the gap between the FLRs 31, when the number of FLRs 31 is large, the specified breakdown voltage of the edge termination region 2 cannot be obtained, whereas when the number of FLRs 31 is small, the specified breakdown voltage of the edge termination region 2 can be stably ensured.

[0106] FIG. 16 shows the results of simulating the breakdown voltage of edge termination region 2 versus the extension dimension of the FLR structure in the experimental example. The horizontal axis of FIG. 16 is the extension dimension (=d n+1 -d n ), with the vertical axis representing the minimum breakdown voltage in FIG. 12. The horizontal line ref in FIG. 16 represents the breakdown voltage of edge termination region 102 of the conventional example. From the results shown in FIGS. 12 and 16, it was confirmed that when the extension dimension of the FLR structure is approximately 0.1 μm or more and 2.5 μm or less (judged △ and ○), the breakdown voltage of edge termination region 2 can be made 1500 V or more, and when the extension dimension of the FLR structure is, for example, 0.2 μm or more and 1.0 μm or less (judged ○), the breakdown voltage of edge termination region 2 can be made 1550 V or more.

[0107] Although not shown in the figure, during high temperature (150° C. or higher) operation in the experimental example, when positive charges are accumulated at the interface between the passivation film (polyimide protective film) covering the front surface of the semiconductor substrate 40 in the edge termination region 2 and the oxide film (a single layer of the interlayer insulating film 19, or a laminated film of the field oxide film and the interlayer insulating film 19) underneath, p --The inventors have confirmed that the target dose of the mold region 32 (vertical dashed lines in FIGS. 13-15) shifts to the high dose side (right side in FIGS. 13-15), decreasing the breakdown voltage of the edge termination region 2. No adverse effects are caused by negative charge accumulation at the interface between the passivation film and the oxide film.

[0108] Simulation results of the breakdown voltage BVdss of the edge termination region 2 for the arrangement of the FLR structure (multiple FLRs 31) are shown in Figures 17 and 18. Figure 17 shows the simulation results for "SMJTE+Ring(10)" of the experimental setting condition 1. Figure 17 shows "SMJTE+Ring(10)" of the experimental setting condition 1, as well as a condition in which the overall arrangement of the FLR structure of this experimental example is shifted 1 μm outward and inward, respectively (shown as "SMJTE+Ring(10)+1 μm shift" and "SMJTE+Ring(10)-1 μm shift", respectively).

[0109] FIG. 18 shows the simulation results of the embodiment. In the embodiment, the setting condition 1 of the experimental example, “SMJTE+Ring(10)”, + The mold extension 22a and the innermost p -- An FLR 31 is added, which is arranged across the mold region 32 (shown in FIG. 18 as SMJTE+Ring(10+1)). FIG. 18 shows this "SMJTE+Ring(10+1)" as well as conditions in which the overall arrangement of the FLR structure of this example is shifted 1 μm outward and inward (shown as "SMJTE+Ring(10+1)+1 μm shift" and "SMJTE+Ring(10+1)-1 μm shift," respectively).

[0110] From the results shown in FIG. 17, it was confirmed that in the experimental example, when the FLR structure is positioned at a position shifted outward by 1 μm, the breakdown voltage of edge termination region 2 decreases. On the other hand, from the results shown in FIG. 18, it was confirmed that in the working example, even if the FLR structure is positioned at a position shifted outward by 1 μm, the breakdown voltage of edge termination region 2 does not decrease. The reason for this is that in the working example, even if the FLR structure is shifted outward by about 1 μm, the p + The mold extension 22a and the innermost p-- It is presumed that this is because the FLR 31 can be arranged across the mold region 32, thereby making it possible to suppress fluctuations in the withstand voltage characteristics of the spatially modulated JTE structure.

[0111] The reason for setting the shift amount of the FLR structure to 1 μm is that it is assumed that the positional deviation during alignment of the ion implantation mask for forming the FLR 31 is a maximum of about 0.2 μm, and that a positional deviation of up to 1 μm occurs, including the variation in the size of the opening of the ion implantation mask. Although not shown in the figure, even when positive charges are accumulated at the interface between the passivation film and the oxide film, p + The mold extension 22a and the innermost p -- It was confirmed that the provision of FLR 31 across mold region 32 did not change the breakdown voltage characteristics of edge termination region 2, similar to the simulation result of FIG.

[0112] The present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the spirit of the present invention. The present invention also applies when the conductivity types (n-type, p-type) are reversed. [Industrial Applicability]

[0113] INDUSTRIAL APPLICABILITY As described above, the silicon carbide semiconductor device and the method for manufacturing a silicon carbide semiconductor device according to the present invention are useful for power semiconductor devices used in power conversion devices and power supply devices for various industrial machines and the like. [Explanation of symbols]

[0114] 1 active area 1a Central part of the active region 1b Outer periphery of active region 2 Edge Termination Area 10 Silicon carbide semiconductor device 11 n + Type drain region 12n - Mold Drift Region 13 p-type base region 13a p type base extension 14 n+ Type Source Area 15 p ++ Mold Contact Area 15a p ++ Type contact extension 16 Trench 17 Gate insulating film 18 Gate electrode 19 Interlayer insulating film 20 Source electrode 21,22 p + type area 22a p + Mold extension 23 p + Mold step area 24. Step on the front surface of a semiconductor substrate 25 Drain electrode 30 Spatially Modulated JTE Structure 30a Spatial modulation area 30b JTE area 30c Spatial modulation area 31 FLR 33n + Type channel stopper region 40 Semiconductor Substrate 40a: a first surface of the front surface of the semiconductor substrate (a portion inside the step on the front surface of the semiconductor substrate) 40b: a second surface of the front surface of the semiconductor substrate (a portion outside the step on the front surface of the semiconductor substrate) 40c: the third surface of the front surface of the semiconductor substrate (step mesa edge) 41 n + Starting substrate 42n - mold silicon carbide layer 42a n - The portion where the thickness of the silicon carbide layer is increased 43 p-type silicon carbide layer 50 Semiconductor Wafers 50a Chip Area 50b Dicing Line 51 n + Starting wafer 52 p + Lower part of mold extension 53 p + Upper part of mold extension 61 n-type region 62n - type area X: A first direction parallel to the front surface of the semiconductor substrate Y: A second direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction Z depth direction

Claims

1. an active region provided in a semiconductor substrate made of silicon carbide; a termination region provided in the semiconductor substrate and surrounding the active region; a first conductivity type region provided within the semiconductor substrate across the active region and the termination region; a second conductivity type region provided in the active region between the first main surface of the semiconductor substrate and the first conductivity type region; a semiconductor element provided in a center portion of the active region and having a pn junction between the first conductivity type region and the second conductivity type region; a second conductivity type peripheral region provided on the outer periphery of the active region and surrounding a central portion of the active region; a first electrode of the semiconductor element provided on a first main surface of the semiconductor substrate and electrically connected to the second conductivity type region and the second conductivity type peripheral region; a second electrode of the semiconductor element provided on a second main surface of the semiconductor substrate and electrically connected to the first conductivity type region; a plurality of second-conductivity-type FLRs selectively provided in the termination region between the first main surface of the semiconductor substrate and the first-conductivity-type region and spaced apart from one another, the FLRs concentrically surrounding the active region to form an FLR structure; a plurality of second conductivity type low concentration regions having an impurity concentration lower than that of the FLR, the second conductivity type low concentration regions being selectively provided, spaced apart from one another, between the first main surface of the semiconductor substrate and the first conductivity type region in the termination region, and concentrically surrounding the active region to form a JTE structure; Equipped with a first second conductivity type low concentration region which is an innermost region among the plurality of second conductivity type low concentration regions is adjacent to an outer side of the second conductivity type peripheral region and extends from a boundary with the second conductivity type peripheral region to an outer side of the FLR; a second second-conductivity-type low-concentration region other than the first second-conductivity-type low-concentration region among the plurality of second-conductivity-type low-concentration regions is disposed outside the FLR; a first FLR which is an innermost one of the plurality of FLRs, arranged across the second conductivity type peripheral region and the first second conductivity type low concentration region,

2. 2 . The silicon carbide semiconductor device according to claim 1 , wherein a depth of said FLR is shallower than a depth of said second conductivity type low concentration region.

3. 3 . The silicon carbide semiconductor device according to claim 1 , wherein an impurity concentration of the FLR is higher than an impurity concentration of the second conductivity type peripheral region.

4. The impurity concentration of the FLR is 1×10 18 / cm 3 Above 1 x 10 21 / cm 3 4. The silicon carbide semiconductor device according to claim 1, wherein:

5. The dose of the second conductive type low concentration region is 5.5×10 12 / cm 2 Above 2.1 x 10 13 / cm 2 5. The silicon carbide semiconductor device according to claim 1, wherein:

6. The interval between the adjacent FLRs becomes wider as the distance from the active region increases.

6. The silicon carbide semiconductor device according to claim 1, wherein a spreading dimension of a space between adjacent said FLRs is not less than 0.1 μm and not more than 2.5 μm.

7. 7. The silicon carbide semiconductor device according to claim 6, wherein a spreading dimension of a space between the adjacent FLRs is not less than 0.2 μm and not more than 1.0 μm.

8. The semiconductor device is a first semiconductor region of a first conductivity type selectively provided between a first main surface of the semiconductor substrate and the second conductivity type region; a second semiconductor region of a second conductivity type selectively provided between the first main surface of the semiconductor substrate and the second conductivity type region and having an impurity concentration higher than that of the second conductivity type region; a gate insulating film provided in contact with a region between the first semiconductor region and the first conductive type region of the second conductive type region; a gate electrode provided on the opposite side of the second conductivity type region with the gate insulating film interposed therebetween; Equipped with the first electrode is electrically connected to the second conductivity type region via the first semiconductor region and the second semiconductor region; 8. The silicon carbide semiconductor device according to claim 1, wherein an impurity concentration of the FLR is the same as an impurity concentration of the second semiconductor region.

9. A method for manufacturing a silicon carbide semiconductor device comprising: a semiconductor substrate made of silicon carbide; an active region having a semiconductor element having a pn junction between a first conductivity type region and a second conductivity type region provided in a central portion thereof; and a termination region surrounding the active region, A first step of forming a first conductivity type semiconductor layer that becomes the first conductivity type region on a starting substrate made of silicon carbide; a second step of forming a second conductive type semiconductor layer on the first conductive type semiconductor layer in the active region, the second conductive type semiconductor layer being the second conductive type region; a third step of selectively forming a first semiconductor region of a first conductivity type in a surface region of the second conductivity type semiconductor layer; a fourth step of selectively forming a second semiconductor region of a second conductivity type in a surface region of the second conductivity type semiconductor layer; a fifth step of forming a second conductivity type peripheral region on the outer periphery of the active region so as to surround a central portion of the active region; a sixth step of selectively forming a plurality of second-conductivity-type FLRs in the termination region, the FLRs being spaced apart from one another in a surface region of the first-conductivity-type semiconductor layer and concentrically surrounding the active region to form an FLR structure; a seventh step of selectively forming a plurality of second conductivity type low concentration regions having an impurity concentration lower than that of the FLR, the second conductivity type low concentration regions being disposed apart from each other in the surface region of the first conductivity type semiconductor layer in the termination region and concentrically surrounding the periphery of the active region to form a JTE structure; an eighth step of forming a first electrode of the semiconductor element on a first main surface of the semiconductor substrate, the first electrode being electrically connected to the second conductivity type region and the second conductivity type peripheral region; a ninth step of forming a second electrode of the semiconductor element on a second main surface of the semiconductor substrate, the second electrode being electrically connected to the first conductivity type region; Including, In the seventh step, a first second-conductivity-type low-concentration region which is the innermost of the plurality of second-conductivity-type low-concentration regions is disposed adjacent to the outside of a formation region of the second-conductivity-type peripheral region and extends from a boundary with the formation region of the second-conductivity-type peripheral region to the outside of a formation region of the FLR; a second low concentration region of the second conductivity type, excluding the first low concentration region of the second conductivity type, among the plurality of low concentration regions of the second conductivity type, is disposed outside a region where the FLR is formed; In the sixth step, a first FLR that is an innermost one of the plurality of FLRs is disposed across a region where the second conductivity type outer periphery region is formed and a region where the first second conductivity type low concentration region is formed; a silicon carbide semiconductor device manufacturing method comprising the steps of:

10. A method for manufacturing a silicon carbide semiconductor device comprising: a semiconductor substrate made of silicon carbide; an active region having a semiconductor element having a pn junction between a first conductivity type region and a second conductivity type region provided in a central portion thereof; and a termination region surrounding the active region, A first step of forming a first conductivity type semiconductor layer that becomes the first conductivity type region on a starting substrate made of silicon carbide; a second step of forming a second conductive type semiconductor layer on the first conductive type semiconductor layer in the active region, the second conductive type semiconductor layer being the second conductive type region; a third step of selectively forming a first semiconductor region of a first conductivity type in a surface region of the second conductivity type semiconductor layer; a fourth step of selectively forming a second semiconductor region of a second conductivity type in a surface region of the second conductivity type semiconductor layer; a fifth step of forming a second conductivity type peripheral region on the outer periphery of the active region so as to surround a central portion of the active region; a sixth step of selectively forming a plurality of second-conductivity-type FLRs in the termination region, the FLRs being spaced apart from one another in a surface region of the first-conductivity-type semiconductor layer and concentrically surrounding the active region to form an FLR structure; a seventh step of selectively forming a plurality of second conductivity type low concentration regions having an impurity concentration lower than that of the FLR, the second conductivity type low concentration regions being disposed apart from each other in the surface region of the first conductivity type semiconductor layer in the termination region and concentrically surrounding the periphery of the active region to form a JTE structure; an eighth step of forming a gate insulating film in contact with a region of the second conductive type region between the first semiconductor region and the first conductive type region; a ninth step of forming a gate electrode on the opposite side of the second conductivity type region with the gate insulating film interposed therebetween; a tenth step of introducing a second conductivity type impurity into a region between the first semiconductor region and the first conductivity type region of the second conductivity type region to adjust a gate threshold voltage; an eleventh step of forming a first electrode of the semiconductor element on a first main surface of the semiconductor substrate, the first electrode being electrically connected to the second conductivity type region and the second conductivity type peripheral region; a twelfth step of forming a second electrode of the semiconductor element on a second main surface of the semiconductor substrate, the second electrode being electrically connected to the first conductivity type region; Including, In the seventh step, a thirteenth step of selectively forming a first conductivity type low concentration region having the same first conductivity type impurity concentration as the second conductivity type impurity concentration of the second conductivity type low concentration region in a surface region of the first conductivity type semiconductor layer in the termination region; a fourteenth step of introducing a second conductivity type impurity into an entire surface region of the first conductivity type semiconductor layer in the termination region to form the second conductivity type low concentration region in a portion other than a region where the first conductivity type low concentration region is to be formed, and lowering the first conductivity type impurity concentration in the region where the first conductivity type low concentration region is to be formed; a first second-conductivity-type low-concentration region which is the innermost of the plurality of second-conductivity-type low-concentration regions is disposed adjacent to the outside of a formation region of the second-conductivity-type peripheral region and extends from a boundary with the formation region of the second-conductivity-type peripheral region to the outside of a formation region of the FLR; a second low concentration region of the second conductivity type, excluding the first low concentration region of the second conductivity type, among the plurality of low concentration regions of the second conductivity type, is disposed outside a region where the FLR is formed; In the sixth step, a first FLR that is an innermost one of the plurality of FLRs is disposed across a region where the second conductivity type outer periphery region is formed and a region where the first second conductivity type low concentration region is formed; A method for manufacturing a silicon carbide semiconductor device, comprising: simultaneously carrying out said tenth step and said fourteenth step.

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