Super-junction semiconductor device

Abstract

To provide a super-junction semiconductor device capable of suppressing withstanding voltage reduction with respect to manufacturing variation.SOLUTION: A semiconductor device has an active region 30 in which a current flows, and a termination structure part 40. A first semiconductor layer 2 of a first conductivity type is provided on a front face of a semiconductor substrate. A second semiconductor region 5 is provided on an upper surface of the first semiconductor layer 2 in the active region 30. A second parallel pn structure composed of a third column 3b of the first conductivity type and a fourth column 4b of a second conductivity type is provided in the first semiconductor layer 2 in the termination structure part 40. A surface of the fourth column 4b is provided at a side closer to the semiconductor substrate side than a lower surface of the second semiconductor region 5. A first semiconductor region 17 of the second conductivity type is provided between a surface of the first semiconductor layer 2 and the second parallel pn structure. The first semiconductor region 17 has a first region 17a at the active region 30 side, and a second region 17b provided outside of the first region 17a in a separated manner. A plurality of fourth columns 4b are in contact with the first region 17a.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a superjunction semiconductor device. [Background technology]

[0002] In a typical n-type channel vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor: Insulated Gate Field Effect Transistor), of the multiple semiconductor layers formed in the semiconductor substrate, the n-type conduction layer (drift layer) is the semiconductor layer with the highest resistance. The electrical resistance of this n-type drift layer has a large effect on the on-resistance of the entire vertical MOSFET. The on-resistance of the entire vertical MOSFET can be reduced by reducing the thickness of the n-type drift layer and shortening the current path.

[0003] However, the vertical MOSFET also has a function of maintaining a breakdown voltage by spreading the depletion layer to the high-resistance n-type drift layer in the off state. Therefore, if the n-type drift layer is thinned to reduce the on-resistance, the distance over which the depletion layer spreads in the off state is shortened, so that the breakdown field strength is easily reached at a low applied voltage, and the breakdown voltage is reduced. On the other hand, in order to increase the breakdown voltage of the vertical MOSFET, it is necessary to increase the thickness of the n-type drift layer, which increases the on-resistance. Such a relationship between the on-resistance and the breakdown voltage is called a trade-off relationship, and it is generally difficult to improve both of them in the trade-off relationship. It is known that this trade-off relationship between the on-resistance and the breakdown voltage also holds true in semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors), bipolar transistors, and diodes.

[0004] A super junction (SJ) structure is known as a semiconductor device structure that solves the above-mentioned problems. For example, a MOSFET having a super junction structure (hereinafter, SJ-MOSFET) is known. Fig. 19 is a cross-sectional view showing the structure of a conventional SJ-MOSFET.

[0005] As shown in FIG. 19, the SJ-MOSFET 150 is a high-impurity n + The wafer is made of an n-type semiconductor substrate 101 on which an n-type drift layer 102 is grown. + A p-type column region 104 reaching the p-type semiconductor substrate 101 is provided.

[0006] The n-type drift layer 102 has a parallel structure (hereinafter referred to as a parallel pn region) in which p-type regions (p-type column regions 104) and n-type regions (portions of the n-type drift layer 102 sandwiched between adjacent p-type column regions 104, hereinafter referred to as n-type column regions 103) that extend in a direction perpendicular to the substrate main surface and have a narrow width in a plane parallel to the substrate main surface are alternately and repeatedly arranged in a plane parallel to the substrate main surface. The p-type column regions 104 and n-type column regions 103 that constitute the parallel pn region are regions with a high impurity concentration corresponding to the n-type drift layer 102. In the parallel pn region, by making the impurity concentrations contained in the p-type column regions 104 and n-type column regions 103 approximately equal, a pseudo non-doped layer can be created in the off state to achieve high breakdown voltage.

[0007] A p-type base region 105 is provided on the parallel pn region on the side of the active region 130 of the SJ-MOSFET 150 where an element is formed and a current flows when the element is in an on-state. + A p-type source region 106 is provided. A gate insulating film 107 is provided over the surfaces of the p-type base region 105 and the n-type column region 103. A gate electrode 108 is provided on the surface of the gate insulating film 107, and an insulating film 113 is provided so as to cover the gate electrode 108. + A source electrode 110 is provided on the n-type source region 106. + A drain electrode 114 is provided on the back surface of the semiconductor substrate 101 .

[0008] In the edge termination region 140 of the SJ-MOSFET 150 that surrounds the periphery of the active region 130, a parallel pn region and an insulating film 113 are provided in the n-type drift layer 102 in the same manner as in the active region 130, and the n + A drain electrode 114 is provided on the back surface of the semiconductor substrate 101 .

[0009] In addition, in a power semiconductor device, the edge termination region 140 must also maintain a breakdown voltage, similar to the active region 130. In order to obtain a high breakdown voltage in the edge termination region 140, known techniques include structures in which a field plate, a RESURF, a guard ring, etc. are formed. FIG. 19 shows an SJ-MOSFET 150 having a RESURF structure. In the SJ-MOSFET 150, when maintaining a breakdown voltage, the RESURF region 117 is partially or completely depleted to alleviate the electric field concentration in the edge termination region 140. The RESURF region 117 may also be connected to a parallel pn region. In this case, a depletion layer extends from the junction of the parallel pn region connected to the RESURF region 117, and the drift layer is completely depleted at a low voltage. As the voltage increases, the parallel pn region performs a guard ring effect, and the depletion layer further extends from the adjacent parallel pn regions, and the depletion layers are bonded to each other to form a depletion layer at the time of complete depletion, thereby ensuring a high breakdown voltage.

[0010] For example, in an SJ-MOSFET having an n-type pillar layer 2 and a p-type pillar layer 3 in the element portion and an n-type pillar layer 10 and a p-type pillar layer 11 in the element termination portion, a high resistance n - The n-type layer 12 is provided, and the n-type pillar layer 2 of the element portion and the high resistance n - A semiconductor device is known that has an outermost p-type pillar layer 14 between a gate layer 12, a p-type base layer 4 at the boundary between the element section and the element termination section, and a RESURF layer 13 adjacent to the p-type base layer 4 (for example, see Patent Document 1 below).

[0011] In addition, in an SJ-MOSFET in which the repetition pitch P2 of the second parallel pn layer 15 in the element peripheral portion 3 is narrower than the repetition pitch P1 of the first parallel pn layer 12 in the center of the element active portion 1, a p-base region 5 is provided across a plurality of first p-type regions 14 and second p-type regions 17 at the boundary between the first parallel pn layer 12 and the second parallel pn layer 15, and a n-type base region 5 surrounding the first parallel pn layer 12 is provided between the second parallel pn layer 15 and the first main surface. - A surface region 19 is provided, and n - A semiconductor device in which two or more p-type guard ring regions 20 are provided separately from each other on the first main surface side of surface region 19 is known (see, for example, Patent Document 2 below).

[0012] Also, a semiconductor device is known in which the p-type pillar regions 6 in the peripheral region 120 are in contact with the p-type connection regions 17, the p-type connection regions 17 being in ohmic contact with the source electrode 10 via the body region 5', and an n-type depletable semiconductor region 18 is provided between the p-type connection region 17 and the first main surface 101, the n-type depletable semiconductor region 18 having a doping concentration higher than that of the lightly doped semiconductor region 2 between the end of the pn column and a field stopper region 8 provided on the outermost periphery (see, for example, Patent Document 3 below). [Prior art documents] [Patent documents]

[0013] [Patent Document 1] JP 2006-5275 A [Patent Document 2] JP 2013-149761 A [Patent Document 3] U.S. Patent No. 9,281,392 Summary of the Invention [Problem to be solved by the invention]

[0014] In the parallel pn region, when the amount of impurities in the n-type column region 103 is approximately equal to the amount of impurities in the p-type column region 104 (charge balance is "1"), the breakdown voltage of the SJ-MOSFET 150 reaches a maximum value. However, the amount of impurities in the parallel pn region is prone to variation due to manufacturing variations in semiconductor devices. This can lead to an imbalance in the charge balance, making it easy for a decrease in breakdown voltage to occur. Furthermore, variations in the amount of impurities and the diffusion depth of the impurities in the resurf region 117 can also cause a further decrease in breakdown voltage. This can lead to the problem that individual elements with low breakdown voltages are likely to occur.

[0015] SUMMARY OF THE PRESENT EMBODIMENT In order to solve the above-mentioned problems associated with the prior art, an object of the present invention is to provide a super-junction semiconductor device capable of suppressing a decrease in breakdown voltage due to manufacturing variations. [Means for solving the problem]

[0016] In order to solve the above-mentioned problems and achieve the object of the present invention, a super junction semiconductor device according to the present invention has the following features: A super junction semiconductor device having an active region through which a current flows, and a termination structure disposed outside the active region and having a breakdown voltage structure surrounding the periphery of the active region. The super junction semiconductor device has a semiconductor substrate of a first conductivity type, a first semiconductor layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate and disposed on a front surface of the semiconductor substrate, a first parallel pn structure provided in the active region, in which first columns of the first conductivity type and second columns of the second conductivity type are repeatedly and alternately arranged in a plane parallel to the front surface and disposed on an upper surface of the first semiconductor layer, and a second parallel pn structure provided in the termination structure, in which third columns of the first conductivity type and fourth columns of the second conductivity type are repeatedly and alternately arranged in a plane parallel to the front surface and disposed within the first semiconductor layer; a first semiconductor region of a second conductivity type provided between a surface and the second parallel pn structure and having a first region and a second region provided outside the first region from the side of the active region, a second semiconductor region of a second conductivity type provided on a surface of the second column of the second conductivity type of the first parallel pn structure of the active region, a third semiconductor region of a first conductivity type selectively provided in a surface layer of the second semiconductor region on the opposite side to the semiconductor substrate side, a gate insulating film in contact with the second semiconductor region, and a gate electrode provided on a surface of the gate insulating film on the opposite side to the surface in contact with the second semiconductor region. A surface of the fourth column of the second conductivity type is provided closer to the semiconductor substrate than a lower surface of the second semiconductor region, and a lower surface of the first region of the first semiconductor region is in contact with a plurality of the fourth columns of the second conductivity type. The lower surface of the second region of the first semiconductor region is farther from the semiconductor substrate the further it is from the active region.

[0017] In order to solve the above-mentioned problems and achieve the object of the present invention, a super junction semiconductor device according to the present invention has the following features: A super junction semiconductor device having an active region through which a current flows, and a termination structure disposed outside the active region and having a breakdown voltage structure surrounding the periphery of the active region. The super junction semiconductor device has a semiconductor substrate of a first conductivity type, a first semiconductor layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate and disposed on a front surface of the semiconductor substrate, a first parallel pn structure provided in the active region, in which first columns of the first conductivity type and second columns of the second conductivity type are repeatedly and alternately arranged in a plane parallel to the front surface and disposed on an upper surface of the first semiconductor layer, and a second parallel pn structure provided in the termination structure, in which third columns of the first conductivity type and fourth columns of the second conductivity type are repeatedly and alternately arranged in a plane parallel to the front surface and disposed within the first semiconductor layer; The semiconductor device includes a first semiconductor region of a second conductivity type provided between a surface and the second parallel pn structure, the first region being located on the active region side and a second region being located outside the first region, a second semiconductor region of a second conductivity type provided on a surface of the second column of the second conductivity type of the first parallel pn structure of the active region, a third semiconductor region of a first conductivity type selectively provided in a surface layer of the second semiconductor region on the opposite side to the semiconductor substrate side, a gate insulating film in contact with the second semiconductor region, and a gate electrode provided on a surface of the gate insulating film on the opposite side to the surface in contact with the second semiconductor region. The surface of the fourth column of the second conductivity type is provided closer to the semiconductor substrate than the lower surface of the second semiconductor region, and the lower surface of the first region of the first semiconductor region is in contact with a plurality of the fourth columns of the second conductivity type. The second region of the first semiconductor region has a higher impurity concentration as it approaches the active region.

[0018] In addition, the super junction semiconductor device of the present invention is characterized in that, in the above-mentioned invention, the underside of the second region of the first semiconductor region has an end portion on the active region side equal to the depth of the underside of the first region of the first semiconductor region.

[0019] In addition, the super junction semiconductor device of the present invention is characterized in that, in the above-mentioned invention, in the second region of the first semiconductor region, an outer region away from the active region is not in contact with the fourth column of the second conductivity type.

[0020] In addition, the super junction semiconductor device of the present invention, in the above-mentioned invention, is characterized in that the first region and the second region of the first semiconductor region have a ratio of the width of the first region to the width of the second region of 3:7 to 5:5.

[0021] In addition, in the super junction semiconductor device according to the present invention, the first region and the second region of the first semiconductor region have an annular planar shape.

[0022] In addition, the super junction semiconductor device of the present invention is characterized in that, in the above-mentioned invention, the width of the first column and the width of the second column of the first parallel pn structure in the active region are wider than the width of the third column and the width of the fourth column of the second parallel pn structure in the termination structure portion.

[0023] In addition, the super junction semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, a fourth semiconductor region of the first conductivity type is provided on a surface of the first semiconductor region opposite to the semiconductor substrate.

[0024] In addition, in the super junction semiconductor device according to the present invention, the fourth semiconductor region is provided on the entire surface of the second region opposite to the semiconductor substrate.

[0025] In the super junction semiconductor device according to the present invention, in the above-mentioned invention, the second region of the first semiconductor region has a higher impurity concentration as it is closer to the active region.

[0026] In addition, in the super junction semiconductor device according to the present invention, the second region of the first semiconductor region is in contact with a plurality of the fourth columns.

[0027] In addition, the super junction semiconductor device of the present invention, in the above-mentioned invention, is characterized in that it has a fourth column between the first region and the second region of the first semiconductor region, the fourth column not contacting the first region or the second region.

[0028] According to the above-mentioned invention, the RESURF region (first semiconductor region of the second conductivity type) is divided into two or more. As a result, the RESURF region closer to the stopper electrode acts as a buffer, and a steep drop in withstand voltage can be alleviated. This makes it possible to suppress a drop in withstand voltage due to manufacturing variations. Furthermore, when charge accumulates on the protective film, the movement of the equipotential lines stops at the point where the RESURF region is divided, and the effect of the charge is localized. This makes it possible to suppress fluctuations in withstand voltage when charge accumulates on the protective film of the semiconductor device.

[0029] In addition, because the movement of the equipotential lines stops at the points where the RESURF region is divided, by dividing the RESURF region into four, the effect of the electric charge can be localized more than in a form in which the RESURF region is divided into two, and the variation in the breakdown voltage when the electric charge accumulates on the protective film of the semiconductor device can be further suppressed. Also, by forming the RESURF region in a shape that becomes narrower and has a lower impurity concentration toward the outside of the element, the variation in the breakdown voltage when the electric charge accumulates on the protective film of the semiconductor device can be further suppressed. Effect of the Invention

[0030] The super-junction semiconductor device according to the present invention has an effect of suppressing a decrease in breakdown voltage due to manufacturing variations. [Brief description of the drawings]

[0031] [Figure 1] 1 is a cross-sectional view showing a structure of an SJ-MOSFET according to a first embodiment. [Diagram 2] 2 is a plan view of the A-A' portion of FIG. 1 showing the structure of the SJ-MOSFET according to the first embodiment. [Diagram 3]2 is a plan view of the BB' portion of FIG. 1 showing the structure of the SJ-MOSFET according to the first embodiment. [Figure 4] 2 is another plan view of the BB' portion of FIG. 1 showing the structure of the SJ-MOSFET according to the first embodiment. [Diagram 5] FIG. 11 is a cross-sectional view showing a structure of an SJ-MOSFET according to a second embodiment. [Figure 6] FIG. 11 is a cross-sectional view showing the internal state of the potential distribution of an SJ-MOSFET of a comparative example. [Figure 7A] 4 is a cross-sectional view showing an internal state of a potential distribution of the SJ-MOSFET according to the first embodiment. FIG. [Figure 7B] FIG. 11 is a cross-sectional view showing an internal state of a potential distribution of an SJ-MOSFET according to a second embodiment. [Figure 8] 1 is a cross-sectional view (part 1) illustrating a state during manufacturing of the SJ-MOSFET according to the first and second embodiments. FIG. [Figure 9] FIG. 2 is a cross-sectional view (part 2) illustrating a state during the manufacture of the SJ-MOSFET according to the first and second embodiments. [Figure 10] FIG. 3 is a cross-sectional view (part 3) showing a state during the manufacture of the SJ-MOSFET according to the first and second embodiments. [Figure 11] FIG. 4 is a cross-sectional view showing a state during manufacturing of the SJ-MOSFET according to the first and second embodiments (part 4). [Figure 12] FIG. 5 is a cross-sectional view showing a state during the manufacture of the SJ-MOSFET according to the first and second embodiments (part 5). [Figure 13] FIG. 6 is a cross-sectional view showing a state during the manufacture of the SJ-MOSFET according to the first and second embodiments (part 6). [Figure 14] FIG. 11 is a cross-sectional view showing a structure of an SJ-MOSFET according to a third embodiment. [Figure 15] FIG. 11 is a cross-sectional view showing a structure of an SJ-MOSFET according to a fourth embodiment. [Figure 16] FIG. 11 is a cross-sectional view showing a detailed structure of a RESURF layer of an SJ-MOSFET according to a fourth embodiment. [Figure 17]1 is a graph showing the relationship between charge balance and breakdown voltage in the SJ-MOSFETs according to the first, third and fourth embodiments and the SJ-MOSFET of the comparative example. [Figure 18] 1 is a graph showing the relationship between the surface charge and the breakdown voltage in the SJ-MOSFETs according to the first, third and fourth embodiments and the SJ-MOSFET of the comparative example. [Figure 19] FIG. 1 is a cross-sectional view showing the structure of a conventional SJ-MOSFET. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] A preferred embodiment of the superjunction semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, in layers and regions prefixed with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - appended to n or p mean that the impurity concentration is higher and lower than that of layers and regions not prefixed with them, respectively. When the notations of n and p including + and - are the same, it indicates that the concentrations are close, but not necessarily the same. In the following description of the embodiments and the accompanying drawings, the same symbols are assigned to similar configurations, and duplicate explanations will be omitted.

[0033] (Embodiment 1) The super-junction semiconductor device according to the present invention will be described by taking an SJ-MOSFET as an example. FIG. 1 is a cross-sectional view showing the structure of an SJ-MOSFET according to a first embodiment. FIG. 2 is a plan view of the A-A' portion of FIG. 1 showing the structure of the SJ-MOSFET according to the first embodiment. FIG. 3 is a plan view of the B-B' portion of FIG. 1 showing the structure of the SJ-MOSFET according to the first embodiment. FIG. 4 is another plan view of the B-B' portion of FIG. 1 showing the structure of the SJ-MOSFET according to the first embodiment. FIG. 1 is a cross-sectional view of the a-a' portion of FIGS. 2 to 4.

[0034] The SJ-MOSFET 50 shown in FIG. 1 is an SJ-MOSFET 50 having a MOS (Metal Oxide Semiconductor) gate on the front surface (the surface on the side of the p-type base region 5 described later) of a semiconductor substrate (silicon substrate: semiconductor chip) made of silicon (Si). This SJ-MOSFET 50 has an active region 30 and an edge termination region 40 surrounding the periphery of the active region 30. The active region 30 is a region through which a current flows in an on-state. The edge termination region 40 is a region that relaxes the electric field on the front surface side of the substrate of the drift region and maintains a withstand voltage. In the active region 30 in FIG. 1, only one unit cell (functional unit of an element) is shown, and other unit cells adjacent to it are not shown. The boundary between the active region 30 and the edge termination region 40 is the end of the p-type base region 5.

[0035] n + The n-type semiconductor substrate (first conductivity type semiconductor substrate) 1 is, for example, a silicon single crystal substrate doped with phosphorus (P). The n-type drift layer (first conductivity type first semiconductor layer) 2 is + The low-concentration n-type drift layer is doped with, for example, phosphorus at a lower impurity concentration than the n-type semiconductor substrate. + The n-type semiconductor substrate 1 and the n-type drift layer 2 together constitute a semiconductor body. A MOS gate structure (device structure) is formed on the front surface side of the semiconductor body. In addition, a drain electrode 14 is provided on the back surface of the semiconductor body.

[0036] A first parallel pn region is provided on the active region 30 side of the SJ-MOSFET 50. In the first parallel pn region, n-type column regions 3a and p-type column regions 4a are arranged alternately and repeatedly. The p-type column regions 4a extend from the surface of the n-type drift layer 2 to the n-type + The n-type column region 3a and the p-type column region 4a are provided so as not to reach the surface of the n-type semiconductor substrate layer 1. As shown in Fig. 2 to Fig. 4, the planar shape of the n-type column region 3a and the p-type column region 4a in the active region 30 is a stripe shape.

[0037] In addition, a p-type base region (a second semiconductor region of a second conductivity type) 5 is selectively provided in contact with the p-type column region 4a in the surface layer of the n-type drift layer 2. + A p-type source region (third semiconductor region of the first conductivity type) 6 is selectively provided. + A gate electrode 8 is provided on the surface of a portion sandwiched between the n-type source region 6 and the n-type column region 3a, with a gate insulating film 7 interposed therebetween. The gate electrode 8 may be provided on the surface of the n-type column region 3a, with the gate insulating film 7 interposed therebetween.

[0038] An insulating film 13 is provided on the front surface side of the semiconductor substrate so as to cover the gate electrode 8. The source electrode 10 is connected to an n-type + a p-type source region 6 and a p-type base region 5; + The p-type source region 6 and the p-type base region 5 are electrically connected to the p-type source region 6 and the p-type base region 5 .

[0039] The source electrode 10 is electrically insulated from the gate electrode 8 by an insulating film 13. On the source electrode 10, a protective film (not shown) such as a passivation film made of polyimide is selectively provided.

[0040] A field plate electrode 15 is disposed outside (on the edge termination region 40 side) of the source electrode 10 and spaced apart from the source electrode 10. The field plate electrode 15 is provided in a substantially annular shape along the boundary between the active region 30 and the edge termination region 40. The field plate electrode 15 may also serve as a gate wiring electrically connected to the gate electrode 8.

[0041] A second parallel pn region is also provided on the edge termination region 40 side of the SJ-MOSFET 50. As shown in Figure 3, the planar shape of the n-type column region 3b and the p-type column region 4b in the edge termination region 40 may be a stripe shape, and as shown in Figure 4, the planar shape of the n-type column region 3b and the p-type column region 4b in the edge termination region 40 may be a rectangular shape.

[0042] 1 to 4, the widths of n-type column regions 3a and p-type column regions 4a in active region 30 are wider than the widths of n-type column regions 3b and p-type column regions 4b in edge termination region 40, respectively. This allows the impurity concentration of the second parallel pn structure in edge termination region 40 to be lower than the impurity concentration of the first parallel pn region in active region 30. This allows the withstand voltage of edge termination region 40 to be higher than the withstand voltage of active region 30.

[0043] An n-type drift layer 2 is provided outside the second parallel pn region so as to surround the second parallel pn region, and a n-type drift layer 3 is provided on the surface of the n-type drift layer 2 so as to function as a channel stopper. + A resurf region (a first semiconductor region of a second conductivity type) 17 is provided on the surface of the second parallel pn region. An insulating film 13 is provided on the surfaces of the resurf region 17 and the n-type drift layer 2. In addition, + A stopper electrode 16 is provided on the surface of the mold region.

[0044] 1 and 2, in the first embodiment, the resurf region 17 extends in the direction of the stopper electrode 16 so as to overlap the outer end of the field plate electrode 15 in a plan view, and is divided into two or more regions. In the example of FIG. 1, the resurf region 17 is divided into two regions: a first resurf region 17a close to the active region 30, and a second resurf region 17b away from the active region 30.

[0045] As shown in Fig. 2, the first resurf region 17a and the second resurf region 17b are provided in a circular shape in plan view. The first resurf region 17a and the second resurf region 17b are electrically connected to the p-type column region 4a of the second parallel pn region. Furthermore, as shown in Fig. 1, a p-type column region 4b that is not connected to the first resurf region 17a and the second resurf region 17b may be disposed between the first resurf region 17a and the second resurf region 17b.

[0046] An n-type region 18 is provided between the first resurf region 17a and the second resurf region 17b and the insulating film 13 thereover. An end 25 of the first resurf region 17a on the active region 30 side may be in contact with the insulating film 13. The end 25 of the first resurf region 17a may be electrically connected to the field plate electrode 15. The end 25 of the first resurf region 17a may be provided in a ring shape.

[0047] As described above, when the breakdown voltage is maintained, the resurf region 17 is partially or completely depleted, thereby alleviating the electric field concentration in the edge termination region 40. By dividing the resurf region 17, the potential in the resurf region 17 can be shared among the regions, and the electric field strength increases partially. Therefore, even if the charge balance is such that the p-type impurities are more abundant in the second parallel pn region due to manufacturing variations, or the concentration of the p-type impurities in the resurf region 17 increases, the resurf region 17b on the side closer to the stopper electrode 16 acts as a buffer, and a steep decrease in the breakdown voltage can be alleviated. Therefore, it is possible to suppress the decrease in the breakdown voltage due to manufacturing variations.

[0048] (Embodiment 2) FIG. 5 is a cross-sectional view showing the structure of an SJ-MOSFET according to the second embodiment. A-A' portion of FIG. 5 is the same as the plan view of FIG. 2 showing the structure of the SJ-MOSFET according to the first embodiment. A-B' portion of FIG. 5 showing the structure of the SJ-MOSFET according to the second embodiment is the same as the plan view of FIG. 3 showing the structure of the SJ-MOSFET according to the first embodiment. Another plan view of B-B' portion of FIG. 5 showing the structure of the SJ-MOSFET according to the second embodiment is the same as the plan view of FIG. 4.

[0049] The second embodiment is different in that the p-type column region 4b that is not connected to the first resurf region 17a and the second resurf region 17b is not disposed between the first resurf region 17a and the second resurf region 17b.

[0050] In the second embodiment, the same effect as in the first embodiment can be obtained even if a p-type column region 4b that is not connected to the first resurf region 17a and the second resurf region 17b is not disposed between the first resurf region 17a and the second resurf region 17b.

[0051] Furthermore, one SJ-MOSFET 50 may have a portion in which p-type column region 4b that is not connected to first resurf region 17a and second resurf region 17b is arranged between first resurf region 17a and second resurf region 17b as shown in FIG. 1, and a portion in which p-type column region 4b that is not connected to first resurf region 17a and second resurf region 17b is not arranged between first resurf region 17a and second resurf region 17b as shown in FIG. 5.

[0052] However, when they are mixed, the first resurf region 17a and the second resurf region 17b are separated from each other. Furthermore, the width w1 of the first resurf region 17a and the width w2 of the second resurf region 17b away from the active region 30 satisfy the relationship described below.

[0053] 1 is used in a state where it is sealed with a sealing resin such as a mold resin. If the adhesion between the sealing resin and the SJ-MOSFET 50 is insufficient, ionic substances such as moisture may enter between the sealing resin and the SJ-MOSFET 50. In this case, charges are accumulated on the protective film of the SJ-MOSFET 50.

[0054] FIG. 6 is a cross-sectional view showing the internal state of the potential distribution of the SJ-MOSFET of the comparative example. The SJ-MOSFET of the comparative example is different from the SJ-MOSFET of the first embodiment in that the resurf region 117 is not divided into the first resurf region 17a and the second resurf region 17b. As shown in FIG. 6, if the resurf region 117 is not divided, the equipotential lines 60 are arranged almost evenly on the resurf region 117. In this state, if charges are accumulated on the surface protective film 70, the equipotential lines 60 move inward (toward the active region 30) or outward (toward the stopper electrode 16). For example, if a positive charge is accumulated, the equipotential lines 60 move inward, and if a negative charge is accumulated, the equipotential lines 60 move outward. In this case, a portion where the equipotential lines 60 are dense is generated at the end of the resurf region 117, causing a fluctuation in the breakdown voltage.

[0055] FIG. 7A is a cross-sectional view showing the internal state of the potential distribution of the SJ-MOSFET according to the first embodiment. As shown in FIG. 7A, when the resurf region 17 is divided, the interval between the equipotential lines 60 becomes wider at the divided points. When charges are accumulated on the surface protective film 70 in this state, even if the equipotential lines 60 move inward or outward, the movement of the equipotential lines 60 stops at the divided points. This makes it possible to localize the influence of the charges. Therefore, it is possible to suppress the breakdown voltage fluctuation when charges are accumulated on the protective film of the semiconductor device. In addition, since the movement of the equipotential lines 60 stops at the divided points, the more divisions of the resurf region 17, the more the breakdown voltage fluctuation when charges are accumulated can be suppressed.

[0056] Fig. 7B is a diagram showing an internal state of the potential distribution of the SJ-MOSFET according to the embodiment 2. Fig. 7B can provide the same effect as Fig. 7A.

[0057] 1 and 5, the ratio of the width w1 of the first resurf region 17a close to the active region 30 to the width w2 of the second resurf region 17b farther from the active region 30 is preferably in the range of 3:7 to 5:5. Here, the width w1 of the first resurf region 17a refers to the length from the inside to the outside of the first resurf region 17a. The same is true for the width w2 of the second resurf region 17b. In other words, the range from when the width w1 of the first resurf region 17a is 3 and the width w2 of the second resurf region 17b is 7 to when the width w1 of the first resurf region 17a is 5 and the width w2 of the second resurf region 17b is 5 is preferable.

[0058] In order to maintain the breakdown voltage, it is desirable that the resurf region is completely depleted, but the breakdown voltage can also be maintained by partially depleting the resurf region. When the first resurf region 17a on the active region 30 side is partially depleted as shown in FIG. 7A and FIG. 7B, the intervals of the equipotential lines 60 tend to be wider overall than when the resurf region 117 is completely depleted as shown in FIG. 6. Also, the intervals of the equipotential lines 60 become narrower (more dense) in the region sandwiched between the first resurf region 17a and the second resurf region 17b. This widens the intervals of the equipotential lines 60 in the second resurf region 17b, and the electric field is relaxed. By relaxing the electric field on the side close to the stopper electrode 16, it is possible to suppress a decrease in the breakdown voltage due to surface charges.

[0059] Furthermore, when the resurf region 17 is divided into two, in order to reduce a decrease in breakdown voltage due to surface charges, it is preferable that the width w1 of the first resurf region 17a close to the active region 30 is shorter than the width w2 of the second resurf region 17b away from the active region 30. Moreover, when the resurf region 17 is divided into three or more regions, it is preferable that the width of the resurf region closest to the stopper electrode 16 is made the longest in order to reduce a decrease in breakdown voltage due to surface charges.

[0060] Furthermore, by providing n-type region 18 between resurf region 17 and insulating film 13, it is possible to further stabilize the fluctuation in the breakdown voltage of edge termination region 40 due to surface charge. Furthermore, n-type region 18 can reduce the intrusion of holes (positive holes) into insulating film 13.

[0061] (Method of Manufacturing Super-Junction Semiconductor Device According to First and Second Embodiments) Next, a method for manufacturing the super-junction semiconductor device according to the first and second embodiments will be described. FIGS. 8 to 13 are cross-sectional views showing a state during the manufacturing process of the SJ-MOSFET 50 according to the first and second embodiments. First, n + The n-type drain layer + A type semiconductor substrate 1 is prepared. Next, + On the front surface of the n-type semiconductor substrate 1, + Then, an n-type layer 2a having a lower impurity concentration than that of the n-type semiconductor substrate 1 is epitaxially grown. The state up to this point is shown in FIG.

[0062] The impurity concentration of the n-type layer 2a is, for example, 1.0×10 14 / cm 3 Above 1.0×10 17 / cm 3 The epitaxial growth may be performed by doping with n-type impurities as follows:

[0063] Next, an ion implantation mask 20a having a predetermined opening width is formed on the surface of the n-type layer 2a by photolithography, for example, using photoresist. At this time, the opening width w11 of the active region and the pitch P1 of the openings are made wider than the opening width w12 of the edge termination region and the pitch P2 of the openings. Using this ion implantation mask 20a as a mask, ion implantation 21 of p-type impurities, for example boron (B), is performed to form p-type regions 19 in the surface layer of the n-type layer 2a. The state up to this point is shown in FIG. 9. Next, the ion implantation mask 20a is removed.

[0064] Next, an n-type layer 2b having the same impurity concentration as the n-type layer 2a is epitaxially grown on the front surface side of the n-type layer 2a. Next, an ion implantation mask 20a having a predetermined opening width is formed on the surface of the n-type layer 2b by photolithography, for example, using photoresist. At this time, the opening width w11 of the active region and the pitch P1 of the openings are made wider than the opening width w12 of the edge termination region and the pitch P2 of the openings. Using this ion implantation mask 20a as a mask, ion implantation 21 of p-type impurities, for example boron (B), is performed to form a p-type region 19 in the surface layer of the n-type layer 2b. Next, the ion implantation mask 20a is removed.

[0065] Next, an n-type layer 2c having the same impurity concentration as the n-type layer 2b is epitaxially grown on the front surface side of the n-type layer 2b. Next, an ion implantation mask 20a having a predetermined opening width is formed on the surface of the n-type layer 2c by photolithography, for example, using photoresist. At this time, the opening width w11 of the active region and the pitch P1 of the openings are made wider than the opening width w12 of the edge termination region and the pitch P2 of the openings. Using this ion implantation mask 20a as a mask, ion implantation 21 of p-type impurities, for example boron (B), is performed to form a p-type region 19 in the surface layer of the n-type layer 2c. Next, the ion implantation mask 20a is removed.

[0066] Next, an n-type layer 2d having the same impurity concentration as the n-type layer 2c is epitaxially grown on the front surface side of the n-type layer 2c. Next, an ion implantation mask 20a having a predetermined opening width is formed on the surface of the n-type layer 2d by photolithography, for example, using photoresist. At this time, the opening width w11 of the active region and the pitch P1 of the openings are made wider than the opening width w12 of the edge termination region and the pitch P2 of the openings. Using this ion implantation mask 20a as a mask, ion implantation 21 of p-type impurities, for example boron (B), is performed to form a p-type region 19 in the surface layer of the n-type layer 2d. As a result, the first and second parallel pn regions in the lower part are formed, which are composed of the n-type layers 2a to 2d and the p-type region 19. The state up to this point is shown in FIG. 10.

[0067] In the example of FIG. 10, ion implantation and epitaxial growth are repeated four times, but the present invention is not limited to this, and the number of times ion implantation and epitaxial growth can be appropriately changed depending on the target characteristics such as breakdown voltage.

[0068] Next, the ion implantation mask 20a is removed. Next, an n-type layer 2e having the same impurity concentration as the n-type layer 2d is epitaxially grown on the front surface side of the n-type layer 2d. Next, an ion implantation mask 20b having a predetermined opening width is formed on the surface of the n-type layer 2e by photolithography technology, for example, with photoresist. At this time, the opening width w13 of the edge termination region and the pitch P3 of the openings are made narrower than the opening width w12 of the edge termination region and the pitch P2 of the openings of the mask formed on the n-type layers 2a to 2d. In addition, the photoresist width w15 at the portion where the resurf region 17 is divided into the first resurf region 17a and the second resurf region 17b is made wider than the photoresist width w14 (=P3-w13) of the edge termination region. Using this ion implantation mask 20b as a mask, ion implantation 21 of p-type impurities, for example boron (B), is performed to form p-type region 19 in the surface layer of n-type layer 2e. As a result, upper first and second parallel pn regions consisting of n-type layer 2e and p-type region 19 are formed in active region 30, and resurf region 17 is formed in edge termination region 40. The state up to this point is shown in Figure 11. Next, ion implantation mask 20b is removed.

[0069] Next, an n-type layer 2f having the same impurity concentration as that of the n-type layer 2e is epitaxially grown on the front surface side of the n-type layer 2e. The state up to this point is shown in FIG.

[0070] Next, a heat treatment (annealing) is performed to activate the p-type regions 19. This heat treatment diffuses the implanted impurities, and the diffused impurities connect vertically to form the p-type column regions 4a, 4b. In addition, since the p-type regions 19 formed in the n-type layer 2e are spaced apart from each other narrowly, the diffused impurities connect horizontally to form the RESURF region 17.

[0071] Here, in the edge termination region 40, the mask opening width is narrower than in the active region 30, so the amount of impurities implanted in one location is smaller and the amount of diffusion is smaller. Therefore, the impurities do not reach the surface of the n-type region 2f during heat treatment. Therefore, the n-type region 18 is formed on the upper part of the resurf region 17. On the other hand, in the active region 30, the amount of impurities is large and the amount of diffusion is large, so the impurities reach the surface of the n-type region 2f and the p-type column region 4a is exposed on the surface. Depending on the amount of impurities, the impurities may not reach the surface of the n-type region 2f even in the active region 30, but when the p-type base region 5 is formed, ion implantation is performed, so in the active region 30, the p-type column region 4a and the p-type base region 5 are connected and the p-type region is exposed on the surface. The state up to this point is shown in FIG. 13.

[0072] Next, a mask having desired openings is formed, for example, from a resist on the surfaces of the n-type column region 3a and the p-type column region 4a on the active region 30 side by photolithography. Then, using this resist mask as a mask, p-type impurities are ion-implanted by ion implantation. As a result, a p-type base region 5 is formed in the entire surface region of the p-type column region 4a and in a part of the surface region of the n-type column region 3a. Next, the mask used during the ion implantation to form the p-type base region 5 is removed.

[0073] Next, a mask having desired openings is formed on the surface of the p-type base region 5 by photolithography, for example, using a resist. Then, using this resist mask as a mask, n-type impurities are ion-implanted by ion implantation. As a result, n-type impurities are implanted into a part of the surface region of the p-type base region 5. + A type source region 6 is then formed. + The mask used during ion implantation to form the source region 6 is removed.

[0074] Next, the p-type base region 5 and the n + A heat treatment (annealing) is performed to activate the p-type source region 6. Also, the p-type base region 5 and the n-type + The order in which the type source regions 6 are formed can be changed in various ways.

[0075] Next, the front surface side of the semiconductor substrate is thermally oxidized to form a gate insulating film 7. Next, a polycrystalline silicon layer doped with, for example, phosphorus is formed as a gate electrode 8 on the gate insulating film 7. Next, the polycrystalline silicon layer is patterned and selectively removed to form an n-type base region 5. + A polycrystalline silicon layer is left on the portion between the n-type source region 6 and the n-type column region 3a. At this time, the polycrystalline silicon layer may be left on the n-type column region 3a.

[0076] Next, for example, phosphorus glass (PSG: Phospho Silicate Glass) is formed as the insulating film 13 so as to cover the gate electrode 8. Next, the insulating film 13 and the gate insulating film 7 are patterned and selectively removed. For example, + The insulating film 13 on the n-type source region 6 and the gate insulating film 7 are removed to form a contact hole. + This exposes the source region 6. Next, a heat treatment (reflow) is performed to flatten the interlayer insulating film 9.

[0077] Next, the source electrode 10, the field plate electrode 15, and the stopper electrode 16 are formed by sputtering, and the source electrode 10, the field plate electrode 15, and the stopper electrode 16 are patterned by photolithography and etching. At this time, the source electrode 10 is buried in the contact hole, and the n + The source region 6 is electrically connected to the source electrode 10. A tungsten plug or the like may be embedded in the contact hole via a barrier metal.

[0078] Next, n + On the surface of the n-type semiconductor substrate 1 (the back surface of the semiconductor body), for example, a nickel film is formed as the drain electrode 14. Then, a heat treatment is performed to form an n + An ohmic junction is formed between the type semiconductor substrate 1 and the drain electrode 14. This completes the SJ-MOSFET 50 shown in FIG.

[0079] As described above, according to the first and second embodiments, the resurf region is divided into two or more. This allows the resurf region closer to the stopper electrode to act as a buffer, and a steep drop in breakdown voltage can be alleviated. This makes it possible to suppress a drop in breakdown voltage due to manufacturing variations. Furthermore, when charges are accumulated on the protective film, the movement of the equipotential lines stops at the point where the resurf region is divided, and the effect of the charges is localized. This makes it possible to suppress a change in breakdown voltage when charges are accumulated on the protective film of the semiconductor device.

[0080] (Embodiment 3) 14 is a cross-sectional view showing the structure of an SJ-MOSFET according to embodiment 3. Embodiment 3 differs from embodiments 1 and 2 in that resurf region 17 is divided into four regions: first resurf region 17a, second resurf region 17b, third resurf region 17c, and fourth resurf region 17d.

[0081] In the third embodiment, the width w1 of the first resurf region 17a, the width w2 of the second resurf region 17b, the width w3 of the third resurf region 17c, and the width w4 of the fourth resurf region 17d preferably have a relationship of w1≦w2≦w3≦w4. In Fig. 14, the end 25 of the first resurf region 17a is a part of the p-type base region 5, and the first resurf region 17a may be connected to the field plate electrode 15a via the p-type base region 5. Similarly, the second resurf region 17b, the third resurf region 17c, and the fourth resurf region 17d may be connected to the field plate electrode 15b, the field plate electrode 15c, and the field plate electrode 15d via the p-type base region 5, respectively.

[0082] Field plate electrode 15a may serve as a gate electrode that is electrically connected to gate electrode 8. However, if field plate electrodes 15b, 15c, and 15d are electrically connected to gate electrode 8, they will have the same potential as gate electrode 8 and will not be able to maintain the withstand voltage. Therefore, field plate electrodes 15b, 15c, and 15d are not electrically connected to gate electrode 8.

[0083] The p-type column region 4c and the p-type column region 4d arranged on both ends of the third RESURF region 17c may or may not be in contact with the third RESURF region 17c.

[0084] As described above, in the third embodiment, the resurf region is divided into four. This makes it possible to alleviate a steep drop in withstand voltage, as in the first and second embodiments, and to suppress a drop in withstand voltage due to manufacturing variations. Furthermore, since the movement of the equipotential lines stops at the point where the resurf region is divided, the third embodiment can localize the effect of charge more than the first and second embodiments in which the resurf region is divided into two. Therefore, the third embodiment can suppress the variation in withstand voltage when charge is accumulated on the protective film of the semiconductor device more than the first and second embodiments.

[0085] (Embodiment 4) 15 is a cross-sectional view showing the structure of an SJ-MOSFET according to the fourth embodiment. The fourth embodiment differs from the third embodiment in the impurity concentration of the fourth resurf region 17d and the length of the outer p-type column region 4b. In the fourth embodiment, similarly to the third embodiment, the width w1 of the first resurf region 17a, the width w2 of the second resurf region 17b, the width w3 of the third resurf region 17c, and the width w4 of the fourth resurf region 17d preferably have a relationship of w1≦w2≦w3≦w4.

[0086] 15, in the fourth embodiment, the second parallel pn structure in the edge termination region 40 is composed of an inner structure S1 on the inside of the element (the active region 30 side) and an outer structure S2 on the outside of the element (the stopper electrode 16 side) which is farther away from the active region 30 than the inner structure S1. The length t2 from the surface of the n-type drift layer of the p-type column region 4b of the outer structure S2 may be shorter than or equal to the length t1 from the surface of the n-type drift layer of the p-type column region 4b of the inner structure S1 (the length t2 may be equal to or shorter than the length t1 (t2≦t1)). Note that the p-type column region 4c and the p-type column region 4d arranged at both ends of the third resurf region 17c may or may not be in contact with the third resurf region 17c.

[0087] Fig. 16 is a cross-sectional view showing a detailed structure of the resurf layer of the SJ-MOSFET according to the fourth embodiment. Fig. 16 is an enlarged view of the fourth resurf region 17d. As shown in Fig. 16, the width of the fourth resurf region 17d becomes narrower toward the outside of the element. Also, the impurity concentration of the fourth resurf region 17d becomes lower toward the outside of the element. The fourth resurf region 17d has a first portion 17d1 inside the element (closer to the active region 30), a second portion 17d2 farther from the active region 30 than the first portion 17d1, and a third portion 17d3 outside the element farther from the active region 30 than the second portion 17d2. The (diffusion) distance from the resurf region center depth t3 of the first portion 17d1 to the surface is d1, the impurity concentration is D1, the (diffusion) distance from the resurf region center depth t3 of the second portion 17d2 to the surface is d2, the impurity concentration is D2, the (diffusion) distance from the resurf region center depth t3 of the third portion 17d3 to the surface is d3, and the impurity concentration is D3. In this case, it is preferable that d1>d2>d3, D1:D2=1.5:1 to 1.2:1, and D2:D3=1:0.75 to 1:0.5.

[0088] In the fourth embodiment, only the fourth resurf region 17d is shaped so that its width becomes narrower and its impurity concentration becomes lower toward the outside of the element, but the first resurf region 17a, the second resurf region 17b, and the third resurf region 17c on the inside may also be shaped in a similar manner.

[0089] As described above, in the fourth embodiment, the fourth RESURF region is shaped so that the width becomes narrower and the impurity concentration becomes lower toward the outside of the element. As a result, the fourth embodiment can suppress the breakdown voltage fluctuation when charge is accumulated on the protective film of the semiconductor device more effectively than the first to third embodiments.

[0090] 17 is a graph showing the relationship between charge balance and breakdown voltage in the SJ-MOSFETs according to the first, third and fourth embodiments and the SJ-MOSFET of the comparative example. The SJ-MOSFET of the comparative example differs from the SJ-MOSFET of the first embodiment in that the resurf region 117 is not divided into the first resurf region 17a and the second resurf region 17b as shown in FIG. 6. In FIG. 17, the vertical axis indicates the breakdown voltage of the SJ-MOSFET in V. The horizontal axis indicates the charge balance, with charge balance "1" indicating a state in which the amount of impurities in the n-type column regions 3a and 3b is substantially equal to the amount of impurities in the p-type column regions 4a and 4b in the first and second parallel pn regions, the side closer to the origin than charge balance "1" (the (n-rich) side) indicating a state in which the amount of n-type impurities is greater, and the side farther from the origin than charge balance "1" (the (p-rich) side) indicating a state in which the amount of p-type impurities is greater.

[0091] 17, in the case of charge balance "1", the SJ-MOSFETs according to the first, third and fourth embodiments have a withstand voltage equivalent to that of the SJ-MOSFET of the comparative example. Moreover, even in a state where the charge balance is unbalanced (a state where the amount of either the n-type or p-type impurity is greater), the SJ-MOSFETs according to the first, third and fourth embodiments have a smaller drop in withstand voltage than the SJ-MOSFET of the comparative example. Moreover, in a state where the charge balance is unbalanced, the SJ-MOSFETs according to the third and fourth embodiments have a smaller drop in withstand voltage than the SJ-MOSFET of the first embodiment.

[0092] The same effect can be obtained in the SJ-MOSFET according to the second embodiment. The same effect can be obtained even if the cross-sectional shape according to the first embodiment shown in Fig. 1 and the cross-sectional shape according to the second embodiment shown in Fig. 5 are mixed in one SJ-MOSFET.

[0093] FIG. 18 is a graph showing the relationship between the surface charge and the breakdown voltage in the SJ-MOSFETs according to the first, third, and fourth embodiments and the comparative SJ-MOSFET. In FIG. 18, the vertical axis shows the breakdown voltage of the SJ-MOSFET in V. The horizontal axis shows the surface charge. On the horizontal axis, the position of 0 indicates a state in which the surface charge is zero, the side closer to the origin than the position of 0 (the negative (-) side) indicates a state in which the negative charge is more abundant, and the side farther from the origin than the position of 0 (the positive (+) side) indicates a state in which the positive charge is more abundant. FIG. 18 also shows the relationship between the surface charge and the breakdown voltage in the case of a charge balance of "1". The surface charge is the charge accumulated in a surface protective film (for example, the surface protective film 70 shown in FIG. 6, FIG. 7A, and FIG. 7B, etc.) arranged on the outermost surface of the superjunction semiconductor device (SJ-MOSFET).

[0094] 18, in a state where the surface charge is zero, the SJ-MOSFETs according to the first, third, and fourth embodiments have a withstand voltage equivalent to that of the SJ-MOSFET of the comparative example. Even in a state where there is more negative charge, the SJ-MOSFET of the first embodiment has a withstand voltage equivalent to that of the SJ-MOSFET of the comparative example. On the other hand, in a state where there is more positive charge, the SJ-MOSFET of the first embodiment experiences less reduction in withstand voltage than the SJ-MOSFET of the comparative example.

[0095] The SJ-MOSFETs according to the third and fourth embodiments have a smaller drop in withstand voltage than the SJ-MOSFET of the comparative example, whether the negative charge is more abundant or the positive charge is more abundant. Also, the SJ-MOSFET according to the third embodiment has the smallest drop in withstand voltage when the positive charge is more abundant. The SJ-MOSFET according to the fourth embodiment has the smallest drop in withstand voltage when the negative charge is more abundant.

[0096] The same effect can be obtained in the SJ-MOSFET according to the second embodiment. The same effect can be obtained even if the cross-sectional shape according to the first embodiment shown in Fig. 1 and the cross-sectional shape according to the second embodiment shown in Fig. 5 are mixed in one SJ-MOSFET.

[0097] In the above, the present invention has been described by taking an example in which a MOS gate structure is formed on the first main surface of a silicon substrate, but the present invention is not limited to this, and various changes can be made to the type of semiconductor (e.g., silicon carbide (SiC)), the surface orientation of the substrate main surface, etc. Also, in each embodiment of the present invention, the first conductivity type is p-type and the second conductivity type is n-type, but the present invention is similarly valid even if the first conductivity type is n-type and the second conductivity type is p-type. [Industrial Applicability]

[0098] INDUSTRIAL APPLICABILITY As described above, the super-junction semiconductor device according to the present invention is useful as a high-voltage semiconductor device used in power conversion devices and power supply devices for various industrial machines. [Explanation of symbols]

[0099] 1, 101 n + Semiconductor Substrate 2, 102 n-type drift layer 2a~2f n-type layer 3a, 3b, 103 n-type column area 4a, 4b, 4c, 4d104 p-type column region 5, 105 p-type base region 6, 106 n + Type Source Area 7, 107 Gate insulating film 8, 108 Gate electrode 10, 110 Source electrode 13, 113 Insulating film 14, 114 Drain electrode 15 Field plate electrode 15a Field plate electrode 15b Field plate electrode 15c Field plate electrode 15d Field plate electrode 16 Stopper electrode 17, 117 Resurf area 17a First RESURF region 17b Second RESURF region 17c 3rd RESURF Region 17d 4th RESURF Region 18 n-type region 19 p-type region 20a, 20b Ion implantation mask 21 Ion Implantation 25 Edge of the first RESURF region 30, 130 active area 40, 140 Edge Termination Area 50, 150 SJ-MOSFET 60 Equipotential Lines 70 Surface protective film w1 Width of the first resurf region w2 Width of the second resurf region w3 Width of the third resurf region w4 Width of the fourth resurf region w11 Active region opening width w12 Opening width of edge termination area w13 Opening width of edge termination area w14 Photoresist width in edge termination area w15: photoresist width at a portion divided into the first resurf region 17a and the second resurf region 17b P1 Aperture pitch (active area) P2 Pitch of openings (edge ​​termination area) P3 Aperture pitch (edge ​​termination area)

Claims

1. 1. A super-junction semiconductor device having an active region through which a current flows, and a termination structure disposed outside the active region and having a breakdown voltage structure surrounding the active region, a semiconductor substrate of a first conductivity type; a first semiconductor layer of a first conductivity type provided on a front surface of the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate; a first parallel pn structure provided in the active region, the first column having a first conductivity type and the second column having a second conductivity type being repeatedly and alternately arranged in a plane parallel to the front surface, the first semiconductor layer being provided on an upper surface of the first semiconductor layer; a second parallel pn structure provided in the termination structure, in which third columns of a first conductivity type and fourth columns of a second conductivity type are repeatedly and alternately arranged in a plane parallel to the front surface, the second parallel pn structure being provided in the first semiconductor layer; a first semiconductor region of a second conductivity type provided between a surface of the first semiconductor layer and the second parallel pn structure, the first semiconductor region having a first region on the side of the active region and a second region provided outside the first region at a distance; a second semiconductor region of a second conductivity type provided on a surface of the second column of the second conductivity type of the first parallel pn structure in the active region; a third semiconductor region of the first conductivity type selectively provided in a surface layer of the second semiconductor region on the opposite side to the semiconductor substrate; a gate insulating film in contact with the second semiconductor region; a gate electrode provided on a surface of the gate insulating film opposite to a surface in contact with the second semiconductor region, a surface of the fourth column of the second conductivity type is provided closer to the semiconductor substrate than a lower surface of the second semiconductor region; a lower surface of the first region of the first semiconductor region contacts a plurality of fourth columns of the second conductivity type; 13. A super-junction semiconductor device, comprising: a first semiconductor region having a bottom surface of the second region that is spaced apart from the semiconductor substrate as the bottom surface of the second region of the first semiconductor region is spaced apart from the active region.

2. A superjunction semiconductor device as described in claim 1, characterized in that the underside of the second region of the first semiconductor region has an end on the active region side equal to the depth of the underside of the first region of the first semiconductor region.

3. A superjunction semiconductor device as described in Claim 2, characterized in that in the second region of the first semiconductor region, an outer region away from the active region does not contact the fourth column of the second conductivity type.

4. The super junction semiconductor device as described in claim 1, characterized in that the first region and the second region of the first semiconductor region have a ratio of the width of the first region to the width of the second region of 3:7 to 5:

5.

5. The superjunction semiconductor device as described in claim 1, characterized in that the planar shapes of the first region and the second region of the first semiconductor region are annular.

6. A superjunction semiconductor device as described in claim 1, characterized in that the width of the first column and the width of the second column of the first parallel pn structure in the active region are wider than the width of the third column and the width of the fourth column of the second parallel pn structure in the termination structure portion.

7. A superjunction semiconductor device as described in claim 1, characterized in that a fourth semiconductor region of a first conductivity type is provided on a surface of the first semiconductor region opposite the semiconductor substrate.

8. A super junction semiconductor device as described in Claim 7, characterized in that the fourth semiconductor region is provided on the entire surface of the second region opposite the semiconductor substrate.

9. The superjunction semiconductor device as described in claim 1, characterized in that the second region of the first semiconductor region has a higher impurity concentration the closer it is to the active region.

10. The superjunction semiconductor device of claim 1, wherein the second region of the first semiconductor region contacts multiple of the fourth columns.

11. A superjunction semiconductor device as described in Claim 10, characterized in that a fourth column is provided between the first region and the second region of the first semiconductor region, the fourth column not contacting the first region and the second region.

12. A superjunction semiconductor device having an active region through which a current flows, and a termination structure disposed outside the active region and having a breakdown voltage structure surrounding the active region, a semiconductor substrate of a first conductivity type; a first semiconductor layer of a first conductivity type provided on a front surface of the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate; a first parallel pn structure provided in the active region, the first column having a first conductivity type and the second column having a second conductivity type being repeatedly and alternately arranged in a plane parallel to the front surface, the first semiconductor layer being provided on an upper surface of the first semiconductor layer; a second parallel pn structure provided in the termination structure, in which third columns of a first conductivity type and fourth columns of a second conductivity type are repeatedly and alternately arranged in a plane parallel to the front surface, the second parallel pn structure being provided in the first semiconductor layer; a first semiconductor region of a second conductivity type provided between a surface of the first semiconductor layer and the second parallel pn structure, the first semiconductor region having a first region on the side of the active region and a second region provided outside the first region at a distance; a second semiconductor region of a second conductivity type provided on a surface of the second column of the second conductivity type of the first parallel pn structure in the active region; a third semiconductor region of the first conductivity type selectively provided in a surface layer of the second semiconductor region on the opposite side to the semiconductor substrate; a gate insulating film in contact with the second semiconductor region; a gate electrode provided on a surface of the gate insulating film opposite to a surface in contact with the second semiconductor region, a surface of the fourth column of the second conductivity type is provided closer to the semiconductor substrate than a lower surface of the second semiconductor region; a lower surface of the first region of the first semiconductor region contacts a plurality of fourth columns of the second conductivity type; 1. A superjunction semiconductor device, comprising: a first semiconductor region having a second region, the second region having a higher impurity concentration as it approaches the active region.

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