Step-up DC / DC converter control circuits, power supply circuits, electronic devices

Abstract

To suppress an overshoot of an output voltage.SOLUTION: A current detection circuit 300 generates a current detection signal ISNS indicating a current IOUT flowing through a first PMOS transistor MP1. A load switch drive circuit 270E is configured to be switchable between a first mode and a second mode, and fully turns on the first PMOS transistor MP1 in the first mode. In the second mode, the load switch drive circuit 270E changes a gate voltage of the first PMOS transistor MP1 according to the current detection signal ISNS so that the first PMOS transistor MP1 has current supply capability IOUT(MAX) larger than a current amount IOUT(SNS) indicated by the current detection signal.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a step-up DC / DC converter. [Background technology]

[0002] A boost converter is used to operate devices that require a higher voltage than the power supply voltage. A boost converter always has conduction between the input line and the output line via an inductor and the body diode of the high-side transistor. Therefore, even when the boost converter is stopped, a voltage equal to the input voltage is generated on the output line and supplied to the load.

[0003] To prevent voltage from being supplied to the load while the step-up DC / DC converter is stopped, a load switch is inserted between the high-side transistor and the output line. Alternatively, instead of a load switch, a high-side switch may be inserted between the input line and the inductor. When the step-up DC / DC converter is stopped, turning off the load switch or high-side switch can prevent voltage from being generated on the output line.

[0004] When the input voltage is lower than the target level of the output voltage, the load switch is turned on fully to minimize losses, and the output voltage of the boost DC / DC converter is stabilized at the target level by feedback control (pulse width modulation) of the boost converter. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2020-120473 A Summary of the Invention [Problem to be solved by the invention]

[0006] As a result of studying a step-up DC / DC converter equipped with a load switch, the present inventors have come to recognize the following problems. Note that these problems should not be taken as general recognition by those skilled in the art.

[0007] Suppose the step-up DC / DC converter begins to start up when the input voltage exceeds the target level of the output voltage. If the step-up DC / DC converter is operated with the load switch fully on, there is a possibility that the output voltage will jump up significantly due to the effect of the induced voltage of the inductor.

[0008] The present disclosure has been made in response to such a problem, and one of its exemplary objectives is to provide a control circuit capable of suppressing a jump in output voltage. [Means for solving the problem]

[0009] An embodiment of the present disclosure relates to a control circuit for a boost DC / DC converter. The boost DC / DC converter includes a high-side transistor, a low-side transistor, and a load switch connected between the high-side transistor and an output line of the boost DC / DC converter. The control circuit includes a pulse modulator that generates a pulse signal that is pulse-modulated so that the output voltage of the output line approaches a target level, a logic circuit that generates a high-side control signal and a low-side control signal based on the pulse signal, a load switch drive circuit that drives a first PMOS transistor provided as a load switch, and a current detection circuit that generates a current detection signal indicating a current flowing through the first PMOS transistor. The load switch drive circuit is configured to be switchable between (i) a first mode in which the first PMOS transistor is fully turned on, and (ii) a second mode in which the gate voltage of the first PMOS transistor is changed according to the current detection signal so that the first PMOS transistor has a current supply capacity larger than the current amount indicated by the current detection signal.

[0010] Another embodiment of the present disclosure is also a control circuit for a step-up DC / DC converter. The control circuit includes a pulse modulator that generates a pulse signal that is pulse-modulated so that the output voltage of an output line approaches a target level, a logic circuit that generates a high-side control signal and a low-side control signal based on the pulse signal, a load switch drive circuit that drives a first PMOS transistor provided as a load switch, and a current detection circuit that generates a current detection signal indicating a current flowing through the first PMOS transistor. The load switch drive circuit includes a second PMOS transistor having a size 1 / M times the size of the first PMOS transistor, a gate of the second PMOS transistor connectable to the gate of the first PMOS transistor, a source of the second PMOS transistor connected to the source of the first PMOS transistor, and a constant current circuit that supplies a current of K / M times or more the amount of current indicated by the current detection signal to the second PMOS transistor.

[0011] Any combination of the above components, or mutual substitution of components or expressions between methods, devices, systems, etc. are also valid aspects of the present invention. Effect of the Invention

[0012] According to an aspect of the present disclosure, output voltage jumps can be suppressed. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1 is a circuit diagram of a step-up DC / DC converter according to a first embodiment. [Diagram 2] FIG. 2 is a diagram illustrating the operation of the DC / DC converter of FIG. [Diagram 3] FIG. 3 is a diagram showing the IV (current-voltage) characteristics of the first PMOS transistor. [Figure 4] FIG. 4 is an operational waveform diagram of a DC / DC converter according to a comparative technique. [Diagram 5] FIG. 5 is an operational waveform diagram of the DC / DC converter of FIG. [Figure 6] FIG. 6 is a circuit diagram showing a configuration example of the load switch driving circuit and its peripheral circuits. [Figure 7] FIG. 7 is a diagram illustrating the operation of the load switch driving circuit of FIG. [Figure 8] FIG. 8 is a circuit diagram showing a configuration example of the load switch driver circuit and the current detection circuit. [Figure 9] FIG. 9 is a circuit diagram of a control circuit according to the second embodiment. [Figure 10] FIG. 10 is a diagram for explaining overcurrent protection by the control circuit of FIG. [Figure 11] FIG. 11 is a circuit diagram of a control circuit according to the third embodiment. [Figure 12] FIG. 12 is a diagram for explaining the operation of the control circuit of FIG. [Figure 13] FIG. 13 is a diagram illustrating an example of an electronic device including a DC / DC converter according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] (Overview of the embodiment) A summary of some exemplary embodiments of the present disclosure will be described. This summary is intended to provide a simplified overview of some concepts of one or more embodiments for a basic understanding of the embodiments as a prelude to the detailed description that follows, and is not intended to limit the scope of the invention or disclosure. This summary is not intended to be an exhaustive overview of all possible embodiments, nor is it intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may be used to refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed in this specification.

[0015] A control circuit for a step-up DC / DC converter according to one embodiment includes a pulse modulator that generates a pulse signal that is pulse-modulated so that the output voltage of an output line approaches a target level, a logic circuit that generates a high-side control signal and a low-side control signal based on the pulse signal, a load switch drive circuit that drives a first PMOS transistor provided as a load switch, and a current detection circuit that generates a current detection signal that indicates a current flowing through the first PMOS transistor. The load switch drive circuit is configured to be switchable between (i) a first mode in which the first PMOS transistor is fully turned on, and (ii) a second mode in which the gate voltage of the first PMOS transistor is changed in response to the current detection signal so that the first PMOS transistor has a current supply capacity larger than the amount of current indicated by the current detection signal.

[0016] According to this configuration, in a situation where the input voltage is higher than the target level of the output voltage, the second mode is selected, thereby making it possible to suppress a sudden increase in the output voltage.

[0017] In one embodiment, in the second mode, the load switch driver circuit (ii) may bias the gate of the first PMOS transistor so that the first PMOS transistor has a current supply capability that is at least K times (K>1) the amount of current indicated by the current detection signal.

[0018] In one embodiment, the load switch drive circuit may include a second PMOS transistor having a size 1 / M times that of the first PMOS transistor, the second PMOS transistor having a gate connected to the gate of the first PMOS transistor in the second mode, a source connected to the source of the first PMOS transistor, and a gate and drain of the second PMOS transistor connected together; and a constant current circuit supplying a current that is K / M times or more the amount of current indicated by the current detection signal, where K is a parameter such that K>1, to the second PMOS transistor.

[0019] A control circuit according to one embodiment includes a pulse modulator that generates a pulse signal that is pulse-modulated so that the output voltage of an output line approaches a target level, a logic circuit that generates a high-side control signal and a low-side control signal based on the pulse signal, a load switch drive circuit that drives a first PMOS transistor provided as a load switch, and a current detection circuit that generates a current detection signal indicating a current flowing through the first PMOS transistor. The load switch drive circuit includes a second PMOS transistor having a size 1 / M times the size of the first PMOS transistor, a gate of the second PMOS transistor connectable to the gate of the first PMOS transistor, a source of the second PMOS transistor connected to the source of the first PMOS transistor, and a constant current circuit that supplies a current of at least K / M times the amount of current indicated by the current detection signal to the second PMOS transistor.

[0020] According to this configuration, when the input voltage is higher than the target level of the output voltage, a sudden increase in the output voltage can be suppressed.

[0021] In one embodiment, the amount of current indicated by the current detection signal is I OUT(SNS) , the current supply capability of the first PMOS transistor is I OUT(MAX) , I OFS where (>0) and K(>1) are constants. I OUT(MAX) =K×I OUT(SNS) +I OFS This allows the output current I OUT Even if the potential becomes zero, the first PMOS transistor can be prevented from being completely turned off.

[0022] In one embodiment, the constant current circuit may include a first transistor having a first end connected to a drain of the second PMOS transistor, a first resistor connected between a second end of the first transistor and a ground line, and a first operational amplifier having an output connected to a control terminal of the first transistor, a first input node receiving a current detection signal, and a second input node connected to the second end of the first transistor.

[0023] In one embodiment, the first op-amp may have a non-zero input offset voltage. In one embodiment, a first input node of the first op-amp may be provided with a voltage that offsets the current sense signal. These offsets can cause the output current I OUT Even if the potential becomes zero, the first PMOS transistor can be prevented from being completely turned off.

[0024] In one embodiment, the load switch driver circuit may set the current supply capability of the first PMOS transistor to the first overcurrent threshold in a region where the amount of current indicated by the current detection signal exceeds the first overcurrent threshold.

[0025] In one embodiment, the constant current circuit may adjust the current supplied to the second PMOS transistor so that the amount of current indicated by the current detection signal does not exceed the first overcurrent threshold.

[0026] In one embodiment, the constant current circuit may further include a current limiting circuit that controls the voltage of the control terminal of the first transistor so that the amount of current indicated by the current detection signal does not exceed a first overcurrent threshold.

[0027] In one embodiment, the current limiting circuit may include a second transistor having a first end connected to the control terminal of the first transistor and a second end connected to a ground line, and a third operational amplifier having an output connected to the control terminal of the second transistor, receiving a voltage defining the first overcurrent threshold at its first input node, and receiving the current detection signal at its second input node.

[0028] In one embodiment, the load switch driver circuit may be switchable to a third mode in which a voltage corresponding to the input voltage of the step-up DC / DC converter is applied to the gate of the first PMOS transistor.

[0029] With this configuration, when the step-up DC / DC converter is stopped, the load switch (PMOS transistor) is not immediately turned off, but a voltage Vc according to the input voltage is applied to the gate of the PMOS transistor, so that the PMOS transistor can operate as a source follower circuit (grounded drain circuit). At this time, the source voltage of the PMOS transistor, i.e., the voltage V at the connection node between the load switch and the high-side transistor, MID teeth, V MID =Vc+V GS ≒V IN +V GS This clamps the voltage V at the node (switching pin) between the high-side transistor and the low-side transistor, preventing overvoltage. SW teeth, V SW =V MID +V F =Vc+V GS +V F ≒V IN +V GS +V F This also suppresses overvoltage on the switching pin. V F is the forward voltage of the body diode of the high-side transistor. Also, the voltage across the inductor, V L teeth, V L =V IN -V SW =V IN -(Vc+V GS +V F )≒-(V GS +V F ) This reduces the coil current to -(V GS +V F ) / L over time.

[0030] In one embodiment, the load switch driver circuit may enter the third mode when the amount of current indicated by the current detection signal exceeds a second overcurrent threshold that is greater than the first overcurrent threshold.

[0031] In one embodiment, the load switch driver circuit may return to the original mode when the amount of current indicated by the current detection signal falls below a release threshold that is lower than the first overcurrent threshold.

[0032] In one embodiment, the current detection circuit may include: a third PMOS transistor having a size 1 / N times that of the first PMOS transistor, the third PMOS transistor having a gate connected to the gate of the second PMOS transistor and a source connected to the source of the second PMOS transistor; the third transistor having a first end connected to the drain of the third PMOS transistor; a second resistor connected between a second end of the third transistor and a ground line; and a third operational amplifier having an output connected to a control terminal of the third transistor, a first input node connected to the drain of the first PMOS transistor, and a second input node connected to the drain of the third PMOS transistor, and the current detection signal may be responsive to a voltage drop across the second resistor.

[0033] In one embodiment, the control circuit may be monolithically integrated on a single semiconductor substrate. "Monolithic integration" includes cases where all of the circuit components are formed on a semiconductor substrate, and cases where the main components of the circuit are monolithically integrated, and some resistors and capacitors for adjusting the circuit constants may be provided outside the semiconductor substrate. By integrating the circuit on a single chip, the circuit area can be reduced and the characteristics of the circuit elements can be kept uniform.

[0034] (Embodiment) The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing are given the same reference numerals, and duplicated descriptions are omitted as appropriate. In addition, the embodiments are not intended to limit the invention, but are merely examples, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

[0035] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.

[0036] Similarly, "a state in which component C is provided between components A and B" includes not only the case in which components A and C, or components B and C, are directly connected to each other, but also the case in which they are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the functions or effects achieved by their combination.

[0037] Furthermore, "signal A (voltage, current) corresponds to signal B (voltage, current)" means that signal A has a correlation with signal B, specifically meaning (i) when signal A is signal B, (ii) when signal A is proportional to signal B, (iii) when signal A is obtained by level-shifting signal B, (iv) when signal A is obtained by amplifying signal B, (v) when signal A is obtained by inverting signal B, (vi) or any combination thereof. Those skilled in the art will understand that the scope of "corresponding to" is determined according to the types and applications of signals A and B.

[0038] The vertical and horizontal axes of the waveform diagrams and time charts referred to in this specification have been appropriately enlarged or reduced to facilitate understanding, and each waveform shown has been simplified or exaggerated or emphasized to facilitate understanding.

[0039] (Embodiment 1) Components related to the first embodiment are given the subscript E. Fig. 1 is a circuit diagram of a step-up DC / DC converter 100E according to the first embodiment. A step-up DC / DC converter (hereinafter simply referred to as a DC / DC converter) 100E receives an input voltage V IN The output voltage is boosted and stabilized to a predetermined voltage level, and then supplied to a load (not shown) connected to an output terminal (output line) 104 .

[0040] The DC / DC converter 100E includes a main circuit 110E and a control circuit 200E. The main circuit 110E includes an inductor L1, a low-side transistor (switching transistor) ML, a high-side transistor (synchronous rectification transistor) MH, an output capacitor C1, and a load switch SW1. In this embodiment, the load switch SW1 includes a PMOS transistor (hereinafter, referred to as a first PMOS transistor MP1).

[0041] The control circuit 200E is a functional integrated circuit (IC) integrated on a single semiconductor substrate (die). In this embodiment, the low-side transistor ML, the high-side transistor MH, and the first PMOS transistor MP1 are integrated into the control circuit 200E.

[0042] The control circuit 200E includes a low-side transistor ML, a high-side transistor MH, and a first PMOS transistor MP1, as well as a pulse modulator 210, a logic circuit 220, a high-side driver 230, a low-side driver 232, a load switch drive circuit 270E, a voltage monitoring circuit 280, a current detection circuit 300, and resistors R11 and R12.

[0043] The control circuit 200E is provided with a switching pin SW, a ground pin PGND, an input pin VIN, an output pin VOUT, and a sense pin VOUT_SNS.

[0044] An external inductor L1 is connected to the switching pin SW. An output capacitor C1 is connected to the output pin VOUT. A low-side transistor ML is connected between the switching pin SW and a ground pin PGND. A high-side transistor MH and a first PMOS transistor MP1 are connected directly between the switching pin SW and the output pin VOUT. An input pin VIN is connected to the input voltage V IN is supplied.

[0045] The DC / DC converter 100E is a constant voltage output converter, and the pulse modulator 210 controls the output voltage V OUT Target level V OUT(REF) A pulse signal Sp is generated that is pulse modulated so as to approach

[0046] The sense pin VOUT_SNS detects the output voltage V OUT is fed back. The output voltage V OUT is divided by resistors R11 and R12, and the output voltage V OUT The feedback signal V FB The pulse modulator 210 generates the feedback signal V FB is the reference voltage V REF The pulse signal Sp is pulse-modulated so as to approach

[0047] Output voltage V OUT Target level V OUT(REF) is expressed by the following formula: V OUT(REF) =V REF ×(R11+R12) / R12

[0048] There are no particular limitations on the configuration or control method of pulse modulator 210. For example, pulse modulator 210 may be a voltage mode controller, or a peak current mode or average current mode controller. Alternatively, pulse modulator 210 may be a ripple control controller, specifically, hysteresis control (Bang-Bang control), bottom detection fixed on-time control, or peak detection fixed off-time control.

[0049] The modulation method of the pulse modulator 210 is also not particularly limited, and may be pulse width modulation, pulse frequency modulation, or another modulation method.

[0050] The logic circuit 220 generates a high-side control signal HGCTL and a low-side control signal LGCTL based on the pulse signal Sp, and also generates a control signal SWCTL for the first PMOS transistor MP1.

[0051] The high-side driver 230 drives the high-side transistor MH based on a high-side control signal HGCTL, and the low-side driver 232 drives the low-side transistor ML based on a low-side control signal LGCTL.

[0052] The load switch driving circuit 270E drives the first PMOS transistor MP1, which is the load switch SW1, based on the control signal SWCTL. Specifically, when the control signal SWCTL is at an on level (e.g., high), the first PMOS transistor MP1 is turned on, and when the control signal SWCTL is at an off level (e.g., low), the first PMOS transistor MP1 is turned off.

[0053] The load switch driving circuit 270E is configured to be able to switch between two modes while the control signal SWCTL is at the on level (high). A control signal MODE that specifies the mode is input to the load switch driving circuit 270E.

[0054] In the first mode, the load switch driver 270E fully turns on the first PMOS transistor MP1. For example, the load switch driver 270E fully turns on the first PMOS transistor MP1 when the source voltage V MID The first PMOS transistor MP1 generates a voltage that is lower than the threshold voltage Vgs of the first PMOS transistor MP1 by a predetermined voltage step ΔV and supplies it to the gate of the first PMOS transistor MP1. (th) Greater than.

[0055] The input pin VIN of the control circuit 200E is connected to the input line 102 and receives the input voltage V IN The voltage monitoring circuit 280 detects the input voltage V IN is the threshold voltage V TH and generates a comparison signal VINCOMP according to the comparison result. IN >V THIt is assumed that VINCOMP is high when the voltage monitoring circuit 280 is a voltage comparator.

[0056] The logic circuit 220 controls the operation mode of the DC / DC converter 100C based on the comparison signal VINCOMP. IN <V OUT(REF) When , the DC / DC converter 100C operates in boost mode and V IN >V OUT(REF) At this time, the DC / DC converter 100C is operated in the through mode.

[0057] The current detection circuit 300 detects a current in the first PMOS transistor MP1, i.e., the output current I OUT The current detection circuit 300 may detect the current flowing through the first PMOS transistor MP1 as described later. Alternatively, since the current flowing through the first PMOS transistor MP1 is equal to the current flowing through the high-side transistor MH and the coil current flowing through the inductor L1, the current ISNS of the first PMOS transistor MP1 may be indirectly detected based on the currents of the high-side transistor MH and the inductor L1. OUT may be detected.

[0058] The current detection signal ISNS is supplied to the load switch driving circuit 270E. In the second mode, the load switch driving circuit 270E detects the amount of current I OUT(SNS) Higher current supply capability I OUT(MAX) The gate voltage of the first PMOS transistor MP1 is changed in response to the current detection signal ISNS so as to have the following. I OUT(MAX) >I OUT(SNS) Current supply capacity I OUT(MAX) can be understood as the drain current Id in the saturation region of a FET (Field-Effect Transistor). Id=1 / 2×K

[0059] In the second mode, feedback control is not performed to bring the current detection signal ISNS closer to a target value, but the current detection signal ISNS serves as a reference signal that determines the bias point of the first PMOS transistor MP1.

[0060] For example, in the second mode, the load switch driver circuit 270E: (ii) detects the amount of current I OUT(SNS) Current supply capability I of K times (K>1) or more OUT(MAX) The gate of the first PMOS transistor MP1 is biased to have K=K, where K is a design parameter. I OUT(MAX) ≧K×I OUT(SNS)

[0061] The above is the configuration of the DC / DC converter 100E. Next, the operation of the DC / DC converter 100E will be described.

[0062] FIG. 2 is a diagram for explaining the operation of the DC / DC converter 100E of FIG. 1. The horizontal axis represents the input voltage V IN The vertical axis is the output voltage V OUT Shows.

[0063] Input voltage V IN is the output voltage V OUT Target level V OUT(REF) At lower states, the DC / DC converter 100E operates in boost mode. In boost mode, the high-side and low-side transistors switch to boost the output voltage V OUT Target level V OUT(REF) is stabilized to.

[0064] In this boost mode, the logic circuit 220 operates the load switch driver 270E in the first mode, which turns the first PMOS transistor MP1 fully on and keeps the loss in the first PMOS transistor MP1 small.

[0065] Input voltage V IN is the output voltage V OUT Target level V OUT(REF)At a higher state, the DC / DC converter 100E operates in a through mode, in which the duty cycle of the pulse signal Sp drops to zero and switching stops with the low-side transistor ML turned off and the high-side transistor MH turned on.

[0066] The load switch driver 270E operates in the second mode in the through mode. At this time, the first PMOS transistor MP1 has not yet reached the full-on state and is biased so as to have a current supply capability sufficient to supply the load current at that time.

[0067] 3 is a diagram showing the IV (current-voltage) characteristics of the first PMOS transistor MP1. The horizontal axis represents the drain-source voltage V DS The vertical axis is the drain current I D The current in the saturated region (also called the saturation current) I D(SAT) is expressed by the following formula: I D(SAT) =-W / 2L μC OX (V GS -V T ) 2 =-A(V GS -V T ) 2 A = W / 2L μC OX V GS is the gate-source voltage (bias point) of the first PMOS transistor MP1, V T is the threshold voltage of the P-channel MOSFET, W is the gate width, L is the gate length, μ is the mobility, and C OX is the capacitance of the gate insulating film.

[0068] As mentioned above, the current supply capacity I OUT(MAX) is the current in the saturation region I D(SAT) It can be understood as follows. A certain output current I OUT When a current is flowing, the operating point is determined so as to satisfy the following relationship: I D(SAT) =A(V GS -V T )2 >I OUT V GS >√(I OUT / A)+V T

[0069] For example, the output current I OUT Current supply capability I OUT(MAX) In this case, the operating point is as follows, and the first PMOS transistor MP1 operates in the linear region. I D(SAT) =A(V GS -V T ) 2 =K×I OUT V GS =√(K×I OUT / A)+V T

[0070] V IN ≧V OUT(REF) When the second mode is selected, the output voltage V OUT teeth, V OUT =V IN -(R ON(MH) +R ON(MP1) )×I OUT and the input voltage V IN Takes a voltage level slightly lower than R ON(MH) is the on-resistance of the high-side transistor MH. Since the high-side transistor MH is in a fully on state, its on-resistance is very small. R ON(MP1) is the on-resistance of the first PMOS transistor MP1. ON(MP1) can be determined according to the above-mentioned parameter K. The larger K is, the smaller the on-resistance R ON(MP1) From this viewpoint, K is preferably 1.5 or more, more preferably 2 or more, and when K is 4 or more, the on-resistance can be made sufficiently small to reduce losses.

[0071] The above is the operation of the DC / DC converter 100. We will now explain the advantage of operating the load switch driver circuit 270E in the second mode rather than the first mode in the through mode. This advantage will become clear through a comparison with the comparative technology.

[0072] In the comparative technique, the load switch driving circuit 270E operates in the first mode in the through mode, and the first PMOS transistor MP1 is fully turned on. FIG. 4 is an operational waveform diagram of the DC / DC converter according to the comparative technique. The input voltage V IN is the output voltage V OUT The target voltage V OUT(REF) Consider a situation where the voltage is higher than V. At time t0, a start command is input to the DC / DC converter. IN >V OUT(REF) When this is detected, the through mode is selected and the load switch driver circuit 270E is set to the first mode. As a result, the first PMOS transistor MP1 immediately goes into a full-on state. This causes a current to rise sharply from the input line 102 to the output line 104. This current flows through the inductor L1, and an induced voltage is generated when the coil current changes sharply. This induced voltage increases the output voltage V OUT will overshoot.

[0073] FIG. 5 is a waveform diagram showing the operation of the DC / DC converter 100E in FIG. 1. As in FIG. 4, the input voltage V IN is the output voltage V OUT The target voltage V OUT(REF) Consider a situation where the voltage is higher than V. At time t0, a start command is input to the DC / DC converter. IN >V OUT(REF)When this is detected, the through mode is selected and the load switch driver circuit 270E is set to the second mode. In this case, the first PMOS transistor MP1 does not immediately go into a full-on state, and the gate-source voltage of the first PMOS transistor MP1 increases more slowly than in the case of the comparative technology due to a delay in the feedback loop of the load switch driver circuit 270E. As a result, the current flowing from the input line 102 to the output line 104 increases more slowly than in the comparative technology (FIG. 4). This suppresses sudden changes in the coil current and reduces the induced voltage. As a result, the output voltage V OUT This can suppress overshoot.

[0074] Next, a specific configuration example of the control circuit 200E will be described. Fig. 6 is a circuit diagram showing a configuration example of the load switch driving circuit 270E and its peripheral circuits.

[0075] The load switch driver circuit 270E includes a second PMOS transistor MP2, a voltage source 272, a selector 274, a second PMOS transistor MP2, and a constant current circuit 310E.

[0076] In the first mode, the voltage source 272 generates a gate voltage for turning on the first PMOS transistor MP1. Specifically, the voltage source 272 generates a source voltage V MID is level-shifted to the source voltage V MID A voltage that is lower by a certain voltage width ΔV than MID -ΔV) In the first mode, the selector 274 selects the output voltage of the voltage source 272 and supplies it to the gate of the first PMOS transistor MP1.

[0077] The second PMOS transistor MP2 and the constant current circuit 310E generate the gate voltage of the first PMOS transistor MP1 in the second mode.

[0078] The second PMOS transistor MP2 has a size 1 / M times that of the first PMOS transistor MP1. In the second mode, the gate of the second PMOS transistor MP2 is connected to the gate of the first PMOS transistor MP1 via the selector 274, and the source of the second PMOS transistor MP2 is connected to the source of the first PMOS transistor MP1. The gate and drain of the second PMOS transistor MP2 are wired together.

[0079] In the second mode, the selector 274 connects the gate of the second PMOS transistor MP2 to the gate of the first PMOS transistor MP1. In the second mode, the second PMOS transistor MP2 and the first PMOS transistor MP1 are connected to configure a current mirror circuit with the second PMOS transistor MP2 as the input and the first PMOS transistor MP1 as the output. However, since the first PMOS transistor MP1 operates in a linear region where the drain-source voltage is small, the first PMOS transistor MP1 receives the current I FRC The current supply capacity of the first PMOS transistor MP1 is not M times that of I FRC ×M.

[0080] The constant current circuit 310E detects the amount of current I indicated by the current detection signal ISNS generated by the current detection circuit 300. OUT(SNS) Force current I is K / M times or more FRC to the second PMOS transistor MP2. I FRC ≧K / M×I OUT(SNS)

[0081] For example, the constant current circuit 310E detects the amount of current I OUT(SNS) K / M times the force current I FRC may be supplied to the second PMOS transistor MP2. I FRC =K / M×I OUT(SNS) In this case, however, the output current I OUT When becomes zero, the force current IFRC becomes zero, the gate-source voltages of the first PMOS transistor MP1 and the second PMOS transistor MP2 become 0V, the first PMOS transistor MP1 is completely turned off, and additional control for restarting is required.

[0082] Therefore, the constant current circuit 310E detects the amount of current I OUT(SNS) K / M times offset I OFS The force current I FRC to the second PMOS transistor MP2. I FRC =K / M×I OUT(SNS) +I OFS

[0083] This results in an output current I OUT Even if becomes zero, the force current I FRC I OFS As a result, the first PMOS transistor MP1 and the second PMOS transistor MP2 can be maintained in an unturned state.

[0084] The above is the configuration of the load switch driving circuit 270E. Next, the operation of the load switch driving circuit 270E will be described. FIG. 7 is a diagram for explaining the operation of the load switch driving circuit 270E of FIG. 6. The horizontal axis represents the output current I OUT The vertical axis represents the current supply capability I OUT(MAX) Shows.

[0085] In this way, according to the load switch driving circuit 270E of FIG. 6, the output current I OUT The current supply capability I OUT(MAX) (Saturation current amount I D(SAT) ) can be increased linearly.

[0086] Fig. 8 is a circuit diagram showing a configuration example of the load switch driving circuit 270E and the current detection circuit 300. In Fig. 8, the voltage source 272 and the selector 274 are omitted.

[0087] The current detection circuit 300 includes a third PMOS transistor MP3, a third transistor M23, a second resistor R22, and a second operational amplifier OP2.

[0088] The third PMOS transistor MP3 has a size 1 / N times that of the first PMOS transistor MP1 (M / N times that of the second PMOS transistor MP2). The gate of the third PMOS transistor MP3 is connected to the gate of the second PMOS transistor MP2, and the source of the third PMOS transistor MP3 is connected to the sources of the second PMOS transistor MP2 and the first PMOS transistor MP1.

[0089] The third transistor M23 is a P-channel MOSFET, and a first end (source) thereof is connected to the drain of the third PMOS transistor MP3.

[0090] The second resistor R22 is connected between the second end (drain) of the third transistor M23 and the ground line. The output of the second operational amplifier OP2 is connected to the control terminal (gate) of the third transistor M23, the first input node (non-inverting input terminal +) of which is connected to the drain (VOUT pin) of the first PMOS transistor MP1, and the second input node (inverting input terminal -) of which is connected to the drain of the third PMOS transistor MP3.

[0091] The second operational amplifier OP2 and the third transistor M23 provide feedback so that the drain voltage of the third PMOS transistor MP3 is equal to the drain voltage of the first PMOS transistor MP1. As a result, the third transistor M23 outputs an output current I OUT Current I OUT / N flows through the second resistor R22. OUT Voltage drop proportional to I OUT / N×R22 occurs.

[0092] The current detection circuit 300 outputs a current detection signal ISNS that corresponds to the voltage drop across the second resistor R22. ISNS = R22 × I OUT / N

[0093] The constant current circuit 310E includes a first transistor M21, a first resistor R21, and a first operational amplifier OP1.

[0094] The first transistor M21 is an N-channel MOSFET, and its first end (drain) is connected to the drain of the second PMOS transistor MP2. The first resistor R21 is connected between the second end (source) of the first transistor M21 and the ground line. The output of the first operational amplifier OP1 is connected to the control terminal (gate) of the first transistor M21, its first input node (non-inverting input terminal +) receives the current detection signal ISNS, and its second input node (inverting input terminal -) is connected to the second end (source) of the first transistor M21.

[0095] The first op-amp, OP1, has a non-zero input offset voltage, V OFS In this case, the force current I generated by the constant current circuit 310E may be FRC teeth, I FRC =(ISNS+V OFS ) / R21 V OFS / R21 is the offset current I OFS is equivalent to.

[0096] The above is an example of the configuration of the current detection circuit 300 and the constant current circuit 310E. With this configuration, the current supply capability I OUT(MAX) is expressed by the following formula: I OUT(MAX) =I FRC ×M=(ISNS+V OFS ) / R21×M =(R22×I OUT / N+V OFS ) / R21×M =(R22 / R21) M / N × I OUT +V OFS / R21×M

[0097] That is, K = (R22 / R21) M / N, I OFS =V OFSFor example, M=N and R22=R21×K.

[0098] Offset voltage V OFS There is no particular restriction on how to give the offset voltage V OFS A voltage source 312 is added to generate a current detection signal ISNS, OFS Voltage offset by ISNS+V OFS may be supplied to the first input node (+) of the first operational amplifier OP1.

[0099] Alternatively, a current source 314 that sources a current Iz may be added to the second resistor R22 of the current detection circuit 300 to offset the current detection signal ISNS. OFS =Iz×R22.

[0100] (Embodiment 2) Please refer to FIG. 6. The configuration related to the second embodiment is given the subscript F. The load switch driving circuit 270F has a current limiting function that is enabled in the second mode. The load switch driving circuit 270F limits the amount of current I OUT(SNS) is the first overcurrent threshold I OCP1 In the larger area, the current supply capability I OUT(MAX) The first overcurrent threshold I OCP1 to be limited.

[0101] More specifically, the constant current circuit 310F detects the amount of current I OUT(SNS) is the first overcurrent threshold I OCP1 The force current I supplied to the second PMOS transistor MP2 is set so as not to exceed FRC Adjust.

[0102] 9 is a circuit diagram of a control circuit 200F according to the second embodiment. The constant current circuit 310F further includes a current limiting circuit 320 in addition to the constant current circuit 310E of FIG. 8. The current limiting circuit 320 limits the amount of current I OUT(SNS)is the first overcurrent threshold I OCP1 The voltage of the control terminal (gate) of the first transistor M21 is controlled so as not to exceed

[0103] The current limiting circuit 320 includes a second transistor M22 and a third operational amplifier OP3. The second transistor M22 is a PMOS transistor, and a first end (source) thereof is connected to the control terminal (gate) of the first transistor M21, and a second end (drain) thereof is connected to the ground line. The third operational amplifier OP3 has an output connected to the control terminal (gate) of the second transistor M22, and a first input node (non-inverting input terminal +) connected to a first overcurrent threshold II OCP1 and receives the current detection signal ISNS at its second input node (inverting input terminal -).

[0104] The configuration of the constant current circuit 310F with a current limiting function is not particularly limited to that shown in FIG.

[0105] FIG. 10 is a diagram illustrating overcurrent protection by the control circuit 200F of FIG. OUT is the first overcurrent threshold I OCP1 When the current supply capability I of the first PMOS transistor MP1 is exceeded, the current limiting circuit 320 OUT(MAX) The first overcurrent threshold I OCP1 It drops to.

[0106] According to the control circuit 200F of the second embodiment, overcurrent protection can be achieved by lowering the current supply capability of the first PMOS transistor MP1.

[0107] (Embodiment 3) The subscript G is added to the configuration related to the third embodiment. In the second mode (through mode), the first PMOS transistor MP1 operates in a linear region and has an excessive current supply capability. Therefore, when the output line 104 of the DC / DC converter 100F is grounded, a large current may instantaneously flow through the first PMOS transistor MP1 during the delay time until the current limiting circuit 320 operates to provide protection. After that, the current limiting circuit 320 reduces the current supply capability I OUT(MAX) When the current supply capacity I OUT(MAX) Coil current I exceeds L flows into the source of the first PMOS transistor MP1, and the source voltage V MID There is a risk of it jumping up.

[0108] 11 is a circuit diagram of a control circuit 200G according to embodiment 3. In order to solve the above problem, the control circuit 200G performs two-stage overcurrent protection.

[0109] The load switch driver circuit 270G has a current limiting function in the second mode, similar to the load switch driver circuit 270E.

[0110] The load switch driving circuit 270G is configured to be able to select a third mode in addition to the first and second modes. In the third mode, the load switch driving circuit 270G applies an input voltage V IN The third mode is also called the off mode. When the voltage Vc is equal to or smaller than the input voltage V IN "Depends on the voltage Vc" means that the voltage Vc is IN This includes the fact that the voltage Vc is generated using the input voltage V IN Not only when the voltage Vc is equal to the input voltage V IN When the voltage Vc is a positive or negative level shifted voltage, or when the voltage Vc is a IN In this embodiment, the voltage Vc may be a voltage obtained by multiplying the input voltage V INIn the third mode, the selector 274 connects the gate of the first PMOS transistor MP1 to the input pin VIN.

[0111] The load switch driver circuit 270G detects the amount of current I indicated by the current detection signal ISNS during operation in the second mode. OUT(SNS) is the first overcurrent threshold I OCP1 A larger second overcurrent threshold I OCP2 When the current detection signal ISNS exceeds the threshold, the load switch driver 270G switches to the third mode. OUT(SNS) is the first overcurrent threshold I OCP1 Smaller release threshold I RELEASE When it falls below this value, it reverts to the second mode.

[0112] The control circuit 200G includes an overcurrent protection circuit 330. The overcurrent protection circuit 330 outputs the current detection signal ISNS as a second overcurrent threshold I OCP2 The threshold voltage ILIM2 that determines the release threshold I RELEASE The overcurrent protection circuit 330 may be configured with a hysteresis comparator. The logic circuit 220 controls the mode of the load switch driver circuit 270G according to the output OCP2 of the overcurrent protection circuit 330.

[0113] 12 is a diagram for explaining the operation of the control circuit 200G of FIG. 11. Before time t0, the control circuit 200G operates in the second mode (through mode). When a ground fault occurs in the output line 104 at time t0, the output voltage V OUT As the output current I OUT At time t1, the current I OUT is the second overcurrent threshold I OCP2 When the input voltage V IN (=Vc) is applied.

[0114] At this time, the first PMOS transistor MP1 does not immediately turn off, but operates as a source follower circuit. As a result, the source voltage of the first PMOS transistor MP1, i.e., the voltage V of the connection node between the load switch SW1 and the high-side transistor MH, MID teeth, V MID =Vc+V GS This clamps the input voltage to prevent overvoltage from occurring.

[0115] At this time, the voltage V of the switching pin SW, which is the connection node between the high-side transistor MH and the low-side transistor ML, SW teeth, V SW =V MID +V F =Vc+V GS +V F ≒V IN +V GS +V F This also suppresses overvoltage on the switching pin SW.

[0116] At this time, the voltage across the inductor V L teeth, V L =V IN -V SW =V IN -(Vc+V GS +V F ) As mentioned above, Vc ≒ V IN If we define it as: V L ≒-(V GS +V F ) This results in the coil current I L , and thus the output current I OUT , -(V GS +V F ) / L over time.

[0117] At time t2, the output current I OUT is the release threshold I RELEASEWhen the output current drops to 100mA, the output returns to the second mode (through mode). However, since the ground fault condition still persists, the output current I OUT At time t3, the output current I OUT is the first overcurrent threshold I OCP1 If the output current exceeds I, the load switch driver 270G will start to limit the current. OUT But, I OCP1 is clamped to

[0118] After that, when the ground fault condition is resolved at time t4, the output voltage V OUT is the input voltage V IN After time t5, the current limit is released.

[0119] The above is the operation of the control circuit 200G. According to this control circuit 200G, when a sudden overcurrent occurs, the load switch driver circuit 270G is operated in the third mode, so that the voltage V MID This can suppress overvoltage and ringing.

[0120] (Modification) The above-described embodiment is merely an example, and it will be understood by those skilled in the art that various modifications are possible in the combination of each component and each processing step. Such modifications will be described below.

[0121] In relation to the first to third embodiments, the low-side transistor ML and the high-side transistor MH may be externally connected as discrete elements.

[0122] In relation to the first to third embodiments, the first PMOS transistor MP1 may be externally attached as a discrete element. In this case, a part or the whole of the load switch driving circuit 270 may be configured as a discrete element outside the IC of the control circuit 200E.

[0123] The load switch driver circuit 270 may support a fourth mode. In the fourth mode, the load switch driver circuit 270 supports an output voltage V OUT Target level VOUT(REF) The gate voltage of the first PMOS transistor MP1 is feedback-controlled so as to approach the fourth mode, which is also called an LDO (Low Drop Output) mode.

[0124] The load switch driver 270 may operate in the fourth mode when the DC / DC converter 100 is started up. At this time, the reference voltage V REF By gradually increasing the output voltage V OUT At the end of the soft start, the input voltage V IN is the output voltage V OUT Target level V OUT(REF) If it is higher, a transition to the second mode (through mode) may be made.

[0125] (Application) Next, applications of the DC / DC converters 100E to 100G (hereinafter simply referred to as 100) will be described.

[0126] 13 is a diagram showing an example of an electronic device 700 including a DC / DC converter 100 according to an embodiment. The electronic device 700 is a battery-driven device such as a mobile phone terminal, a digital camera, a digital video camera, a tablet terminal, or a portable audio player. The electronic device 700 includes a housing 702, a battery 704, a microprocessor 706, and a DC / DC converter 100. The DC / DC converter 100 receives a battery voltage V from a battery 704 at its input terminal. BAT (=V IN ) and the output voltage V OUT supplies.

[0127] The type of electronic device 700 is not limited to a battery-powered device, but may be an in-vehicle device, an office automation device such as a facsimile, or an industrial device.

[0128] The embodiments are merely examples, and it will be understood by those skilled in the art that there are various variations in the combination of each component and each treatment process, and that such variations are also included in the present disclosure and may constitute the scope of the present invention. [Explanation of symbols]

[0129] 100 DC / DC Converter 102 input lines 104 Output Line 110 Main circuit ML Low Side Transistor MH High Side Transistor SW1 Load switch 200 Control circuit 210 Pulse Modulator 220 Logic Circuit 230 High Side Driver 232 Low Side Driver 270 Load switch driver circuit 272 Voltage Source 274 Selector 280 Voltage Monitoring Circuit 300 Current detection circuit MP1 First PMOS transistor MP2 Second PMOS transistor MP3 3rd PMOS transistor 310 Constant current circuit 320 Current limiting circuit R21 1st resistor R22 2nd resistor M21 1st transistor M22 Second transistor M23 3rd transistor OA1 1st operational amplifier OA2 2nd operational amplifier OA3 3rd operational amplifier 330 Overcurrent protection circuit

Claims

1. A control circuit for a step-up DC / DC converter, comprising: The step-up DC / DC converter comprises: a high-side transistor and a low-side transistor; a load switch connected between the high-side transistor and an output line of the step-up DC / DC converter; Contains The control circuit includes: a pulse modulator for generating a pulse signal that is pulse modulated so that the output voltage of the output line approaches a target level; a logic circuit that generates a high-side control signal and a low-side control signal based on the pulse signal; a load switch driver circuit that drives a first PMOS transistor provided as the load switch; a current detection circuit for generating a current detection signal indicative of a current flowing through the first PMOS transistor; Equipped with the load switch drive circuit is configured to be switchable between (i) a first mode in which the first PMOS transistor is fully on, and (ii) a second mode in which a gate voltage of the first PMOS transistor is changed in response to the current detection signal so that the first PMOS transistor has a current supply capability larger than an amount of current indicated by the current detection signal.

2. 2. The control circuit according to claim 1, wherein the load switch drive circuit biases the gate of the first PMOS transistor so that, in the second mode, the load switch drive circuit has a current supply capability that is K times (K>1) or more the amount of current indicated by the current detection signal.

3. The amount of current indicated by the current detection signal is I ＯＵＴ（ＳＮＳ） , the current supply capability of the first PMOS transistor is I ＯＵＴ（ＭＡＸ） , I ＯＦＳ and K (>1) is a constant, I ＯＵＴ（ＭＡＸ） =K×I ＯＵＴ（ＳＮＳ） +I ＯＦＳ The control circuit according to claim 1 or 2, which satisfies the following:

4. The load switch driving circuit includes: a second PMOS transistor having a size 1 / M times the size of the first PMOS transistor, the gate of the second PMOS transistor being connected to the gate of the first PMOS transistor in the second mode, the source of the second PMOS transistor being connected to the source of the first PMOS transistor, and the gate and drain of the second PMOS transistor being connected together; a constant current circuit that supplies a current that is equal to or greater than K / M times the current amount indicated by the current detection signal to the second PMOS transistor, where K is a parameter that satisfies K>1; 4. A control circuit as claimed in claim 1, comprising:

5. A control circuit for a step-up DC / DC converter, comprising: The step-up DC / DC converter comprises: a high-side transistor and a low-side transistor; a load switch connected between the high-side transistor and an output line of the step-up DC / DC converter; Contains The control circuit includes: a pulse modulator for generating a pulse signal that is pulse modulated so that the output voltage of the output line approaches a target level; a logic circuit that generates a high-side control signal and a low-side control signal based on the pulse signal; a load switch driver circuit that drives a first PMOS transistor provided as the load switch; a current detection circuit for generating a current detection signal indicative of a current flowing through the first PMOS transistor; Equipped with The load switch driving circuit includes: a second PMOS transistor having a size 1 / M times the size of the first PMOS transistor, the gate of which can be connected to the gate of the first PMOS transistor, the source of which is connected to the source of the first PMOS transistor, and the gate and drain of the second PMOS transistor are connected; a constant current circuit that supplies a current to the second PMOS transistor that is equal to or greater than K / M times the current amount indicated by the current detection signal; a control circuit.

6. The constant current circuit is a first transistor having a first end connected to the drain of the second PMOS transistor; a first resistor connected between the second end of the first transistor and a ground line; a first operational amplifier having an output connected to a control terminal of the first transistor, a first input node receiving the current detection signal, and a second input node connected to the second end of the first transistor; 6. A control circuit as claimed in claim 4 or 5, comprising:

7. 7. The control circuit of claim 6, wherein the first operational amplifier has a non-zero input offset voltage.

8. 7. The control circuit according to claim 6, wherein a voltage obtained by offsetting the current detection signal is supplied to the first input node of the first operational amplifier.

9. 9. The control circuit according to claim 1, wherein the load switch drive circuit sets a current supply capability of the first PMOS transistor to the first overcurrent threshold in a region where the amount of current indicated by the current detection signal exceeds a first overcurrent threshold.

10. 9. The control circuit according to claim 4, wherein the constant current circuit adjusts the current supplied to the second PMOS transistor so that the amount of current indicated by the current detection signal does not exceed a first overcurrent threshold value.

11. 9. The control circuit according to claim 6, wherein the constant current circuit further includes a current limiting circuit that controls a voltage of a control terminal of the first transistor so that the amount of current indicated by the current detection signal does not exceed a first overcurrent threshold.

12. The current limiting circuit includes: a second transistor having a first end connected to the control terminal of the first transistor and a second end connected to a ground line; a third operational amplifier having an output connected to the control terminal of the second transistor, a first input node receiving a voltage defining the first overcurrent threshold, and a second input node receiving the current detection signal; The control circuit of claim 11 , comprising:

13. the load switch drive circuit is switchable to a third mode in which a voltage corresponding to an input voltage of the step-up DC / DC converter is applied to a gate of the first PMOS transistor; 13. The control circuit according to claim 9, wherein the load switch drive circuit is configured to enter the third mode when the amount of current indicated by the current detection signal exceeds a second overcurrent threshold value that is larger than the first overcurrent threshold value.

14. The control circuit according to claim 13 , wherein the load switch drive circuit returns to the original mode when the amount of current indicated by the current detection signal falls below a release threshold that is smaller than the first overcurrent threshold.

15. The current detection circuit includes: a third PMOS transistor having a size 1 / N times that of the first PMOS transistor, the gate of which is connected to the gate of the second PMOS transistor and the source of which is connected to the source of the second PMOS transistor; a third transistor having a first end connected to the drain of the third PMOS transistor; a second resistor connected between the second end of the third transistor and a ground line; a third operational amplifier, the output of which is connected to the control terminal of the third transistor, the first input node of which is connected to the drain of the first PMOS transistor, and the second input node of which is connected to the drain of the third PMOS transistor; 9. A control circuit as claimed in claim 4, comprising: a first resistor connected to said first resistor and a second resistor connected to said second resistor;

16. 13. The control circuit according to claim 1, wherein the load switch drive circuit is switchable to a third mode in which a voltage according to an input voltage of the step-up DC / DC converter is applied to a gate of the first PMOS transistor.

17. 17. The control circuit according to claim 1, which is monolithically integrated on a single semiconductor substrate.

18. A main circuit of a step-up DC / DC converter; A control circuit according to any one of claims 1 to 16; A power supply circuit comprising:

19. An electronic device comprising a control circuit according to any one of claims 1 to 16.

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