Semiconductor structure and method of manufacture thereof

Abstract

The present disclosure relates to a semiconductor structure and a method for fabricating the same, the method including providing a substrate, forming an ion implantation region in the substrate, where a top surface of the ion implantation region is spaced from a top surface of the substrate, forming an initial wordline trench in the substrate, where the initial wordline trench extends from the top surface of the substrate into the ion implantation region, and performing a widening process on the initial wordline trench to form the wordline trench, where a bottom width of the wordline trench is greater than a minimum width of the wordline trench. The method for fabricating the semiconductor structure according to the disclosed embodiment includes forming an ion implantation region in the substrate, and then performing a widening process on the initial wordline trench to form the wordline trench, so as to increase a bottom cross-sectional area of ​​the formed wordline trench and reduce electrical resistance of the wordline formed in the subsequent fabrication process, thereby avoiding increased power consumption and increased RC delay of the device.

Description

[Technical field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims priority to a Chinese patent application bearing application number 202210598976.8, filed with the China Patent Office on May 30, 2022, the entire contents of which are incorporated herein by reference.

[0002] TECHNICAL FIELD Embodiments of the present disclosure relate to the field of semiconductor manufacturing technology, and more particularly to semiconductor structures and methods for manufacturing the same. [Background technology]

[0003] As semiconductor memory devices (e.g., dynamic random access memories (DRAMs)) become more highly integrated, the area of ​​a unit cell on a semiconductor substrate is gradually shrinking accordingly, and the channel length of a metal-oxide-semiconductor (MOS) transistor is also gradually decreasing. The decrease in channel length is likely to lead to the occurrence of a short channel effect.

[0004] In order to maintain a high degree of integration of semiconductor memory devices, the current mainstream DRAM process uses Buried Wordline (BW) MOS as the memory cell transistor, which can reduce the short channel effect to a certain extent and reduce the leakage phenomenon of the device.

[0005] However, as the size of the memory cell shrinks, the size of the BW trench also shrinks, and the cross-sectional area of ​​the metal filled in the BW trench also decreases, which results in an increase in the electrical resistance of the wordline (WL), which in turn leads to higher power consumption and an increase in signal delay (abbreviated as RC delay) caused by the charging and discharging process of the electrical resistance (R) and parasitic capacitance (C). Summary of the Invention

[0006] Various embodiments of the present disclosure provide semiconductor structures and methods for fabricating the same.

[0007] According to some embodiments, one aspect of the present disclosure provides a method for manufacturing a semiconductor structure, the method comprising: Providing a substrate; forming an ion implantation region in the substrate, the ion implantation region having an upper surface spaced apart from an upper surface of the substrate; forming initial wordline trenches in the substrate, the initial wordline trenches extending from an upper surface of the substrate into the ion implanted region; performing a widening process on the initial wordline trench to form a wordline trench, the width of the wordline trench at a bottom being greater than a minimum width of the wordline trench.

[0008] According to some embodiments, fluorine or boron ions are implanted into the substrate to form the ion implanted region.

[0009] According to some embodiments, the ion concentration of the ion implantation region is 1×10 17 cm 3 ~1×10 22 cm 3 and The distance between the ion implantation region and the upper surface of the substrate is 100 nm to 200 nm.

[0010] According to some embodiments, performing a widening process on the initial wordline trench to form the wordline trench includes: forming a sacrificial dielectric layer on sidewalls and a bottom of the initial wordline trench by an in-situ process, the thickness of the sacrificial dielectric layer located in the ion implantation region being greater than the thickness of the remaining sacrificial dielectric layer; removing the sacrificial dielectric layer to form the wordline trenches.

[0011] According to some embodiments, after forming the word line trenches, the method for manufacturing the semiconductor structure includes: implanting ions of a first conductivity type into the substrate, removing the ion implanted region, and forming a first doped region, a bottom of the first doped region being lower than a bottom of the wordline trench and a top of the first doped region being higher than a bottom of the wordline trench; implanting ions of a second conductivity type into the substrate to form a second doped region, the second doped region being above the first doped region and extending to an upper surface of the substrate, the wordline trenches extending through the second doped region and into the first doped region, the first doped region being a doped region of a first conductivity type and the second doped region being a doped region of a second conductivity type; forming a gate oxide layer on the sidewalls and bottom of the wordline trench; forming a wordline conductive layer on a surface of the gate oxide layer, the top of the wordline conductive layer being lower than the top of the wordline trench; Further comprising forming a fill dielectric layer in the wordline trench, the fill dielectric layer being on top of the wordline conductive layer and at least completely filling the wordline trench.

[0012] According to some embodiments, the first conductivity type is P-type and the second conductivity type is N-type.

[0013] According to some embodiments, the ion concentration in the first doped region is 1×10 16 cm 3 ~1×10 20 cm 3 and the ion concentration in the second doped region is 1×10 16 cm 3 ~1×10 20 cm 3 It is.

[0014] According to some embodiments, the ion implantation region is a first doped region, and prior to forming the ion implantation region in the substrate, the method for manufacturing the semiconductor structure comprises: The method further includes forming a second doped region in the substrate, the second doped region being located above the first doped region and extending to an upper surface of the substrate, the initial wordline trench extending through the second doped region and into the first doped region, the first doped region being a doped region of a first conductivity type and the second doped region being a doped region of a second conductivity type.

[0015] According to some embodiments, performing a widening process on the initial wordline trench to form the wordline trench includes: Wet etching the initial word line trench with a wet etching solution to obtain the word line trench, wherein an etch rate of the wet etching solution for a portion of the initial word line trench in the first doped region is greater than an etch rate of the wet etching solution for a portion of the initial word line trench in the second doped region.

[0016] According to some embodiments, the first conductivity type is P-type, the second conductivity type is N-type, and the wet etching solution includes a mixture of aqueous ammonia and hydrogen peroxide.

[0017] According to some embodiments, the ion concentration in the first doped region is 1×10 16 cm 3 ~1×10 20 cm 3 and the ion concentration in the second doped region is 1×10 16 cm 3 ~1×10 20 cm 3 and The distance between the first doped region and the upper surface of the substrate is between 100 nm and 200 nm.

[0018] According to some embodiments, after forming the word line trenches, the method for manufacturing the semiconductor structure includes: forming a gate oxide layer on the sidewalls and bottom of the wordline trench; forming a wordline conductive layer on a surface of the gate oxide layer, the top of the wordline conductive layer being lower than the top of the wordline trench; Further comprising forming a fill dielectric layer in the wordline trench, the fill dielectric layer being on top of the wordline conductive layer and at least completely filling the wordline trench.

[0019] According to some embodiments, another aspect of the present disclosure provides a semiconductor structure, the semiconductor structure comprising a substrate and a wordline trench; a first doped region and a second doped region are provided in the substrate, the second doped region extends from an upper surface of the substrate into the substrate, the first doped region is located below the second doped region, the first doped region is a doped region of a first conductivity type, and the second doped region is a doped region of a second conductivity type; The wordline trench extends through the second doped region into the first doped region, and a width of the bottom of the wordline trench is greater than a minimum width of the wordline trench.

[0020] According to some embodiments, the ion concentration in the first doped region is 1×10 16 cm 3 ~1×10 20 cm 3 and the ion concentration in the second doped region is 1×10 16 cm 3 ~1×10 20 cm 3 and the first conductivity type is P type and the second conductivity type is N type; The distance between the first doped region and the upper surface of the substrate is between 100 nm and 200 nm.

[0021] According to some embodiments, the semiconductor structure further comprises a gate oxide layer, a wordline conductive layer, and a fill dielectric layer; the gate oxide layer is on the sidewalls and bottom of the wordline trench; the wordline conductive layer is located on a surface of the gate oxide layer, the top of the wordline conductive layer being lower than the top of the wordline trench; The fill dielectric layer is on top of the wordline conductive layer and completely fills at least the wordline trenches.

[0022] Embodiments of the present disclosure may have at least the following advantages.

[0023] In a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure, an initial word line trench is formed by forming an ion implantation region in a substrate, and then a widening process is performed on the initial word line trench to form the word line trench, thereby increasing the bottom cross-sectional area of ​​the formed word line trench, reducing the electrical resistance of the word lines formed in the subsequent manufacturing process, and avoiding an increase in power consumption and RC delay of the device.

[0024] The semiconductor structure according to the embodiments of the present disclosure includes wordline trenches having a relatively large bottom cross-sectional area, which reduces the electrical resistance of the wordlines formed during subsequent manufacturing steps and avoids increased power consumption and RC delay of the device.

[0025] The details of one or more embodiments of the disclosed embodiments are set forth in the drawings and description which follow. Other features, objects, and advantages of the disclosed embodiments will become apparent from the description, drawings, and claims. [Brief description of the drawings]

[0026] [Figure 1] FIG. 2 is a schematic cross-sectional view of a structure obtained after forming a mountain-shaped trench for a buried word line by dry etching in a buried word line process. [Diagram 2] FIG. 2 is a schematic cross-sectional view of the resulting structure after forming the word line structure in a buried word line process. [Diagram 3]1 is a flow chart of a method for manufacturing a semiconductor structure in accordance with one embodiment of the present disclosure. [Figure 4] FIG. 2 is a schematic cross-sectional view of a structure obtained at step S1 in a method for manufacturing a semiconductor structure according to one of the embodiments of the present disclosure. [Diagram 5] FIG. 2 is a schematic cross-sectional view of a structure obtained at step S2 in a method for manufacturing a semiconductor structure according to one of the embodiments of the present disclosure. [Figure 6] FIG. 2 is a schematic cross-sectional view of a structure obtained at step S3 in a method for manufacturing a semiconductor structure according to one of the embodiments of the present disclosure. [Figure 7] 1 is a flow chart of step S4 of a method for manufacturing a semiconductor structure according to one of the embodiments of the present disclosure. [Figure 8] FIG. 2 is a schematic cross-sectional view of a structure obtained in step S401 in a method for manufacturing a semiconductor structure according to one of the embodiments of the present disclosure. [Figure 9] FIG. 2 is a schematic cross-sectional view of a structure obtained in step S402 in a method for manufacturing a semiconductor structure according to one of the embodiments of the present disclosure. [Figure 10] 1 is a flow chart of a method for manufacturing a semiconductor structure according to one of the embodiments of the present disclosure after forming word line trenches. [Figure 11] FIG. 2 is a schematic cross-sectional view of a structure obtained at step S512 in a method for manufacturing a semiconductor structure according to one of the embodiments of the present disclosure. [Figure 12] FIG. 2 is a schematic cross-sectional view of a structure obtained in step S513 in a method for manufacturing a semiconductor structure according to one of the embodiments of the present disclosure. [Figure 13] FIG. 2 is a schematic cross-sectional view of a structure obtained in step S515 in a method for manufacturing a semiconductor structure according to one of the embodiments of the present disclosure, and further is a schematic cross-sectional view of a semiconductor structure according to one of the embodiments of the present disclosure. [Figure 14]FIG. 2 is a schematic cross-sectional view of a structure obtained by forming a second doped region in a substrate in a method for manufacturing a semiconductor structure according to one of the embodiments of the present disclosure. [Figure 15] FIG. 11 is a schematic cross-sectional view of a structure obtained at step S3 in a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] In order to more clearly describe the technical solutions of the embodiments of the present disclosure, the above briefly introduces the drawings used in the description of the embodiments. The drawings described above are only some examples of the embodiments of the present disclosure, and it is obvious to those skilled in the art that other drawings can also be obtained according to these drawings without creative work.

[0028] In order to make the embodiments of the present disclosure easier to understand, the embodiments of the present disclosure will be described more generally below with reference to the accompanying drawings. In the drawings, preferred embodiments of the present disclosure are shown. However, the embodiments of the present disclosure can be realized in various forms and should not be limited to the embodiments described herein. On the contrary, the purpose of providing these examples is to make the disclosed contents of the embodiments of the present disclosure clearer and more complete.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the embodiments of the present disclosure belong. In this specification, the terms used in the description of the embodiments of the present disclosure are only for describing particular embodiments and are not intended to limit the embodiments of the present disclosure.

[0030] It should be understood that when an element or layer is "located on" another element or layer, it may be directly on the other element or layer, or there may be an intervening element or layer therebetween. It should be understood that, although terms such as first, second, etc. may be used to describe each element, component, region, layer, dope type, and / or portion, these elements, components, regions, layers, dope types, and / or portions should not be limited to these terms. These terms are used only to distinguish one element, component, region, layer, dope type, or portion from another element, component, region, layer, dope type. Thus, without departing from the teachings of the embodiments of the present disclosure, a first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion, e.g., the first doped region may be referred to as a second doped region, and similarly, the second doped region may be referred to as a first doped region, where the first doped region and the second doped region are different doped regions, e.g., the first doped region may be a doped region of a first conductivity type and the second doped region may be a doped region of a second conductivity type, or the first doped region may be a doped region of a second conductivity type and the second doped region may be a doped region of a first conductivity type.

[0031] In this specification, spatial relationship terms such as "located below" and "located above" may be used to describe the relationship between an element or feature and another element or feature as shown in the figures. It should be understood that in addition to the orientation shown in the figures, the spatial relationship terms also include different orientations of the device during use and operation. For example, if the device in the figures is turned over, the orientation "located below other elements" would be described as being "above" the other elements or features. Thus, the term "located above" may include two orientations: above and below. Furthermore, the device may include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial terms used herein are interpreted accordingly.

[0032] As used herein, the singular forms "one," "one," and "said" may include the plural, unless the context clearly dictates otherwise. It should be further understood that when the terms "comprising" and / or "comprising" are used herein, the presence of stated features, integers, steps, operations, elements and / or components may be determined, but the presence or addition of one or more other features, integers, steps, operations, elements and / or components may not be precluded. Also, as used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0033] Embodiments of the present disclosure are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of embodiments of the present disclosure, and as such, variations in the shapes shown due to manufacturing techniques and / or tolerances are to be expected. Thus, the embodiments of the present disclosure are not limited to the particular shapes of regions illustrated herein but are to include deviations in shapes due, for example, to manufacturing techniques. Thus, the regions illustrated in the figures are exemplary in nature and these shapes are not intended to represent the actual shapes of regions on a device and are not intended to limit the scope of the embodiments of the present disclosure.

[0034] Please refer to Figures 1 to 15. It should be noted that the drawings provided in this embodiment are merely for illustrative purposes of the basic concepts of the embodiments of the present disclosure, and only components related to the embodiments of the present disclosure are shown in the drawings, and the drawings are not drawn according to the number, shape, and size of components in an actual implementation, and in an actual implementation, the shape, quantity, and ratio of each component may be arbitrarily changed, and the layout pattern of the components may also be more complicated.

[0035] In order to maintain a high degree of integration of semiconductor memory devices, the current mainstream DRAM process uses buried word lines as memory cell transistors, which can reduce the short channel effect to a certain extent and reduce the leakage phenomenon of the device.

[0036] In the DRAM buried word line process, as shown in FIG. 1, generally, first, an island structure is formed in a substrate 1' by dry etching, then a buried word line chevron trench is formed by dry etching, and then, as shown in FIG. 2, a thermal oxidation process is carried out to form a gate oxide layer 132', and then a metal 133' and a filling dielectric layer 134' are sequentially deposited from bottom to top to form a word line structure.

[0037] However, as the size of the memory cell decreases, the size of the buried wordline trench also decreases, and therefore the cross-sectional area of ​​the metal filled in the buried wordline trench also decreases, which results in an increase in the electrical resistance of the wordline, thereby resulting in higher power consumption and increased RC delay.

[0038] In view of the deficiencies of the prior art, some embodiments of the present disclosure provide a method for manufacturing a semiconductor structure.

[0039] Referring to FIG. 3, in one embodiment, the manufacturing method may include the following steps.

[0040] In step S1, a substrate is provided.

[0041] In step S2, an ion implantation region is formed in the substrate, with a space between an upper surface of the ion implantation region and an upper surface of the substrate.

[0042] In step S3, initial wordline trenches are formed in the substrate, the initial wordline trenches extending from the upper surface of the substrate into the ion implant region.

[0043] In step S4, a widening process is performed on the initial wordline trench to form a wordline trench, the width of the bottom of the wordline trench being greater than the minimum width of the wordline trench.

[0044] A method for manufacturing a semiconductor structure according to an embodiment of the present disclosure can include forming an initial wordline trench by forming an ion implantation region in a substrate, and then performing a widening process on the initial wordline trench to form the wordline trench, thereby increasing the bottom cross-sectional area of ​​the formed wordline trench and reducing the electrical resistance of the wordline formed in the subsequent manufacturing process, thus reducing the power consumption of the device and reducing the RC delay.

[0045] Hereinafter, the method for manufacturing a semiconductor structure according to the embodiment of the present disclosure will be described in more detail with reference to FIGS.

[0046] In step S1, as shown in FIG. 4, a substrate 1 is provided.

[0047] The embodiment of the present disclosure is not particularly limited to the material of the substrate 1. For example, the substrate 1 may include, but is not limited to, any one or more of a silicon substrate, a sapphire substrate, a glass substrate, a silicon carbide substrate, a gallium nitride substrate, or a gallium arsenide substrate. That is, the material of the substrate 1 may include, but is not limited to, any one or more of silicon, sapphire, glass, silicon carbide, gallium nitride, or gallium arsenide.

[0048] In some possible embodiments, before step S1, the manufacturing method may further include a step of etching the initial substrate to form an island structure as shown in Fig. 4. The embodiments of the present disclosure are not particularly limited to the etching method of the initial substrate. For example, the initial substrate can be etched by dry etching, but is not limited to this method.

[0049] 5, an ion implantation region 11 is formed in the substrate 1. Specifically, there must be a gap between the upper surface of the ion implantation region 11 and the upper surface of the substrate 1.

[0050] The embodiment of the present disclosure is not particularly limited to the ion concentration of the ion implantation region 11. For example, the ion concentration of the ion implantation region 11 is 1×1017 cm 3 ~1×10 22 cm 3 For example, the ion concentration of the ion implantation region 11 may be 1×10 17 cm 3 , 1×10 18 cm 3 , 1×10 19 cm 3 , 1×10 20 cm 3 , 1×10 21 cm 3 Or 1×10 22 cm 3 etc.

[0051] The embodiments of the present disclosure are not particularly limited with respect to the size of the distance between the ion implantation region 11 and the upper surface of the substrate 1. For example, the distance between the ion implantation region 11 and the upper surface of the substrate 1 may be 100 nm to 200 nm, and for example, the distance between the ion implantation region 11 and the upper surface of the substrate 1 may be 100 nm, 125 nm, 150 nm, 175 nm, or 200 nm.

[0052] In step S3, an initial word line trench 12 is formed in the substrate 1, as shown in Figure 6. Specifically, the initial word line trench 12 must extend from the upper surface of the substrate 1 to the ion implantation region 11.

[0053] The embodiment of the present disclosure is not particularly limited to a method for forming the initial word line trenches 12. For example, the initial word line trenches 12 can be formed in the substrate 1 by dry etching, but is not limited thereto.

[0054] For example, the step of forming the initial word line trench 12 in the silicon substrate can be performed in the following manner: For example, the silicon substrate is dry-etched using carbon tetrafluoride (CF4) as an etching gas, and the carbon tetrafluoride is dissociated into trifluoromethyl (CF3) and fluorine (F) neutral radicals in a capacitively coupled plasma (CCP) or inductively coupled plasma (ICP). These fluorine neutral radicals are highly reactive due to electronic unsaturation, and therefore easily react with the silicon substrate to form volatile silicon tetrafluoride (SiF4), and finally form the initial word line trench 12.

[0055] The embodiments of the present disclosure are not particularly limited with respect to the width of the initial wordline trench 12. In one embodiment, the width of the initial wordline trench 12 formed in step S2 may be 1 / 3 to 2 / 3 of the width of the wordline trench 13 formed in the subsequent manufacturing process, for example, the width of the initial wordline trench 12 formed in step S2 may be 1 / 3, 1 / 2, or 2 / 3, etc., of the width of the wordline trench 13 formed in the subsequent manufacturing process.

[0056] Additionally, the embodiments of the present disclosure are not particularly limited with respect to the depth of the initial wordline trenches 12. In one embodiment, the bottom of the initial wordline trenches 12 can be located within the ion implantation region 11.

[0057] 8 and 9, in step S4, a widening process is performed on the initial wordline trench 12 to form the wordline trench 13. Specifically, the width d1 of the bottom of the wordline trench 13 must be greater than the minimum width d2 of the wordline trench 13. In some embodiments, the minimum width of the wordline trench 13 may be the width of the top of the wordline trench 13 (the region above the bottom of the wordline trench 13), for example, the top of the wordline trench 13 is rectangular.

[0058] The embodiment of the present disclosure is not particularly limited to the manner of performing the widening process on the initial word line trench 12. Referring to Figure 7, in one embodiment, step S4 may include the following steps.

[0059] In step S401, as shown in Fig. 8, a sacrificial dielectric layer 131 is formed on the sidewall and bottom of the initial word line trench 12 by an in-situ process. Specifically, the thickness of the sacrificial dielectric layer 131 located in the ion implantation region 11 needs to be greater than the thickness of the remaining sacrificial dielectric layer 131.

[0060] In step S402, the sacrificial dielectric layer 131 is removed to form word line trenches 13, as shown in FIG.

[0061] In step S401, the embodiment of the present disclosure is not particularly limited to the in-situ process for forming the sacrificial dielectric layer 131.

[0062] It can be understood that if the substrate 1 includes a silicon substrate, after forming the initial wordline trench 12 by etching, the exposed sidewall and bottom of the initial wordline trench 12 should include silicon (Si). For example, the step of forming a sacrificial dielectric layer 131 on the sidewall and bottom of the initial wordline trench 12 can be performed in the following manner: Through a thermal oxidation (e.g., dry oxygen oxidation or wet oxygen oxidation) process, the silicon exposed after etching is oxidized to silicon dioxide (SiO2), and the sacrificial dielectric layer 131 is formed.

[0063] Because the reaction rate of silicon in the initial wordline trenches 12 in the ion implantation region 11 is relatively fast, more silicon is consumed, which causes the thickness of the sacrificial dielectric layer 131 formed in the ion implantation region 11 to be greater than the thickness of the remaining sacrificial dielectric layer 131.

[0064] The embodiment of the present disclosure is not particularly limited to the type of ions implanted in the ion implantation region 11. For example, the ion implantation region 11 may be formed by implanting fluorine ions into the substrate 1. Here, by implanting fluorine ions into the substrate 1, the activation energy of silicon element and oxygen (O) element can be reduced, and a Si-F bond with lower activity than a Si-Si bond is formed, that is, the Si-F bond is more easily broken, that is, the oxygen gas is more likely to break the Si-F and form a Si-O bond. Therefore, the oxidation rate of the formed ion implantation region 11 can be higher, and more silicon can be consumed, which is conducive to the formation of a thicker sacrificial dielectric layer 131.

[0065] For example, the step of implanting fluorine ions into the substrate 1 to form the ion implantation region 11 can be performed in the following manner: for example, boron trifluoride (BF3) is used as an ion source, the boron trifluoride is ionized, and then accelerated by an electric field to be sent to a mass analyzer, and the magnetic field of the mass analyzer is used to select fluorine ions (F+ or F++), and the energy of the fluorine ions is made to reach 120 KeV by the accelerator, and the doping concentration is made to be 1×10 in a region 100 nm to 200 nm away from the upper surface of the substrate 1. 17 cm 3 ~1×10 22 cm 3 The ion implantation region 11 is formed as follows.

[0066] In step S402, the embodiment of the present disclosure is not particularly limited to a method for removing the sacrificial dielectric layer 131. For example, the sacrificial dielectric layer 131 may be removed using a wet etching process, but is not limited thereto.

[0067] Additionally, the embodiments of the present disclosure are not particularly limited to the type of wet etching solution used in step S402, for example, but not limited to, diluted hydrofluoric acid (DHF) or buffered oxide etchant (BOE) can be used to completely remove the sacrificial dielectric layer 131.

[0068] Referring now to FIG. 10, in one embodiment, after forming the word line trenches 13, the manufacturing method may further include the following steps.

[0069] In step S511, ions of a first conductivity type are implanted into the substrate 1 to remove the ion implanted region 11 and form a first doped region 141. Specifically, the bottom of the first doped region 141 must be lower than the bottom of the word line trench 13, and the top of the first doped region 141 must be higher than the bottom of the word line trench 13.

[0070] In step S512, ions of a second conductivity type are implanted into the substrate 1 to remove the second doped region 142. Specifically, as shown in Fig. 11, the second doped region 142 needs to be located above the first doped region 141 and extend to the upper surface of the substrate 1, and the word line trench 13 needs to extend through the second doped region 142 into the first doped region 141, where the first doped region 141 is a doped region of a first conductivity type and the second doped region 142 is a doped region of a second conductivity type.

[0071] In step S513, a gate oxide layer 132 is formed on the sidewalls and bottom of the word line trenches 13, as shown in FIG.

[0072] In step S514, a word line conductive layer 133 is formed on the surface of the gate oxide layer 132. Specifically, the top of the word line conductive layer 133 is lower than the top of the word line trench 13.

[0073] In step S515, a filler dielectric layer 134 is formed in the wordline trenches 13. Specifically, as shown in FIG. 13, the filler dielectric layer 134 should be on top of the wordline conductive layer 133 and at least completely fill the wordline trenches 13.

[0074] The embodiment of the present disclosure is not particularly limited to the manner of forming the gate oxide layer 132. For example, the gate oxide layer 132 can be formed on the sidewalls and bottom of the wordline trenches 13 by any of a free radical oxidation process, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, a flowable chemical vapor deposition (FCVD) process, a high density plasma deposition (HDP) process, a plasma enhanced deposition process, or an atomic layer deposition process, but is not limited thereto.

[0075] Moreover, the embodiments of the present disclosure are not particularly limited with respect to the material of the gate oxide layer 132. For example, the gate oxide layer 132 may include, but is not limited to, any one or more of a silicon dioxide layer, a high-k dielectric material layer, or other dielectric material layer, etc., i.e., the material of the gate oxide layer 132 may include, but is not limited to, any one or more of a silicon dioxide layer, a high-k dielectric material, or other dielectric material, etc.

[0076] For example, the gate oxide layer 132 can be formed by a free radical oxidation process at 850° C. to 1050° C., for example, 850° C., 900° C., 950° C., 1000° C., or 1050° C. The gate oxide layer 132 can be formed by a free radical oxidation process at 850° C., 900° C., 950° C., 1000° C., or 1050° C. * ) or oxyhydrogen neutral free radical (OH * ) are intermediate products in the process of hydrogen (H2) and oxygen (O2) reacting to form water. Because the electrons outside the nucleus are not saturated and have strong chemical activity, the free radicals can break relatively weak chemical bonds and then form stronger chemical bonds, thus obtaining a higher quality gate oxide layer 132.

[0077] For example, in the process of forming the gate oxide layer 132 by the free radical oxidation process, the reaction pressure can be controlled within 20 Torr, and a lower pressure can increase the mean free path of the gas molecules, thus obtaining a longer radical lifetime.

[0078] The embodiments of the present disclosure are not particularly limited to the manner of forming the word line conductive layer 133. For example, the word line conductive layer 133 can be formed on the surface of the gate oxide layer 132 by any of a physical vapor deposition process, a chemical vapor deposition process, a fluid chemical vapor deposition process, a high density plasma deposition process, a plasma enhanced deposition process, or an atomic layer deposition process, etc., but are not limited thereto.

[0079] For example, the step of forming the word line conductive layer 133 on the surface of the gate oxide layer 132 can be performed in the following manner: for example, a word line conductive material layer is formed on the surface of the gate oxide layer 132, and a part of the word line conductive material layer is etched back to form the word line conductive layer 133.

[0080] Moreover, the embodiments of the present disclosure are not particularly limited to the material of the word line conductive layer 133. For example, the material of the word line conductive layer 133 may include, but is not limited to, one or more of titanium nitride (TiN), titanium (Ti), tungsten silicide (SiW), or tungsten (W), etc.

[0081] For example, the step of forming the word line conductive layer 133 on the surface of the gate oxide layer 132 may be performed in the following manner: depositing tungsten metal as the word line conductive material layer by a chemical vapor deposition process with good step coverage, in which the reaction gas may include, but is not limited to, silane (SiH4) and tungsten hexafluoride (WF6), and then etching back the word line conductive material layer by dry etching, in which the etching gas may include, but is not limited to, sulfur hexafluoride.

[0082] Embodiments of the present disclosure are not particularly limited with respect to the manner of forming the fill dielectric layer 134. For example, the fill dielectric layer 134 can be formed in the wordline trenches 13 by any one of a physical vapor deposition process or a chemical vapor deposition process.

[0083] The embodiment of the present disclosure is not particularly limited to the material of the filled dielectric layer 134. For example, the material of the filled dielectric layer 134 may include, but is not limited to, one or more of silicon dioxide, silicon nitride (Si3N4), or silicon oxynitride (SiON), etc.

[0084] For example, the step of forming the fill dielectric layer 134 in the word line trench 13 can be performed in the following manner: for example, by using chemical vapor deposition to react hexachlorodisilane (Si2Cl6, abbreviated as HCD) or dichlorosilane (SiH2Cl2, abbreviated as DCS) with ammonia (NH3) to form silicon nitride as the fill dielectric material layer, and then by chemical mechanical polishing (CMP) to form the fill dielectric layer 134.

[0085] In the embodiment of the present disclosure, the first conductivity type may be P-type, in which case the second conductivity type must be N-type.

[0086] For example, the step of forming the P-type first doped region 141 can be performed in the following manner: For example, boron ions (B+) generated by ionization of boron trifluoride are used as an ion source, and the P-type first doped region 141 doped with boron ions is formed by an ion implantation process.

[0087] For example, the step of forming the N-type second doped region 142 may be performed in the following manner: For example, phosphorus ions (P+) generated by vapor ionization of phosphorus (P) are used as an ion source to form the N-type second doped region 142 doped with phosphorus ions above the first doped region 141 by an ion implantation process.

[0088] The embodiment of the present disclosure is not particularly limited to the ion concentration in the first doped region 141 and the ion concentration in the second doped region 142. For example, the ion concentration in the first doped region 141 is 1×10 16 cm 3 ~1×10 20 cm 3 For example, the ion concentration in the first doped region 141 may be 1×10 16 cm 3 , 1×10 17 cm 3 , 1×10 18 cm 3 , 1×10 19 cm 3 Or 1×10 20 cm 3 For example, the ion concentration in the second doped region 142 may be 1×10 16 cm 3 ~1×10 20 cm 3 For example, the ion concentration in the second doped region 142 may be 1×10 16 cm 3 , 1×10 17 cm 3 , 1×10 18 cm 3 , 1×10 19 cm 3 Or 1×10 20 cm 3 etc.

[0089] For example, the ion implantation region 11 may be formed by implanting boron (B) ions into the substrate 1. When the ion implantation region 11 is formed by implanting boron ions into the substrate 1, the ion implantation region can be used as the first doped region 141. In this case, when the ion implantation region 11 (which may be the first doped region 141 in this embodiment) is formed in the substrate 1, the manufacturing method may further include a step of forming a second doped region 142 in the substrate 1.

[0090] Specifically, the second doped region 142 must be located above the first doped region 141 and extend to the upper surface of the substrate 1, as shown in FIG.

[0091] It should be noted that, regarding the manner of forming the first doped region 141 and the second doped region 142, the above content can be referred to, and the description will not be repeated here.

[0092] In this case, the structure resulting from step S3 may be as shown in FIG. 15, where the initial wordline trench 12 extends through the second doped region 142 into the first doped region 141, where the first doped region 141 is a doped region of a first conductivity type and the second doped region 142 is a doped region of a second conductivity type.

[0093] It should be noted that the above content can be referred to for the manner of forming the initial word line trench 12, and will not be described again here. In some embodiments, the width of the top of the initial word line trench 12 is, for example, smaller than 1 / 2 of the width of the top of the word line trench 13. If the width of the top of the initial word line trench 12 is relatively large, the width of the top of the initial word line trench 12 will be large in the subsequent widening process, so that the interval between the adjacent word line trenches 13 will be small, which is disadvantageous to the subsequent manufacture of the bit line contact pads, and the bit line contact pads are located between the word line trenches 13, and the interval between the word line trenches 13 is small, which results in the connection between the bit line contact pads and the word line trenches 13, that is, the bit line is directly connected to the word line, which affects the performance of the memory.

[0094] In one embodiment, the first conductivity type may be P-type, in which case the second conductivity type must be N-type.

[0095] In one embodiment, step S4 may further include the following steps:

[0096] A wet etching solution is used to wet etch the initial word line trench 12 (shown in FIG. 6) to obtain word line trench 13, and still referring to FIG. 11, FIG. 11 is a schematic cross-sectional view of the structure after obtaining word line trench 13 in this embodiment.

[0097] Specifically, the etching rate of the wet etching solution for some of the initial word line trenches 12 in the first doped region 141 must be greater than the etching rate of the wet etching solution for some of the initial word line trenches 12 in the second doped region 142 so that the width of the bottom of the formed word line trenches 13 is greater than the minimum width of the word line trenches 13.

[0098] The embodiments of the present disclosure are not particularly limited to the type of wet etching solution, for example, the wet etching solution may include, but is not limited to, a mixture of ammonia water and hydrogen peroxide (H2O2).

[0099] During the wet etching of the initial word line trench 12, the hole concentration of the first doped region 141 is much higher than that of the second doped region 142 located thereon, so that hydrogen peroxide ions (HO) formed after ionization of hydrogen peroxide are ionized. 2- ) tends to bond with the silicon at the surface of the first doped region 141, which has a higher hole concentration, and reacts to form silicon dioxide, which then reacts with the hydroxide ions (OH - ) reacts with silicate ions (SiO3 2- ) and dissolved in solution. Thus, the wet etching rate of the first doped region 141 is relatively fast and consumes more silicon, while the wet etching rate of the second doped region 142 located above the first doped region 141 is relatively slow and consumes less silicon. In this way, the bottom of the word line trench 13 formed is wider.

[0100] Continuing to refer to Figures 12 and 13, in one embodiment, after wet etching the initial word line trenches 12 using a wet etching solution to obtain word line trenches 13, the manufacturing method may further include the following steps.

[0101] As shown in FIG. 12, a gate oxide layer 132 is formed on the sidewalls and bottom of the wordline trench 13, and a wordline conductive layer 133 is formed on the surface of the gate oxide layer 132, with the top of the wordline conductive layer 133 being lower than the top of the wordline trench 13; as shown in FIG. 13, a filling dielectric layer 134 is formed in the wordline trench 13, with the filling dielectric layer 134 being located on the top of the wordline conductive layer 133 and at least completely filling the wordline trench 13.

[0102] It should be noted that the manners of forming the gate oxide layer 132, the word line conductive layer 133 and the filling dielectric layer 134 can be referred to above, and will not be described again here.

[0103] It should be understood that although the steps in the flowcharts of Figures 3, 7, and 10 are shown sequentially according to the direction of the arrows, the steps are not necessarily performed in the order indicated by the arrows. Unless expressly specified herein, the order of execution of the steps is not strictly limited, and the steps may be performed in other orders. Furthermore, at least some of the steps in Figures 3, 7, and 10 may include multiple steps or multiple stages, and the steps or stages are not necessarily performed simultaneously, but may be performed at different times, and the order of execution of the steps or stages is not necessarily performed sequentially, but may be performed in order or alternately with other steps or at least some of the steps or stages in other steps.

[0104] According to some embodiments, embodiments of the present disclosure further provide a semiconductor structure.

[0105] With continued reference to FIG. 13, in one embodiment, the semiconductor structure may comprise a substrate 1 and a wordline trench 13 .

[0106] A first doped region 141 and a second doped region 142 are provided in the substrate 1 141, where the second doped region 142 extends from an upper surface of the substrate 1 into the substrate 1 and the first doped region 141 is located below the second doped region 142, specifically, the first doped region 141 may be a doped region of a first conductivity type, and in this case, the second doped region 142 may be a doped region of a second conductivity type.

[0107] The word line trench 13 extends through the second doped region 142 into the first doped region 141 ; specifically, the width of the bottom of the word line trench 13 must be greater than the minimum width of the word line trench 13 .

[0108] The semiconductor structure according to the embodiments of the present disclosure includes wordline trenches 13 with a relatively large bottom cross-sectional area, which can reduce the electrical resistance of the wordlines formed during subsequent manufacturing steps, thus reducing the power consumption and reducing the RC delay of the device.

[0109] The embodiment of the present disclosure is not particularly limited with respect to the size of the distance between the first doped region 141 and the upper surface of the substrate 1. For example, the distance between the first doped region 141 and the upper surface of the substrate 1 may be 100 nm to 200 nm, for example, the distance between the first doped region 141 and the upper surface of the substrate 1 may be 100 nm, 125 nm, 150 nm, 175 nm, or 200 nm.

[0110] With continued reference to FIG. 13, in one embodiment, the semiconductor structure may further comprise a gate oxide layer 132, a wordline conductive layer 133, and a filler dielectric layer .

[0111] Specifically, gate oxide layer 132 is located on the sidewalls and bottom of wordline trench 13, wordline conductive layer 133 is located on the surface of gate oxide layer 132, the top of wordline conductive layer 133 is lower than the top of wordline trench 13, and fill dielectric layer 134 is located on top of wordline conductive layer 133 and completely fills at least wordline trench 13.

[0112] It should be noted that all the manufacturing methods of the embodiments of the present disclosure can be used to manufacture corresponding semiconductor structures, and therefore the technical features between the method embodiments and the structure embodiments can be mutually replaced and supplemented on the premise that there is no contradiction, thereby allowing those skilled in the art to understand the technical content of the embodiments of the present disclosure.

[0113] Each embodiment in this specification is described step by step, with each embodiment focusing on the differences from other embodiments, and the same or similar parts between each embodiment can be cross-referenced.

[0114] The technical features of the above embodiments can be combined in any manner, and for the sake of brevity, not all possible combinations of the technical features in the above embodiments are described, but as long as there is no contradiction in the combinations of these technical features, they are all within the scope of the present invention.

[0115] The above examples only describe some embodiments of the embodiments of the present disclosure, and the description is relatively specific and detailed, but should not be construed as limiting the scope of the present application. It should be noted that those skilled in the art can make some modifications or improvements without departing from the concept of the embodiments of the present disclosure, and all such modifications or improvements are included in the protection scope of the embodiments of the present disclosure. Therefore, the protection scope of the embodiments of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. 1. A method for manufacturing a semiconductor structure, comprising the steps of: Providing a substrate; forming an ion implantation region in the substrate, the ion implantation region having an upper surface spaced apart from an upper surface of the substrate; forming initial wordline trenches in the substrate, the initial wordline trenches extending from an upper surface of the substrate into the ion implanted region; performing a widening process on the initial wordline trench to form a wordline trench, the width of a bottom of the wordline trench being greater than a minimum width of the wordline trench; performing a widening process on the initial word line trench to form the word line trench; forming a sacrificial dielectric layer on sidewalls and a bottom of the initial wordline trench by an in-situ process, the thickness of the sacrificial dielectric layer located in the ion implantation region being greater than the thickness of the remaining sacrificial dielectric layer; removing the sacrificial dielectric layer to form the wordline trenches.

2. implanting fluorine ions or boron ions into the substrate to form the ion implanted region; A method for manufacturing a semiconductor structure according to claim 1.

3. The ion concentration in the ion implantation region is 1×10 １７ cm ３ ~1×10 ２２ cm ３ and the distance between the ion implantation region and the upper surface of the substrate is 100 nm to 200 nm; A method for manufacturing a semiconductor structure according to claim 2.

4. After forming the word line trenches, the method for fabricating the semiconductor structure includes: implanting ions of a first conductivity type into the substrate, removing the implanted region, and forming a first doped region, a bottom of the first doped region being lower than a bottom of the wordline trench and a top of the first doped region being higher than a bottom of the wordline trench; implanting ions of a second conductivity type into the substrate to form a second doped region, the second doped region being above the first doped region and extending to an upper surface of the substrate, the wordline trenches extending through the second doped region and into the first doped region, the first doped region being a doped region of a first conductivity type and the second doped region being a doped region of a second conductivity type; forming a gate oxide layer on the sidewalls and bottom of the wordline trench; forming a wordline conductive layer on a surface of the gate oxide layer, the top of the wordline conductive layer being lower than the top of the wordline trench; forming a fill dielectric layer in the wordline trench, the fill dielectric layer being on top of the wordline conductive layer and completely filling at least the wordline trench. A method for manufacturing a semiconductor structure according to any one of claims 1 to 3.

5. The first conductivity type is P type and the second conductivity type is N type. A method for manufacturing a semiconductor structure according to claim 4.

6. The ion concentration in the first doped region is 1×10 １６ cm ３ ~1×10 ２０ cm ３ and the ion concentration in the second doped region is 1×10 １６ cm ３ ~1×10 ２０ cm ３ That is, A method for manufacturing a semiconductor structure according to claim 4.

7. The ion implanted region is a first doped region, and prior to forming the ion implanted region in the substrate, the method of manufacturing the semiconductor structure includes: forming a second doped region in the substrate, the second doped region being above the first doped region and extending to an upper surface of the substrate, the initial wordline trenches extending through the second doped region and into the first doped region, the first doped region being a doped region of a first conductivity type and the second doped region being a doped region of a second conductivity type. A method for manufacturing a semiconductor structure according to claim 1.

8. performing a widening process on the initial word line trench to form the word line trench; wet etching the initial word line trench with a wet etching solution to obtain the word line trench, wherein an etch rate of the wet etching solution for a portion of the initial word line trench in the first doped region is greater than an etch rate of the wet etching solution for a portion of the initial word line trench in the second doped region; A method for manufacturing a semiconductor structure according to claim 7.

9. the first conductivity type is P-type, the second conductivity type is N-type, and the wet etching solution contains a mixture of ammonia water and hydrogen peroxide; The method of claim 8 .

10. The ion concentration in the first doped region is 1×10 １６ cm ３ ~1×10 ２０ cm ３ and the ion concentration in the second doped region is 1×10 １６ cm ３ ~1×10 ２０ cm ３ and the distance between the first doped region and the upper surface of the substrate is between 100 nm and 200 nm; A method for manufacturing a semiconductor structure according to claim 7.

11. After forming the word line trenches, the method for fabricating the semiconductor structure includes: forming a gate oxide layer on the sidewalls and bottom of the wordline trench; forming a wordline conductive layer on a surface of the gate oxide layer, a top of the wordline conductive layer being lower than a top of the wordline trench; forming a fill dielectric layer in the wordline trench, the fill dielectric layer being on top of the wordline conductive layer and completely filling at least the wordline trench. A method for manufacturing a semiconductor structure according to any one of claims 7 to 10.

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