Semiconductor device and method for fabricating same

Abstract

The embodiments of the present invention disclose a semiconductor device and a method for fabricating the same, the semiconductor device includes an active area and a non-active area surrounding the active area, the semiconductor device further includes a substrate, a plurality of semiconductor layers located on one side of the substrate, and at least one shielding structure located on one side of the substrate, the shielding structure being electrically connected to a predetermined potential to form an electric field or a zero electric field from the active area to the non-active area. The technical solution of the embodiments of the present invention provides a shielding structure and electrically connects the shielding structure to a predetermined potential to form an electric field or a zero electric field from the active area to the non-active area, effectively shielding silver ions and inhibiting their migration to the central region of the front surface of the semiconductor chip, so as to obtain a semiconductor device with stable performance.

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present invention relate to the field of semiconductor technology, and more particularly to semiconductor devices and methods for making same. [Background technology]

[0002] After the fabrication of the semiconductor chip is completed, the semiconductor chip needs to be packaged to form a semiconductor device. The semiconductor device is generally packaged using a patching method. Among the methods for patching semiconductor devices, the silver paste patching method has low cost, so the silver paste patching method is generally used to electrically connect some metal connection electrodes in the semiconductor device to metal electrodes in the package case by the patching silver paste.

[0003] However, due to the patching of the silver paste, electrochemical migration of silver ions occurs under the action of an electric field, and the silver ions move to the front surface of the semiconductor chip and come into contact with other electrodes in the central region of the front surface of the semiconductor chip, leading to increased leakage or a short circuit, making it impossible to use the semiconductor device normally. Summary of the Invention [Problem to be solved by the invention]

[0004] In view of this, an embodiment of the present invention provides a semiconductor device and a method for manufacturing the same, which provides a shielding structure and electrically connects the shielding structure to a predetermined potential to form an electric field or a zero electric field from the active region to the non-active region, effectively shielding silver ions and suppressing their migration to the central region of the front surface of the semiconductor chip, thereby obtaining a semiconductor device with stable performance. [Means for solving the problem]

[0005] In a first aspect, an embodiment of the present invention provides a semiconductor device including an active area and a non-active area surrounding the active area, Semiconductor devices are A substrate; a plurality of semiconductor layers disposed on one side of a substrate; and at least one shielding structure located on one side of the substrate, the shielding structure being electrically connected to a predetermined potential to create an electric field or a zero electric field from the active area to the non-active area.

[0006] Optionally, the plurality of semiconductor layers includes a conductive region and a two-dimensional electron gas elimination region located in the inactive region, the two-dimensional electron gas elimination region being located between the conductive region and the active region, the conductive region being a shielding structure, and / or The semiconductor device further includes a dielectric layer located on a side of the multiple semiconductor layers farther from the substrate, and at least one conductive wiring located on a side of the dielectric layer farther from the multiple semiconductor layers, the conductive wiring being a shielding structure.

[0007] Optionally, the shielding structure includes at least a first shielding portion, the first shielding portion being located on a side of the inactive area away from the active area.

[0008] Optionally, the shielding structure further comprises a second shielding portion and a third shielding portion; the first shielding portion is electrically connected to the second shielding portion and the third shielding portion, and an extension direction of the first shielding portion intersects both an extension direction of at least a part of the second shielding portion and an extension direction of at least a part of the third shielding portion; Shielding structures are located on at least three sides of the non-active area away from the active area.

[0009] Optionally, the shielding structure includes a fourth shielding portion and a fifth shielding portion, the fourth shielding portion extends along a first direction, and the fifth shielding portion extends along a second direction, the first direction and the second direction intersect and are both parallel to a plane on which the substrate is located; the fourth shielding portion includes a plurality of first sub-shielding structures, and two first sub-shielding structures adjacent to each other along the first direction are offset in the second direction and overlap each other in vertical projection onto a first plane, and the first plane is parallel to the first direction and perpendicular to a plane on which the substrate is located; and / or The fifth shielding portion includes a plurality of second sub-shielding structures, and two adjacent second sub-shielding structures along the second direction are offset in the first direction and overlap each other in vertical projection onto a second plane, which is parallel to the second direction and perpendicular to the plane in which the substrate is located.

[0010] Optionally, at least some of the shielding structures are free of a dielectric layer on a side remote from the substrate.

[0011] Optionally, the plurality of semiconductor layers includes a conductive region and a two-dimensional electron gas elimination region located in the inactive region; The conductive region is a two-dimensional electron gas forming region or a semiconductor doped region.

[0012] Optionally, the semiconductor device further includes a gate located on a side of the plurality of semiconductor layers away from the substrate and located in the active region; The semiconductor device further includes a gate bonding pad located on a side of the plurality of semiconductor layers away from the substrate and located in the non-active region, the gate bonding pad being electrically connected to the gate; The at least one shielding structure includes a gate shielding structure, which is for shielding and protecting the gate bonding pad, and the potential of the predetermined potential is equal to or greater than zero.

[0013] Optionally, the semiconductor device further includes a drain located on a side of the plurality of semiconductor layers away from the substrate and located in the active region; The semiconductor device further includes a drain bond pad located on a side of the plurality of semiconductor layers away from the substrate and located in the non-active region, the drain bond pad being electrically connected to the drain; The at least one shielding structure includes a drain shielding structure, which is for shielding and protecting the drain bonding pad, and the potential of the predetermined potential is equal to or greater than zero.

[0014] In a second aspect, an embodiment of the present invention provides a method for producing a semiconductor device as provided in the previous aspect, comprising the steps of: Preparing a substrate; forming a plurality of semiconductor layers on one side of a substrate; The present invention further provides a method for fabricating a semiconductor device, the method including fabricating at least one shielding structure on one side of the substrate, the shielding structure being electrically connected to a predetermined potential to form an electric field or a zero electric field from the active area to the non-active area.

[0015] In the semiconductor device according to the embodiment of the present invention, a shielding structure is added and electrically connected to a predetermined potential, thereby forming an electric field or a zero electric field from the active area to the non-active area, effectively shielding silver ions and inhibiting their migration to the central area of ​​the front surface of the semiconductor chip, thereby ensuring normal operation of the semiconductor device.

[0016] In a first aspect, an embodiment of the present invention provides a semiconductor device including an operating area and a scribe area surrounding the operating area, the operating area including an active area and a passive area surrounding the active area; The semiconductor device is A substrate; a plurality of semiconductor layers located on one side of the substrate; at least one bonding pad located on a side of the plurality of semiconductor layers away from the substrate and located in the passive region; The present invention provides a semiconductor device further comprising at least one shielding structure located on a side of the plurality of semiconductor layers away from the substrate, the shielding structure being for shielding and protecting the bonding pad, the shielding structure being electrically connected to a predetermined potential, the predetermined potential U satisfying U≧0.

[0017] Optionally, the semiconductor device further includes a gate located on a side of the plurality of semiconductor layers away from the substrate and located in the active region; the at least one bonding pad includes a gate bonding pad, the gate bonding pad being electrically connected to the gate; The at least one shielding structure includes a gate shielding structure, which is for shielding and protecting the gate bonding pad.

[0018] Optionally, the semiconductor device further includes a drain located on a side of the plurality of semiconductor layers away from the substrate and located in the active region; The at least one bond pad further includes a drain bond pad, the drain bond pad being electrically connected to the drain; The at least one shielding structure includes a drain shielding structure, which is for shielding and protecting the drain bonding pad.

[0019] Optionally, the active area further comprises a plurality of fixed potential structures; The shielding structure is electrically connected to the fixed potential structure.

[0020] Optionally, the fixed potential structure includes a source and the shielding structure is electrically connected to the source.

[0021] Optionally, the shielding structure comprises a gate shielding structure; The fixed potential structure includes a drain, and the gate shield structure is electrically connected to the drain.

[0022] Alternatively, the sources include a first source and an Nth source arranged along a first direction, the first direction being parallel to a plane in which the substrate is located, the first source being located at a first end of the active region, and the Nth source being located at a second end of the active region, the first end and the second end being provided opposite to each other along the first direction; The shielding structure is electrically connected to the first source and the Nth source, respectively, and the gate bonding pad is located within an area defined by the shielding structure and the active area.

[0023] Optionally, the source is electrically connected to a source back electrode through a via hole; The overlapping area between the vertical projection of the shielding structure onto the plane on which the substrate is located and the vertical projection of the via hole onto the plane on which the substrate is located is S1; The area of ​​the vertical projection of the via hole onto the plane on which the substrate is located is S2; Here, S1 <S2 / 4である。

[0024] Optionally, a vertical projection of the shielding structure onto a plane in which the substrate lies and a vertical projection of the via hole onto the plane in which the substrate lies do not overlap.

[0025] Optionally, the shielding structure includes a first shielding portion, a second shielding portion, and a third shielding portion, the second shielding portion being connected to the first shielding portion and the third shielding portion, respectively; The second shielding portion is located in the scribe region, the first shielding portion is located in the operating region and is electrically connected to the first source, and the third shielding portion is located in the operating region and is electrically connected to the N source.

[0026] Optionally, the semiconductor device further includes a first dielectric layer located on a side of the plurality of semiconductor layers away from the substrate and located in the passive region; the first shielding portion and the third shielding portion are both located on a side of the first dielectric layer farther from the substrate, Along a direction perpendicular to the substrate, a thickness of the shielding structure is greater than a thickness of the first dielectric layer such that the first shielding portion and the third shielding portion are both electrically connected to the second shielding portion.

[0027] Optionally, the semiconductor device further includes a first dielectric layer located on a side of the plurality of semiconductor layers away from the substrate and located in the passive region; Along a direction perpendicular to the substrate, a thickness of the source is greater than a thickness of the first dielectric layer such that the first shielding portion and the third shielding portion are both electrically connected to the source.

[0028] Optionally, the semiconductor device further comprises a second dielectric layer located in the active region; the second dielectric layer covers the first shielding portion, the third shielding portion, and the source; In a direction perpendicular to the substrate, the sum of the thicknesses of the first dielectric layer, the first shielding portion, and the second dielectric layer is greater than the thickness of the source, such that the second dielectric layer located on the side of the first shielding portion farther from the substrate is connected to the second dielectric layer located on the side of the source farther from the substrate.

[0029] Optionally, the shielding structure includes a first shielding portion, a second shielding portion, and a third shielding portion, the second shielding portion being connected to the first shielding portion and the third shielding portion, respectively; The first shielding portion, the second shielding portion and the third shielding portion are all located in the active region, the first shielding portion is electrically connected to the first source, and the third shielding portion is electrically connected to the N source.

[0030] Optionally, the semiconductor device further includes at least one dielectric layer located on a side of the plurality of semiconductor layers away from the substrate and located in the passive region; At least one of the dielectric layers includes a first surface located on a side of the plurality of semiconductor layers that is remote from the substrate; the shielding structure includes a second surface of the plurality of semiconductor layers located away from the substrate; Along a direction perpendicular to the substrate, the second surface is located on the side of the first surface that is farther from the substrate.

[0031] Optionally, the source includes a multi-layer source metal layer; The shielding structure includes one shielding metal layer, and the shielding metal layer and any one of the multiple source metal layers are provided in the same layer and are made of the same material, or the shielding structure includes multiple shielding metal layers, and the multiple shielding metal layers and the multiple source metal layers have a one-to-one correspondence, and the corresponding shielding metal layer and source metal layer are provided in the same layer and are made of the same material.

[0032] In a second aspect, an embodiment of the present invention provides a method for producing a semiconductor device according to any one of the above claims, comprising the steps of: Preparing a substrate; forming a plurality of semiconductor layers on one side of the substrate; fabricating at least one bonding pad on a side of the plurality of semiconductor layers remote from the substrate in the passive region; The present invention further provides a method for fabricating a semiconductor device, the method including: fabricating at least one shielding structure on a side of the plurality of semiconductor layers away from the substrate, the shielding structure being for shielding and protecting the bonding pad, the shielding structure being electrically connected to a predetermined potential, the predetermined potential U satisfying U≧0.

[0033] In the semiconductor device according to the embodiment of the present invention, a shielding structure is added and the shielding structure is electrically connected to a predetermined potential, thereby effectively blocking the migration of silver ions in the silver paste for patching to the bonding pad during packaging, ensuring stable performance of the bonding pad and the electrodes connected to the bonding pad, avoiding the occurrence of short circuits between the bonding pad and the electrode connected to the bonding pad and the source, and ensuring normal operation of the semiconductor device.

[0034] In a first aspect, an embodiment of the present invention provides a semiconductor device including an operating area and a scribe area surrounding the operating area, the operating area including an active area and a passive area surrounding the active area; The semiconductor device is A substrate; a plurality of semiconductor layers located on one side of the substrate; a gate located on a side of the plurality of semiconductor layers away from the substrate and located in the active region; at least one bonding pad located on a side of the plurality of semiconductor layers away from the substrate and located in the passive region, the bonding pad including at least a gate bonding pad, the gate bonding pad being electrically connected to the gate; The present invention provides a semiconductor device further comprising at least one shielding structure located on a side of the plurality of semiconductor layers away from the substrate, the shielding structure including a gate shielding structure, the gate shielding structure being for shielding and protecting the gate bonding pad.

[0035] Optionally, the semiconductor device further includes a drain located on a side of the plurality of semiconductor layers away from the substrate and located in the active region; The bonding pad further includes a drain bonding pad, the drain bonding pad being electrically connected to the drain; The shielding structure further includes a drain shielding structure, which is for shielding and protecting the drain bonding pad.

[0036] Optionally, the shielding structure is electrically connected to a predetermined potential, where the predetermined potential U satisfies U≧0.

[0037] Optionally, the active area further comprises a plurality of fixed potential structures; The shielding structure is electrically connected to the fixed potential structure.

[0038] Optionally, the shielding structure includes a first shielding portion, a second shielding portion, and a third shielding portion, the second shielding portion being connected to the first shielding portion and the third shielding portion, respectively; The shape of the connection portion between the first shielding portion and the second shielding portion includes an "L" shape or a "T" shape; The shape of the connection portion between the third shielding portion and the second shielding portion includes an "L" shape or a "T" shape.

[0039] Optionally, the shielding structure includes a first portion extending along a first direction and a second portion extending along a second direction, the first direction and the second direction are both parallel to a plane on which the substrate is located, and the first direction and the second direction intersect; A connecting corner between the first portion and the second portion includes a chamfered corner or an arc-shaped corner, or the shielding structure further includes a third portion, the third portion is connected to the first portion and the second portion, respectively, and an included angle between the third portion and the first portion is an obtuse angle, and an included angle between the third portion and the second portion is an obtuse angle.

[0040] Optionally, the shielding structure includes a first portion extending along a first direction and a second portion extending along a second direction, the first direction and the second direction are both parallel to a plane on which the substrate is located, and the first direction and the second direction intersect; the semiconductor device includes a first boundary extending along the first direction and a second boundary extending along the second direction; A minimum distance L1 between the first portion and the first boundary satisfies L1>30 μm; The minimum distance L2 between the second portion and the second boundary satisfies L2>30 μm.

[0041] Optionally, the shielding structure includes a first portion extending along a first direction and a second portion extending along a second direction, the first direction and the second direction are both parallel to a plane on which the substrate is located, and the first direction and the second direction intersect; The extension width D1 of the first portion in the second direction satisfies D1>10 μm, The second portion has an extension width D2 in the first direction that satisfies D2>10 μm.

[0042] Optionally, a minimum pitch L3 between a vertical projection of the shielding structure onto the plane in which the substrate lies and a vertical projection of the gate bonding pad onto the plane in which the substrate lies satisfies L3>10 μm.

[0043] A minimum pitch L4 between the vertical projection of the shielding structure onto the plane on which the substrate lies and the vertical projection of the drain bonding pad onto the plane on which the substrate lies satisfies L4>10 μm.

[0044] In a second aspect, an embodiment of the present invention provides a method for producing a semiconductor device according to any one of the above claims, comprising the steps of: Preparing a substrate; forming a plurality of semiconductor layers on one side of the substrate; fabricating a gate in the active area on a side of the plurality of semiconductor layers away from the substrate; fabricating at least one bonding pad in the passive region on a side of the plurality of semiconductor layers remote from the substrate, the bonding pad including at least a gate bonding pad, the gate bonding pad being electrically connected to the gate; and fabricating at least one shielding structure on a side of the plurality of semiconductor layers away from the substrate, the shielding structure including a gate shielding structure for shielding and protecting the gate bonding pad. Effect of the Invention

[0045] In the semiconductor device according to the embodiment of the present invention, by adding a shielding structure, the migration of silver ions in the silver paste for patching to the bonding pad during packaging is effectively blocked, the stable performance of the bonding pad and the electrodes connected to the bonding pad is ensured, the occurrence of short circuits between the bonding pad and the electrodes connected to the bonding pad and the source is avoided, and the semiconductor device can be ensured to operate normally. [Brief description of the drawings]

[0046] [Figure 1] FIG. 1 is a schematic diagram showing the structure of a semiconductor device according to the prior art. [Diagram 2] FIG. 2 is a schematic plan view of the structure of a semiconductor device according to an embodiment of the present invention. [Diagram 3] FIG. 3 is a schematic plan view of the structure of another semiconductor device according to an embodiment of the present invention. [Figure 4] FIG. 4 is a schematic plan view of the structure of another semiconductor device according to an embodiment of the present invention. [Diagram 5] FIG. 5 is a schematic cross-sectional view of the semiconductor device taken along line AA' in FIG. [Figure 6]FIG. 6 is a schematic cross-sectional view of another semiconductor device taken along line AA' in FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view of another semiconductor device taken along line AA' in FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view of another semiconductor device taken along line AA' in FIG. [Figure 9] FIG. 9 is a schematic plan view of the structure of another semiconductor device according to an embodiment of the present invention. [Figure 10] FIG. 10 is a schematic plan view of the structure of another semiconductor device according to an embodiment of the present invention. [Figure 11] FIG. 11 is a schematic plan view of the structure of a semiconductor device according to an embodiment of the present invention. [Figure 12] FIG. 12 is a schematic plan view of the structure of another semiconductor device according to an embodiment of the present invention. [Figure 13] FIG. 13 is a schematic plan view of the structure of another semiconductor device according to an embodiment of the present invention. [Figure 14] FIG. 14 is a schematic plan view of the structure of another semiconductor device according to an embodiment of the present invention. [Figure 15] FIG. 15 is a schematic cross-sectional view of the semiconductor device of FIG. 14 taken along line AA'. [Figure 16] FIG. 16 is a schematic cross-sectional view of the semiconductor device of FIG. 14 taken along line BB'. [Figure 17] FIG. 17 is a schematic plan view of the structure of another semiconductor device according to an embodiment of the present invention. [Figure 18] FIG. 18 is a schematic cross-sectional view of the semiconductor device of FIG. 17 taken along line CC'. [Figure 19] FIG. 19 is a schematic plan view of the structure of another semiconductor device according to an embodiment of the present invention. [Figure 20] FIG. 20 is a schematic plan view of the structure of another semiconductor device according to an embodiment of the present invention. [Figure 21] FIG. 21 is a partial plan view of a shielding structure according to an embodiment of the present invention. [Figure 22] FIG. 22 is a partial plan view of another shielding structure according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0047] The present invention will be described in more detail below with reference to the drawings and examples. It is to be understood that the specific examples described herein are merely for the purpose of interpreting the present invention, and are not intended to limit the present invention. It should also be noted that, for the sake of convenience, the drawings show only some structures related to the present invention, rather than all structures.

[0048] 1 is a structural schematic diagram of a semiconductor device in the prior art. As shown in FIG. 1, the semiconductor device includes a source 12 and a gate 13 located in an active region 11, and a gate bonding pad 14 located in a passive region, and the gate bonding pad 14 is electrically connected to a plurality of gates 13, and the source 12 is electrically connected to a source back electrode (not shown) through a via hole. When forming a semiconductor device by packaging, the source back electrode is electrically connected to an electrode in a package case through a patching silver paste. Due to the patching of the silver paste, electrochemical migration of silver ions occurs under the action of an electric field, and the silver ions migrate to the front surface of the semiconductor chip and contact the gate in the central region of the front surface of the semiconductor chip, leading to an increase in leakage or a short circuit between the gate 13 and the source 12, and the semiconductor device cannot be used normally.

[0049] In view of the above problems, a semiconductor device according to an embodiment of the present invention includes an active area and a non-active area surrounding the active area, and the semiconductor device further includes a substrate, a plurality of semiconductor layers located on one side of the substrate, and at least one shielding structure located on one side of the substrate, the shielding structure being electrically connected to a predetermined potential and for forming an electric field or a zero electric field from the active area to the non-active area. By using the above technical solution, the shielding structure is electrically connected to the predetermined potential, so that an electric field or a zero electric field can be generated to suppress the migration of silver ions to the central area of ​​the front surface of the semiconductor chip, and the normal operation of the semiconductor device can be ensured.

[0050] The above is the core idea of ​​the present invention, and the technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the drawings in the embodiments of the present invention. Based on the embodiments of the present invention, other embodiments obtained by those skilled in the art without paying creative labor shall all be included in the protection scope of the present invention.

[0051] FIG. 2 is a schematic planar structure diagram of a semiconductor device according to an embodiment of the present invention, which includes an active area aa and a non-active area na surrounding the active area, and further includes a substrate 21, a plurality of semiconductor layers (not shown) located on one side of the substrate 21, and at least one shielding structure 31 located on one side of the substrate, the shielding structure 31 being electrically connected to a predetermined potential (not shown) for forming an electric field or a zero electric field from the active area aa to the non-active area na.

[0052] 2, the semiconductor device includes an active region 32 and a scribe region 33 surrounding the active region, and the active region 32 includes an active region aa and a passive region bb surrounding the active region, where the "inactive region na" specifically refers to the scribe region 33 and the passive region bb in the active region 32.

[0053] Specifically, the operating region 32 can be understood as the region where the semiconductor device operates, and includes an active region aa and a passive region bb, the active region aa can be understood as the region where two-dimensional electron gas, electrons or holes exist, and its operating state and characteristics are affected by an external circuit, and is the active operating region of the semiconductor device, and the passive region bb can be understood as the region outside the active region aa that participates in the operation of the device but whose operating state is not affected by the external circuit. The scribe region 33 refers to the region where the semiconductor device is scribed and cut to form multiple independent semiconductor devices.

[0054] The semiconductor device further includes a gate, a source, and a drain, which are usually located on the side of the semiconductor layer far from the substrate and are located in the active area aa. Usually, the gate is connected to a reverse bias, the drain is connected to a forward bias, and the source is at zero potential. Since there is a potential difference between the source and the gate, an electric field is formed from the edge of the semiconductor chip toward the center region, so that the silver ions move to the center region of the semiconductor chip and contact the gate, leading to an increase in leakage or a short circuit between the gate and the source. Similarly, the silver ions may also contact the drain when moving, leading to an increase in leakage or a short circuit between the drain and the source. Therefore, in order to ensure stable performance of the semiconductor device, the shielding structure may be a gate shielding structure for shielding and protecting the gate, and / or the shielding structure may be a drain shielding structure for shielding and protecting the drain, but the embodiment of the present invention is not specifically limited.

[0055] In addition, the semiconductor device generally further includes an electrode connection structure, such as a bonding pad, located on the semiconductor layer farther from the substrate and located in the passive region bb, and may specifically include a gate bonding pad and a drain bonding pad, in which the gate bonding pad is electrically connected to the gate, and the drain bonding pad is electrically connected to the drain. Adaptively, the gate shielding structure can shield and protect the gate bonding pad, and further realize shielding and protection for the gate, and the drain shielding structure can shield and protect the drain bonding pad, and further realize shielding and protection for the drain.

[0056] 2 illustrates an example in which the bonding pad is a gate bonding pad 29 and the shielding structure 31 is a gate shielding structure 301. FIG. 3 illustrates a schematic planar structure of another semiconductor device according to an embodiment of the present invention, in which the bonding pad is a drain bonding pad 30 and the shielding structure 31 is a drain shielding structure 302. FIG. 4 illustrates a schematic planar structure of another semiconductor device according to an embodiment of the present invention, in which the bonding pad includes a gate bonding pad 29 and a drain bonding pad 30, and the shielding structure 31 includes a gate shielding structure 301 and a drain shielding structure 302.

[0057] Furthermore, since the shielding structure 31 is electrically connected to a predetermined potential and can form an electric field or a zero electric field from the active area aa to the non-active area na, the electric field or the zero electric field can be utilized to suppress the movement of silver ions toward the central region of the front surface of the semiconductor chip.

[0058] Specifically, since silver ions cannot move under a zero electric field, the zero electric field can serve to shield the silver ions and inhibit their movement toward the central region of the semiconductor chip, and the electric field direction is from the active region aa toward the non-active region na, thereby inhibiting the movement of silver ions toward the central region of the semiconductor chip.

[0059] Furthermore, the predetermined potential may be introduced by an external power source or may be directly connected to a fixed potential structure in the active area aa, but the embodiment of the present invention is not limited thereto.

[0060] It should be noted that the direction from the active area aa to the non-active area na only indicates the direction of the electric field or zero electric field, and does not indicate the area where the electric field or zero electric field is located, which is specifically the area between the shielding structure and the outer edge of the non-active area na.

[0061] Furthermore, the shielding structure 31 may be provided in the operating area 32 and / or the scribe area 33, although the embodiment of the present invention is not limited thereto.

[0062] 2 shows an example in which the shielding structure 31 (gate shielding structure 301) is provided in the operating region 32, in which case the semiconductor device including the shielding structure 31 is provided compactly, and the semiconductor device can be guaranteed to have a small volume, which is advantageous for realizing a miniaturized design of the semiconductor device. In another embodiment, the shielding structure 31 may be provided in the scribe region 33, which ensures that the normal operation of the semiconductor device is not affected by the installation of the shielding structure 31 under the premise that silver ions are shielded, and ensures stable performance of the semiconductor device. In addition, the shielding structure 31 may be provided partially in the operating region 32 and the other part in the scribe region 33, but the embodiment of the present invention is not limited thereto.

[0063] In summary, the semiconductor device according to the embodiment of the present invention adds a shielding structure and is electrically connected to a predetermined potential, thereby forming an electric field or a zero electric field from the active area to the non-active area, effectively shielding silver ions and inhibiting their migration to the central area of ​​the front surface of the semiconductor chip, thereby ensuring normal operation of the semiconductor device.

[0064] Based on the above embodiment, referring to FIG. 2, optionally, the semiconductor device further includes a gate 25 located on a side of the multiple semiconductor layers farther from the substrate 21 and located in an active region aa, the semiconductor device further includes a gate bonding pad 29 located on a side of the multiple semiconductor layers farther from the substrate 21 and located in a non-active region na, the gate bonding pad 29 is electrically connected to the gate 25, and the at least one shielding structure 31 includes a gate shielding structure 301, the gate shielding structure 301 is for shielding and protecting the gate bonding pad 29, and in this case, the potential of the predetermined potential is equal to or greater than 0.

[0065] 2, the semiconductor device further includes a gate 25, which is electrically connected to a gate bonding pad 29, and the gate shielding structure 301 is for shielding and protecting the gate bonding pad 29 and the gate 25. This prevents silver ions in the patching silver paste from moving onto the gate bonding pad 29 during packaging, leading to increased leakage or short circuit between the gate 25 and the source 24, affecting the performance of the gate bonding pad 29 and the gate 25, and further affecting the performance of the semiconductor device, which prevents the semiconductor device from being used normally.

[0066] Referring to FIG. 4, further optionally, the semiconductor device further includes a drain 26 located on a side of the multiple semiconductor layers farther from the substrate 21 and located in an active region aa, the semiconductor device further includes a drain bonding pad 30 located on a side of the multiple semiconductor layers farther from the substrate 21 and located in a non-active region na, the drain bonding pad 30 being electrically connected to the drain 26, and the at least one shielding structure 31 includes a drain shielding structure 302, the drain shielding structure 302 being for shielding and protecting the drain bonding pad 30, and in this case, the potential of the predetermined potential is equal to or greater than 0.

[0067] As shown in FIG. 4, the semiconductor device further includes a gate 25 and a drain 26, the gate 25 is electrically connected to a gate bonding pad 29, and the gate shielding structure 301 is for shielding and protecting the gate bonding pad 29 and the gate 25. This prevents silver ions in the patching silver paste from moving onto the gate bonding pad 29 during packaging, leading to a short circuit between the gate 25 and the source 24, and affecting the performance of the gate bonding pad 29 and the gate 25. The drain 26 is electrically connected to a drain bonding pad 30, and the drain shielding structure 302 is for shielding and protecting the drain bonding pad 30 and the drain 26. This prevents silver ions in the patching silver paste from moving onto the drain bonding pad 30 during packaging, leading to an increase in leakage or a short circuit between the drain 26 and the source 24, affecting the performance of the drain bonding pad 30 and the drain 26, and further affecting the performance of the semiconductor device, which prevents the semiconductor device from being used normally.

[0068] Based on the above embodiment, the specific installation manner of the shielding structure will be described in more detail below by taking the example where the shielding structure is the gate shielding structure 301.

[0069] Optionally, the multiple semiconductor layers include a conductive region and a two-dimensional electron gas elimination region located in the inactive region na, the two-dimensional electron gas elimination region being located between the conductive region and the active region, and the conductive region being a shielding structure; and / or the semiconductor device further includes a dielectric layer located on a side of the multiple semiconductor layers farther from the substrate, and at least one conductive wiring is provided on the side of the dielectric layer farther from the multiple semiconductor layers, and the conductive wiring is a shielding structure.

[0070] As one possible embodiment, Fig. 5 is a schematic cross-sectional structure diagram of a semiconductor device cut along A-A' in Fig. 2. Referring to Fig. 5, the multiple semiconductor layers 22 include a conductive region 221 and a two-dimensional electron gas elimination region 222 located in the inactive region na, and the two-dimensional electron gas elimination region 222 is located between the conductive region 221 and the active region. In this case, the conductive region 221 can be electrically connected to a predetermined potential as a shielding structure, for example, a gate shielding structure 301, and the gate bonding pad 29 and the gate can be shielded and protected by the conductive region 221. This prevents silver ions in the patching silver paste from moving onto the gate bonding pad 29 during packaging, leading to an increase in leakage or a short circuit between the gate and the source, and affecting the performance of the gate bonding pad 29 and the gate.

[0071] Furthermore, when the conductive region 221 is a shielding structure, optionally the conductive region 221 is a two-dimensional electron gas forming region or a semiconductor doped region.

[0072] Exemplarily, the conductive region 221 may be a two-dimensional electron gas. Specifically, the multi-layer semiconductor layer 22 in the semiconductor device according to the embodiment of the present invention may include a nucleation layer located on the substrate, a buffer layer located on the side of the nucleation layer farther from the substrate, a channel layer located on the side of the buffer layer farther from the nucleation layer, and a barrier layer located on the side of the channel layer farther from the buffer layer, and a heterojunction structure is formed by the barrier layer and the channel layer, and a two-dimensional electron gas (2DEG) is formed at the heterojunction interface (not shown). Usually, the two-dimensional electron gas is left only in the active region aa, and the two-dimensional electron gas needs to be removed in the inactive region na to form the two-dimensional electron gas removed region 222. In this embodiment, the conductive region 221 is provided to be a two-dimensional electron gas, which not only avoids the occupied space caused by providing a shielding structure, but also avoids an increase in the manufacturing process, and when removing the two-dimensional electron gas in the inactive region na, it is only necessary to leave a part of the two-dimensional electron gas at the edge of the semiconductor device, making the process simpler and more efficient. In addition, the conductive region 221 may be formed by semiconductor doping the multiple semiconductor layers 22 in the inactive region na, but those skilled in the art can set it themselves according to their needs, and the embodiment of the present invention is not limited thereto.

[0073] As another possible embodiment, Fig. 6 is a schematic cross-sectional structure diagram of another semiconductor device cut along A-A' in Fig. 2. Referring to Fig. 6, the semiconductor device further includes a dielectric layer 23 located on the side of the multiple semiconductor layers 22 far from the substrate 21, and at least one conductive wiring 25 is provided on the side of the dielectric layer 23 far from the multiple semiconductor layers 22. In this case, the conductive wiring 25 can be electrically connected to a predetermined potential as a shielding structure (e.g., gate shielding structure 301), and the gate bonding pad 29 and the gate can be shielded and protected by the conductive wiring 25. This prevents silver ions in the patching silver paste from moving onto the gate bonding pad 29 during packaging, leading to an increase in leakage or a short circuit between the gate and the source, and affecting the performance of the gate bonding pad 29 and the gate.

[0074] 6 exemplarily shows an example in which two conductive wires 25 are provided on the dielectric layer 23 on the side farther from the multiple semiconductor layers 22, and the conductive wires 25 may be any metal wire with good electrical conductivity, and the embodiment of the present invention does not limit the material. By providing the conductive wires 25 as a shielding structure, the bonding pad can be effectively shielded and protected in the same way. Furthermore, as shown in FIG. 6, a second dielectric layer 24 is usually provided on the side of the gate bonding pad 29 farther from the substrate ("second" is used only for distinction and has no practical meaning), and the second dielectric layer 24 exposes the gate bonding pad 29 and plays a role of protecting the film layer structure thereunder. 5 and 6, compared with the conductive region 221 in the multi-layer semiconductor layer 22, the conductive wiring 25 is provided on the dielectric layer 23 on the side farther from the multi-layer semiconductor layer 22. Therefore, the dielectric layer (only the second dielectric layer 24) above the conductive wiring 25 is thin, and therefore the influence on the shielding effect of the conductive wiring 25 is small, i.e., the shielding effect of the conductive wiring 25 is better.

[0075] As another possible embodiment, FIG. 7 is a schematic cross-sectional structure diagram of another semiconductor device cut along A-A' in FIG. 2. Referring to FIG. 7, the multiple semiconductor layers 22 include a conductive region 221 and a two-dimensional electron gas elimination region 222 located in the inactive region na, the two-dimensional electron gas elimination region 222 is located between the conductive region 221 and the active region, the conductive region 221 is a shielding structure (e.g., a gate shielding structure 301) and is electrically connected to a predetermined potential (not shown), and the semiconductor device further includes a dielectric layer 23 located on the side of the multiple semiconductor layers 22 farther from the substrate 21, and at least one conductive wiring 25 is provided on the side of the dielectric layer 23 farther from the multiple semiconductor layers 22, and the conductive wiring 25 is a shielding structure (e.g., a gate shielding structure 301) and is electrically connected to a predetermined potential (not shown).

[0076] In this embodiment, by providing both the conductive region 221 and the conductive wiring 25 as the shielding structure, the shielding effect can be guaranteed, and even if one shielding structure becomes defective due to an external factor, the other shielding structure can provide a good shielding effect, so that the reliability of the shielding structure is increased, the bonding pad is effectively shielded and protected, and the performance of the semiconductor device is guaranteed. It can be understood that when both the conductive region 221 and the conductive wiring 25 are used as the shielding structure, they are connected to the same predetermined potential.

[0077] Based on any of the aspects described in the above three possible embodiments, the installation manner of the shielding structure will be further described below.

[0078] FIG. 8 is a schematic cross-sectional structure diagram of another semiconductor device cut along A-A' in FIG. 2. Referring to FIG. 8, selectively, at least a portion of the shielding structure does not have a dielectric layer on the side farther from the substrate.

[0079] As described above, when a dielectric layer (e.g., the dielectric layer 23 and the second dielectric layer 24) is provided on the side of the shielding structure (e.g., the gate shielding structure 301) far from the substrate 21, the dielectric layer affects the shielding effect of the shielding structure. Therefore, in order to avoid weakening the shielding effect of the shielding structure, it is preferable not to provide a dielectric layer on the side of the shielding layer far from the substrate. It should be noted that the shielding structure may be partially or entirely exposed, but the embodiment of the present invention is not limited thereto.

[0080] FIG. 9 is a schematic planar structure diagram of another semiconductor device according to an embodiment of the present invention. Referring to FIG. 9, optionally, the shielding structure 31 includes at least a first shielding portion 310, and the first shielding portion 310 is located on the side of the inactive area na away from the active area aa.

[0081] As shown in FIG. 9, the first shielding portion is located on one side of the inactive region na that is far from the active region aa. FIG. 9 shows a gate shielding structure 301 as an example. By providing the gate shielding structure 301 on one side of the long side of the gate bonding pad 29, most of the silver ions can be shielded, and the silver ions in the patching silver paste can be prevented from migrating onto the gate bonding pad 29 during packaging, which would lead to increased leakage or short circuit between the gate and the source, and affect the performance of the gate bonding pad 29 and the gate.

[0082] Continuing to refer to FIG. 9 , further optionally, the shielding structure further includes a second shielding portion 320 and a third shielding portion 330, the first shielding portion 310 is electrically connected to the second shielding portion 320 and the third shielding portion 330, respectively, the extension direction of the first shielding portion 310 intersects both the extension direction of at least a portion of the second shielding portion 320 and the extension direction of at least a portion of the third shielding portion 330, and the shielding structure 31 is located on at least three sides of the inactive area na far from the active area aa.

[0083] 9, the gate shielding structure 301 is located on the four sides of the non-active area na far from the active area aa. In this way, the gate shielding structure 301 can semi-enclose the gate bonding pad 29 and omnidirectionally shield the silver ions moving to the gate bonding pad 29, so as to prevent the silver ions in the patching silver paste from moving onto the gate bonding pad 29 during packaging, which leads to an increase in leakage or a short circuit between the gate and the source, and affects the performance of the gate bonding pad 29 and the gate.

[0084] 9, the second shielding portion 320 and the third shielding portion 330 include not only a portion intersecting the extension direction of the first shielding portion 310 but also a portion parallel to the extension direction of the first shielding portion 310. In this way, the shielding range of the shielding structure is increased, and the shielding effect is improved. In other embodiments, a semi-encircling shielding structure may be provided with reference to FIG. 9, but the embodiments of the present invention are not limited thereto.

[0085] It should be noted that, due to the high operating frequency of the semiconductor device, if the shielding structure forms a closed loop, an induction signal will be generated and easily affect the performance of the semiconductor device, so it is preferable that the shielding structure is not provided as a closed loop structure as much as possible.

[0086] FIG. 10 is a schematic planar structure diagram of another semiconductor device according to an embodiment of the present invention. Referring to FIG. 10 , optionally, the shielding structure 31 includes a fourth shielding portion 340 and a fifth shielding portion 350, the fourth shielding portion 340 extends along a first direction, and the fifth shielding portion 350 extends along a second direction, the first direction and the second direction intersect and are both parallel to a plane on which the substrate is located, and the fourth shielding portion 340 includes a plurality of first sub-shielding structures 341, and two first sub-shielding structures 341 adjacent to each other along the first direction are arranged in a plane parallel to the substrate. The fifth shielding structure 341 is offset in the second direction and has a vertical projection onto a first plane that overlaps with the first plane, which is parallel to the first direction and perpendicular to the plane on which the substrate is located; and / or the fifth shielding portion 350 includes a plurality of second sub-shielding structures 351, and two second sub-shielding structures 351 adjacent along the second direction are offset in the first direction and have a vertical projection onto a second plane that overlaps with the second plane, which is parallel to the second direction and perpendicular to the plane on which the substrate is located.

[0087] FIG. 10 shows an example in which the shielding structure is a gate shielding structure 301, and as shown in FIG. 10, the gate shielding structure is composed of a plurality of sub-shielding structures. For example, FIG. 10 shows an example in which the fourth shielding portion 340 includes a plurality of first sub-shielding structures 341, and two adjacent first sub-shielding structures 341 along the first direction are offset in the second direction and overlap vertically projected onto the first plane, and the fifth shielding portion 350 includes a plurality of second sub-shielding structures 351, and two adjacent second sub-shielding structures 351 along the second direction are offset in the first direction and overlap vertically projected onto the second plane. In this embodiment, two adjacent sub-shielding structures extending along the same direction are arranged so that their vertical projections in a direction perpendicular to the extending direction overlap, which can also play a good shielding role, and those skilled in the art can set them up by themselves according to their needs, and the embodiment of the present invention is not limited thereto. It can be understood that when the shielding structure is made up of a number of discontinuous sub-shielding structures, each of the sub-shielding structures is electrically connected to a predetermined potential.

[0088] In summary, the above embodiment takes the example of the shielding structure being a gate shielding structure, and describes in detail the specific installation manner of the shielding structure. Based on the above embodiment, the active area aa may include a plurality of fixed potential structures, for example, the source may be a fixed potential structure, and the source potential may be 0, and further, for example, the drain may be a fixed potential structure, and the drain fixed potential is greater than 0, so that the shielding structure may be electrically connected to the fixed potential structure in the active area aa. In this way, it is possible to avoid the need for a separate external power supply, and ensure the simple structure of the semiconductor device.

[0089] Optionally, the fixed potential structure includes a source and the shielding structure is electrically connected to the source.

[0090] Since the potential of the source is 0 and the predetermined potential of the shielding structure is equal to or greater than 0, the source is also used as a fixed potential structure and the shielding structure is directly electrically connected to the source, thereby realizing shielding and protection for the bonding pad and ensuring a simple structure of the semiconductor device. The embodiments of the present invention do not limit the manner of electrically connecting the shielding structure and the source, and those skilled in the art can design it themselves.

[0091] Optionally, the fixed potential structure includes a drain and the shielding structure is electrically connected to the drain.

[0092] For example, since the potential of the drain is greater than 0 and the predetermined potential of the shielding structure is equal to or greater than 0, the drain is also used as a fixed potential structure and the shielding structure is directly electrically connected to the drain (not shown), thereby realizing shielding and protection for the bonding pad and ensuring a simple structure of the semiconductor device. The embodiment of the present invention does not limit the method of electrically connecting the shielding structure and the drain, and those skilled in the art can design it themselves.

[0093] It should be noted that when the drain is a fixed potential structure and the shielding structure is electrically connected to the drain, the possible shielding structure is the gate shielding structure, not the drain shielding structure; otherwise, if silver ions move to the drain shielding structure during packaging, it will also lead to increased leakage or short circuit between the drain and the source, and the semiconductor device will not be able to operate normally.

[0094] It should be noted that when the source or drain is also used as a fixed potential structure, when electrically connecting to the shielding structure, both ends of the shielding structure may be connected to the same source or drain or to different sources or drains, but the embodiments of the present invention are not limited thereto.

[0095] Based on the same inventive concept, an embodiment of the present invention further provides a semiconductor device manufacturing method for manufacturing the semiconductor device provided in any of the above embodiments, and the manufacturing method may specifically include the following steps S101 to S103. S101 is to prepare a substrate. S102 is to fabricate multiple semiconductor layers on one side of a substrate. Exemplarily, the plurality of semiconductor layers are located on one side of the substrate, and the plurality of semiconductor layers may be specifically made of III-V compound semiconductor materials, and a 2DEG is formed in the plurality of semiconductor layers. S103 is to fabricate at least one shielding structure on one side of the substrate, where the shielding structure is electrically connected to a predetermined potential to form an electric field or a zero electric field from the active area to the non-active area.

[0096] The fabrication method according to an embodiment of the present invention fabricates a shielding structure on one side of a substrate, and arranges the shielding structure to be electrically connected to a predetermined potential, thereby forming an electric field or a zero electric field from the active area to the non-active area, which can effectively shield silver ions and inhibit their migration to the central area of ​​the front surface of the semiconductor chip, and ensure the normal operation of the semiconductor device.

[0097] In view of the above problems of the prior art in FIG. 1, a semiconductor device according to an embodiment of the present invention includes an operating area and a scribe area surrounding the operating area, the operating area includes an active area and a passive area surrounding the active area, and the semiconductor device further includes a substrate, a plurality of semiconductor layers located on one side of the substrate, at least one bonding pad located on the side of the plurality of semiconductor layers far from the substrate and located in the passive area, and at least one shielding structure located on the side of the plurality of semiconductor layers far from the substrate, the shielding structure being electrically connected to a predetermined potential, and the predetermined potential U satisfies U≧0. By using the above technical solution, the shielding structure is electrically connected to the predetermined potential, so that the migration of silver ions in the patching silver paste to the bonding pad during packaging is effectively blocked, the stable performance of the bonding pad and the electrode connected to the bonding pad is ensured, and the occurrence of a short circuit between the bonding pad and the electrode connected to the bonding pad and the source is avoided, and the normal operation of the semiconductor device is ensured.

[0098] The above is the core idea of ​​the present invention, and the technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the drawings in the embodiments of the present invention. Based on the embodiments of the present invention, other embodiments obtained by those skilled in the art without paying creative labor shall all be included in the protection scope of the present invention.

[0099] FIG. 11 is a schematic planar structure diagram of a semiconductor device according to an embodiment of the present invention, and FIG. 12 is a schematic planar structure diagram of another semiconductor device according to an embodiment of the present invention. As shown in FIGS. 11 and 12, the semiconductor device according to the embodiment of the present invention includes an operating region 32 and a scribe region 33 surrounding the operating region 32, the operating region 32 includes an active region aa and a passive region bb surrounding the active region aa, Semiconductor devices are A substrate 21; A plurality of semiconductor layers (not shown) located on one side of a substrate; At least one bonding pad located on a side of the plurality of semiconductor layers farther from the substrate 21 and located in the passive region bb; The semiconductor device further includes at least one shielding structure 31 located on a side of the multiple semiconductor layers 22 away from the substrate 21, the shielding structure 31 shielding and protecting the bonding pads, the shielding structure 31 being electrically connected to a predetermined potential, and the predetermined potential U satisfying U≧0.

[0100] The bonding pad may be a gate bonding pad located in the passive region bb, and the shielding structure may be a gate shielding structure correspondingly, and / or the bonding pad may be a drain bonding pad, and the shielding structure is a drain shielding structure correspondingly, but the embodiment of the present invention is not specifically limited. Here, Fig. 11 illustrates an example in which the bonding pad is a gate bonding pad 29 and the shielding structure 31 is a gate shielding structure 301, Fig. 12 illustrates an example in which the bonding pad is a drain bonding pad 30 and the shielding structure 31 is a drain shielding structure 302, and Fig. 13 illustrates an example in which the bonding pad includes the gate bonding pad 29 and the drain bonding pad 30, and the shielding structure 31 includes the gate shielding structure 301 and the drain shielding structure 302.

[0101] Furthermore, the shielding structure 31 is electrically connected to a predetermined potential, where the predetermined potential U satisfies U≧0. The shielding structure 31 can shield and protect the bonding pad, effectively block the migration of silver ions in the silver paste for patching to the bonding pad, ensure the stable performance of the bonding pad and the electrodes connected to the bonding pad, avoid the occurrence of short circuits between the bonding pad and the electrodes connected to the bonding pad and the source, and ensure the normal operation of the semiconductor device.

[0102] Furthermore, the predetermined potential may be a positive potential or a zero potential introduced by an external power source, or may be directly connected to a fixed potential structure of the active area aa, but the embodiment of the present invention is not limited thereto.

[0103] In summary, the semiconductor device according to the embodiment of the present invention adds a shielding structure and is electrically connected to a predetermined potential, thereby effectively shielding and protecting the bonding pad, effectively blocking the migration of silver ions in the silver paste used for patching the bonding pad to the bonding pad during packaging, ensuring stable performance of the bonding pad and the electrodes connected to the bonding pad, avoiding the occurrence of short circuits between the bonding pad and the electrodes connected to the bonding pad and the source, and ensuring normal operation of the semiconductor device.

[0104] The following describes in detail two specific installation methods of the shielding structure and the technical solutions according to the embodiments of the present invention.

[0105] Continuing to refer to FIG. 11, the semiconductor device further includes a gate 25 located on a side of the multiple semiconductor layers away from the substrate 21 and located in the active area aa, the at least one bonding pad includes a gate bonding pad 29, the gate bonding pad 29 is electrically connected to the gate 25, and the at least one shielding structure 31 includes a gate shielding structure 301, the gate shielding structure 301 is for shielding and protecting the gate 25 bonding pad.

[0106] 11, the semiconductor device further includes a gate 25, which is electrically connected to a gate bonding pad 29, and the gate shielding structure 301 is for shielding and protecting the gate bonding pad 29 and the gate 25. This prevents silver ions in the patching silver paste from migrating onto the gate bonding pad 29 during packaging, leading to a short circuit between the gate 25 and the source 24, which affects the performance of the gate bonding pad 29 and the gate 25, and further affects the performance of the semiconductor device, preventing the semiconductor device from being used normally.

[0107] Continuing to refer to FIG. 13, the semiconductor device further includes a drain 26 located on a side of the multiple semiconductor layers farther from the substrate 21 and located in the active area aa, the at least one bonding pad further includes a drain bonding pad 30, the drain bonding pad 30 being electrically connected to the drain 26, and the at least one shielding structure 31 includes a drain shielding structure 302, which is for shielding and protecting the drain bonding pad 30.

[0108] As shown in FIG. 13, the semiconductor device further includes a gate 25 and a drain 26, the gate 25 is electrically connected to a gate bonding pad 29, and the gate shielding structure 301 is for shielding and protecting the gate bonding pad 29 and the gate 25. This prevents silver ions in the patching silver paste from moving onto the gate bonding pad 29 during packaging, leading to a short circuit between the gate 25 and the source 24, and affecting the performance of the gate bonding pad 29 and the gate 25. The drain 26 is electrically connected to a drain bonding pad 30, and the drain shielding structure 302 is for shielding and protecting the drain bonding pad 30 and the drain 26. This prevents silver ions in the patching silver paste from moving onto the drain bonding pad 30 during packaging, leading to a short circuit between the drain 26 and the source 24, and affecting the performance of the drain bonding pad 30 and the drain 26, and further affecting the performance of the semiconductor device, which prevents the semiconductor device from being used normally.

[0109] Based on the above embodiment, the active area aa may include multiple fixed potential structures, for example, the source may be a fixed potential structure, and the source potential may be 0, and further for example, the drain may be a fixed potential structure, and the drain fixed potential may be greater than 0, so that the shielding structure may be electrically connected to the fixed potential structure in the active area aa, thereby avoiding the need for a separate external power supply and ensuring the simple structure of the semiconductor device.

[0110] Optionally, with continued reference to FIGS. 11, 12 and 13, the fixed potential structure includes a source 24 and a shielding structure 31 is electrically connected to the source 24.

[0111] Since the potential of the source 24 is 0 and the predetermined potential of the shielding structure is 0 or more, the source 24 is also used as a fixed potential structure and the shielding structure 31 is provided to be directly electrically connected to the source 24, thereby realizing shielding and protection for the bonding pad and ensuring a simple structure of the semiconductor device. As shown in Figures 11, 12 and 13, the shielding structure 31 here may include a gate shielding structure 301 and / or a drain shielding structure 302.

[0112] Optionally, the shielding structure includes a gate shielding structure, the fixed potential structure includes a drain, and the gate shielding structure is electrically connected to the drain.

[0113] For example, since the potential of the drain is greater than 0 and the predetermined potential of the shielding structure is equal to or greater than 0, the drain is also used as a fixed potential structure, and the shielding structure is directly electrically connected to the drain (not shown), thereby realizing shielding and protection for the bonding pad and ensuring the simple structure of the semiconductor device. It should be noted that when the drain is a fixed potential structure and the shielding structure is electrically connected to the drain, the possible shielding structure is not the drain shielding structure but the gate shielding structure, otherwise, if silver ions move to the drain shielding structure during packaging, it will also lead to a short circuit between the drain and the source, and the semiconductor device will not be able to operate normally.

[0114] It should be noted that when the source or drain is also used as a fixed potential structure, when electrically connecting to the shielding structure, both ends of the shielding structure may be connected to the same source or drain or to different sources or drains, but the embodiments of the present invention are not limited thereto.

[0115] In the following, an example will be described in which the source doubles as a fixed potential structure, the shielding structure is electrically connected to a different source, and the shielding structure is a gate shielding structure.

[0116] FIG. 14 is a schematic planar structure diagram of another semiconductor device according to an embodiment of the present invention. As shown in FIG. 14, optionally, the source 24 includes a first source 241 and an Nth source arranged along a first direction, the first direction is parallel to a plane on which the substrate 21 is located, the first source 241 is located at a first end of the active region aa, and the Nth source is located at a second end of the active region aa, and the first end and the second end are arranged opposite to each other along the first direction; The shielding structure 31 is electrically connected to the first source and the Nth source, respectively, and the gate bonding pad 29 is located within the section defined by the shielding structure and the active area aa.

[0117] Illustratively, FIG. 14 illustrates an example in which N is equal to 2. As shown in FIG. 14, the first source 241, the gate 25, and the drain 26 extend in the active area aa along a second direction (Y direction shown in the figure), and the extension length does not exceed the range of the active area aa; the first source 241, the gate 25, and the drain 26 are arranged in the active area aa along a first direction (X direction shown in the figure), and the arrangement length does not exceed the range of the active area aa; the first direction is parallel to the direction from the first source 241 to the drain 26; the second direction and the first direction intersect and are all parallel to the plane in which the substrate 21 is located. 14, one end of the shielding structure 31 is electrically connected to the first source 241, and the other end is electrically connected to the second source 242, the shielding structure 31 has a semi-annular structure, the gate bonding pad 29 is located within the section defined by the shielding structure 31 and the active area aa, and the gate bonding pad 29 is completely surrounded by the shielding structure 31. In this way, the shielding structure 31 is electrically connected to the source 24, which effectively blocks the silver ions in the patching silver paste that have migrated to the gate under the action of the electric field, and there is no need to provide a separate power supply for electrical connection to the shielding structure 31, which reduces complex wiring and reduces costs.

[0118] Optionally, FIG. 15 is a schematic cross-sectional structure diagram along the cutting line A-A' of the semiconductor device according to FIG. 14. As shown in FIGS. 14 and 15, the source 24 is electrically connected to a source back electrode (not shown) via a via hole 34. The overlapping area of the vertical projection of the shielding structure 31 on the plane where the substrate is located and the vertical projection of the via hole 34 on the plane where the substrate is located is S1. The area of the vertical projection of the via hole 34 on the plane where the substrate is located is S2. Here, S1 < S2 / 4.

[0119] Exemplarily, the source 24 is electrically connected to the source back electrode via the via hole 34. The shape of the via hole 34 may be circular, elliptical, semi-circular, etc., but the embodiments of the present invention are not limited thereto. Considering that an effective electrical connection between the shielding structure 31 and the source 24 is required, in order to avoid the shielding structure 31 being virtually connected due to the connection between the shielding structure 31 and the via hole 34 and the shielding effect not being achieved by the shielding structure 31, the overlapping area S1 of the vertical projection of the shielding structure 31 on the plane where the substrate 21 is located and the vertical projection of the via hole 34 on the plane where the substrate 21 is located is smaller than one-fourth of the area S2 of the vertical projection of the via hole 34 on the plane where the substrate 21 is located, that is, S1 < S2 / 4. Thereby, an effective electrical connection between the shielding structure 31 and the source 24 is ensured, and the shielding effect of the shielding structure 31 is realized.

[0120] Preferably, the vertical projection of the shielding structure 31 on the plane where the substrate 21 is located and the vertical projection of the via hole 34 on the plane where the substrate 21 is located do not overlap.

[0121] Exemplarily, as shown in FIG. 14, the vertical projection of the shielding structure 31 on the plane where the substrate 21 is located and the vertical projection of the via hole 34 on the plane where the substrate 21 is located do not overlap. In this case, regardless of the shape and area of the via hole 34, the shielding structure 31 can realize an effective electrical connection with the source 24, achieve an optimal shielding effect, and further realize the stable performance of the semiconductor device.

[0122] Based on the above embodiment, the shielding structure 31 can correspond to various different installation positions, and the film layer configurations of the semiconductor device can be different when the installation positions are different, which will be described in detail in the following in two possible embodiments.

[0123] As one possible embodiment, still referring to FIG. 14 , optionally, the shielding structure 31 includes a first shielding portion 311, a second shielding portion 312 and a third shielding portion 313, the second shielding portion 312 is connected to the first shielding portion 311 and the third shielding portion 313, respectively, the second shielding portion 312 is located in the scribe region 33, the first shielding portion 311 is located in the operating region 32 and is electrically connected to the first source 241, and the third shielding portion 313 is located in the operating region 32 and is electrically connected to the second source 242.

[0124] Specifically, the operating region 32 can be understood as the region where the semiconductor device operates, and includes an active region aa and a passive region bb, where the active region aa can be understood as the region where two-dimensional electron gas, electrons or holes exist, and its operating state and characteristics are affected by an external circuit, and is the active operating region of the semiconductor device, and the passive region bb can be understood as the region outside the active region aa, which participates in the operation of the device, but its operating state is not affected by an external circuit. The scribe region 33 refers to the region where the semiconductor device is scribed to form a plurality of independent semiconductor devices. The second shielding portion 312 is located in the scribe region 33, that is, most of the structure in the shielding structure 31 is arranged to be located in the scribe region 33, so that under the premise that silver ions are shielded, it is ensured that the normal operation of the semiconductor device is not affected by the installation of the shielding structure 31, and the stable performance of the semiconductor device is ensured.

[0125] Based on the above embodiment, and still referring to Figures 14 and 15, optionally, the semiconductor device further includes a first dielectric layer 41 located on a side of the multiple semiconductor layers 22 farther from the substrate 21 and located in a passive region bb, wherein the first shielding portion 311 and the third shielding portion 313 are both located on a side of the first dielectric layer 41 farther from the substrate 21, and the thickness of the shielding structure 31 is greater than the thickness of the first dielectric layer 41 along a direction perpendicular to the substrate 21, such that the first shielding portion 311 and the third shielding portion 313 are both electrically connected to the second shielding portion 312.

[0126] Exemplarily, the semiconductor device may further include a first dielectric layer 41 located in the passive region bb, and the first dielectric layer 41 may be, for example, an insulating layer or a waterproof layer that protects the semiconductor structure located in the passive region. And since the scribe region 33 needs to be scribed later, the first dielectric layer 41 is generally not provided in the scribe region 33 to ensure that the scribe process is simple. Then, there is a step between the installation surface of the second shielding portion 312 located in the scribe region 33 and the installation surfaces of the first shielding portion 311 and the second shielding portion 313. In order to ensure that the connection between the second shielding portion 312 and the first shielding portion 311 and the third shielding portion 313 is maintained, it is necessary to provide the shielding structure 31 so that the thickness is greater than the thickness of the first dielectric layer 41 along the direction perpendicular to the substrate 21. In this way, the second shielding portion 312, the first shielding portion 311 and the third shielding portion 313 are not disconnected at their connection positions, the integrity of the shielding structure 31 is guaranteed, and shielding and protection for the gate bonding pad is achieved.

[0127] The material of the first dielectric layer 41 may be a dielectric material such as SiN or SiO.

[0128] Figure 16 is a schematic cross-sectional structure diagram of the semiconductor device of Figure 14 taken along the cutting line B-B'. As shown in Figures 14 and 16, the semiconductor device further includes a first dielectric layer 41 located on the side of the multiple semiconductor layers 22 farther from the substrate 21 and located in the passive region bb, and the thickness of the source 24 is greater than the thickness of the first dielectric layer 41 along the direction perpendicular to the substrate 21 so that the first shielding portion 311 and the third shielding portion 313 are both electrically connected to the source 24.

[0129] Exemplarily, the semiconductor device may further include a first dielectric layer 41 located in the passive region bb, and the first dielectric layer 41 may be, for example, an insulating layer or a waterproof layer that protects the semiconductor structure located in the passive region bb. Since the source 24 needs to form an ohmic contact with the multiple semiconductor layers 22, the first dielectric layer 41 is generally not provided between the source 24 and the multiple semiconductor layers 22.

[0130] In addition, since it is necessary to ensure that the first shielding portion 311 and the third shielding portion 313 are electrically connected to the source 24 and the shielding structure 31 is connected to a fixed potential, it is necessary to reasonably set the thickness of the source 24 and the thickness of the first dielectric layer 41 so that the first shielding portion 311 and the third shielding portion 313 can be electrically connected to the source 24. Specifically, the thickness of the source 24 may be set to be greater than the thickness of the first dielectric layer 41 along the direction perpendicular to the substrate 21 so that the first shielding portion 311 and the third shielding portion 313 are both electrically connected to the source 24; otherwise, the effective connection between the source 24 and the shielding structure 31 cannot be formed, and the shielding structure 31 is also floating, and the electric field shielding effect is not achieved, so that the silver ions in the patching silver paste are transferred to the gate bonding pad 29, and the gate 25 and the source 24 have the same potential, causing a short circuit between the gate 25 and the source 24.

[0131] Continuing to refer to FIG. 16, optionally, the semiconductor device further includes a second dielectric layer 42 located in the active region 32, the second dielectric layer 42 covering the first shielding portion 311, the third shielding portion 313 and the source 24; In a direction perpendicular to the substrate 21, the sum of the thicknesses of the first dielectric layer 41, the first shielding portion 311, and the second dielectric layer 42 is greater than the thickness of the source 24 so that the second dielectric layer 42 located on the side of the first shielding portion 311 farther from the substrate 21 is connected to the second dielectric layer 42 located on the side of the source 24 farther from the substrate.

[0132] Exemplarily, the semiconductor device according to the embodiment of the present invention may further include a second dielectric layer 42, which can cover and protect the operating region 32. Specifically, the second dielectric layer 42 covers the first shielding portion 311, the third shielding portion 313, and the source 24. Since the upper surfaces of the first shielding portion 311 and the third shielding portion 313 located in the passive region bb may not be flush with the upper surface of the source 24, that is, there is a step between the first shielding portion 311 and the third shielding portion 313, and the source 24, it is necessary to reasonably set the relationship between the total thickness of the first dielectric layer 41, the first shielding portion 311 or the third shielding portion 313, and the second dielectric layer 42, and the thickness of the source 24, so as to avoid the occurrence of breakage of the second dielectric layer 42 in the connection region between the first shielding portion 311 and the third shielding portion 313, and the source 24. Specifically, in the direction perpendicular to the substrate 21, the total thickness of the first dielectric layer 41, the first shielding portion 311 and the second dielectric layer 42 may be greater than the thickness of the source 24; otherwise, the second dielectric layer 42 located in the passive region bb and the second dielectric layer 42 located in the active region aa may be broken, and the second dielectric layer 42 may no longer be able to protect the entire operating region 32, allowing water and oxygen to enter the semiconductor device, and the metal layer of the source 24 to be oxidized or damaged, leading to the risk of reliability problems and directly affecting the performance of the semiconductor device.

[0133] The material of the second dielectric layer 42 may be a dielectric material such as SiN, SiO, or the like.

[0134] As one possible embodiment, FIG. 17 is a schematic plan view of another semiconductor device according to an embodiment of the present invention. As shown in FIG. 17, optionally, the shielding structure 31 includes a first shielding portion 311, a second shielding portion 312 and a third shielding portion 313, and the second shielding portion 312 is connected to the first shielding portion 311 and the third shielding portion 313 respectively; The first shielding portion 311, the second shielding portion 312 and the third shielding portion 313 are all located in the active region 32, the first shielding portion 311 is electrically connected to the first source 241, and the third shielding portion 313 is electrically connected to the second source 242.

[0135] For example, the first shielding portion 311, the second shielding portion 312, and the third shielding portion 313 are all located in the operating region 32, rather than being provided in the scribe region 33. In this way, the semiconductor device including the shielding structure 31 can be provided compactly, and it can be ensured that the semiconductor device has a small volume, which is advantageous for realizing a miniaturized design of the semiconductor device.

[0136] Based on the above embodiment, FIG. 18 is a schematic cross-sectional structure diagram of the semiconductor device according to FIG. 17 taken along the cutting line CC'. As shown in FIG. 18, optionally, the semiconductor device further includes at least one dielectric layer located on the side of the multiple semiconductor layers 22 farther from the substrate 21 and located in the passive region bb; The at least one dielectric layer includes a first surface located on a side of the semiconductor layer 22 that is farther from the substrate 21; The shielding structure 31 includes a second surface of the plurality of semiconductor layers 22 located away from the substrate 21; Along a direction perpendicular to the substrate 21, the second surface is located on the side of the first surface that is remote from the substrate 21.

[0137] 18, the at least one dielectric layer may include, for example, a first dielectric layer 41 and a second dielectric layer 42, the first dielectric layer 41 may be, for example, an insulating layer or a waterproof layer that protects the semiconductor structure located in the passive region bb, and the second dielectric layer 42 may protect the entire operating region 32 and prevent water and oxygen from entering the semiconductor device and affecting the performance of the semiconductor device. When the dielectric layer includes multiple dielectric layers, the first surface can be understood as the surface of the top dielectric layer that is farther from the substrate, and in the example of FIG. 18, the first surface is the surface of the second dielectric layer 42 that is farther from the substrate 21. Furthermore, the shielding structure 31 includes a second surface that is located on the side farther from the substrate 21 in the multiple semiconductor layers 22, and in the direction perpendicular to the substrate 21, the second surface is located on the side of the first surface that is farther from the substrate 21, i.e., the shielding structure 31 protrudes from the dielectric layer, and from the viewpoint of the electric field lines, it can be understood that the radiation area of ​​the electric field lines of the shielding structure 31 is wider. In this way, the shielding structure 31 can shield more silver ions, and the shielding effect of the shielding structure 31 is good.

[0138] Furthermore, as shown in Figure 18, when the shielding structure 31 and the second dielectric layer 42 are both located on the side of the first dielectric layer 41 farther from the substrate 21, the surface of the shielding structure 31 farther from the substrate 21 is farther from the substrate 21 than the surface of the second dielectric layer 42 farther from the substrate 21, and it can be understood that the thickness of the shielding structure 31 is greater than the thickness of the second dielectric layer 42.

[0139] Optionally, the source 24 may include multiple source metal layers, The shielding structure 31 includes one shielding metal layer, and the shielding metal layer and any one of the multiple source metal layers are provided in the same layer and are made of the same material, or the shielding structure 31 includes multiple shielding metal layers, and the multiple shielding metal layers and the multiple source metal layers have a one-to-one correspondence, and the corresponding shielding metal layers and source metal layers are provided in the same layer and are made of the same material.

[0140] Wherein, the source 24 includes multiple source metal layers, and the material composition of the multiple source metal layers includes, but is not limited to, metals such as Ti, Al, Ni, Au, etc. The shielding structure 31 may include one or multiple shielding metal layers, and when the shielding structure 31 includes one shielding metal layer, the shielding metal layer and any one of the multiple source metal layers are provided in the same layer and are made of the same material, and can be fabricated in the same process, so that the fabrication process of the shielding structure 31 is ensured to be simple, and when the shielding structure 31 includes multiple shielding metal layers, the multiple shielding metal layers and the multiple source metal layers correspond one-to-one, and the corresponding shielding metal layers and source metal layers are provided in the same layer and are made of the same material, and can be fabricated in the same process, so that the fabrication process of the shielding structure 31 is ensured to be simple.

[0141] Based on the above embodiment, the multiple semiconductor layers 22 in the semiconductor device 20 according to the embodiment of the present invention may specifically include a nucleation layer located on the substrate 21, a buffer layer located on the side of the nucleation layer farther from the substrate 21, a channel layer located on the side of the buffer layer farther from the nucleation layer, and a barrier layer located on the side of the channel layer farther from the buffer layer, whereby a heterojunction structure is formed by the barrier layer and the channel layer, and a 2DEG (not shown) is formed at the heterojunction interface.

[0142] Based on the same inventive concept, an embodiment of the present invention further provides a method for fabricating a semiconductor device, which may include the following steps S201 to S204. S201 is to prepare a substrate. Exemplarily, the substrate material may be Si, SiC, gallium nitride or sapphire, or other materials suitable for gallium nitride growth. The substrate fabrication method may be atmospheric pressure chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, metal organic chemical vapor deposition, low pressure chemical vapor deposition, high density plasma chemical vapor deposition, ultra-high vacuum chemical vapor deposition, plasma enhanced chemical vapor deposition, catalytic chemical vapor deposition, hybrid physical chemical vapor deposition, rapid thermal chemical vapor deposition, vapor phase epitaxy, pulsed laser deposition, atomic layer epitaxy, molecular beam epitaxy, sputtering or evaporation. S202 is to fabricate multiple semiconductor layers on one side of a substrate. Exemplarily, the plurality of semiconductor layers are located on one side of the substrate, and the plurality of semiconductor layers may be specifically made of III-V compound semiconductor materials, and a 2DEG is formed in the plurality of semiconductor layers. S203 is to fabricate at least one bonding pad in a passive region on a side of the plurality of semiconductor layers away from the substrate. S204 is to fabricate at least one shielding structure on a side of the multiple semiconductor layers away from the substrate, the shielding structure being for shielding and protecting the bonding pad, the shielding structure being electrically connected to a predetermined potential, and the predetermined potential U satisfies U≧0.

[0143] By fabricating the shielding structure on the side of the multiple semiconductor layers farther from the substrate and arranging the shielding structure to be electrically connected to a predetermined potential, the migration of silver ions in the patching silver paste to the bonding pad during packaging is effectively blocked, stable performance of the bonding pad and the electrodes connected to the bonding pad are ensured, and short circuits between the bonding pad and the electrode connected to the bonding pad and the source are avoided, thereby ensuring normal operation of the semiconductor device.

[0144] Based on the above embodiments, the source may include multiple source metal layers, and the shielding structure may include one or multiple shielding metal layers, so that the shielding structure and the source can be fabricated in the same fabrication process, and the fabrication process of the semiconductor device is ensured to be simple.

[0145] In view of the above problems of the prior art in FIG. 1, a semiconductor device according to an embodiment of the present invention includes an operating area and a scribe area surrounding the operating area, the operating area including an active area and a passive area surrounding the active area, and the semiconductor device further includes a substrate, a plurality of semiconductor layers located on one side of the substrate, a gate located on a side of the plurality of semiconductor layers far from the substrate and located in the active area, at least one bonding pad located on a side of the plurality of semiconductor layers far from the substrate and located in the passive area, the bonding pad including at least a gate bonding pad, the at least one bonding pad electrically connected to a gate, and at least one shielding structure located on a side of the plurality of semiconductor layers far from the substrate, the shielding structure including a gate shielding structure, and the gate shielding structure for shielding and protecting the gate bonding pad. By using the above technical solution, a shielding structure is provided to effectively block the migration of silver ions in the silver paste for patching to the bonding pad during packaging, ensuring the stable performance of the bonding pad and the electrodes connected to the bonding pad, avoiding the occurrence of short circuits between the bonding pad and the electrodes connected to the bonding pad and the source, and ensuring the normal operation of the semiconductor device.

[0146] The above is the core idea of ​​the present invention, and the technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the drawings in the embodiments of the present invention. Based on the embodiments of the present invention, other embodiments obtained by those skilled in the art without paying creative labor shall all be included in the protection scope of the present invention.

[0147] FIG. 11 is a schematic planar structure diagram of a semiconductor device according to an embodiment of the present invention, and FIG. 13 is a schematic planar structure diagram of another semiconductor device according to an embodiment of the present invention. As shown in FIGS. 11 and 13, the semiconductor device according to the embodiment of the present invention includes an operating region 32 and a scribe region 33 surrounding the operating region 32, the operating region 32 includes an active region aa and a passive region bb surrounding the active region aa, Semiconductor devices are A substrate 21; A plurality of semiconductor layers (not shown) located on one side of a substrate 21; A gate 25 is located on a side of the multiple semiconductor layers farther from the substrate 21 and located in the active region aa; At least one bonding pad located on a side of the plurality of semiconductor layers away from the substrate 21 and located in the passive region bb, the bonding pad including at least a gate bonding pad 29, the gate bonding pad 29 being electrically connected to the gate 25; The semiconductor layer further includes at least one shielding structure 31 located on a side of the multiple semiconductor layers away from the substrate 21, the shielding structure 31 including a gate shielding structure 301, the gate shielding structure 301 further including at least one shielding structure 31 for shielding and protecting the gate bonding pad 29.

[0148] Alternatively, the material of the substrate 21 may be formed of one or more of the following materials, such as silicon, sapphire, silicon carbide, gallium arsenide, gallium nitride, diamond, etc., or may be a material suitable for the growth of gallium nitride.

[0149] The multiple semiconductor layers are located on one side of the substrate 21, and the multiple semiconductor layers may be specifically made of III-V compound semiconductor materials, for example, one or more of gallium arsenide, aluminum gallium arsenide, gallium nitride, aluminum gallium nitride, or indium gallium nitride.

[0150] The bonding pad may be a gate bonding pad 29 located in the passive region bb, and the shielding structure 31 may be a gate shielding structure 301, which is for shielding and protecting the gate bonding pad 29. During packaging, the gate shielding structure 301 can effectively shield the migration of silver ions in the patching silver paste to the gate bonding pad 29, ensure the stable performance of the gate bonding pad 29 and the gate 25 electrically connected to the gate bonding pad 29, prevent the occurrence of a short circuit with the source 24, ensure the normal potential of the semiconductor device gate 25 and source 24, and ensure the normal operation of the semiconductor device.

[0151] In summary, in the semiconductor device according to the embodiment of the present invention, by adding a gate shielding structure, the gate bonding pad is effectively shielded and protected by the gate shielding structure, the migration of silver ions in the silver paste used for patching the gate bonding pad during packaging is effectively blocked, the stable performance of the gate bonding pad and the electrode connected to the gate bonding pad is ensured, and the occurrence of a short circuit between the gate bonding pad and the electrode connected to the gate bonding pad and the source is avoided, so that the normal operation of the semiconductor device is ensured.

[0152] FIG. 13 is a schematic plan view of another semiconductor device according to an embodiment of the present invention. As shown in FIG. 13, optionally, the semiconductor device further includes a drain 26 located on the side of the multiple semiconductor layers farther from the substrate 21 and located in the active region aa; The bond pad further includes a drain bond pad 30, the drain bond pad 30 being electrically connected to the drain 26; The shielding structure further includes a drain shielding structure 302 , which is for shielding and protecting the drain bonding pad 30 .

[0153] 13, the semiconductor device includes a drain 26, which is electrically connected to a drain bonding pad 30, and the drain shielding structure 302 is for shielding and protecting the drain bonding pad 30 and the drain 26. This prevents silver ions in the patching silver paste from migrating onto the drain bonding pad 30 during packaging, leading to a short circuit between the drain 26 and the source 24, affecting the performance of the drain bonding pad 30 and the drain 26, and further affecting the performance of the semiconductor device, which prevents the semiconductor device from being used normally.

[0154] Optionally, the shielding structure is electrically connected to a predetermined potential, where the predetermined potential U satisfies U≧0.

[0155] Furthermore, the potential at the shielding structure 31 may be a potential equal to or greater than 0. The shielding structure 31 can shield and protect the bonding pad, effectively shield the migration of silver ions in the silver paste for patching to the bonding pad, ensure the stable performance of the bonding pad and the electrodes connected to the bonding pad, avoid the occurrence of short circuits between the bonding pad and the electrodes connected to the bonding pad and the source, and ensure the normal operation of the semiconductor device.

[0156] Furthermore, the predetermined potential may be a positive potential or a zero potential introduced by an external power source, or may be directly connected to a fixed potential structure of the active area aa, but the embodiment of the present invention is not limited thereto.

[0157] Based on the above embodiment, the active area aa may include multiple fixed potential structures, for example, the source may be a fixed potential structure, and the source potential may be 0, and further for example, the drain may be a fixed potential structure, and the drain fixed potential may be greater than 0, so that the shielding structure may be electrically connected to the fixed potential structure in the active area aa, thereby avoiding the need for a separate external power supply and ensuring the simple structure of the semiconductor device.

[0158] Optionally, the fixed potential structure includes a source 24 and the shielding structure 31 is electrically connected to the source 24 .

[0159] Since the potential of the source 24 is 0 and the predetermined potential of the shielding structure is 0 or more, the source 24 is also used as a fixed potential structure and the shielding structure 31 is provided to be directly electrically connected to the source 24, thereby realizing shielding and protection for the bonding pad and ensuring a simple structure of the semiconductor device. As shown in Figures 11 and 13, the shielding structure 31 here may include a gate shielding structure 301 and / or a drain shielding structure 302.

[0160] Optionally, the fixed potential structure includes a drain 26 , and the gate shield structure 301 is electrically connected to the drain 26 .

[0161] For example, since the potential of the drain is greater than 0 and the predetermined potential of the shielding structure is equal to or greater than 0, the drain is also used as a fixed potential structure, and the shielding structure is directly electrically connected to the drain (not shown), thereby realizing shielding and protection for the bonding pad and ensuring the simple structure of the semiconductor device. It should be noted that when the drain is a fixed potential structure and the shielding structure is electrically connected to the drain, the possible shielding structure is not the drain shielding structure but the gate shielding structure, otherwise, if silver ions move to the drain shielding structure during packaging, it will also lead to a short circuit between the drain and the source, and the semiconductor device will not be able to operate normally.

[0162] It should be noted that when the source or drain is used as a fixed potential structure, both ends of the shielding structure may be connected to the same source or drain or different sources or drains when electrically connected to the shielding structure, but the embodiment of the present invention is not limited thereto. Hereinafter, an example will be described in which the source is used as a fixed potential structure, the shielding structure is electrically connected to different sources, and the shielding structure is a gate shielding structure.

[0163] FIG. 19 is a schematic planar structure diagram of another semiconductor device according to an embodiment of the present invention. As shown in FIG. 19, optionally, the source 24 includes a first source 241 and an Nth source arranged along a first direction, the first direction is parallel to a plane on which the substrate is located, the first source is located at a first end of the active area aa, and the Nth source is located at a second end of the active area aa, and the first end and the second end are arranged opposite to each other along the first direction; The shielding structure 31 is electrically connected to the first source 241 and the Nth source, respectively, and the gate bonding pad 29 is located within the section defined by the shielding structure and the active area aa.

[0164] 19 illustrates an example in which N is equal to 2, in which the first source 241, the gate 25, and the drain 26 extend in the active area aa along a second direction (Y direction shown in the figure), and the extension length does not exceed the range of the active area aa; the first source 241, the gate 25, and the drain 26 are arranged in the active area aa along a first direction (X direction shown in the figure), and the arrangement length does not exceed the range of the active area aa; the first direction is parallel to the direction from the first source 241 to the drain 26; the second direction and the first direction intersect and are all parallel to the plane in which the substrate 21 is located. 19, one end of the shielding structure 31 is electrically connected to the first source 241, and the other end is electrically connected to the second source 242, the shielding structure 31 has a semi-annular structure, the gate bonding pad 29 is located within the section defined by the shielding structure 31 and the active area aa, and the gate bonding pad 29 is completely surrounded by the shielding structure 31. In this way, the shielding structure 31 is electrically connected to the source 24, which effectively blocks the silver ions in the patching silver paste that have moved to the gate 25 under the action of the electric field, and there is no need to provide a separate power supply for electrical connection to the shielding structure 31, which reduces complex wiring and reduces costs.

[0165] Based on the above examples, the shielding structure 31 can accommodate a variety of different installation positions, which are detailed below in three possible embodiments.

[0166] Optionally, the shielding structure 31 includes a first shielding portion 311, a second shielding portion 312 and a third shielding portion 313, the second shielding portion 312 being connected to the first shielding portion 311 and the third shielding portion 313, respectively; The second shielding portion 312 is located in the scribe region 33, the first shielding portion 311 is located in the operating region 32 and is electrically connected to the first source 241, and the third shielding portion 313 is located in the operating region 32 and is electrically connected to the Nth source, or Or, the second shielding portion 312 is located in the boundary region between the operating region 32 and the scribe region 33, the first shielding portion is located in the operating region 32 and is electrically connected to the first source 241, and the third shielding portion 313 is located in the operating region 32 and is electrically connected to the Nth source; or Or, the first shielding portion 311, the second shielding portion 312 and the third shielding portion 313 are all located in the active region 32, the first shielding portion 311 is electrically connected to the first source 241, and the third shielding portion 313 is electrically connected to the Nth source.

[0167] As one possible embodiment, still referring to FIG. 19 , optionally, the shielding structure 31 includes a first shielding portion 311, a second shielding portion 312, and a third shielding portion 313, the second shielding portion 312 being connected to the first shielding portion 311 and the third shielding portion 313, respectively; The second shielding portion 312 is located in the scribe region 33, the first shielding portion 311 is located in the operating region 32 and is electrically connected to the first source 241, and the third shielding portion 313 is located in the operating region 32 and is electrically connected to the second source 242.

[0168] Specifically, the operating region 32 can be understood as the region where the semiconductor device operates, and includes an active region aa and a passive region bb, where the active region aa can be understood as the region where two-dimensional electron gas, electrons or holes exist, and its operating state and characteristics are affected by an external circuit, and is the active operating region of the semiconductor device, and the passive region bb can be understood as the region outside the active region aa, which participates in the operation of the device, but its operating state is not affected by an external circuit. The scribe region 33 refers to the region where the semiconductor device is scribed to form a plurality of independent semiconductor devices. The second shielding portion 312 is located in the scribe region 33, that is, most of the structure in the shielding structure 31 is arranged to be located in the scribe region 33, so that under the premise that silver ions are shielded, it is ensured that the normal operation of the semiconductor device is not affected by the installation of the shielding structure 31, and the stable performance of the semiconductor device is ensured.

[0169] As one possible embodiment, FIG. 14 is a schematic plan view of another semiconductor device according to an embodiment of the present invention, illustrating an example where N is equal to 2. As shown in FIG. 14, optionally, the shielding structure 31 includes a first shielding portion 311, a second shielding portion 312 and a third shielding portion 313, and the second shielding portion 312 is connected to the first shielding portion 311 and the third shielding portion 313 respectively; The second shielding portion 312 is located in the boundary region between the operating region 32 and the scribe region 33, the first shielding portion 311 is located in the operating region 32 and is electrically connected to the first source 241, and the third shielding portion 313 is located in the operating region 32 and is electrically connected to the second source 242.

[0170] For example, the second shielding portion 312 is located in the boundary region between the operating region 32 and the scribe region 33, and the second shielding portion 312 and the third shielding portion 313 are both located in the operating region 32. By providing them in this manner, the installation of the shielding structure 31 can effectively shield silver ions, ensuring normal operation of the semiconductor device, and ensuring that the semiconductor device including the shielding structure 31 is provided in a relatively compact manner, which is advantageous for realizing a miniaturized design of the semiconductor device.

[0171] As one possible embodiment, FIG. 17 is a schematic planar structure diagram of another semiconductor device according to an embodiment of the present invention, illustrating an example in which N is equal to 2, and as shown in FIG. 17, optionally, the shielding structure 31 includes a first shielding portion 311, a second shielding portion 312 and a third shielding portion 313, and the second shielding portion 312 is connected to the first shielding portion 311 and the third shielding portion 313, respectively.

[0172] The first shielding portion 311, the second shielding portion 312 and the third shielding portion 313 are all located in the active region 32, the first shielding portion 311 is electrically connected to the first source 241, and the third shielding portion 313 is electrically connected to the second source 242.

[0173] For example, the first shielding portion 311, the second shielding portion 312, and the third shielding portion 313 are all located in the operating region 32, rather than being provided in the scribe region 33. In this way, the semiconductor device including the shielding structure 31 can be provided compactly, and it can be ensured that the semiconductor device has a small volume, which is advantageous for realizing a miniaturized design of the semiconductor device.

[0174] FIG. 20 is a schematic planar structure diagram of another semiconductor device according to an embodiment of the present invention. As shown in FIG. 19, FIG. 14, FIG. 17 and FIG. 20, optionally, the shape of the connection portion between the first shielding portion 311 and the second shielding portion 312 includes an "L" shape or a "T" shape, and the shape of the connection portion between the third shielding portion 313 and the second shielding portion 312 includes an "L" shape or a "T" shape.

[0175] 19, 14, and 17, the shape of the connection portion between the first shielding portion 311 and the second shielding portion 312 includes an “L” shape, and as shown in FIG. 20, the shape of the connection portion between the first shielding portion 311 and the second shielding portion 312 includes a “T” shape. The shape of the connection portion between the first shielding portion 311 and the second shielding portion 312 includes an “L” shape means that the shielding structure 31 is directly bent on the gate bonding pad 29 side to connect to the source in the active region aa and does not extend toward the drain bonding pad 30, and the shape of the connection portion between the first shielding portion 311 and the second shielding portion 312 includes a “T” shape means that the shielding structure 31 may be directly bent on the gate bonding pad 29 side to connect to the source in the active region aa and extend toward the drain bonding pad 30. The embodiments of the present invention are described by taking two possible embodiments as examples, but do not limit the specific shape of the shielding structure 31, as long as the connection point between the first shielding portion 311 and the second shielding portion 312 is an effective connection, the shielding effect of the shielding structure 31 is not affected, and the stable performance of the semiconductor device can be effectively guaranteed.

[0176] FIG. 21 is a partial planar structural schematic diagram of a shielding structure according to an embodiment of the present invention. Optionally, the shielding structure 31 includes a first portion 81 extending along a first direction (X direction shown in the figure) and a second portion 82 extending along a second direction (Y direction shown in the figure), and the first direction and the second direction are both parallel to a plane on which the substrate 21 is located, and the first direction and the second direction intersect; The connecting corner between the first portion 81 and the second portion 82 includes a chamfered corner or a rounded corner.

[0177] For example, as shown in FIG. 21 , the connection corner between the first part 81 and the second part 82 is an arc-shaped corner, and the connection corner between the first part 81 and the second part 82 of the shielding structure 31 is a chamfered corner or an arc-shaped corner, which not only can effectively shield silver ions during packaging and effectively shield and protect the gate bonding pad 29, but also can effectively reduce the peak value of the tip electric field and ensure good performance of the semiconductor device.

[0178] FIG. 22 is a partial planar structural schematic diagram of another shielding structure according to an embodiment of the present invention. As shown in FIG. 22, the shielding structure 31 includes a first portion 81 extending along a first direction and a second portion 82 extending along a second direction, the first direction and the second direction are both parallel to a plane on which the substrate is located, and the first direction and the second direction intersect with each other. The shielding structure 31 further includes a third portion 83, which is connected to the first portion 81 and the second portion 82, respectively, and an included angle r1 between the third portion 83 and the first portion 81 is an obtuse angle, and an included angle r2 between the third portion 83 and the second portion 82 is an obtuse angle.

[0179] For example, as shown in FIG. 22, the third part 83 of the shielding structure 31 is connected to the first part 81 and the second part 82, respectively, and the included angles r1 and r2 in FIG. 22 are formed, respectively. The rational connection between the first part 81, the second part 82 and the third part 83 not only can effectively shield silver ions during packaging and effectively shield and protect the gate bonding pad 29, but also can reduce the peak value of the tip electric field, realize a rational distribution of the electric field, and ensure good performance of the semiconductor device.

[0180] Continuing to refer to FIG. 19 , optionally, the shielding structure 31 includes a first portion 81 extending along a first direction and a second portion 82 extending along a second direction, the first direction and the second direction are both parallel to a plane in which the substrate is located, and the first direction and the second direction intersect; The semiconductor device includes a first boundary extending along a first direction and a second boundary extending along a second direction; A minimum distance L1 between the first portion 81 and the first boundary satisfies L1>30 μm; The minimum distance L2 between the second portion 82 and the second boundary satisfies L2>30 μm.

[0181] For example, by controlling the minimum distance L1 between the first portion 81 and the first boundary and the minimum distance L2 between the second portion 82 and the second boundary to be both greater than 30 μm, it is favorable to increase the distance that the silver ions in the patching silver paste travel to the gate bonding pad 29 under the action of the electric field, and the good shielding effect of the shielding structure 31 is further ensured.

[0182] Continuing to refer to FIG. 19 , optionally, the shielding structure 31 includes a first portion 81 extending along a first direction and a second portion 82 extending along a second direction, the first direction and the second direction are both parallel to a plane in which the substrate is located, and the first direction and the second direction intersect; The extension width D1 of the first portion 81 in the second direction satisfies D1>10 μm, The extension width D2 of the second portion 82 in the first direction satisfies D2>10 μm.

[0183] For example, the extension width D1 in the second direction of the first part 81 of the shielding structure 31 and the extension width D2 in the first direction of the second part 82 are both greater than 10 μm, which is a reasonable extension width, which is beneficial to ensure the shielding effect of the shielding structure 31; otherwise, the shielding effect may be too poor, and some silver ions may migrate to the gate bonding pad, causing a short circuit between the gate and the source, which may directly affect the stable performance of the semiconductor device.

[0184] Continuing to refer to FIG. 19, optionally, a minimum pitch L3 between the vertical projection of the shielding structure 31 onto the plane in which the substrate 21 lies and the vertical projection of the gate bonding pad 29 onto the plane in which the substrate 21 lies satisfies L3>10 μm.

[0185] The minimum pitch L4 between the vertical projection of the shielding structure 31 onto the plane on which the substrate 21 lies and the vertical projection of the drain bonding pad 30 onto the plane on which the substrate 21 lies satisfies L4>10 μm.

[0186] For example, the minimum pitch L3 between the vertical projection of the shielding structure 31 onto the plane on which the substrate 21 is located and the vertical projection of the gate bonding pad 29 onto the plane on which the substrate 21 is located is greater than 10 μm, and the minimum pitch L4 between the vertical projection of the shielding structure 31 onto the plane on which the substrate 21 is located and the vertical projection of the drain bonding pad 30 onto the plane on which the substrate 21 is located is greater than 10 μm. This arrangement not only reduces the parasitic capacitance between the shielding structure 31 and the gate bonding pad 29 and the drain bonding pad 30, but also effectively shields silver ions during packaging to effectively shield and protect the gate bonding pad 29, and ensures good performance of the semiconductor device.

[0187] Based on the above embodiment, the multiple semiconductor layers in the semiconductor device 20 according to the embodiment of the present invention may specifically include a nucleation layer located on a substrate, a buffer layer located on the side of the nucleation layer away from the substrate, a channel layer located on the side of the buffer layer away from the nucleation layer, and a barrier layer located on the side of the channel layer away from the buffer layer, whereby a heterojunction structure is formed by the barrier layer and the channel layer, and a 2DEG (not shown) is formed at the heterojunction interface.

[0188] Exemplarily, the materials of the nucleation layer and the buffer layer may be nitrides, specifically GaN, AlN, or other nitrides, and the nucleation layer and the buffer layer may be used to match the material of the underlying substrate 10 and the epitaxial channel layer. The material of the channel layer may be GaN or other semiconductor materials, for example, InAlN. The barrier layer is located on the channel layer, and the material of the barrier layer may be any semiconductor material capable of forming a heterojunction structure with the channel layer, including a gallium-based compound semiconductor material or a nitride-based compound semiconductor material, for example, InAlN. x Al y Ga z N 1-x-y-zwhere 0≦x≦1, 0≦y≦1, and 0≦z≦1. Optionally, the channel layer and the barrier layer form a semiconductor heterojunction structure, and a high concentration of two-dimensional electron gas is formed at the interface between the channel layer and the barrier layer.

[0189] It should be understood that the embodiments of the present invention provide for improving the output power of a semiconductor device in terms of the structural design of the semiconductor device. The semiconductor devices include high-power gallium nitride high electron mobility transistors (HEMTs) that operate in high-voltage, high-current environments, silicon-on-insulator (SOI) transistors, gallium arsenide (GaAs)-based transistors, and metal-oxide-semiconductor field-effect transistors (MOSFETs), metal-semiconductor field-effect transistors (MISFETs), double heterojunction field-effect transistors (DHFETs), junction field-effect transistors (JFETs), metal-semiconductor field-effect transistors (MESFETs), and metal-semiconductor heterojunction field-effect transistors (MESFETs). Field-Effect Transistor (abbreviated as MISHFET) or other field effect transistors, but are not limited to these.

[0190] Based on the same inventive concept, an embodiment of the present invention further provides a method for fabricating a semiconductor device, which may include the following steps S301 to S305. S301 is to prepare a substrate. By way of example, the substrate material may be Si, SiC, gallium nitride or sapphire, or any other material suitable for the growth of gallium nitride. S302 is to fabricate multiple semiconductor layers on one side of a substrate. Exemplarily, the plurality of semiconductor layers are located on one side of the substrate, and the plurality of semiconductor layers may be specifically made of III-V compound semiconductor materials, and a 2DEG is formed in the plurality of semiconductor layers. S303 is to fabricate a gate in an active area of ​​the semiconductor layers on the side farther from the substrate. S304 is to fabricate at least one bonding pad in a passive region on a side of the multiple semiconductor layers away from the substrate, the bonding pad including at least a gate bonding pad, the gate bonding pad being electrically connected to a gate. S305 is to fabricate at least one shielding structure on a side of the multiple semiconductor layers away from the substrate, the shielding structure including a gate shielding structure, the gate shielding structure being for shielding and protecting a gate bonding pad.

[0191] By fabricating the shielding structure on the side of the multiple semiconductor layers farther from the substrate, the installation of the shielding structure can effectively block the migration of silver ions in the silver paste used for patching to the bonding pads during packaging, ensure the stable performance of the bonding pads and the electrodes connected to the bonding pads, avoid the occurrence of short circuits between the bonding pads and the electrodes connected to the bonding pads and the source, and ensure the normal operation of the semiconductor device.

[0192] It should be noted that the above is merely a preferred embodiment of the present invention and the technical principles applied thereto. As can be understood by those skilled in the art, the present invention is not limited to the specific embodiment described herein, and various obvious changes, adjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in relatively detail by the above embodiment, the present invention is not limited to the above embodiment, and can further include many other equivalent embodiments without departing from the concept of the present invention, and the scope of protection of the present invention is defined by the appended claims.

Claims

1. 1. A semiconductor device comprising: an active area; and a non-active area surrounding the active area; The semiconductor device is A substrate; a plurality of semiconductor layers located on one side of the substrate; at least one shielding structure located on one side of the substrate, the shielding structure being electrically connected to a predetermined potential to create an electric field or a zero electric field from the active area to the non-active area; Further comprising: The plurality of semiconductor layers includes a conductive region and a two-dimensional electron gas elimination region located in the non-active region, the two-dimensional electron gas elimination region being located between the conductive region and the active region, the conductive region being the shielding structure, and / or The semiconductor device further includes a dielectric layer located on a side of the plurality of semiconductor layers farther from the substrate, and at least one conductive wiring located on a side of the dielectric layer farther from the plurality of semiconductor layers, the conductive wiring being the shielding structure; the shielding structure includes a fourth shielding portion and a fifth shielding portion, the fourth shielding portion extends along a first direction, the fifth shielding portion extends along a second direction, the first direction and the second direction intersect with each other and are both parallel to a plane on which the substrate is located; the fourth shielding portion includes a plurality of first sub-shielding structures, two of the first sub-shielding structures adjacent to each other along the first direction are shifted in the second direction and overlap each other in vertical projection onto a first plane, the first plane being parallel to the first direction and perpendicular to a plane on which the substrate is located; and / or A semiconductor device, wherein the fifth shielding portion includes a plurality of second sub-shielding structures, and two adjacent second sub-shielding structures along the second direction are offset in the first direction and have overlapping vertical projections onto a second plane, and the second plane is parallel to the second direction and perpendicular to a plane in which the substrate is located.

2. an operating area and a scribe area surrounding the operating area, the operating area including the active area and the passive area; The semiconductor device is at least one bonding pad located on a side of the plurality of semiconductor layers away from the substrate and located in the passive region; 2. The semiconductor device according to claim 1, wherein the shielding structure is for shielding and protecting the bonding pad, and the predetermined potential is equal to or greater than 0.

3. the shielding structure includes a first shielding portion, a second shielding portion, and a third shielding portion, the first shielding portion being located on a side of the inactive area away from the active area; the first shielding portion is electrically connected to the second shielding portion and the third shielding portion, and an extension direction of the first shielding portion intersects with both an extension direction of at least a part of the second shielding portion and an extension direction of at least a part of the third shielding portion; 2. The semiconductor device of claim 1, wherein the shielding structure is located on at least three sides of the non-active area away from the active area.

4. 4. The semiconductor device of claim 3, wherein at least some of the shielding structures are free of a dielectric layer on a side remote from the substrate.

5. the plurality of semiconductor layers includes a conductive region located in the inactive region and the two-dimensional electron gas elimination region; 2. The semiconductor device of claim 1, wherein the conductive region is a two-dimensional electron gas forming region or a semiconductor doped region.

6. The semiconductor device further includes a gate located on a side of the plurality of semiconductor layers farther from the substrate and located in the active region, and a drain located on a side of the plurality of semiconductor layers farther from the substrate and located in the active region, the bonding pads include a gate bonding pad electrically connected to the gate and / or a drain bonding pad electrically connected to the drain; 3. The semiconductor device of claim 2, wherein at least one shielding structure includes a gate shielding structure for shielding and protecting the gate bonding pad and / or a drain shielding structure for shielding and protecting the drain bonding pad.

7. 3. The semiconductor device of claim 2, wherein the active area further comprises a plurality of fixed potential structures, and the shielding structure is electrically connected to the fixed potential structures.

8. the fixed potential structure includes a source, the shielding structure is electrically connected to the source; the sources include a first source and an Nth source arranged along a first direction, the first direction being parallel to a plane in which the substrate is located, the first source being located at a first end of the active region, the Nth source being located at a second end of the active region, and the first end and the second end being provided opposite to each other along the first direction; 8. The semiconductor device of claim 7, wherein the shielding structure is electrically connected to the first source and the Nth source, respectively, and a gate bonding pad is located within an area defined by the shielding structure and the active area.

9. The source is electrically connected to a source back electrode through a via hole; an overlapping area between the vertical projection of the shielding structure onto the plane on which the substrate is located and the vertical projection of the via hole onto the plane on which the substrate is located is S1; The area of ​​the vertical projection of the via hole onto the plane on which the substrate is located is S2, 9. The semiconductor device of claim 8, wherein S1<S2 / 4.

10. 10. The semiconductor device of claim 9, wherein a vertical projection of the shielding structure onto the plane in which the substrate lies and a vertical projection of the via hole onto the plane in which the substrate lies do not overlap.

11. the shielding structure includes a first shielding portion, a second shielding portion, and a third shielding portion, the second shielding portion being connected to the first shielding portion and the third shielding portion, respectively; 9. The semiconductor device of claim 8, wherein the second shielding portion is located in the scribe region, the first shielding portion is located in the operating region and is electrically connected to the first source, and the third shielding portion is located in the operating region and is electrically connected to the N source.

12. The semiconductor device further includes a first dielectric layer located on a side of the plurality of semiconductor layers away from the substrate and located in the passive region; the first shielding portion and the third shielding portion are both located on a side of the first dielectric layer farther from the substrate, 12. The semiconductor device of claim 11, wherein a thickness of the shielding structure is greater than a thickness of the first dielectric layer along a direction perpendicular to the substrate, such that the first shielding portion and the third shielding portion are both electrically connected to the second shielding portion.

13. The semiconductor device further includes a first dielectric layer located on a side of the plurality of semiconductor layers away from the substrate and located in the passive region; 12. The semiconductor device of claim 11, wherein a thickness of the source is greater than a thickness of the first dielectric layer along a direction perpendicular to the substrate such that the first shielding portion and the third shielding portion are both electrically connected to the source.

14. The semiconductor device further includes a second dielectric layer located in the active region; the second dielectric layer covers the first shielding portion, the third shielding portion, and the source; 14. The semiconductor device of claim 13, wherein in a direction perpendicular to the substrate, a sum of thicknesses of the first dielectric layer, the first shielding portion, and the second dielectric layer is greater than a thickness of the source, such that the second dielectric layer located on the side of the first shielding portion farther from the substrate is connected to the second dielectric layer located on the side of the source farther from the substrate.

15. the shielding structure includes a first shielding portion, a second shielding portion, and a third shielding portion, the second shielding portion being connected to the first shielding portion and the third shielding portion, respectively; 9. The semiconductor device of claim 8, wherein the first shielding portion, the second shielding portion, and the third shielding portion are all located in the active region, the first shielding portion is electrically connected to the first source, and the third shielding portion is electrically connected to the N source.

16. The semiconductor device further includes at least one dielectric layer located on a side of the plurality of semiconductor layers away from the substrate and located in the passive region; At least one of the dielectric layers includes a first surface located on a side of the plurality of semiconductor layers that is remote from the substrate; the shielding structure includes a second surface of the plurality of semiconductor layers located away from the substrate; 16. The semiconductor device of claim 15, wherein the second surface is located on a side of the first surface that is farther from the substrate along a direction perpendicular to the substrate.

17. the source includes a plurality of source metal layers; 9. The semiconductor device of claim 8, wherein the shielding structure includes one shielding metal layer, and the shielding metal layer and any one of the multiple source metal layers are provided in the same layer and are made of the same material, or the shielding structure includes multiple shielding metal layers, and the multiple shielding metal layers and the multiple source metal layers correspond one-to-one, and the corresponding shielding metal layer and source metal layer are provided in the same layer and are made of the same material.

18. the shielding structure includes a first portion extending along a first direction and a second portion extending along a second direction, the first direction and the second direction are both parallel to a plane on which a substrate is located, and the first direction and the second direction intersect; the semiconductor device includes a first boundary extending along the first direction and a second boundary extending along the second direction; A minimum distance L1 between the first portion and the first boundary satisfies L1>30 μm; The semiconductor device according to claim 1 , wherein a minimum distance L2 between the second portion and the second boundary satisfies L2>30 μm.

19. the shielding structure includes a first portion extending along a first direction and a second portion extending along a second direction, the first direction and the second direction are both parallel to a plane on which a substrate is located, and the first direction and the second direction intersect; The extension width D1 of the first portion in the second direction satisfies D1>10 μm, The semiconductor device according to claim 1 , wherein an extension width D2 of the second portion in the first direction satisfies D2>10 μm.

20. A minimum pitch L3 between the vertical projection of the shielding structure onto the plane on which the substrate is located and the vertical projection of the gate bonding pad onto the plane on which the substrate is located satisfies L3>10 μm; 7. The semiconductor device of claim 6, wherein a minimum pitch L4 between the vertical projection of the shielding structure onto the plane in which the substrate is located and the vertical projection of the drain bonding pad onto the plane in which the substrate is located satisfies L4>10 μm.

21. A method for producing a semiconductor device according to any one of claims 1 to 20, comprising the steps of: Preparing a substrate; forming a plurality of semiconductor layers on one side of the substrate; and fabricating at least one shielding structure on one side of the substrate, the shielding structure being electrically connected to a predetermined potential to create an electric field or a zero electric field from the active area to the non-active area.

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