Silicon carbide semiconductor device and manufacturing method thereof

Abstract

To improve the performance of a silicon carbide semiconductor device that comprises a vertical SiC power MISFET with a trench formed on a top face of an SiC epitaxial substrate.SOLUTION: A silicon carbide semiconductor device has: a trench 9 formed on a top face of a semiconductor layer, comprising a lateral face 9a and a lateral face 9b opposed to each other in a first direction along the top face of the semiconductor layer; a gate electrode 2 formed inside the trench 9 via an insulating film 7; a body layer 5 in contact with the lateral face 9a; and a guard region 8 that covers a lateral face 9a side corner of a bottom face of the trench 9, being separated from a lateral face 9b side corner of the bottom face of the trench 9. In the first direction, a film thickness of the insulating film 7 covering the lateral face 9b is larger than that of the insulating film 7 covering the lateral face 9a.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a silicon carbide semiconductor device, which is a power semiconductor device, and in particular to one having a trench structure, and to a method for manufacturing the same. [Background technology]

[0002] Semiconductor power elements are required to have high breakdown voltage, low on-resistance, and low switching loss, but silicon (Si) power elements, which are currently the mainstream, are approaching their theoretical performance limits. Silicon carbide (SiC) has a dielectric breakdown field strength approximately one order of magnitude higher than Si, so by making the drift layer that maintains the breakdown voltage approximately one-tenth thinner and increasing the impurity concentration by approximately 100 times, it is theoretically possible to reduce element resistance by three orders of magnitude or more. In addition, because the band gap is approximately three times larger than that of Si, high temperature operation is also possible, and SiC semiconductor elements are expected to exceed the performance of Si semiconductor elements, and the development of SiC power devices is underway.

[0003] Patent Document 1 (JP 2015-72999 A) describes a semiconductor device having an n-type substrate made of silicon carbide, an n-type drift layer on the substrate, and a plurality of trenches formed in a stripe pattern on the drift layer. Here, it is described that the semiconductor device has a gate electrode formed in each trench via an insulating film, and an n-type current spreading layer formed on the drift layer and having a higher impurity concentration than the drift layer. The gate electrode constitutes a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and the bottom of the trench is covered with a p-type bottom layer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2015-72999 A [Patent Document 2] Patent Publication No. 2021-12934 Summary of the Invention [Problem to be solved by the invention]

[0005] A structure with a trench allows an increase in the channel area, and is expected to reduce the on-resistance. However, in general, there is a trade-off between on-resistance and breakdown voltage. In addition, since a large electric field is applied to the insulating film in the trench, it is also important to alleviate the electric field in the insulating film. As a technique for alleviating the electric field in the insulating film, for example, as described in Patent Document 1 and Patent Document 2, covering the bottom of the trench with a p-type layer is effective.

[0006] However, forming a p-type layer that covers the entire bottom of the trench requires a large gap between adjacent trenches, which increases the cell pitch. In addition, in Patent Document 1, a p-type layer is further formed between the trenches to prevent the gate insulating film from being destroyed by a surge due to the floating potential of the p-type layer at the bottom of the trench. This p-type layer increases the cell pitch, and a depletion layer is formed from the p-type layer, which increases the on-resistance.

[0007] Patent Document 2 describes a structure in which the channel is oriented vertically and the bottom of the trench is covered with a p-type bottom layer, based on the structure of Patent Document 1. However, the structure of Patent Document 2 has a problem that when the cell pitch is narrowed to achieve low on-resistance, the trench spacing affects the width of the JFET region, resulting in high JFET resistance.

[0008] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0009] A brief outline of a representative embodiment of the present invention will be described below.

[0010] One embodiment of a silicon carbide semiconductor device includes a trench formed in an upper surface of a semiconductor layer, the trench having a first side and a second side opposing each other in a first direction along the upper surface of the semiconductor layer, a gate electrode formed inside the trench via an insulating film, a body layer in contact with the first side, and a guard region covering a corner of a bottom surface of the trench on the first side surface side and spaced apart from a corner of the bottom surface of the trench on the second side surface side, wherein in the first direction, the thickness of the insulating film covering the first side surface is greater than the thickness of insulating film 7 covering the first side surface.

[0011] A method for manufacturing a silicon carbide semiconductor device according to one embodiment includes the steps of forming, in order from the top surface side of a semiconductor substrate containing silicon carbide, a source region, a body layer, and a drift layer, forming a guard region in the drift layer, and forming a trench on the top surface of the semiconductor substrate and a gate electrode in the trench. The trench has a first side and a second side opposing each other in a first direction along the top surface of the semiconductor substrate. Here, in the gate electrode forming step, a portion of a conductive film buried in the trench via an insulating film that faces the second side is removed to form a gate electrode made of the conductive film on the first side. Effect of the Invention

[0012] The effects obtained by the representative inventions among those disclosed in this application will be briefly described as follows.

[0013] According to the present invention, the performance of a silicon carbide semiconductor device can be improved. [Brief description of the drawings]

[0014] [Figure 1] 1 is a plan view showing a silicon carbide semiconductor device according to a first embodiment of the present invention. [Diagram 2] 1 is a perspective view showing a silicon carbide semiconductor device according to a first embodiment of the present invention. [Diagram 3] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Figure 4] FIG. 4 is an enlarged cross-sectional view of a part of FIG. [Diagram 5] 1A to 1C are cross-sectional views illustrating a method for manufacturing a silicon carbide semiconductor device according to a first embodiment of the present invention. [Figure 6] 6 is a cross-sectional view illustrating the method for manufacturing the silicon carbide semiconductor device subsequent to FIG. 5. [Figure 7] 7 is a cross-sectional view illustrating the method for manufacturing the silicon carbide semiconductor device subsequent to FIG. 6. [Figure 8] 8 is a cross-sectional view illustrating the method for manufacturing the silicon carbide semiconductor device subsequent to FIG. 7. [Figure 9] 9 is a cross-sectional view illustrating the method for manufacturing the silicon carbide semiconductor device subsequent to FIG. 8. [Figure 10] 10 is a cross-sectional view illustrating the method for manufacturing the silicon carbide semiconductor device subsequent to FIG. 9. [Figure 11] 11 is a cross-sectional view illustrating the method for manufacturing the silicon carbide semiconductor device subsequent to FIG. 10. [Figure 12] 1 is a cross-sectional view showing a silicon carbide semiconductor device according to a first modification of the first embodiment of the present invention. [Figure 13] FIG. 2 is a plan view showing a silicon carbide semiconductor device according to a second modification of the first embodiment of the present invention. [Figure 14] FIG. 11 is a cross-sectional view showing a silicon carbide semiconductor device according to a second embodiment of the present invention. [Figure 15] 5A to 5C are cross-sectional views illustrating a method for manufacturing a silicon carbide semiconductor device according to a second embodiment of the present invention. [Figure 16] 16 is a cross-sectional view illustrating the method for manufacturing the silicon carbide semiconductor device subsequent to FIG. 15. [Figure 17] 17 is a cross-sectional view illustrating the method for manufacturing the silicon carbide semiconductor device subsequent to FIG. 16. [Figure 18] 18 is a cross-sectional view illustrating the method for manufacturing the silicon carbide semiconductor device subsequent to FIG. 17. [Figure 19] 19 is a cross-sectional view illustrating the method for manufacturing the silicon carbide semiconductor device subsequent to FIG. 18. [Figure 20] 10A to 10C are cross-sectional views illustrating a method for manufacturing a silicon carbide semiconductor device according to a modified example of the second embodiment of the present invention. [Figure 21]21 is a cross-sectional view illustrating the method for manufacturing the silicon carbide semiconductor device continued from FIG. 20. [Figure 22] 22 is a cross-sectional view illustrating the method for manufacturing the silicon carbide semiconductor device subsequent to FIG. 21. [Diagram 23] FIG. 1 is a cross-sectional view showing a silicon carbide semiconductor device as a comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Hereinafter, the embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, the same reference numerals are used for the members having the same functions, and the repeated explanations are omitted. In addition, in the following embodiments, the explanations of the same or similar parts are not repeated in principle, except when particularly necessary. In addition, in the drawings for explaining the embodiments, hatching may be used even in plan views or perspective views, etc., in order to make the configuration easier to understand. Furthermore, in the drawings for explaining the embodiments, hatching may be omitted in cross-sectional views in order to make the configuration easier to understand.

[0016] Also," - " and " + " is a code that indicates the relative impurity concentration of the conductivity type, n-type or p-type. For example, "n -- ", "n - ", "n", "n + ", "n ++ The concentration of n-type impurities increases in this order.

[0017] <Details of areas for improvement> Hereinafter, the room for improvement will be described in detail with reference to FIG. 23. As shown in FIG. 23, in the comparative example, n + On a silicon carbide (SiC) substrate on which a drain region 12 of n-type is formed, - A drain region 12, a drift layer 4, an n-type current diffusion region 17, a p-type body layer 5, and a source region 6 are formed in this order. ++A plurality of trenches 9 are formed in a row on the upper surface of a semiconductor substrate consisting of a source region 6 of a silicon carbide type. The bottom of each trench 9 reaches halfway to the depth of the current diffusion region 17, and a guard region 8a is formed in the semiconductor substrate so as to cover the bottom. A gate electrode 2 is formed in the trench 9 via an insulating film 7f, which is a gate insulating film, and the upper surface of the gate electrode 2 is covered with an insulating film 16. A source electrode 1 covering the gate electrode 2 and the insulating film 16 is formed on the semiconductor substrate. The guard regions 8a at the bottoms of adjacent trenches 9 are spaced apart from each other, and a JFET region 13 is formed in the region between the trenches 9. A drain electrode 3 is formed in contact with the lower surface of the drain region 12, that is, the lower surface of the semiconductor substrate. The gate electrode 2, the source region 6, and the drain region 12 constitute a SiC power MISFET (Metal Insulator Semiconductor Field Effect Transistor).

[0018] The structure with a trench as in the comparative example is expected to increase the area of ​​the channel and reduce the on-resistance. However, in general, there is a trade-off between on-resistance and breakdown voltage, and particularly in the case of a JFET region, narrowing the width of the JFET region increases the breakdown voltage, but also increases the resistance (JFET resistance). For this reason, the design of the JFET region is very important. Furthermore, SiC has a wider band gap and higher dielectric breakdown strength than Si, but the electric field applied to the insulating film is also larger, so it is important to mitigate the electric field of the insulating film. If the electric field in the insulating film is strong, a leakage current occurs in the gate insulating film, which leads to a decrease in the gate insulating film life and device malfunction such as dielectric breakdown of the gate insulating film.

[0019] In the above comparative example, the electric field applied to the insulating film 7f is alleviated by covering the bottom of the trench 9 with a p-type guard region 8a. However, in order to prevent an increase in on-resistance, it is necessary to provide a certain distance between adjacent guard regions 8a. For this reason, if the guard region 8a is formed to cover the entire bottom of the trench 9, it becomes necessary to ensure a large distance between adjacent trenches 9. In other words, if the adjacent guard regions 8a are brought closer to each other, the width of the JFET region becomes narrower and the resistance (JFET resistance) becomes higher, so it is necessary to ensure a large cell pitch in order to prevent such an increase in resistance.

[0020] Furthermore, in the comparative example, there is a risk that the gate insulating film will be destroyed by a surge due to the floating potential of the p-type layer at the bottom of trench 9. To prevent this, it is conceivable to form an additional p-type layer between trenches 9. However, this p-type layer increases the cell pitch, and furthermore, a depletion layer is formed from the p-type layer, which increases the on-resistance.

[0021] Thus, in a SiC power MISFET having a trench, there is room for improvement in terms of achieving both a reduction in on-resistance and a sufficient breakdown voltage.

[0022] In view of this, the embodiment of the present application is devised to solve the above-mentioned room for improvement. The technical concept of the embodiment in which this devised is devised will be described below.

[0023] (Embodiment 1) Hereinafter, a silicon carbide semiconductor device will be described with reference to the drawings, taking as an example a trench-type MOSFET, which is a SiC power MISFET having the inner side surface of a trench (groove, recess) as a channel region.

[0024] <Structure of Silicon Carbide Semiconductor Device> The structure of the silicon carbide semiconductor device according to the first embodiment will be described with reference to Figs. 1 to 4. Fig. 1 shows an extended portion that is a part of the source electrode as a structure on the semiconductor substrate, but the insulating film and part of the gate electrode that are structures on the semiconductor substrate are omitted. Fig. 1 also omits the illustration of the source region 6 on the upper surface of the semiconductor substrate, and shows a see-through view of the guard region 8 and JFET region 13 that are formed midway through the semiconductor substrate and are aligned with each other. Fig. 2 omits the illustration of the insulating film 7 (gate insulating film and interlayer insulating film), gate electrode 2, and source electrode 1 for ease of understanding.

[0025] As shown in FIG. 1, the cell array constituting the silicon carbide semiconductor device of this embodiment has a configuration in which a plurality of unit cells having a predetermined planar layout are arranged in a matrix. In FIG. 1, one unit cell is surrounded by a dashed line, and a trench formation region in which a plurality of trenches 9 are arranged is surrounded by a dashed line. The X direction and Y direction shown in FIG. 1 are directions along the upper surface (main surface) of the semiconductor substrate. That is, the X direction and the Y direction are directions along the upper surface of the semiconductor layer and the upper surface of the silicon carbide substrate. The X direction and the Y direction are orthogonal to each other in a plan view. The silicon carbide semiconductor device has a plurality of source electrodes 1 formed on the semiconductor substrate and extending in the Y direction. In FIG. 1, a plurality of source electrodes 1 extending in the Y direction are arranged in the X direction, but these source electrodes 1 are integrated via a source electrode 1 (not shown) covering the cell array on the plurality of source electrodes 1 arranged in a stripe shape, and are electrically connected to each other. The source electrode 1 is formed on a p ++ The source electrode 1 is electrically connected to a potential fixing region 14, which is a type semiconductor region. In the following description, unless otherwise specified, the term "source electrode" refers to the portion (source plug, conductive connection portion) formed in a stripe shape in a plan view, and does not include the source electrode 1 on the plurality of stripe-shaped source electrodes 1.

[0026] One unit cell is made up of n ++The semiconductor device has a source region 6 which is a type semiconductor region, a potential clamping region 14 which surrounds the periphery of the source region 6, and a trench 9 which is formed on the upper surface of the semiconductor substrate and which contacts the source region 6 and the potential clamping region 14 in a plan view. The source region 6 formed on the upper surface of the semiconductor substrate is not shown in FIG. 1. The source region 6 is formed directly above the guard region 8 and JFET region 13 shown in FIG. 1. That is, the shape of the source region 6 in a plan view is the same as the shape including the guard region 8 and JFET region 13 shown in FIG. 1.

[0027] The trenches 9 are formed in a matrix in the Y and X directions in contact with the source region 6 extending in the Y direction. Specifically, two trenches 9 are formed in a row in the X direction in contact with one source region 6 in one unit cell, and four trenches 9 are formed in a row in the Y direction. That is, one unit cell has eight trenches 9. A gate electrode 2 is embedded inside each trench 9 via an insulating film 7, which is a gate insulating film. In the present application, the gate electrode 2 in the trench 9 may be called a trench gate electrode. The source electrode 1 extends so as to straddle the source region 6 and the potential fixing region 14 surrounding the periphery of the source region 6. That is, the source region 6 and the potential fixing region 14 are formed directly below the extending source electrode 1. Directly below the source electrode 1, the source electrode 1 and the potential fixing region 14 are electrically connected to the source electrode 1.

[0028] 1, one unit cell has both ends in the X direction in plan view, the source electrode 1 is located at one of the ends, and a potential fixing region 14 is formed on the top surface of the semiconductor substrate at the other end. That is, in plan view, of both ends in the X direction of the unit cell, the end opposite to the end where the source electrode 1 is formed is separated from the source region 6. Therefore, in the X direction, the source regions 6 are connected between the first unit cell and the second unit cell adjacent to it on one side, and the source regions 6 are separated from each other between the first unit cell and the third unit cell adjacent to it on the other side.

[0029] As shown in FIG. 1, one unit cell occupies a range from the center of one of two source electrodes 1 adjacent to each other in the X direction to the middle between the source electrodes 1. One unit cell occupies a range consisting of one source region 6 and the potential clamping region 14 surrounding the source region 6, among the source regions 6 and potential clamping regions 14 arranged alternately in the Y direction. In plan view, a plurality of such unit cells are arranged in the Y direction, and are arranged while being inverted in the X direction. In other words, the unit cells adjacent to each other in the X direction have a planar layout that is line-symmetrical with respect to the boundary line between them. In other words, the structures of the unit cells adjacent to each other in the X direction are line-symmetrical in plan view.

[0030] Here, the trench 9 extends in the X direction, which allows the channel width of the SiC power MISFET to be easily increased. Such an increase in channel width is difficult to achieve in a trench-type MOSFET in which the trench gate electrode extends in the Y direction like the source electrode 1. In contrast, in this embodiment, the island-shaped trench gate electrodes are arranged spaced apart from each other in the Y direction, so that the trench 9 can be extended in the X direction, and the channel width can be easily increased. As a result, the on-resistance of the SiC power MISFET can be reduced.

[0031] Here, a plurality of trenches 9 are arranged in parallel within the trench formation region, thereby making it possible to increase the channel width and reduce loss.

[0032] In addition, the source electrode 1 (source contact region) and the trench formation region are arranged parallel to each other, and the JFET region 13 is arranged in a direction perpendicular to the source electrode 1. This allows the source contact region, trench formation region, and JFET region 13 to be designed independently, improving design flexibility. In particular, since the JFET region 13 is independent of the source electrode 1, it can be designed independently of the source electrode 1, making it possible to narrow the pitch of the JFET regions 13 and increase the number of JFET regions 13.

[0033] As shown in Figures 2 and 3, the silicon carbide semiconductor device of this embodiment has an n-type silicon carbide (SiC) epitaxial substrate (hereinafter referred to as a SiC epitaxial substrate or a semiconductor substrate). The SiC epitaxial substrate (semiconductor substrate) is an n-type semiconductor substrate that contains silicon carbide. + A silicon carbide substrate and a n-type epitaxially grown silicon carbide substrate - The epitaxial layer is a semiconductor layer containing SiC. In each drawing of the present application, the epitaxial layer is mainly composed of n - The drift layer 4 is an n-type semiconductor region. + 2 and 3 and other cross-sectional views, the portion shown as the drain region 12 is the silicon carbide substrate.

[0034] As described above, the drain region 12 is formed in the semiconductor substrate, and the drift layer 4 is formed in the semiconductor substrate on and in contact with the drain region 12. The n-type impurity concentration of the drain region 12 is higher than the n-type impurity concentration of the drift layer 4. The drift layer 4, the body layer 5, the source region 6, the guard region 8, the drain region 12, the JFET region 13, and the potential clamping region 14 (see FIG. 1) are formed in the epitaxial layer. The potential clamping region 14 is not shown in FIGS. 2 and 3.

[0035] A drain electrode 3 is formed in contact with the lower surface of the drain region 12, i.e., the lower surface of the semiconductor substrate. That is, the lower surface of the semiconductor substrate is covered with the drain electrode 3, and the drain electrode 3 is electrically connected to the drain region 12. The drain electrode 3 is made of a laminated conductor film containing, for example, gold (Au). A source region 6 is formed on the upper surface of the semiconductor substrate (upper surface of the epitaxial layer) from the upper surface of the semiconductor substrate to a predetermined depth, and a body layer 5, which is a p-type semiconductor region, is formed between the source region 6 and the drift layer 4 in contact with the lower surface of the source region 6. The source region 6 has a higher n-type impurity concentration than the current diffusion region 17 described below, and is electrically connected to the source electrode 1. The lower surface of the body layer 5 is in contact with the drift layer 4.

[0036] The trenches 9 are formed from the upper surface of the semiconductor substrate to a depth partway within the drift layer 4, extend in the X direction, and are arranged in a row in the Y direction. The drift layer 4, the body layer 5, and the source region 6 contact, in this order from below, both side surfaces of the trench 9 in the Y direction.

[0037] A gate electrode 2 is buried in the trench 9 via an insulating film 7. However, the thickness of the insulating film 7 in the trench 9 is not the same on one side of the trench 9 and the other side of the trench 9 in the short direction (Y direction) of the trench 9 in a plan view. As shown in FIG. 3, the trench 9 has side surfaces 9a and 9b that face each other in the Y direction. Note that the side surfaces of the trench 9 may be tapered, and in that case, the widths of the trench 9 in the X and Y directions are larger on the upper side than on the lower side. For this reason, a line perpendicular to the side surface 9a does not perpendicularly intersect with the side surface 9b. However, even in such a case, the present application will describe the side surfaces 9a and 9b as facing each other.

[0038] Here, a plurality of trenches 9 are arranged side by side without inverting their planar layout in the Y direction. Therefore, among adjacent trenches 9, a side surface 9a of one trench 9 is adjacent to a side surface 9b of the other trench 9. In other words, among adjacent trenches 9, no other trench 9, insulating film 7, or gate electrode 2 is interposed between the side surface 9a of one trench 9 and the side surface 9b of the other trench 9. Therefore, the side surfaces 9a and the side surfaces 9b are alternately arranged in the Y direction.

[0039] The insulating film 7 includes insulating films 7a, 7b, and 10. The insulating film 7a is a thin film that continuously covers all the side surfaces and the bottom surface of the trench 9 and the upper surface of the semiconductor substrate. The gate electrode 2 is formed from inside the trench 9 to the semiconductor substrate (on the source region 6) on the side surface 9a. On the semiconductor substrate (on the source region 6), the gate electrode 2 is formed via a laminated film consisting of insulating films 10 and 7a that are formed in order on the semiconductor substrate. The insulating film 7a covering the side surface 9b and the gate electrode 2 in the trench 9 are spaced apart from each other, and a part of the insulating film 7b is buried between them. Outside the trench 9, that is, on the semiconductor substrate, the insulating film 7b is an interlayer insulating film that covers the insulating films 7a, 10, and the gate electrode 2. That is, the gate electrode 2, the insulating films 7a, and 7b are all formed from inside the trench 9 to the semiconductor substrate.

[0040] In the trench 9, the insulating films 7a and 7b are formed between the gate electrode 2 and the side surface 9b, whereas only the insulating film 7a is formed between the gate electrode 2 and the side surface 9a, and no insulating film 7b is formed. Therefore, as shown in FIG. 4, the film thickness b in the Y direction of the insulating film 7 covering the side surface 9b is larger than the film thickness a in the Y direction of the insulating film 7 covering the side surface 9a, and the gate electrode 2 is formed closer to the side surface 9a in the trench 9. The upper surface of the insulating film 7, which is an interlayer insulating film, is flattened, and a source electrode 1 is formed on the upper surface. The source electrode 1 shown in FIG. 1 penetrates the insulating film 7 and is connected to the source region 6 and the potential fixing region 14. The source electrode 1 on the insulating film 7 shown in FIG. 2 and FIG. 3 is integrated with each of the multiple source electrodes 1, which are contact plugs shown in FIG. 1.

[0041] In a region not shown, the bottom surface of the potential clamping region 14 contacts the body layer 5. The potential clamping region 14 has a higher p-type impurity concentration than both the body layer 5 and the guard region 8. Since the body layer 5 is electrically connected to the source electrode 1 via the potential clamping region 14, a source voltage can be applied from the source electrode 1 to the body layer 5.

[0042] Moreover, the guard region 8 and the JFET region 13 extend in the X direction, and a plurality of them are arranged in the Y direction. That is, the guard region 8 and the JFET region 13 are arranged in stripes. Therefore, a plurality of trenches 9 whose side surfaces 9a contact the body layer 5 and a plurality of body layers 5 contacting the trenches 9 are arranged in the Y direction. In a region not shown, the guard region 8 is electrically connected to the source electrode 1 via the potential fixing region 14, so that a source voltage can be applied from the source electrode 1 to the guard region 8.

[0043] Here, as shown in FIG. 1, FIG. 2, and FIG. 3, a guard region 8, which is a p-type semiconductor region, is formed in the drift layer 4 and separated from each of the body layer 5 and the drain region 12. The p-type impurity concentration of the guard region 8 is lower than the p-type impurity concentration of the potential fixing region 14 and higher than the p-type impurity concentration of the body layer 5. The guard region 8 is formed in contact with each of the multiple trenches 9. The guard region 8 in contact with one trench 9 extends in the X direction. The guard region 8 is in contact with the bottom surface and the side surface 9a of the trench 9, but is not in contact with the side surface 9b. In addition, the guard region 8 is separated from the bottom surface of the trench 9 near the side surface 9b. That is, the guard region 8 is formed so as to cover the corner portion of the trench 9 on the side surface 9a side, and the corner portion on the side surface 9b side is exposed. In other words, the guard region 8 is in contact with a first surface that covers the side surface 9a of the trench 9 and a part of the bottom surface of the trench 9, and is spaced from a second surface that covers the side surface 9b of the trench and another part of the bottom surface of the trench 9.

[0044] The corner of trench 9 referred to here refers to the vicinity of the boundary between the bottom surface and the side surface of trench 9, including the boundary. Even if the bottom surface and the side surface of trench 9 are smoothly connected by a curved surface, the curved portion is referred to as a corner in this application. The guard region 8 covering the corner of one trench 9 is separated from the other trenches 9. The bottom surface of trench 9 is located above the bottom surface of guard region 8 and below the top surface of guard region 8. In addition, in the X direction, side surface 9a of trench 9 is located between the side surfaces on both sides of guard region 8.

[0045] In the drift layer 4, n-type or - A JFET (Junction Field Effect Transistor) region 13, which is a type semiconductor region, is formed alongside the guard region 8 in the Y direction. Specifically, the JFET region 13 is adjacent to the guard region 8 below the body layer 5. The JFET region 13 extends in the X direction alongside the guard region 8 directly below the source electrode 1. The JFET region 13 is a region located between the guard regions 8 adjacent to each other in the Y direction.

[0046] The n-type impurity concentration of the JFET region 13 is equal to or higher than the n-type impurity concentration of the drift layer 4. The n-type impurity concentration of the JFET region 13 is lower than the n-type impurity concentration of the source region 6. The JFET region 13 is a region where, when the SiC power MISFET is in an off state, depletion layers extend from the opposing side surfaces of adjacent guard regions 8, and the depletion layers come into contact with each other to close a current path.

[0047] 4, the thickness c of the insulating film 7 (7a) directly under the gate electrode 2, which is the shortest distance between the bottom surface of the trench 9 and the gate electrode 2, is greater than the thickness a in the Y direction of the insulating film 7 covering the side surface 9a. This makes it possible to reduce the electric field applied to the insulating film 7 from the bottom of the trench 9. The thickness c is the thickness of the insulating film covering the bottom surface of the trench 9, among the insulating films 7, in the direction perpendicular to the upper surface of the semiconductor substrate. The thickness c is, for example, 50 to 500 nm.

[0048] Furthermore, in the Y direction, a distance d which is the shortest distance from a side surface 9b of trench 9 to guard region 8 in contact with the trench 9 is greater than film thickness b. This allows the electric field of insulating film 7 in the vicinity of the corner on the side surface 9b side of trench 9 to be alleviated. Distance d is the distance from the boundary between side surface 9b of trench 9 and the bottom surface of trench 9 to the boundary between the bottom surface of trench 9 and guard region 8. Distance d is, for example, 100 to 500 nm.

[0049] Furthermore, in the thickness direction of the semiconductor substrate (direction perpendicular to the upper surface of the semiconductor substrate), a distance e from the upper surface (top surface) of guard region 8 to the bottom surface of trench 9 is greater than film thickness c. This means that guard region 8 covers the corners on the side surface 9b of trench 9 and also covers the corners on the side surface 9b of gate electrode 2. This makes it possible to reduce the electric field of insulating film 7 at the corners on the side surface 9a of trench 9. Distance e is, for example, 100 to 1000 nm.

[0050] <Operation of Silicon Carbide Semiconductor Device> Next, the operation of the SiC power MISFET of this embodiment will be described with reference to FIG. 4. The SiC power MISFET has at least a drain region 12, a source region 6, a body layer 5, and a gate electrode 2. When the SiC power MISFET is in an on state, as shown in FIG. 4, a channel is formed in the body layer 5 adjacent to the side surface 9a of the trench 9. In contrast, a channel is difficult to form in the body layer 5 adjacent to the side surface 9b of the trench 9. This is because the insulating film 7 covering the side surface 9b of the trench 9 is larger than the insulating film 7 covering the side surface 9a. Also, because the insulating film 7 covering the side surface 9b of the trench 9 is larger than the insulating film 7 covering the side surface 9a, an accumulation layer in which carriers (here, electrons) are accumulated is formed in the drift layer 4 adjacent to the side surface 9b.

[0051] As a result, when the SiC power MISFET is in an on state, the current flowing from the drain region 12 side is likely to flow into the accumulation layer near the side surface 9b of one of the trenches 9 in the drift layer 4 between the adjacent trenches 9. In the on state, the current flows in a channel formed in the body layer 5 adjacent to the side surface 9a of the other trench 9. Therefore, as shown by the thick line in FIG. 4, the current flows in the accumulation layer near the side surface 9b of the trench 9 in the drift layer 4, and flows in a channel formed near the side surface 9a of the other trench 9 in the body layer 5. The density of the current flowing through the channel in the body layer 5 between the adjacent trenches 9 is higher than the density of the current flowing in the drift layer 4 between the adjacent trenches 9. Therefore, it can be said that the main current path of the SiC power MISFET is present on the side surface 9a side of the trench 9, not on the side surface 9b side.

[0052] Also, when the SiC power MISFET is in the off state, no channel is formed, so no current flows. However, in order to suppress the microcurrent between the source and drain when the SiC power MISFET is in the off state and to improve the breakdown voltage, the guard region 8 and the JFET region 13 are provided under the trench 9. That is, by providing the guard region 8, when the SiC power MISFET is in the off state, the depletion layer extending from the adjacent guard regions 8 closes in the JFET region 13 between those guard regions 8, so that the current path between the source and drain is cut off. That is, the guard region 8 has a role of connecting the depletion layers generated around it between the adjacent guard regions 8, thereby suppressing the microcurrent and improving the breakdown voltage. Therefore, even if the impurity concentration of the drift layer 4 is increased in order to reduce the resistance of the element, the breakdown voltage when the element is off can be secured. Also, the guard region 8 has a role of preventing the electric field from concentrating near the corners of the trench 9 and causing insulation breakdown between the epitaxial layer and the gate electrode 2.

[0053] <Method for manufacturing silicon carbide semiconductor device> Next, a method for manufacturing a silicon carbide semiconductor device according to the present embodiment will be described with reference to Figures 5 to 11. The polarities described below may be reversed between p-type and n-type.

[0054] First, as shown in FIG. 5, a silicon carbide substrate (wafer), that is, a SiC bulk substrate, is prepared. The surface orientation of the upper surface of the silicon carbide substrate is the Si surface, the C surface, or another surface orientation, and the off angle of the upper surface is 4 degrees. The silicon carbide substrate may be a substrate produced using a sublimation method, a substrate produced using a solution method, a substrate produced using a gas growth method, or a substrate on which an epitaxial layer has already been deposited. Chemical mechanical polishing (CMP) may be performed before the epitaxial growth process described later. The n-type impurity concentration of the silicon carbide substrate is, for example, 1×10 18 cm -3 ~1×10 21 cm -3 Here, for example, 1×10 18 cm -3The silicon carbide substrate may be of the 4H-SiC, 6H, or 3C crystal type. It is preferable to use a wafer having an off-angle on the upper surface, but an just-angled substrate may also be used.

[0055] Next, an epitaxial layer is formed on the silicon carbide substrate by an epitaxial growth process. That is, epitaxial growth is performed by heating SiH4 and C3H8 at a temperature of 1500°C or higher using H2 as a carrier gas. In this way, an epitaxial layer is formed on the silicon carbide substrate. The impurity concentration and film thickness of the epitaxial layer at this time vary depending on the device to be manufactured. The impurity concentration is, for example, 1×10 14 cm -3 ~1×10 18 cm -3 The thickness of the epitaxial layer is, for example, from several μm to several tens of μm. Also, a high-concentration buffer layer may be formed in the silicon carbide substrate before the epitaxial layer is formed. The impurity concentration of the buffer layer is 1×10 18 cm -3 This epitaxial layer is also called a drift layer 4.

[0056] Next, a process for forming an ion implantation region will be described. The p-type implantation ions are Al (aluminum) or B (boron). The n-type implantation ions are N (nitrogen) or P (phosphorus).

[0057] A p-type body layer, a p-type junction layer, and a p-type junction layer are formed from the top surface of the drift layer 4 to a predetermined depth in the drift layer 4. ++ A p-type potential clamping region 14 (see FIG. 1), a p-type guard region 8, a JFET region 13, and ++ The source region 6 and the body layer 5 are formed by ion implantation. The body layer 5 may be formed by epitaxial growth. The source region 6 and the potential fixing region 14 are in contact with the upper surface of the wafer (the upper surface of the semiconductor substrate) which is a SiC epitaxial substrate.

[0058] The body layer 5 is in contact with the source region 6 and is formed deeper than the source region 6. The body layer 5 is electrically connected to the potential clamping region 14. A plurality of guard regions 8 are formed in the drift layer 4 deeper than the body layer 5. The guard regions are electrically connected to the potential clamping region 14. The JFET region 13 is a region that connects the body layer 5 and the drift layer 4, and is a region sandwiched between the guard regions 8 adjacent to each other. The region between the adjacent guard regions 8 may be regarded as the JFET region 13 without performing ion implantation to form the JFET region 13, but the JFET region 13 may be formed by performing ion implantation to reduce resistance. In this embodiment, a minimum configuration in which the SiC power MISFET operates has been described, but a structure that adds a function such as a termination region may be fabricated.

[0059] Next, a carbon film is deposited around the silicon carbide substrate and the semiconductor substrate made of the epitaxial layer as a cap material for the impurity activation annealing. Then, the impurity activation annealing is performed at a temperature of, for example, 1600 to 1800°C. The carbon layer of the cap material is then removed by oxygen plasma ashing. This annealing has the effect of preventing the surface of the semiconductor substrate from becoming rough. After that, in order to obtain a cleaner surface, a thermal oxide film may be formed to cover the surface of the semiconductor substrate, and then the thermal oxide film may be removed using a diluted hydrofluoric acid solution.

[0060] Next, as shown in FIG. 6, a trench 9 is formed. Here, a trench 9 is formed on the upper surface of the semiconductor substrate by etching using an insulating film 10 as a hard mask, the trench 9 penetrating the source region 6 and the body layer 5 and having a bottom portion within the drift layer. The trench 9 has one side 9a and the other side 9b in the Y direction. The bottom surface of the trench 9 on the side 9a side reaches the middle depth of one guard region 8. On the other hand, the bottom surface of the trench 9 on the side 9b side is separated from the guard region 8. After this, a process for cleaning the etched surface may be performed. For example, the process is performed by forming a thermal oxide film that covers the surface of the semiconductor substrate including the surface of the trench 9, and then removing the thermal oxide film using a diluted hydrofluoric acid solution.

[0061] Next, as shown in Fig. 7, an insulating film 7a constituting a gate insulating film is formed on the semiconductor substrate. The thickness of the insulating film 7a is, for example, about 10 to 100 nm. The insulating film 7a is made of, for example, a deposited oxide insulating film. The thickness of the insulating film 7a formed by deposition is greater in the portion covering the bottom surface of the trench 9 than in the portions covering each of the side surfaces 9a and 9b.

[0062] Next, as shown in FIG. 8, a conductive film 2a, which is an n-type polycrystalline silicon film having a thickness of about 100 to 300 nm, is formed on the semiconductor substrate. Here, the conductive film 2a is deposited by, for example, a CVD (Chemical Vapor Deposition) method. As a result, the conductive film 2a is embedded in the trench 9 via the insulating film 7a. Next, the conductive film 2a is patterned using photolithography and dry etching, thereby exposing a part of the upper surface of the insulating film 7a outside the trench 9.

[0063] 9, a resist pattern 20 made of a photoresist film is formed on the semiconductor substrate. The resist pattern 20 exposes the conductive film 2a on the side surface 9b of the trench 9 and covers the conductive film 2a on the side surface 9a of the trench 9 in a plan view.

[0064] 10, dry etching (anisotropic etching) is performed using the resist pattern 20 as a mask, and then the resist pattern 20 is removed. Here, the portion of the conductive film 2a facing the side surface 9b is removed. In this manner, the conductive film 2a on the side surface 9b side in the trench 9 is removed, and the gate electrode 2 made of the conductive film 2a on the side surface 9a side in the trench 9 is formed.

[0065] 11, an insulating film 7b, which is an interlayer film, is formed to cover the gate electrode 2. The insulating film 7b is made of, for example, a silicon oxide film, and is formed by, for example, a CVD method. As a result, the insulating film 7b is filled in the region in the trench 9 from which the conductive film 2a has been removed by the etching process described with reference to FIG. 10. The insulating films 10, 7a, and 7b constitute the insulating film 7.

[0066] Next, a contact hole for contacting the source region 6 and the potential fixing region 14 is opened in the insulating film 7. That is, the insulating film 7 is etched using a resist pattern formed on the insulating film 7 as a mask to form a contact hole (opening) exposing the upper surface of the semiconductor substrate. Next, a metal film for silicide is deposited on the semiconductor substrate, and silicide is performed by, for example, annealing at 700°C to 1000°C, thereby forming a silicide layer (not shown) that contacts the upper surface of the semiconductor substrate at the bottom of the contact hole over the upper surfaces of the source region 6 and the potential fixing region 14. The silicide layer is a source-base common contact. Then, a contact hole for contacting the gate electrode 2 is opened in the insulating film 7. That is, the insulating film 7 is etched using a resist pattern formed on the insulating film 7 as a mask to form a contact hole (opening) exposing the upper surface of the gate electrode 2.

[0067] Next, the connection hole on the source region 6 of the insulating film 11 is filled, and a source electrode 1 is formed to cover the upper surface of the insulating film 11. Thereafter, the lower surface of the drain region 12 on the lower surface side of the semiconductor substrate is also silicided to form a drain contact, and then a drain electrode 3 is formed. For the silicide metal film, the source electrode 1, and the drain electrode 3, materials such as Ni (nickel) or Al (aluminum) are used. Then, the entire surface of the semiconductor substrate is covered with a surface protection film made of an insulator to protect the device. Then, a process of wiring each electrode is performed, and the silicon carbide semiconductor device of this embodiment is completed.

[0068] <Effects of silicon carbide semiconductor devices> In this embodiment, a gate insulating film having an asymmetric cross-sectional structure is formed for the purpose of reducing the on-resistance and mitigating the electric field in the gate insulating film. Here, as shown in Fig. 3, the thickness b of the insulating film 7 is larger than the thickness a, and a p-type guard region 8 is formed under the insulating film 7 at the trench corner portion below the channel formation surface which is the main current path of the trench-type SiC power MISFET.

[0069] When the SiC power MISFET is in the on state, an accumulation layer is formed in the n-type region (here, the drift layer 4) in contact with the side surface 9b, and a current passes through the accumulation layer near the side surface 9b, enters the inversion layer formed in the body layer 5 in contact with the side surface 9a, and flows from the source region 6 to the source electrode 1. This makes it possible to reduce the on-resistance.

[0070] In the off state, the trench corners in contact with the side surface 9a are protected by the guard region 8, so no electric field concentration occurs, and the trench corners in contact with the side surface 9b have the thick insulating film 7, so the electric field is alleviated, thereby improving reliability.

[0071] Moreover, here, the guard region 8 at the bottom of the trench 9 is formed in a small region on one side (side surface 9a side) of the trench 9, and the guard region 8 is not formed on the other side (side surface 9b side) of the trench 9. Therefore, compared to the comparative example in which the entire bottom surface of the trench 9 is covered with the guard region 8a (see FIG. 23), the distance between adjacent trenches 9 can be narrowed. This allows the cell pitch to be reduced, and the on-resistance to be reduced. This allows both the reduction in on-resistance and the assurance of the breakdown voltage to be achieved, and the above-mentioned room for improvement can be resolved.

[0072] Moreover, here, a plurality of guard regions 8 are arranged in a stripe pattern, and it is easy to supply a potential to each of them. Therefore, since the potential of the guard regions 8 does not float, there is no need to form an additional p-type layer between the trenches 9 in order to prevent the destruction of the gate insulating film due to a surge. This makes it possible to prevent an increase in the cell pitch.

[0073] As described above, in this embodiment, the performance of the silicon carbide semiconductor device can be improved.

[0074] <Variation 1> 12, a current diffusion region 17 which is an n-type semiconductor region may be formed under the body layer 5 in the semiconductor layer. Here, the current diffusion region 17 is formed in an upper part in the drift layer 4 and contacts the lower surface of the body layer 5. The current diffusion region 17 also contacts the side surfaces of the trench 9 including the side surfaces 9a and 9b. The lower surface of the current diffusion region 17 also contacts the upper surface of the guard region 8. The impurity concentration of the current diffusion region 17 is lower than the impurity concentration of the source region 6 and higher than the impurity concentration of the drift layer 4.

[0075] The current diffusion region 17 is a low-resistance region for diffusing the current flowing in the drift layer 4 laterally (X direction or Y direction) and allowing the current to flow in a wide area. In other words, forming the current diffusion region 17 makes it possible to prevent the current from flowing locally. Therefore, the resistance of the SiC power MISFET can be reduced.

[0076] The current spreading region 17 can be formed by implanting n-type impurities into the epitaxial layer by ion implantation in the manufacturing process of the silicon carbide semiconductor device described with reference to Fig. 5. By increasing the concentration of the impurities introduced in the process of forming the current spreading region 17, the resistance of the current spreading region 17 can be made lower.

[0077] Here, since there is no current diffusion region 17, which is a high-concentration current path, between adjacent guard regions 8, in the off state, a depletion layer is likely to close between adjacent guard regions 8. This makes it possible to improve the reliability of the silicon carbide semiconductor device.

[0078] <Variation 2> The planar layout of the SiC power MISFET may be as shown in Fig. 13. In Fig. 13, one unit cell is surrounded by a dashed line, and a trench formation region where a plurality of trenches 9 are arranged is surrounded by a dashed line.

[0079] The present modified example shown in FIG. 13 differs from the structure shown in FIG. 1 in that the trenches 9 are not lined up in the X direction within one unit cell, but are lined up only in the Y direction.

[0080] Here, a plurality of trenches 9 are arranged in parallel within the trench formation region, thereby making it possible to increase the channel width and reduce loss.

[0081] In addition, the source electrode 1 (source contact region) and the trench formation region are arranged parallel to each other, and the JFET region 13 is arranged in a direction perpendicular to the source electrode 1. This allows the source contact region, trench formation region, and JFET region 13 to be designed independently, improving design flexibility. In particular, since the JFET region 13 is independent of the source electrode 1, it can be designed independently of the source electrode 1, making it possible to narrow the pitch of the JFET regions 13 and increase the number of JFET regions 13.

[0082] In this case, compared to the structure shown in FIG. 1, the source region 6 adjacent to the trench 9 is closer to the source electrode 1, so that a source potential can be stably supplied to the source region 6.

[0083] (Embodiment 2) In the above embodiment 1, a gate electrode is formed and then a portion of the gate electrode is removed. Hereinafter, however, a gate electrode is formed in the trench after an insulating film is formed asymmetrically in the trench.

[0084] A cross section of the SiC power MISFET of the present embodiment is shown in Fig. 14. As shown in Fig. 14, the structure inside the semiconductor substrate is almost the same as that of the first embodiment, but the structures of the insulating film and the gate electrode on the semiconductor substrate are different from those of the first embodiment.

[0085] Here, the insulating film 7 includes insulating films 7c, 7d, 10, and 11. The boundary between the upper end of the side 9a of the trench 9 and the upper surface of the semiconductor substrate is gently connected and is rounded compared to the boundary between the upper end of the side 9b and the upper surface of the semiconductor substrate. The insulating film 10 is adjacent to the side 9b in a plan view, but is separated from the side 9a. The side 9a and the upper surface of the semiconductor substrate between the side 9a and the insulating film 10 are continuously covered with the insulating film 7d, which is a gate insulating film. An insulating film 11 is formed on the insulating film 10 via the insulating film 7c. The side 9a of the trench 9 is covered with the insulating film 7d, which has a relatively thin thickness, while the side 9b is covered with the insulating film 7c, which has a thickness larger than that of the insulating film 7d.

[0086] In the trench 9, the gate electrode 2 is embedded between the insulating films 7c and 7d. A part of the gate electrode 2 is also embedded directly above the trench 9 and directly above the semiconductor substrate between the side surface 9a and the insulating film 10, and another part of the gate electrode 2 is formed so as to cover the upper surface of the insulating film 11. The gate electrode 2 and the insulating film 7 are covered by an insulating film 7e which is an interlayer film. The other structure is similar to that of the first embodiment.

[0087] Next, a method for manufacturing the silicon carbide semiconductor device of the present embodiment will be described with reference to FIGS.

[0088] First, the same steps as those described with reference to Fig. 5 and Fig. 6 are performed. Next, as shown in Fig. 15, an insulating film 7c is formed by, for example, a CVD method to fill the trench 9 and cover the side and upper surface of the insulating film 10. The insulating film 7c is made of, for example, a silicon oxide film. Here, a deposited oxide film is formed to such an extent that the trench 9 is completely filled. The insulating film 7c has a film thickness of, for example, 100 to 1000 nm.

[0089] Next, the insulating film 11 is formed on the insulating film 7c by, for example, a CVD method. In plan view, the insulating film 11 covers the insulating film 7c on the side surface 9b of the trench 9 and exposes the insulating film 7c on the side surface 9a of the trench 9.

[0090] Next, as shown in Fig. 16, anisotropic etching (e.g., dry etching) is performed using the insulating film 11 as a mask. As a result, the insulating film 7c is partially removed, and the side surface 9a and the upper surface of the semiconductor substrate adjacent to the side surface 9a and exposed from the insulating films 10 and 11 are exposed. At this time, the amount of etching is controlled to leave the insulating film 7c covering the bottom surface of the trench 9. This increases the film thickness of the gate insulating film at the bottom of the trench 9, and realizes electric field relaxation at the bottom of the trench 9. The bottom surface of the trench 9 may be exposed by this etching process.

[0091] Next, as shown in FIG. 17, an insulating film 7d is formed by, for example, a CVD method. Since the insulating film 7d is formed by a deposition method here, it is considered that the insulating film 7d actually covers the insulating films 10, 11, etc., but FIG. 17 shows the insulating film 7d only in the vicinity of the side surface 9a of the trench 9. The insulating film 7d continuously covers the side surface 9a of the trench 9 and the upper surface of the semiconductor substrate adjacent to the side surface 9a and exposed from the insulating films 10 and 11. The film thickness of the insulating film 7d is, for example, 10 to 100 nm. The insulating films 7c, 7d, 10, and 11 constitute the insulating film 7. The insulating film 7 covering the bottom surface of the trench 9 has either one or both of the insulating films 7c and 7d.

[0092] 18, a gate electrode 2 is formed to fill the trench 9. Here, a conductive film, which is an n-type polycrystalline silicon film, is formed on a semiconductor substrate by, for example, a CVD method to a thickness of, for example, 100 to 300 nm. Thereafter, the conductive film is patterned by using a photolithography technique and an etching method to form the gate electrode 2 made of the conductive film.

[0093] Next, as shown in Fig. 19, an insulating film 7e that covers the gate electrode 2 and the insulating film 7 is formed on the semiconductor substrate by, for example, a CVD method. Thereafter, a source electrode 1 and a drain electrode 3 are formed in the same manner as in the process described with reference to Fig. 11. This completes the silicon carbide semiconductor device of the present embodiment.

[0094] Even in the case where, as in this embodiment, an insulating film in a trench is formed asymmetrically by anisotropic etching and then a gate electrode is formed in the trench, the same effects as those in the first embodiment can be obtained.

[0095] <Modification> Unlike the manufacturing method described with reference to FIGS. 15 to 19, the insulating film in the trench is formed asymmetrically by isotropic etching, which will be described below with reference to FIGS.

[0096] Here, first, the same steps as those described with reference to Figs. 5 and 6 are performed, and then the same steps as those described with reference to Fig. 15 are performed. Next, as shown in Fig. 20, isotropic etching (for example, wet etching) is performed using the insulating film 11 as a mask. As a result, the insulating film 7c is partially removed, and the side surface 9a and the upper surface of the semiconductor substrate adjacent to the side surface 9a and exposed from the insulating films 10 and 11 are exposed. At this time, the amount of etching is controlled to leave the insulating film 7c covering the bottom surface of the trench 9. As a result, the thickness of the gate insulating film at the bottom of the trench 9 can be increased, and the electric field relaxation at the bottom of the trench 9 can be realized. The bottom surface of the trench 9 may be exposed by this etching process.

[0097] Next, as shown in FIG. 21, steps similar to those described with reference to FIGS. 17 to 19 are carried out to complete the silicon carbide semiconductor device of the present embodiment.

[0098] Even in the case of forming a gate electrode in a trench after forming an insulating film in the trench asymmetrically by isotropic etching as in the present embodiment, the same effect as that of the above-mentioned embodiment 1 can be obtained. Here, the corners of the gate electrode are rounded compared to the silicon carbide semiconductor device described using Figures 1 to 19, so that the electric field in the gate insulating film at the bottom of the trench can be alleviated.

[0099] The invention made by the present inventors has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention.

[0100] For example, the material, conductivity type, and manufacturing conditions of each part are not limited to those described in the above-mentioned embodiment, and it goes without saying that many modifications are possible. Here, for convenience of explanation, the conductivity types of the semiconductor substrate and the semiconductor film are fixed, but they are not limited to the conductivity types described in the above-mentioned embodiment. That is, in the above-mentioned first and second embodiments, an n-type SiC power MISFET is described, but even in a p-type SiC power MISFET in which the conductivity type of each semiconductor region is inverted, the effects of the above-mentioned first and second embodiments can be obtained.

[0101] Moreover, the first and second modifications of the first embodiment can be combined with the second embodiment or a modification of the second embodiment. [Explanation of symbols]

[0102] 2. Gate electrode 3 Drain electrode 4. Drift Layer 5. Body Layer 6 Source Area 8 Guard Area 7, 7a~7e Insulating film 9. Trench 9a, 9b side 12 Drain Region 13 JFET area

Claims

1. a silicon carbide substrate of a first conductivity type; a semiconductor layer of the first conductivity type formed on the silicon carbide substrate and containing silicon carbide; a first semiconductor region of the first conductivity type formed on an upper surface of the semiconductor layer; a second semiconductor region of a second conductivity type different from the first conductivity type, the second semiconductor region being formed in the semiconductor layer from a lower end of the first semiconductor region to a midway depth of the semiconductor layer; a third semiconductor region of the first conductivity type formed in the semiconductor layer below the second semiconductor region; a trench formed from the top surface of the semiconductor layer to a midpoint of the depth of the third semiconductor region, the trench having a first side surface and a second side surface opposed to each other in a first direction along the top surface of the semiconductor layer; a gate electrode formed on the inner side of the trench via an insulating film; a fourth semiconductor region of the first conductivity type formed in the silicon carbide substrate; a fifth semiconductor region of the second conductivity type formed in the third semiconductor region below the second semiconductor region; having the first semiconductor region, the gate electrode, the second semiconductor region, and the fourth semiconductor region constitute a field effect transistor; the first side surface is in contact with the second semiconductor region, and the trench and the fifth semiconductor region in contact with the trench are formed in a plurality of rows in the first direction, In the first direction, the first side surface and the second side surface are alternately arranged, the insulating film includes a first insulating film covering the first side surface, a second insulating film covering the second side surface, and a third insulating film covering a bottom surface of the trench; In the first direction, a thickness of the second insulating film is larger than a thickness of the first insulating film, A silicon carbide semiconductor device, wherein the fifth semiconductor region is in contact with a first surface extending over the first side surface and a portion of the bottom surface of the trench and is spaced from a second surface extending over the second side surface and another portion of the bottom surface of the trench.

2. 2. The silicon carbide semiconductor device according to claim 1, A silicon carbide semiconductor device, wherein the first surface is a surface in which a channel, which is a main current path of the field effect transistor, is formed.

3. 2. The silicon carbide semiconductor device according to claim 1, a silicon carbide semiconductor device, wherein in the first direction, a distance from a boundary between the second side surface and the bottom surface of the trench to a boundary between the bottom surface of the trench and the fifth semiconductor region is smaller than the film thickness of the second insulating film in the first direction.

4. 2. The silicon carbide semiconductor device according to claim 1, a distance from an upper surface of the fifth semiconductor region to the bottom surface of the trench in a direction perpendicular to the upper surface of the semiconductor layer is greater than a thickness of the third insulating film.

5. 2. The silicon carbide semiconductor device according to claim 1, a thickness of the first insulating film being smaller than a thickness of the third insulating film;

6. 2. The silicon carbide semiconductor device according to claim 1, a sixth semiconductor region of the first conductivity type in the semiconductor layer between the second semiconductor region and the fifth semiconductor region, a sixth semiconductor region having an impurity concentration lower than a first semiconductor region and higher than a third semiconductor region;

7. 2. The silicon carbide semiconductor device according to claim 1, a source electrode formed on the semiconductor layer and connected to the first semiconductor region; a seventh semiconductor region of the first conductivity type formed between the fifth semiconductor regions adjacent to each other in the first direction; and each of the fifth semiconductor region and the seventh semiconductor region extends in a second direction that is a direction along the top surface of the semiconductor layer and intersects with the first direction in a plan view; The source electrodes extend in the first direction and are arranged in a row in the second direction.

8. 2. The silicon carbide semiconductor device according to claim 1, a source electrode formed on the semiconductor layer and connected to the first semiconductor region; Each of the plurality of trenches extends in a second direction that is a direction along the upper surface of the semiconductor layer and intersects with the first direction in a plan view; The source electrode extends in the first direction.

9. (a) preparing a semiconductor substrate including a silicon carbide substrate of a first conductivity type; and a semiconductor layer of the first conductivity type formed on the silicon carbide substrate, the semiconductor layer including silicon carbide and having a third semiconductor region of the first conductivity type therein; (b) forming a first semiconductor region of the first conductivity type on an upper surface of the semiconductor layer, forming a second semiconductor region of a second conductivity type different from the first conductivity type in the semiconductor layer from a lower end of the first semiconductor region to a midway depth of the semiconductor layer, and forming a plurality of fifth semiconductor regions of the second conductivity type in the third semiconductor region below the second semiconductor region; (c) forming a plurality of trenches having first and second side surfaces opposed to each other in a first direction along the top surface of the semiconductor layer from the top surface of the semiconductor layer to a midpoint depth of the third semiconductor region; (d) forming a first insulating film covering the side and bottom surfaces of the trench; (e) forming a conductive film on the inside of the trench via the first insulating film; (f) removing a portion of the conductive film that faces the second side surface to form a gate electrode made of the conductive film; (g) filling the region in the trench from which the conductive film has been removed in (f) with a second insulating film; having the silicon carbide substrate includes a fourth semiconductor region of the first conductivity type therein; the first semiconductor region, the gate electrode, the second semiconductor region, and the fourth semiconductor region constitute a field effect transistor; the first side surface is in contact with the second semiconductor region, and the trench and the fifth semiconductor region in contact with the trench are formed in a plurality of rows in the first direction, In the first direction, the first side surface and the second side surface are alternately arranged, a fifth semiconductor region in contact with a first surface extending over the first side surface and a portion of the bottom surface of the trench and spaced apart from a second surface extending over the second side surface and another portion of the bottom surface of the trench.

10. (a) preparing a semiconductor substrate including a silicon carbide substrate of a first conductivity type; and a semiconductor layer of the first conductivity type formed on the silicon carbide substrate, the semiconductor layer including silicon carbide and having a third semiconductor region of the first conductivity type therein; (b) forming a first semiconductor region of the first conductivity type on an upper surface of the semiconductor layer, forming a second semiconductor region of a second conductivity type different from the first conductivity type in the semiconductor layer from a lower end of the first semiconductor region to a midway depth of the semiconductor layer, and forming a plurality of fifth semiconductor regions of the second conductivity type in the third semiconductor region below the second semiconductor region; (c) forming a plurality of trenches having first and second side surfaces opposed to each other in a first direction along the top surface of the semiconductor layer from the top surface of the semiconductor layer to a midpoint depth of the third semiconductor region; (d) forming an insulating film including a first insulating film covering the first side surface, a second insulating film covering the second side surface and having a thickness larger than that of the first insulating film in the first direction, and a third insulating film covering a bottom surface of the trench; (e) forming a gate electrode on the inner side of the trench via the insulating film; having the silicon carbide substrate includes a fourth semiconductor region of the first conductivity type therein; the first semiconductor region, the gate electrode, the second semiconductor region, and the fourth semiconductor region constitute a field effect transistor; the first side surface is in contact with the second semiconductor region, and the trench and the fifth semiconductor region in contact with the trench are formed in a plurality of rows in the first direction, In the first direction, the first side surface and the second side surface are alternately arranged, a fifth semiconductor region in contact with a first surface extending over the first side surface and a portion of the bottom surface of the trench and spaced apart from a second surface extending over the second side surface and another portion of the bottom surface of the trench.

11. 11. The method for manufacturing a silicon carbide semiconductor device according to claim 10, The step (d) comprises: (d1) filling the trench with a fourth insulating film; (d2) removing a portion of the fourth insulating film by anisotropic etching to expose the first side surface; (d3) forming the first insulating film covering the first side surface after the step (d2); having the second insulating film includes the fourth insulating film, the third insulating film includes either the fourth insulating film or the first insulating film, or both of the fourth insulating film and the first insulating film.

12. 11. The method for manufacturing a silicon carbide semiconductor device according to claim 10, The step (d) comprises: (d1) filling the trench with a fourth insulating film; (d2) removing a portion of the fourth insulating film by isotropic etching to expose the first side surface; (d3) after the step (d2), a step of forming the first insulating film covering the first side surface; having the second insulating film includes the fourth insulating film, the third insulating film includes either the fourth insulating film or the first insulating film, or both of the fourth insulating film and the first insulating film.

Images