Manufacturing method for shielded gate semiconductor device structure and shielded gate semiconductor device structure

Abstract

The embodiments of the present application provide a manufacturing method for a shielded gate semiconductor device structure and a shielded gate semiconductor device structure, which further includes the steps of: etching away a first oxide layer, a second oxide layer, and a part of the semiconductor layer located in an upper space of the cell region trench and on a surface of the semiconductor layer, between the trench, during a process from deposition of the source polysilicon to oxidation of the gate polysilicon; etching away the gate polysilicon until a thickness of the remaining gate polysilicon in the source pull-out region trench reaches a preset thickness; and selectively etching away the remaining gate polysilicon located in the source pull-out region trench until no gate polysilicon is left in the source pull-out region trench, and then removing the resist. The embodiments of the present application etch away the gate polysilicon until the gate polysilicon in the source pull-out region trench is completely etched, thereby avoiding the problem that the gate polysilicon in the source pull-out region is left on the sidewall of the source pull-out region trench, avoiding the risk of gate-source short circuit, and improving yield and reliability.

Description

[Technical field]

[0001] The embodiments of the present application belong to the field of integrated circuit processing technology, and in particular to a method for manufacturing a shielded gate semiconductor device structure and a shielded gate semiconductor device structure. [Background technology]

[0002] The on-resistance and stray capacitance of a power MOSFET are contradictory parameters, and in order to reduce the on-resistance, the silicon wafer area must be increased. However, an increase in the silicon wafer area leads to an increase in the stray capacitance, so for a silicon wafer of a certain area, a new process technology must be adopted to reduce the stray capacitance. The shielded gate semiconductor device (Shield Gate Trench MOSFET) as a shielding technology has effectively resolved the contradiction between on-resistance and stray capacitance.

[0003] Except for the gate structure, the rest is a standard power MOSFET that adopts the trench process, the gate is divided into two parts, upper and lower, the lower part is shielded with some special material, the lower part is internally connected to the upper gate, and the shield layer of the lower gate is connected to the source, which reduces the drain-gate floating mirror capacitance, greatly reduces the duration of the mirror platform during switching, and reduces the switch loss. At the same time, this structure changes the form of the internal electric field, changing the traditional triangular electric field into a more compressed trapezoidal electric field, which can further reduce the thickness of the epitaxial layer, reduce the on-resistance, and reduce the thermal resistance.

[0004] However, due to the special nature of the shielded gate semiconductor device, the trench must be etched deep, and the oxide layer at the bottom of the trench is relatively thick; the higher the device voltage, the deeper the trench, and the thicker the oxide layer at the bottom of the trench; thus, in the process of growing the thermal oxide layer in the deep trench, the number of oxygen atoms that reach the bottom of the trench is not as large as that at the surface, and the closer to the bottom of the trench, the thinner the oxide layer becomes; and due to the difference in crystal orientation at the bottom of the trench, the thinner the oxide layer becomes at the bottom corner. Thus, the difference between the oxide layer thickness at the top of the semiconductor material between the trenches and the oxide layer thickness at the trench corners becomes large, which causes a relatively large disruption to product design and subsequent processes.

[0005] In order to solve the above technical problem, as shown in FIG. 1, in the prior art, the oxide layer at the bottom of the trench is first thermally oxidized to grow a first oxide layer, and then a second oxide layer is deposited to solve the above problem. However, when the thickness of the thick oxide layer exceeds a preset thickness, and the proportion of the second oxide layer in the total oxide layer thickness is high, the oxide layer in the source polysilicon pull-out region will also be etched when etching the thick oxide layer, and pits will occur on the trench sidewall in the source pull-out region. During the deposition of gate polysilicon, the gate polysilicon will enter the pits, and the gate polysilicon in the pits cannot be completely removed in the subsequent process, resulting in a high risk of gate-source short circuit and uncontrollable yield risk. Summary of the Invention

[0006] SUMMARY OF THE DISCLOSURE The embodiments of the present application provide a manufacturing method for a shielded gate semiconductor device structure and a shielded gate semiconductor device structure, to partially solve or alleviate technical problems in the prior art.

[0007] One technical solution adopted by the embodiments of the present application to partially solve or alleviate the technical problems in the prior art is that the embodiments of the present application provide a method for manufacturing a shielded gate semiconductor device, the method comprising: forming a second oxide layer and a first oxide layer in sequence on the inner surfaces of the cell region trench and the source pull-out region trench from the outside to the inside, respectively; depositing source polysilicon in spaces formed by being surrounded by the second oxide layer in the cell region trench and the source extension region trench; selectively etching away a portion of the source polysilicon located in an upper space of the trench in the cell region by etching away the source polysilicon on the surface of the semiconductor layer; Etching away the first oxide layer and the second oxide layer on the surface of the semiconductor layer, the cell region trench, and the source lead-out region trench; Etching away a portion of the source polysilicon in the semiconductor layer between the trenches, the cell region trench, and the source pull-out region trench; forming a third oxide layer on the upper surface of the semiconductor layer, the exposed surface of the cell region trench, the exposed surface of the source pull-out region trench, and the exposed surface of the source polysilicon, respectively, and then removing the third oxide layer; forming a fourth oxide layer on the upper surface of the semiconductor layer, the exposed surface of the cell region trench, the exposed surface of the source pull-out region trench, and the exposed surface of the source polysilicon; depositing gate polysilicon in the cell region trench and the source extension region trench; The method includes etching away the gate polysilicon on the surface of the semiconductor layer, and selectively etching away the gate polysilicon located in the source lead-out region trenches until no gate polysilicon remains in the source lead-out region trenches.

[0008] In one preferred embodiment of the present application, the first oxide layer is formed by thermal growth and the second oxide layer is formed by chemical vapor deposition.

[0009] In one preferred embodiment of the present application, the total thickness of the first oxide layer and the second oxide layer is between 1000A-8000A, and the ratio of the thickness of the first oxide layer to the thickness of the second oxide layer is between 0.2-1.8.

[0010] In one preferred embodiment of the present application, the etching rate of the first oxide layer is smaller than the etching rate of the second oxide layer.

[0011] In one preferred embodiment of the present application, after the first oxide layer and the second oxide layer in the surface of the semiconductor layer, the cell region trench, and the source pull-out region trench are etched away, the height difference between the top of the remaining source polysilicon in the cell region trench and the bottom of the top of the second oxide layer in the corresponding cell region trench is between 5000 A and 15000 A, and the height difference between the top of the remaining source polysilicon in the source pull-out region trench and the bottom of the top of the second oxide layer in the corresponding source pull-out region trench is between 3000 A and 12000 A.

[0012] In one preferred embodiment of the present application, after etching away a portion of the source polysilicon in the semiconductor layer between the trenches, the cell area trench, and the source pull-out area trench, the height difference from the top of the remaining source polysilicon in the cell area trench to the bottom of the tip of the second oxide layer is between 500 A and 1500 A, and the height difference from the top of the remaining source polysilicon in the source pull-out area trench to the bottom of the tip of the second oxide layer is between 0 A and 1000 A.

[0013] In one preferred embodiment of the present application, the thickness of the semiconductor layer between the etched away trenches is between 3000 Å and 10000 Å.

[0014] In one preferred embodiment of the present application, a third oxide layer is grown at a temperature of 950°C to 1100°C to a thickness of 200A to 1000A, and a fourth oxide layer is grown at a temperature of 950°C to 1100°C to a thickness of 200A to 1200A.

[0015] Compared with the prior art, the embodiment of the present application provides a manufacturing method of a shielded gate semiconductor device structure, and during the process from depositing the pass-through source polysilicon to oxidizing the gate polysilicon, the steps include the steps of etching away a first oxide layer and a second oxide layer on a surface of the semiconductor layer, a cell region trench and a source pull-out region trench; etching away a part of the source polysilicon in the semiconductor layer between the trenches, the cell region trench and the source pull-out region trench; forming a third oxide layer on an upper surface of the semiconductor layer, an exposed surface of the cell region trench, an exposed surface of the source pull-out region trench and an exposed surface of the source polysilicon, respectively, and then removing the third oxide layer; and etching away the upper surface of the semiconductor layer, the exposed surface of the cell region trench, the exposed surface of the source pull-out region trench and the exposed surface of the source polysilicon. By adding the steps of forming a fourth oxide layer on each exposed surface of the silicon, depositing gate polysilicon in the cell region trench and the source pull-out region trench, and etching away the gate polysilicon on the surface of the semiconductor layer, and selectively etching away the gate polysilicon located in the source pull-out region trench until no gate polysilicon remains in the source pull-out region trench, the embodiment of the present application etches away the gate polysilicon until the gate polysilicon in the source pull-out region trench is completely etched away, thereby avoiding the problem that the gate polysilicon in the source pull-out region is left on the sidewall of the source pull-out region trench, avoiding the risk of gate-source short circuit, and improving yield and reliability.

[0016] According to a second aspect, embodiments of the present application further provide a shielded gate semiconductor device structure, obtained by the method of manufacture described above, said structure comprising: a cell region trench, in which a second oxide layer and a first oxide layer are formed on an inner surface of a lower portion of the cell region trench from the outside to the inside, a fourth oxide layer is formed on an inner surface of an upper portion of the cell region trench, source polysilicon is formed in a space surrounded by the second oxide layer, gate polysilicon is formed in the space surrounded by the fourth oxide layer, the fourth oxide layer is formed on a tip surface of the source polysilicon, and the gate polysilicon covers the tip surface of the source polysilicon; a source lead-out region trench, the inner surface of which is provided with a first oxide layer and a second oxide layer, the space surrounded by the second oxide layer is provided with source polysilicon, and a fourth oxide layer is provided on a tip surface of the source polysilicon; Here, the top of the second oxide layer in the cell region trench and the source extension region trench is lower than the top of the first oxide layer.

[0017] In one preferred embodiment of the present application, the total thickness of the first oxide layer and the second oxide layer is between 1000A-8000A.

[0018] In one preferred embodiment of the present application, the thickness of the fourth oxide layer is between 200 Å and 1200 Å.

[0019] Compared with the prior art, the shielded gate semiconductor device structure according to the second aspect has the same beneficial effects as the manufacturing method of the shielded gate semiconductor device structure according to the first aspect, which will not be described further here. [Brief description of the drawings]

[0020] The drawings described herein are for providing further understanding of the present application and constitute a part of the present application, and the schematic embodiments and the description thereof are for interpreting the present application and do not constitute undue limitations of the present application. Some specific embodiments of the present application will be described in detail below in an illustrative and non-limiting manner with reference to the drawings. In the drawings, the same reference numerals indicate the same or similar components or parts, and it should be understood by those skilled in the art that the drawings are not necessarily drawn to scale. [Figure 1] 1 is a schematic diagram of a shielded gate semiconductor device structure manufactured by a prior art manufacturing process; [Diagram 2] 1 is a flow chart of a method for manufacturing a shielded gate semiconductor device according to an embodiment of the present application. [Figure 3-12] 1A-1D are structural schematic diagrams corresponding to each process flow step according to an embodiment of the present application. [Figure 13] 1 is a schematic diagram of a device structure in which an embodiment of the present application includes a shielded gate semiconductor device structure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] In order to allow those skilled in the art to better understand the form of the present application, the following clearly and completely describes the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, and are not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative effort should fall within the protection scope of the present application.

[0022] As shown in FIG. 1, FIG. 1 is a shielded gate semiconductor device structure manufactured by a conventional technology manufacturing process. The specific manufacturing method of the shielded gate semiconductor device structure shown in FIG. 1 is as follows: First, a step S01 of forming a plurality of cell region trenches and source pull-out region trenches on an epitaxial layer by photolithography, and then forming a second oxide layer and a first oxide layer in that order from the outside to the inside on the inner surfaces of the cell region trenches and the source pull-out region trenches; Step S02 of depositing source polysilicon in the cell region trench and the source lead region trench, then etching the source polysilicon on the surface of the semiconductor layer once until no source polysilicon remains on the surface of the semiconductor layer, photolithographing the cell region source polysilicon, and removing the resist; Step S03 of etching away the first oxide layer and the second oxide layer on the surface of the semiconductor layer, the cell region trench, and the source lead region trench; Step S04 of forming a third oxide layer on the upper surface of the semiconductor layer, the exposed surface of the cell region trench, the exposed surface of the source pull-out region trench, and the exposed surface of the source polysilicon, and then removing the third oxide layer; Step S05 of forming a fourth oxide layer on the upper surface of the semiconductor layer, the exposed surface of the cell region trench, the exposed surface of the source pull-out region trench, and the exposed surface of the source polysilicon; Step S05 of depositing gate polysilicon in the cell region trench and the source pull-out region trench; and a step S06 of etching the gate polysilicon on the surface of the semiconductor layer.

[0023] As can be seen from the above process flow, since the shielded gate semiconductor device has both the cell region and the source pull-out region, the total thickness of the first oxide layer and the second oxide layer exceeds 1000A. The higher the proportion of the second oxide layer in the total thickness, the faster the etching rate of the second oxide layer. Therefore, when the first oxide layer and the second oxide layer are etched, the first oxide layer and the second oxide layer in the source pull-out region are also etched together. As a result, pits 21 are generated on the trench sidewalls in the source pull-out region, and the gate polysilicon is deposited in the pits 21 during the deposition of the gate polysilicon. The gate polysilicon in the pits 21 cannot be completely removed in the subsequent process, which increases the risk of gate-source short circuit, and further causes problems such as the yield risk of the shielded gate semiconductor device being uncontrollable and the reliability risk being unavoidable.

[0024] As shown in FIG. 2, FIG. 2 is a method for manufacturing a shielded gate semiconductor device structure according to an embodiment of the present application, the method including: Step S21 of sequentially forming a second oxide layer and a first oxide layer on the inner surfaces of the cell region trench and the source pull-out region trench from the outside to the inside, respectively; Step S22 of depositing source polysilicon in the spaces formed by the second oxide layer in the cell region trench and the source pull-out region trench; Step S23: selectively etching away a portion of the source polysilicon located in an upper space of the trench in the cell region by etching away the source polysilicon on the surface of the semiconductor layer; A step S24 of etching away the first oxide layer and the second oxide layer on the surface of the semiconductor layer, the cell region trench, and the source lead region trench; Step S25 of etching away a part of the source polysilicon in the semiconductor layer between the trenches, the cell region trench, and the source lead region trench; Step S26 of forming a third oxide layer on the upper surface of the semiconductor layer, the exposed surface of the cell region trench, the exposed surface of the source pull-out region trench, and the exposed surface of the source polysilicon, and then removing the third oxide layer; Step S27 of forming a fourth oxide layer on the upper surface of the semiconductor layer, the exposed surface of the cell region trench, the exposed surface of the source pull-out region trench, and the exposed surface of the source polysilicon; Step S28 of depositing gate polysilicon in the cell region trench and the source extension region trench; and a step S29 of etching away the gate polysilicon on the surface of the semiconductor layer, and selectively etching away the gate polysilicon located in the source lead-out region trench until no gate polysilicon remains in the source lead-out region trench.

[0025] 2 and 3, the processes for forming the cell region trench 32 and the source lead region trench 31 on the semiconductor layer 33 are both well known to those skilled in the art and will not be described further here. The semiconductor layer may be a substrate or an epitaxial layer. The cell region trench 32 and the source lead region trench 31 are formed directly on the semiconductor layer 33 by photolithography, and then the inner surfaces of the cell region trench 32 and the source lead region trench 31 are first grown by a thermal growth process. A layer of a first oxide layer 35 is formed, and then a layer of a second oxide layer 34 is formed on the outer surface of the first oxide layer 35 by a chemical vapor deposition process, where the first oxide layer 35 and the second oxide layer 34 are called thick oxide layers, and the total thickness of the first oxide layer 35 and the second oxide layer 34 is between 1000A-8000A, the ratio of the thickness of the first oxide layer 35 to the thickness of the second oxide layer 34 is between 0.2-1.8, and generally the number of the cell region trenches 32 is more than the source pull-out region trenches 31.

[0026] 2, 4 and 5, source polysilicon 41 is deposited in the spaces formed by the second oxide layer 34 in the cell region trench 32 and the source pull-out region trench 31, respectively, and then the source polysilicon 41 is etched back until the tip of the source polysilicon 41 is no longer higher than the top of the trench. In other words, by etching back the source polysilicon 41 on the surfaces of the multiple semiconductor layers 33, the source polysilicon 41 is eliminated from the surfaces of the semiconductor layers 33.

[0027] 2 and 6, a second resist 61 is applied to the source lead-out region, and the source polysilicon 41 in the upper space in the cell region trench 32 is photolithographed, leaving some of the source polysilicon 41 in the cell region trench 32, and then the second resist 61 is removed.

[0028] 2 and 7, the first oxide layer 35 and the second oxide layer 34 located in the upper space and on the surface of the semiconductor layer 33 in the cell region trench 32 and the source lead-out region trench 31 are etched away. Since the etching rate of the first oxide layer 35 is smaller than the etching rate of the second oxide layer 34, the top of the first oxide layer 35 is higher than the top of the second oxide layer 34 after etching is completed. After the first oxide layer 35 and the second oxide layer 34 located in the cell region trench 32 are etched away, the height difference between the top of the remaining source polysilicon 41 in the cell region trench 32 and the bottom of the top of the second oxide layer 34 in the corresponding cell region trench 32 is between 5000 A and 15000 A, and the height difference between the top of the remaining source polysilicon 41 in the source lead-out region trench 31 and the bottom of the top of the second oxide layer 34 in the corresponding source lead-out region trench 31 is between 3000 A and 12000 A.

[0029] 1 and 8, the semiconductor layer 33 between the trenches, and a portion of the source polysilicon in the cell region trench 32 and the source lead-out region trench 31 are etched away, and the height difference from the top of the source polysilicon 41 in the cell region trench 32 to the bottom of the tip of the second oxide layer 34 is between 500 A and 1500 A, the height difference from the top of the source polysilicon in the source lead-out region trench to the bottom of the tip of the second oxide layer is between 0 A and 1000 A, the etch-back thickness of the semiconductor layer 33 between the trenches is between 3000 A and 10000 A, and the etch-back thickness of the semiconductor layer 33 between the trenches is specifically determined according to the height difference of the semiconductor layer 33 between the bottom of the second oxide layer 34 in the source lead-out region trench 31 and the trench.

[0030] 2 and 9, based on FIG. 8, a third oxide layer (not shown) is formed on the surface of the semiconductor layer 33, the upper surface of the semiconductor layer 33, the exposed surface of the cell region trench 32, the exposed surface of the source pull-out region trench 31, and the exposed surface of the source polysilicon 41, respectively, and then the third oxide layer (not shown) is removed, and the third oxide layer (not shown) can process the topography of its contacting surface to improve the purity of the contacting surface, the thickness of the third oxide layer is 200A to 1000A, and the process temperature is between 950°C to 1100°C.

[0031] Then, after removing the third oxide layer (not shown), a fourth oxide layer 91 is re-formed at the locations where the third oxide layer (not shown) is located, i.e., on the surface of the semiconductor layer 33, the inner surface of the cell region trench 32, the inner surface of the source pull-out region trench 31 and the tip of the source polysilicon 41, and the thickness of the fourth oxide layer 91 is 200A to 1200A, and the process temperature is between 950°C to 1100°C.

[0032] 2 and 10, the gate polysilicon 10 is deposited in the upper space of the cell region trench 32, and the process of depositing the gate polysilicon 10 is a technique well known to those skilled in the art and will not be described further herein.

[0033] 2 and 11, the gate polysilicon 10 is etched back until no gate polysilicon 10 remains on the surface of the semiconductor layer 33, and the remaining gate polysilicon 93 thickness in the source extension region trench 31 is between 0A-5000A.

[0034] 2 and 12, a first resist 12 is applied on FIG. 11, and the remaining gate polysilicon 93 in the upper space of the source lead-out region trench 31 is photolithographed until the remaining gate polysilicon 93 in the source lead-out region trench 31 is completely etched, and then the first resist 12 is removed, at which time no remaining gate polysilicon 93 remains in the source lead-out region trench 31. The embodiment of the present application etches and removes the gate polysilicon until the gate polysilicon in the source lead-out region trench is completely etched, thereby avoiding the problem that the gate polysilicon in the source lead-out region is left on the sidewall of the source lead-out region trench, avoiding the risk of gate-source short circuit, and improving yield and reliability.

[0035] The shielded gate semiconductor device structure manufactured by the above process steps according to the embodiment of the present application is shown in FIG. 12, and the shielded gate semiconductor device structure includes: a cell region trench 32, in which a second oxide layer 34 and a first oxide layer 35 are provided on the inner surface of a lower portion of the cell region trench 32 from the outside to the inside, a fourth oxide layer 91 is provided on the inner surface of an upper portion of the cell region trench 32, a source polysilicon 41 is provided in a space surrounded by the second oxide layer 34, a gate polysilicon 10 is provided in the space surrounded by the fourth oxide layer 91, the fourth oxide layer 91 is provided on a tip surface of the source polysilicon 41, and the gate polysilicon 10 covers the tip surface of the source polysilicon 41; a source lead-out region trench 31, in which a first oxide layer 35 and a second oxide layer 34 are provided on an inner surface of the source lead-out region trench 31, a source polysilicon 41 is provided in a space surrounded by the second oxide layer 34, and a fourth oxide layer 91 is provided on a tip surface of the source polysilicon 41; Here, the end of the second oxide layer 34 in the cell region trench 32 and the source pull-out region trench 31 is lower than the end of the first oxide layer 35, the total thickness of the first oxide layer 35 and the second oxide layer 34 is between 1000A-8000A, and the thickness of the fourth oxide layer 91 is between 200A-1200A.

[0036] Thereafter, a layer of oxide layer 16 is formed on the entire surface of semiconductor layer 33, followed by sequential ion implantation to form well 13, photolithography to form implantation region 14 in well 13, deposition to form medium layers 15 and 20, photolithography to form contact holes 17 and 18, ions are implanted into contact holes 17 and 18 to activate them, and then multiple layers of metal are deposited in contact holes 17 and 18 to form extraction electrodes, and finally a device having a shielded gate semiconductor device structure is formed.

[0037] The shielded gate semiconductor device structure according to the embodiments of the present application avoids the problem of source extension region gate polysilicon being left on the source extension region trench sidewall, avoids the risk of gate-source shorting, and improves yield and reliability.

[0038] Finally, it should be noted that the above embodiments are only for illustrating the technical solutions of the present application, and are not intended to limit the same. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions described in the above embodiments can still be modified or equivalently replaced with some or all of the technical features therein, but such modifications or replacements do not cause the essence of the corresponding technical solutions to depart from the scope of the technical solutions of the embodiments of the present application.

Claims

1. 1. A method for manufacturing a shielded gate semiconductor device, comprising: forming a first oxide layer and a second oxide layer in sequence from the inside to the outside on the inner surfaces of the cell region trench and the source pull-out region trench, respectively; depositing source polysilicon in spaces formed by being surrounded by the second oxide layer in the cell region trench and the source extension region trench; selectively etching away a portion of the source polysilicon located in an upper space of the trench in the cell region by etching away the source polysilicon on the surface of the semiconductor layer; Etching away the first oxide layer and the second oxide layer on the surface of the semiconductor layer, the cell region trench, and the source lead-out region trench; Etching away a portion of the source polysilicon in the semiconductor layer between the trenches, the cell region trench, and the source pull-out region trench; forming a third oxide layer on the upper surface of the semiconductor layer, the exposed surface of the cell region trench, the exposed surface of the source pull-out region trench, and the exposed surface of the source polysilicon, respectively, and then removing the third oxide layer; forming a fourth oxide layer on the upper surface of the semiconductor layer, the exposed surface of the cell region trench, the exposed surface of the source pull-out region trench, and the exposed surface of the source polysilicon; depositing gate polysilicon in the cell region trench and the source extension region trench; Etching away the gate polysilicon on the surface of the semiconductor layer and selectively etching away the gate polysilicon located in the source lead-out region trench until no gate polysilicon remains in the source lead-out region trench; and after the first oxide layer and the second oxide layer in the cell region trench and the source pull-out region trench are etched away from the surface of the semiconductor layer, a height difference between a top end of the remaining source polysilicon in the cell region trench and a bottom of a top end of the second oxide layer in the corresponding cell region trench is between 5000 A and 15000 A, and a height difference between a top end of the remaining source polysilicon in the source pull-out region trench and a bottom of a top end of the second oxide layer in the corresponding source pull-out region trench is between 3000 A and 12000 A.

2. 2. The method of claim 1, wherein the first oxide layer is formed by thermal growth and the second oxide layer is formed by chemical vapor deposition.

3. 2. The method of claim 1, wherein the total thickness of the first oxide layer and the second oxide layer is between 1000 Å-8000 Å.

4. 4. The method for manufacturing a shielded gate semiconductor device according to claim 1, wherein an etching rate of the first oxide layer is smaller than an etching rate of the second oxide layer.

5. 2. The method for manufacturing a shielded gate semiconductor device according to claim 1, wherein after etching away a portion of the source polysilicon in the semiconductor layer between the trenches, the cell area trench, and the source pull-out area trench, a height difference from a top of the remaining source polysilicon in the cell area trench to a bottom of a tip of the second oxide layer is between 500 A and 1500 A, and a height difference from a top of the remaining source polysilicon in the source pull-out area trench to a bottom of a tip of the second oxide layer is between 0 A and 1000 A.

6. 2. The method of claim 1, wherein the thickness of the semiconductor layer between the etched away trenches is between 3000 Å and 10000 Å.

7. A method for manufacturing a shielded gate semiconductor device, comprising: forming a first oxide layer and a second oxide layer in sequence from the inside to the outside on the inner surfaces of the cell region trench and the source pull-out region trench, respectively; depositing source polysilicon in spaces formed by being surrounded by the second oxide layer in the cell region trench and the source extension region trench; selectively etching away a portion of the source polysilicon located in an upper space of the trench in the cell region by etching away the source polysilicon on the surface of the semiconductor layer; Etching away the first oxide layer and the second oxide layer on the surface of the semiconductor layer, the cell region trench, and the source lead-out region trench; Etching away a portion of the source polysilicon in the semiconductor layer between the trenches, the cell region trench, and the source pull-out region trench; forming a third oxide layer on the upper surface of the semiconductor layer, the exposed surface of the cell region trench, the exposed surface of the source pull-out region trench, and the exposed surface of the source polysilicon, respectively, and then removing the third oxide layer; forming a fourth oxide layer on the upper surface of the semiconductor layer, the exposed surface of the cell region trench, the exposed surface of the source pull-out region trench, and the exposed surface of the source polysilicon; depositing gate polysilicon in the cell region trench and the source extension region trench; Etching away the gate polysilicon on the surface of the semiconductor layer and selectively etching away the gate polysilicon located in the source lead-out region trench until no gate polysilicon remains in the source lead-out region trench; 1. A method for manufacturing a shielded gate semiconductor device, comprising: growing a third oxide layer having a thickness of 200A to 1000A at a temperature of 950°C to 1100°C; and growing a fourth oxide layer having a thickness of 200A to 1200A at a temperature of 950°C to 1100°C.

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