Switching device and method for manufacturing same

Abstract

To suppress generation of voids when an electrode is formed.SOLUTION: A switching device has: a semiconductor substrate (12) having a recessed part (25) and a convex part (24) on its top face; a gate insulating film (30) that covers a bottom face (25v) of the recessed part; a gate electrode (32) that covers a top face of the gate insulating film; an interlayer insulating film (34) that covers a top face (32t) of the gate electrode; and an upper electrode (40) that covers a top face (34t) of the interlayer insulating film, being in contact with a top face (24t) of the convex part. The semiconductor substrate has a source layer (14), a body layer (16), and a drain layer (22). At least one of the source, body, and drain layers has a contact part (14a, 16a) extending to the top face of the convex part to be in contact with the upper electrode.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a switching device and a method for manufacturing the same.

[0002] Patent Document 1 discloses a technique for forming a contact hole in an insulating layer provided on a semiconductor substrate and filling the contact hole with a conductive material. The conductive material filled in the contact hole is electrically connected to the semiconductor substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2009-272630 A Summary of the Invention [Problem to be solved by the invention]

[0004] When filling a contact hole with a conductive material as in Patent Document 1, voids (air gaps) may be formed in the contact hole. In particular, when filling a contact hole with a high aspect ratio with a conductive material, it is difficult to completely fill the contact hole with the conductive material, and voids are likely to be formed in the contact hole. This specification proposes a switching device structure and a manufacturing method thereof that can suppress the generation of voids when forming electrodes. [Means for solving the problem]

[0005] The switching device disclosed in this specification includes a semiconductor substrate (12) having a recess (25) and a protrusion (24) on its upper surface, a gate insulating film (30) covering a bottom surface (25v) of the recess, a gate electrode (32) covering an upper surface of the gate insulating film, an interlayer insulating film (34) covering an upper surface (32t) of the gate electrode, and an upper electrode (40) covering an upper surface (34t) of the interlayer insulating film and contacting an upper surface (24t) of the protrusion. The upper surface of the protrusion is at the same height as the upper surface of the gate electrode or is located higher than the upper surface of the gate electrode. The semiconductor substrate includes an n-type source layer (14) contacting the gate insulating film at the bottom surface of the recess, a p-type body layer (16) contacting the gate insulating film at the bottom surface of the recess, and an n-type drain layer (22) contacting the gate insulating film at the bottom surface of the recess and separated from the source layer by the body layer. At least one of the source layer, the body layer and the drain layer has a contact portion (14a, 16a) that extends to the upper surface of the protrusion and contacts the upper electrode.

[0006] In this switching device, a convex portion is provided on the upper surface of a semiconductor substrate. At least one contact portion for the source layer, the body layer, and the drain layer is provided within the convex portion, and the contact portion is in contact with an upper electrode on the upper surface of the convex portion. In this manner, since a convex portion connected to the upper electrode is provided on the upper surface of the semiconductor substrate, the upper electrode can be connected to the convex portion without providing a deep contact hole (i.e., a contact hole with a high aspect ratio) in the interlayer insulating film. Therefore, it is not necessary to fill a contact hole with a high aspect ratio with the upper electrode, and the occurrence of voids can be suppressed when forming the upper electrode.

[0007] The method for manufacturing a switching device disclosed in this specification includes a semiconductor substrate processing step, a gate insulating film forming step, a gate electrode forming step, an interlayer insulating film forming step, a convex portion exposing step, and an upper electrode forming step. In the semiconductor substrate processing step, The upper surface of the semiconductor substrate has a recess and a protrusion. the semiconductor substrate has an n-type source layer exposed at a bottom surface of the recess, a p-type body layer exposed at the bottom surface of the recess, and an n-type drain layer exposed at the bottom surface of the recess and separated from the source layer by the body layer, At least one of the source layer, the body layer, and the drain layer has a contact portion extending to an upper surface of the protrusion. The semiconductor substrate is processed to satisfy the above condition. In the gate insulating film forming step, a gate insulating film covering the bottom surface of the recess is formed. In the gate electrode forming step, a gate electrode covering an upper surface of the gate insulating film is formed. Here, the gate electrode is formed so that the upper surface of the gate electrode is at the same height as the upper surface of the convex portion or is located lower than the upper surface of the convex portion. In the interlayer insulating film forming step, an interlayer insulating film covering the upper surface of the gate electrode and the upper surface of the convex portion is formed. In the convex portion exposing step, a part of the interlayer insulating film is removed to expose the upper surface of the convex portion. In the upper electrode forming step, an upper electrode is formed which covers the upper surface of the interlayer insulating film and contacts the contact portion on the upper surface of the convex portion.

[0008] In this manufacturing method, a convex portion is formed on the upper surface of the semiconductor substrate and the upper electrode is connected to the convex portion, so that the upper electrode can be connected to the convex portion without providing a deep contact hole (i.e., a contact hole with a high aspect ratio) in the interlayer insulating film. Therefore, it is not necessary to fill a contact hole with a high aspect ratio with the upper electrode, and the occurrence of voids when forming the upper electrode can be suppressed. [Brief description of the drawings]

[0009] [Figure 1] FIG. 3 is a cross-sectional view of the switching device of the first embodiment (a cross-sectional view taken along line II in FIG. 2). [Diagram 2] FIG. 2 is a plan view showing the upper surface of a semiconductor substrate of the switching device of the first embodiment. [Diagram 3] FIG. 2 is an explanatory diagram of the manufacturing method according to the first embodiment. [Figure 4] FIG. 2 is an explanatory diagram of the manufacturing method according to the first embodiment. [Diagram 5] FIG. 2 is an explanatory diagram of the manufacturing method according to the first embodiment. [Figure 6] FIG. 2 is an explanatory diagram of the manufacturing method according to the first embodiment. [Figure 7] FIG. 2 is an explanatory diagram of the manufacturing method according to the first embodiment. [Figure 8] FIG. 2 is an explanatory diagram of the manufacturing method according to the first embodiment. [Figure 9] FIG. 2 is an explanatory diagram of the manufacturing method according to the first embodiment. [Figure 10] FIG. 2 is an explanatory diagram of the manufacturing method according to the first embodiment. [Figure 11] FIG. 2 is an explanatory diagram of the manufacturing method according to the first embodiment. [Figure 12] FIG. 11 is an explanatory diagram of a manufacturing method according to a modified example of the first embodiment. [Figure 13] FIG. 6 is a cross-sectional view of a switching device according to a second embodiment. [Figure 14] FIG. 11 is an explanatory diagram of a manufacturing method according to a second embodiment. [Figure 15] FIG. 4 is a cross-sectional view of a switching device of Comparative Example 1 having no protrusion on the upper surface of a semiconductor substrate. [Figure 16] FIG. 11 is a cross-sectional view of a switching device according to a third embodiment. [Figure 17] FIG. 11 is a cross-sectional view of a switching device of Comparative Example 2 having no protrusion on the upper surface of a semiconductor substrate and having a tapered contact hole. [Figure 18] FIG. 4 is a cross-sectional view of a switching device according to a reference example. [Figure 19] FIG. [Figure 20] FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In one example switching device disclosed in this specification, the upper surface of the convex portion may be at the same height as the upper surface of the interlayer insulating film or may be located higher than the upper surface of the interlayer insulating film.

[0011] According to this configuration, the upper electrode covering the upper surface of the interlayer insulating film can be easily brought into contact with the upper surface of the protrusion.

[0012] In the switching device disclosed in the present specification, a contact hole (60) may be provided in the interlayer insulating film, the contact hole reaching the upper surface of the protrusion, and the upper electrode may be in contact with the upper surface of the protrusion within the contact hole.

[0013] In this configuration, the depth of the contact hole can be made shallower than when the protrusion is not provided. That is, the upper electrode can be connected to the upper surface of the protrusion in a contact hole with a low aspect ratio. Therefore, when the contact hole is filled with the upper electrode, the generation of voids can be suppressed.

[0014] When a contact hole reaching the upper surface of the protrusion is provided in the interlayer insulating film, the contact hole may have a tapered shape that narrows toward the bottom.

[0015] According to this configuration, the occurrence of voids can be more effectively suppressed when the contact hole is filled with the upper electrode.

[0016] The switching device of the present disclosure may further include a bottom electrode (42) covering a bottom surface of the semiconductor substrate. The source layer and the body layer may have the contact portion. The drain layer (20) may be in contact with the bottom electrode.

[0017] In the example method for manufacturing a switching device disclosed in the present specification, the step of processing the semiconductor substrate may include forming a plurality of the convex portions on the upper surface of the semiconductor substrate, and the step of removing a portion of the interlayer insulating film to expose the upper surfaces of the convex portions may include etching the interlayer insulating film in a range spanning upper portions of the plurality of convex portions and an upper portion of the gate electrode located between the plurality of convex portions to expose the upper surfaces of the plurality of convex portions.

[0018] According to this configuration, the upper electrode is formed over a wide area spanning the tops of the multiple convex portions and the tops of the gate electrodes located between the multiple convex portions, so that voids are less likely to occur when the upper electrode is formed.

[0019] In addition, in another example of a method for manufacturing a switching device disclosed in this specification, in the step of removing a portion of the interlayer insulating film to expose the upper surface of the convex portion, a contact hole may be formed in a portion of the interlayer insulating film that covers the upper surface of the convex portion.

[0020] According to this structure, the aspect ratio of the contact hole formed in the interlayer insulating film is lower than that in the case where the protrusion does not exist, and therefore voids are less likely to occur when the contact hole is filled with the upper electrode.

[0021] In the structure in which the contact hole is formed, the contact hole may have a tapered shape that narrows toward the bottom.

[0022] According to this configuration, therefore, when the contact hole is filled with the upper electrode, voids are less likely to occur.

[0023] In one example of a method for manufacturing a switching device disclosed in this specification, the step of processing the semiconductor substrate may include a step of forming the contact portion of the body layer by epitaxial growth, and a step of forming a p-type convex portion, which is the convex portion constituted by the contact portion of the body layer, by etching a portion of the contact portion of the body layer.

[0024] In the step of forming the p-type protrusion, a plurality of the p-type protrusions may be formed. The step of processing the semiconductor substrate may include a step of forming an n-type protrusion by injecting an n-type impurity into at least one of the plurality of p-type protrusions. The n-type protrusion may be the contact portion of the source layer.

[0025] In the example method for manufacturing a switching device disclosed in this specification, in the step of forming the gate insulating film, the gate insulating film may be formed so as to cover the bottom surface and side surfaces of the recess.

[0026] This configuration ensures proper insulation between the gate electrode and the protruding portion. EXAMPLES

[0027] The switching device 10 of the first embodiment shown in FIG. 1 has a semiconductor substrate 12. The semiconductor substrate 12 is made of gallium nitride (i.e., GaN). The semiconductor substrate 12 may be made of other semiconductor materials such as silicon and silicon carbide. A plurality of protrusions 24 are provided on the upper surface of the semiconductor substrate 12. When the upper surface of the semiconductor substrate 12 is viewed in a plan view as shown in FIG. 2, the plurality of protrusions 24 extend long in one direction (the y direction in FIG. 2) and are arranged at intervals in the x direction perpendicular to the y direction. Although two protrusions 24 (i.e., the protrusions 24a and 24b) are shown in FIGS. 1 and 2, a plurality of protrusions 24 exist outside the range shown in FIGS. 1 and 2. A recess 25 is provided between each of the protrusions 24. That is, a plurality of recesses are provided on the upper surface of the semiconductor substrate 12. Hereinafter, the recess 25 arranged between the protrusions 24a and 24b is referred to as the recess 25a.

[0028] On the upper portion of the semiconductor substrate 12, a gate insulating film 30, a gate electrode 32, an interlayer insulating film 34, and a source electrode 40 are provided.

[0029] The gate insulating film 30 covers a bottom surface 25v and a side surface 25s of each recess 25. The side surface 25s of the recess 25 can also be said to be the side surface of the protrusion 24. The gate insulating film 30 is made of silicon oxide.

[0030] The gate electrode 32 covers the upper surface of a portion of the gate insulating film 30 that covers the bottom surface 25v. The gate electrode 32 faces the semiconductor substrate 12 via the gate insulating film 30. Each protrusion 24 extends above an upper surface 32t of the gate electrode 32. Therefore, an upper surface 24t of each protrusion 24 is located above an upper surface 32t of the gate electrode 32.

[0031] The interlayer insulating film 34 covers the upper surface 32t of the gate electrode 32. The interlayer insulating film 34 has an NSG (non-doped silicate glass) film 34a and a BPSG (Boron Phosphorus Silicate Glass) film 34b. The NSG film 34a is made of non-doped silicon oxide. The BPSG film 34b is made of silicon oxide doped with boron and phosphorus. The NSG film 34a is disposed in the recess 25 and covers the upper surface 32t of the gate electrode 32. The BPSG film 34b covers the upper surface of the NSG film 34a. In addition, a groove portion 60 is formed in the interlayer insulating film 34. The bottom surface of the groove portion 60 is made of the upper surface of the NSG film 34a and the upper surface 24t of each protrusion 24. Hereinafter, the upper surface of the interlayer insulating film 34 in the groove portion 60 is referred to as the upper surface 34t. An upper surface 24t of each protrusion 24 is located at the same height as an upper surface 34t of the interlayer insulating film 34 (that is, the upper surface of the interlayer insulating film 34 adjacent to each protrusion 24).

[0032] The source electrode 40 covers the interlayer insulating film 34. The source electrode 40 is made of aluminum or the like. In the groove 60, the source electrode 40 covers the upper surface 34t of the interlayer insulating film 34 and the upper surfaces 24t of each protrusion 24. The source electrode 40 is connected to the semiconductor substrate 12 at the upper surfaces 24t of each protrusion 24.

[0033] A drain electrode 42 is provided on the lower part of the semiconductor substrate 12. The drain electrode 42 is in contact with the lower surface of the semiconductor substrate 12.

[0034] The semiconductor substrate 12 has a number of source layers 14 , a number of body layers 16 , and a drain layer 22 .

[0035] As shown in FIG. 2, a plurality of source layers 14 are provided in the area overlapping with each protrusion 24. A plurality of source layers 14 are provided at intervals along the longitudinal direction of each protrusion 24. As shown in FIG. 1, each source layer 14 is of n-type and contacts the gate insulating film 30 at the bottom surface 25v of the recess 25a. Each source layer 14 faces the gate electrode 32 via the gate insulating film 30. Each source layer 14 extends from the position of the bottom surface 25v of the recess 25a into the protrusion 24. Hereinafter, the portion of each source layer 14 within the protrusion 24 is referred to as a contact portion 14a. Each contact portion 14a extends to the upper surface 24t of the protrusion 24. Each contact portion 14a is in ohmic contact with the source electrode 40 at the upper surface 24t of the protrusion 24.

[0036] As shown in FIG. 1, each body layer 16 has a high concentration portion 16a and a low concentration portion 16b. As shown in FIG. 2, each body layer 16 (i.e., the high concentration portion 16a and the low concentration portion 16b) is provided along each protruding portion 24. As shown in FIG. 1, each body layer 16 is p-type. In the range where the source layer 14 is provided in the protruding portion 24, each body layer 16 is distributed from the lower side to the side of the source layer 14. In the range where the source layer 14 is not provided in the protruding portion 24, each body layer 16 is distributed from inside the protruding portion 24 to its lower side. The high concentration portion 16a has a p-type impurity concentration higher than that of the low concentration portion 16b. As shown in FIG. 2, the high concentration portion 16a is provided in the range where the source layer 14 is not provided in the protruding portion 24. As shown in FIG. 1, the high concentration portion 16a is in ohmic contact with the source electrode 40 on the upper surface 24t of the protruding portion 24. The low concentration portion 16b is provided below the high concentration portion 16a and below and to the side of the source layer 14. The low concentration portion 16b is connected to the source electrode 40 via the high concentration portion 16a. The low concentration portion 16b contacts the gate insulating film 30 at a position of the bottom surface 25v of the recess 25a adjacent to the source layer 14. The low concentration portion 16b faces the gate electrode 32 via the gate insulating film 30.

[0037] The drain layer 22 has a drift layer 18 and a high-concentration n-type layer 20. The drift layer 18 is n-type and is disposed below each body layer 16. The drift layer 18 extends from a position below each body layer 16 to a position between the body layers 16. Hereinafter, a portion of the drift layer 18 between the body layers 16 is referred to as a JFET (junction field effect transistor) portion 18a. The drift layer 18 is separated from the source layer 14 by the body layer 16. The JFET portion 18a of the drift layer 18 is in contact with the gate insulating film 30 at a position adjacent to the body layer 16 (more specifically, the low-concentration portion 16b) on the bottom surface 25v of the recess 25a. Therefore, the body layer 16 is in contact with the gate insulating film 30 at a position between the source layer 14 and the JFET portion 18a on the bottom surface 25v of the recess 25a. The JFET portion 18a faces the gate electrode 32 via the gate insulating film 30.

[0038] The high-concentration n-type layer 20 is an n-type layer having a higher n-type impurity concentration than the drift layer 18. The high-concentration n-type layer 20 is disposed below the drift layer 18. The high-concentration n-type layer 20 is in contact with the drain electrode 42 on the lower surface of the semiconductor substrate 12.

[0039] When a potential equal to or greater than the gate threshold is applied to the gate electrode 32, a channel is formed in the low-concentration portion 16b of the body layer 16 in a range adjacent to the gate insulating film 30. The channel connects the source layer 14 and the JFET portion 18a. Therefore, electrons flow from the source layer 14 through the channel and the drift layer 18 to the high-concentration n-type layer 20. That is, the switching device 10 is turned on. When the potential of the gate electrode 32 is reduced to a potential less than the gate threshold, the channel disappears and the switching device 10 is turned off.

[0040] Next, a method for manufacturing the switching device 10 will be described. The switching device 10 is manufactured from a semiconductor substrate constituted by a high-concentration n-type layer 20. First, as shown in FIG. 3, the drift layer 18 is epitaxially grown on the high-concentration n-type layer 20. Next, the low-concentration portion 16b of the body layer 16 is epitaxially grown on the drift layer 18. Next, the high-concentration portion 16a is epitaxially grown on the low-concentration portion 16b. Through epitaxial growth, the high-concentration portion 16a, which is GaN containing a high concentration of p-type impurities, can be appropriately formed.

[0041] Next, as shown in FIG. 4, the JFET portion 18a of the drift layer 18 is formed. The JFET portion 18a can be formed by ion implantation or epitaxial growth. When ion implantation is used, the JFET portion 18a is formed by implanting n-type impurities into the high concentration portion 16a and the low concentration portion 16b. When epitaxial growth is used, a part of the high concentration portion 16a and the low concentration portion 16b (a part corresponding to the JFET portion 18a) is removed by etching, and the JFET portion 18a is epitaxially grown in a recess formed by etching. When the JFET portion 18a is formed, the body layer 16 is divided into a plurality of portions by the JFET portion 18a.

[0042] Next, as shown in Fig. 5, the high concentration portion 16a is partially removed by etching. Here, the high concentration portion 16a is etched so that the high concentration portion 16a remains on a part of the upper surface of the low concentration portion 16b. The portion where the high concentration portion 16a is etched becomes a recess 25, and the portion where the high concentration portion 16a remains becomes a protrusion 24. Here, the low concentration portion 16b and the JFET portion 18a are exposed on the bottom surface 25v of the recess 25.

[0043] Next, as shown in Fig. 6, n-type impurities are selectively ion-implanted into the high concentration portion 16a and the low concentration portion 16b to form the source layer 14. Here, as shown in Fig. 2, a plurality of source layers 14 are formed in each body layer 16. Also, here, as shown in Fig. 6, each source layer 14 is formed so that the source layer 14 is distributed from the bottom surface 25v of the recess 25a to the inside of the protrusion 24. Each source layer 14 is exposed at the bottom surface 25v of the recess 25a in a range adjacent to the low concentration portion 16b.

[0044] Next, as shown in FIG. 7, a gate insulating film 30 is formed on the semiconductor substrate 12. Here, the gate insulating film 30 is formed so as to cover the bottom surface 25v of the recess 25, the side surface 25s of the recess 25, and the upper surface 24t of the protrusion 24. Next, a gate electrode 32 is formed so as to cover the gate insulating film 30. Next, as shown in FIG. 8, the portion of the gate electrode 32 covering the upper surface 24t of the protrusion 24 and the side surface 25s of the recess 25 is removed by etching. The portion of the gate electrode 32 covering the bottom surface 25v of the recess 25 is left. Therefore, the upper surface 32t of the gate electrode 32 is located lower than the upper surface 24t of the protrusion 24.

[0045] Next, as shown in FIG. 9, an interlayer insulating film 34 is formed on the semiconductor substrate 12. More specifically, first, an NSG film 34a is formed on the semiconductor substrate 12. The NSG film 34a is formed along the surface shape of the semiconductor substrate 12 (i.e., the shapes of the recesses 25 and the protrusions 24). Next, a BPSG film 34b is formed on the NSG film 34a. The BPSG film 34b is formed so that its upper surface is substantially flat. By forming the interlayer insulating film 34 in this manner, the upper surface 32t of the gate electrode 32 and the upper surfaces 24t of the protrusions 24 are covered with the interlayer insulating film 34.

[0046] 10, the interlayer insulating film 34 is partially etched to form a groove 60 in the interlayer insulating film 34. Here, the groove 60 is formed in a range spanning the upper parts of the protrusions 24a, 24b, and the recesses 25a, thereby exposing the upper surfaces 24t of the protrusions 24a, 24b in the groove 60. In addition, the interlayer insulating film 34 (more specifically, the NSG film 34a) is left on the gate electrode 32. As a result, the upper surfaces 24t of the protrusions 24a, 24b are located at the same height as the upper surface 34t of the interlayer insulating film 34 in the groove 60.

[0047] Next, as shown in FIG. 11, the source electrode 40 is formed on the semiconductor substrate 12. Here, the source electrode 40 is formed by sputtering or the like so that the groove portion 60 is filled with the source electrode 40. The source electrode 40 contacts the upper surface 24t of the protrusion 24 (i.e., the high concentration portion 16a and the contact portion 14a) in the groove portion 60. Since the groove portion 60 extends across the upper portions of the protrusions 24a, 24b, and the recesses 25a, the width of the groove portion 60 is wide. Therefore, when the groove portion 60 is filled with the source electrode 40, the generation of voids in the source electrode 40 in the groove portion 60 is suppressed.

[0048] Next, a drain electrode 42 is formed on the lower surface of the semiconductor substrate 12. This completes the switching device 10 shown in FIG.

[0049] As described above, according to the manufacturing method of the first embodiment, the upper surfaces 24t of the projections 24a and 24b are exposed in the wide groove 60, and the source electrode 40 is formed in the groove 60 to connect the source electrode 40 to the projections 24a and 24b. Since the projections 24a and 24b extend above the upper surface 32t of the gate electrode 32, the groove 60 can be formed to reach the projections 24a and 24b without interfering with the gate electrode 32, and the width of the groove 60 can be made wide. Therefore, when the source electrode 40 is formed, the generation of voids in the source electrode 40 in the groove 60 can be suppressed. According to this manufacturing method, the source electrode 40 connected to the source layer 14 and the body layer 16 can be suitably formed.

[0050] Moreover, in this manufacturing method, the interlayer insulating film 34 is formed, which is composed of the NSG film 34a and the BPSG film 34b. Since the NSG film 34a has a high withstand voltage, the interlayer insulating film 34 can achieve a high withstand voltage. Furthermore, the surface of the BPSG film 34b is easily planarized. Therefore, when the groove portion 60 is formed in the interlayer insulating film 34, the interlayer insulating film 34 can be appropriately etched. Furthermore, since the BPSG film 34b has an effect of gettering mobile ions such as Na, the influence of external ions on the switching device 10 can be suppressed by the interlayer insulating film 34 having the BPSG film 34b.

[0051] In the first embodiment, in the step of forming the groove 60, the upper surface 24t of the protrusion 24 is at the same height as the upper surface 34t of the interlayer insulating film 34 in the groove 60 as shown in FIG. 10. However, as shown in FIG. 12, the upper surface 24t of the protrusion 24 may be located higher than the upper surface 34t of the interlayer insulating film 34 in the groove 60. Even in this case, the source electrode 40 can be connected to the upper surface 24t of the protrusion 24 by forming the source electrode 40 in the groove 60. Also, with this configuration, when the source electrode 40 is embedded in the groove 60, the generation of voids in the source electrode 40 can be suppressed.

[0052] Furthermore, in the manufacturing method of Example 1, since the side surface 25s of the recess 25 is covered with the gate insulating film 30, the protrusion 24 and the gate electrode 32 can be insulated from each other by the gate insulating film 30. That is, the insulation distance between the protrusion 24 and the gate electrode 32 can be controlled by the thickness of the gate insulating film 30. This makes it possible to minimize the insulation distance between the protrusion 24 and the gate electrode 32 while reliably insulating them from each other. Therefore, the switching device 10 can be miniaturized. EXAMPLES

[0053] Next, a switching device of Example 2 and a manufacturing method thereof will be described. In the switching device of Example 2 shown in FIG. 13, a plurality of contact holes 62 are provided instead of the groove portion 60 of FIG. 1. The other configurations of the switching device of Example 2 are the same as those of the switching device 10 of Example 1. As shown in FIG. 13, each contact hole 62 is provided in the interlayer insulating film 34 on the upper portion of each convex portion 24. The source electrode 40 is in contact with the upper surface 24t of the convex portion 24 (i.e., the contact portion 14a of the source layer 14 and the high concentration portion 16a of the body layer 16) in each contact hole 62.

[0054] In the manufacturing method of Example 2, processing is performed up to the state shown in FIG. 9 in the same manner as in the manufacturing method of Example 1. Next, as shown in FIG. 14, the interlayer insulating film 34 is selectively etched to form contact holes 62. That is, the interlayer insulating film 34 is etched at the upper position of each protrusion 24 to form the contact holes 62. As a result, the upper surface 24t of each protrusion 24 is exposed in the contact holes 62.

[0055] 13, a source electrode 40 is formed on the upper part of the semiconductor substrate 12 by sputtering or the like, and a drain electrode 42 is formed on the lower part of the semiconductor substrate 12. In this way, the switching device of Example 2 is completed.

[0056] As described above, in the manufacturing method of the second embodiment, each contact hole 62 is filled with the source electrode 40. Here, if the convex portion 24 is not formed on the upper surface of the semiconductor substrate 12, it is necessary to form a deep contact hole 62x in the interlayer insulating film 34 in order to expose the source layer 14 and the body layer 16, as shown in FIG. 15. In contrast, in the manufacturing method of the second embodiment, as shown in FIG. 13, the convex portion 24 is formed on the upper surface of the semiconductor substrate 12, so that the source layer 14 and the body layer 16 can be exposed by the shallow contact hole 62. In this way, since each contact hole 62 is shallow (i.e., the aspect ratio of each contact hole 62 is low), in the manufacturing method of the second embodiment, when each contact hole 62 is filled with the source electrode 40, the generation of voids in the source electrode 40 in each contact hole 62 can be suppressed.

[0057] Also, as shown in FIG. 15, when the semiconductor substrate 12 does not have the convex portion 24, if the position at which the contact hole 62x is formed is shifted, the gate electrode 32 is exposed in the contact hole 62x. In this case, if the source electrode 40 is formed in the contact hole 62x, the source electrode 40 and the gate electrode 32 are shorted. In order to prevent such a short circuit in FIG. 15, it is necessary to provide a sufficiently wide interval between the contact hole 62x and the gate electrode 32 in consideration of manufacturing errors. However, providing such a wide interval increases the size of the switching device. In contrast, in the manufacturing method of the second embodiment, as shown in FIG. 13, each convex portion 24 extends above the gate electrode 32 (i.e., the upper surface 24t of each convex portion 24 is located above the upper surface 32t of the gate electrode 32), so that the contact hole 62 formed in the interlayer insulating film 34 is shallow. Therefore, even if the position at which the contact hole 62 is formed is shifted, the contact hole 62 and the gate electrode 32 do not interfere with each other. Thus, according to the configuration of the second embodiment, even if the position is shifted when the contact hole 62 is formed, the gate electrode 32 is not exposed in the contact hole 62. Therefore, the distance between the contact hole 62 and the gate electrode 32 can be narrowed, and the switching device can be made smaller. EXAMPLES

[0058] Next, a switching device of Example 3 and a manufacturing method thereof will be described. In the switching device of Example 3 shown in FIG. 16, each contact hole 62 has a tapered shape that narrows toward the bottom. The other configurations of the switching device of Example 3 are the same as those of Example 2.

[0059] In the method for manufacturing the switching device of Example 3, in the step of forming the contact hole 62, the contact hole 62 is formed to have a tapered shape that narrows toward the bottom. Thereafter, the source electrode 40 is formed on the top of the semiconductor substrate 12, and the drain electrode 42 is formed on the bottom of the semiconductor substrate 12. In this way, the switching device of Example 3 is completed.

[0060] Since each contact hole 62 has a tapered shape that narrows toward the bottom, when each contact hole 62 is filled with the source electrode 40, voids are less likely to occur in the source electrode 40 in the contact hole 62. According to the manufacturing method of Example 3, the occurrence of voids can be more effectively suppressed.

[0061] 17, when the semiconductor substrate 12 does not have the protrusion 24 and a contact hole 62y having a tapered shape is formed, the distance between the upper surface 32t of the gate electrode 32 and the contact hole 62y (i.e., the source electrode 40) becomes extremely narrow. Therefore, when the contact hole 62y is misaligned, the contact hole 62y is likely to interfere with the gate electrode 32. In contrast, in the third embodiment, as shown in FIG. 16, the protrusion 24 extends above the upper surface 32t of the gate electrode 32, so that even if the contact hole 62 has a tapered shape, no interference occurs between the contact hole 62 and the gate electrode 32. The source electrode 40 in the contact hole 62 can be reliably insulated from the gate electrode 32.

[0062] In the above-mentioned first to third embodiments, a switching device (i.e., a vertical switching device) has been described in which a source electrode 40 is provided on an upper portion of the semiconductor substrate 12 and a drain electrode 42 is provided on a lower portion of the semiconductor substrate 12. However, the technology disclosed in this specification may be applied to a horizontal switching device in which a source electrode and a drain electrode are provided on an upper portion of the semiconductor substrate. In this case, a convex portion and a concave portion may be formed on the upper surface of the semiconductor substrate, and the drain layer may be formed so as to extend from the bottom surface of the concave portion to the upper surface of the convex portion, and the drain layer may be connected to the drain electrode on the upper surface of the convex portion. With this configuration, it is possible to suppress the generation of voids in the drain electrode when the drain electrode is formed.

[0063] In the above-described embodiment, the interlayer insulating film 34 includes the NSG film 34a and the BPSG film 34b. However, the interlayer insulating film 34 may be configured as a single layer (for example, a single layer of the NSG film 34a or a single layer of the BPSG film 34b).

[0064] In the above embodiment, the protrusion 24 extends above the upper surface 32t of the gate electrode 32. However, the upper surface 24t of the protrusion 24 may be at the same height as the upper surface 32t of the gate electrode 32.

[0065] (Reference example) Next, a switching device of a reference example and a manufacturing method thereof will be described. Fig. 18 shows the switching device of the reference example. In the description of the switching device of the reference example, components corresponding to the respective parts of the switching devices of Examples 1 to 3 will be described using the same reference numerals as those of Examples 1 to 3.

[0066] 18, in the switching device of the reference example, no convex portion 24 is provided on the upper surface of the semiconductor substrate 12. Further, a contact electrode 124 made of a conductor is provided in a portion corresponding to the convex portion 24. The contact electrode 124 is in contact with the source layer 14 and the high concentration portion 16a of the body layer 16.

[0067] In the method for manufacturing the switching device of the reference example, as shown in FIG. 19, after forming each semiconductor layer (i.e., the high concentration n-type layer 20, the drift layer 18, the body layer 16, and the source layer 14), a contact electrode 124 is formed on the upper surface of the semiconductor substrate 12. Here, the contact electrode 124 is formed so as to protrude upward from the upper surface of the semiconductor substrate 12. For example, the contact electrode 124 is formed on the entire upper surface of the semiconductor substrate 12, and then the contact electrode 124 is partially removed, so that the contact electrode 124 can be patterned as shown in FIG. 19. Next, as shown in FIG. 20, a gate insulating film 30, a gate electrode 32, and an interlayer insulating film 34 are formed in the same manner as in Example 1. Next, as shown in FIG. 18, a groove portion 60 is formed in the interlayer insulating film 34, and the groove portion 60 is filled with the source electrode 40 in the same manner as in Example 1. Next, a drain electrode 42 is formed on the lower surface of the semiconductor substrate 12. Through the above steps, the switching device of the reference example shown in FIG. 18 is completed.

[0068] In the switching device of the reference example, the contact electrode 124 also extends above the upper surface 32t of the gate electrode 32, so that the source electrode 40 can be connected to the contact electrode 124 in the wide groove portion 60. This makes it possible to prevent voids from being generated in the source electrode 40 in the groove portion 60. When the contact electrode 124 is used as in the reference example, the contact hole 62 may be used as in the second and third embodiments.

[0069] The source electrode 40 of the embodiment is an example of an upper electrode. The contact portion 14a of the embodiment is an example of a source layer contact portion. The high concentration portion 16a of the embodiment is an example of a body layer contact portion. The drain electrode 42 of the embodiment is an example of a lower electrode.

[0070] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes to the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or drawings achieves multiple objectives simultaneously, and achieving one of the objectives itself has technical utility. [Explanation of symbols]

[0071] 10: switching device, 12: semiconductor substrate, 14: source layer, 14a: contact portion, 16: body layer, 16a: high concentration portion, 16b: low concentration portion, 22: drain layer, 24: convex portion, 25: concave portion, 30: gate insulating film, 32: gate electrode, 34: interlayer insulating film, 40: source electrode, 42: drain electrode

Claims

1. A switching device comprising: A semiconductor substrate (12) having a recess (25) and a protrusion (24) on an upper surface thereof; a gate insulating film (30) covering a bottom surface (25v) of the recess; a gate electrode (32) covering an upper surface of the gate insulating film; an interlayer insulating film (34) covering an upper surface (32t) of the gate electrode; an upper electrode (40) covering an upper surface (34t) of the interlayer insulating film and contacting an upper surface (24t) of the protrusion; having the upper surface of the protrusion is at the same height as the upper surface of the gate electrode or is located higher than the upper surface of the gate electrode, The semiconductor substrate is an n-type source layer (14) in contact with the gate insulating film at the bottom surface of the recess; a p-type body layer (16) in contact with the gate insulating film at the bottom surface of the recess; an n-type drain layer (22) in contact with the gate insulating film at the bottom surface of the recess and separated from the source layer by the body layer; having At least one of the source layer and the body layer has a contact portion (14a, 16a) that extends to the upper surface of the protrusion and contacts the upper electrode. Switching devices.

2. The switching device according to claim 1 , wherein the upper surface of the protrusion is at the same height as the upper surface of the interlayer insulating film or is located higher than the upper surface of the interlayer insulating film.

3. a contact hole (60) reaching the upper surface of the protrusion is provided in the interlayer insulating film; the upper electrode is in contact with the upper surface of the protrusion within the contact hole; 2. The switching device of claim 1.

4. The switching device according to claim 3 , wherein the contact hole has a tapered shape that narrows toward a lower side.

5. A lower electrode (42) covering the lower surface of the semiconductor substrate, the source layer and the body layer have the contact portion; The drain layer (20) is in contact with the lower electrode. A switching device according to any one of claims 1 to 4.

6. 1. A method for manufacturing a switching device, comprising: A process for processing a semiconductor substrate, comprising the steps of: The upper surface of the semiconductor substrate has a recess and a protrusion. the semiconductor substrate has an n-type source layer exposed at a bottom surface of the recess, a p-type body layer exposed at the bottom surface of the recess, and an n-type drain layer exposed at the bottom surface of the recess and separated from the source layer by the body layer; At least one of the source layer and the body layer has a contact portion extending to an upper surface of the protrusion. processing the semiconductor substrate so as to satisfy the above condition; forming a gate insulating film covering the bottom surface of the recess; forming a gate electrode covering an upper surface of the gate insulating film, the gate electrode being formed so that the upper surface of the gate electrode is at the same height as the upper surface of the convex portion or is located lower than the upper surface of the convex portion; forming an interlayer insulating film covering the upper surface of the gate electrode and the upper surface of the protruding portion; removing a portion of the interlayer insulating film to expose the upper surface of the protrusion; forming an upper electrode covering an upper surface of the interlayer insulating film and contacting the contact portion on the upper surface of the protrusion; The manufacturing method comprising the steps of:

7. In the step of processing the semiconductor substrate, a plurality of the protrusions are formed on the upper surface of the semiconductor substrate; 7. The manufacturing method according to claim 6, wherein in the step of removing a portion of the interlayer insulating film to expose the upper surfaces of the convex portions, the upper surfaces of the multiple convex portions are exposed by etching the interlayer insulating film in an area spanning upper portions of the multiple convex portions and upper portions of the gate electrodes located between the multiple convex portions.

8. 7. The method according to claim 6, wherein in the step of removing a portion of the interlayer insulating film to expose the upper surface of the convex portion, a contact hole is formed in a portion of the interlayer insulating film covering the upper surface of the convex portion.

9. The manufacturing method according to claim 8 , wherein the contact hole has a tapered shape that narrows toward a lower side.

10. The step of processing the semiconductor substrate includes: forming the contact portion of the body layer by epitaxial growth; forming a p-type protrusion, which is the protrusion constituted by the contact portion of the body layer, by etching a part of the contact portion of the body layer; The method according to any one of claims 6 to 9, comprising:

11. In the step of forming the p-type protrusion, a plurality of the p-type protrusions are formed, the step of processing the semiconductor substrate includes a step of forming an n-type protrusion by implanting an n-type impurity into at least one of the plurality of p-type protrusions, the n-type protruding portion is the contact portion of the source layer; The method of claim 10.

12. The method according to claim 6, wherein in the step of forming the gate insulating film, the gate insulating film is formed so as to cover the bottom surface and side surfaces of the recess.

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