Method for reducing effective oxide thickness in semiconductor structures - Patents.com

Abstract

A method and apparatus for forming a semiconductor structure having a scaled effective oxide thickness is disclosed. In an embodiment, the method includes depositing an amorphous silicon capping layer having a first surface on a first surface of a titanium nitride (TiN) layer, the titanium nitride layer overlying a first surface of a high-k dielectric layer disposed in a film stack, depositing the amorphous silicon capping layer having the first surface on the first surface of the titanium nitride (TiN) layer, contacting the first surface of the amorphous silicon capping layer with a nitrogen-containing gas, and annealing the film stack.

Description

[Technical field]

[0001]

[0001] Embodiments of the present disclosure relate generally to the processing of electronic devices, and more specifically to reducing the effective oxide thickness of film stacks and compositions of film stacks, such as high-k dielectric-containing materials and interfacial layer materials. [Background technology]

[0002] Metal gate / high-k stacks are increasingly being utilized in metal oxide semiconductor field effect transistors (MOSFETs) for the 7 nm technology node and beyond. However, the inventors have observed that many challenges remain in the art. In particular, the rapid growth of mobile devices, the Internet, and machine learning is driving demands for better transistor technology performance for more advanced nodes (n<10 nm) with lower power consumption. The demand necessitates a continuation of Moore's law to shrink one or more transistor sizes while increasing transistor density on a chip. With the constant demand for continued miniaturization of chip manufacturing technologies, reduction of effective oxide thickness (EOT) of film stacks including high-k dielectric layers has become increasingly important in FinFET manufacturing. The inventors have observed that capping the high-k dielectric layer during annealing of the high-k dielectric layer during semiconductor device manufacturing with amorphous silicon (a-Si) film is an effective method of reducing the effective oxide thickness. However, annealing temperatures above 800° C. can cause the a-Si to crystallize and agglomerate, resulting in non-uniform thickness and composition, which can reduce device reliability.

[0003] Accordingly, the present inventors have provided an improved method and apparatus for forming semiconductor structures having a reduced effective oxide thickness, as well as a method for reducing a-Si agglomeration at high temperatures. Summary of the Invention

[0004]

[0004] Provided herein are methods and apparatus for forming a semiconductor structure having a reduced effective oxide thickness. In some embodiments, a method for forming a semiconductor structure having a reduced effective oxide thickness includes depositing an amorphous silicon capping layer having an upper surface over a titanium nitride (TiN) layer, the titanium nitride layer having an upper surface over the titanium nitride (TiN) layer, contacting the upper surface of the amorphous silicon capping layer with a nitrogen-containing gas, and annealing the film stack.

[0005]

[0005] In some embodiments, a method for reducing the effective oxide thickness of a film stack includes depositing an amorphous silicon capping layer having an upper surface on a titanium nitride (TiN) layer, the titanium nitride layer overlying a high dielectric constant dielectric layer disposed in the film stack, depositing an amorphous silicon capping layer having an upper surface on a titanium nitride (TiN) layer, the titanium nitride layer overlying a high dielectric constant dielectric layer disposed in the film stack, contacting the upper surface of the amorphous silicon capping layer with a nitrogen-containing gas, and annealing the film stack.

[0006]

[0006] In some embodiments, a method for forming a semiconductor structure having a reduced effective oxide thickness includes depositing an amorphous silicon capping layer having an upper surface directly on a titanium nitride (TiN) layer, the titanium nitride layer being directly on a high k dielectric layer disposed in a film stack, the high k dielectric layer being directly on an interfacial layer disposed in the film stack; contacting the upper surface of the amorphous silicon capping layer with hydrazine gas or hydrazine vapor at a temperature of about 300 degrees Celsius to about 600 degrees Celsius for about 30 seconds to about 5 minutes; annealing the film stack at a temperature of about 700 to 1000 degrees Celsius; and removing the amorphous silicon capping layer.

[0007]

[0007] In some embodiments, the disclosure relates to a non-transitory computer readable medium having instructions stored thereon that, when executed, perform a method of forming a semiconductor structure having a reduced effective oxide thickness, the method including depositing an amorphous silicon capping layer having an upper surface over a titanium nitride (TiN) layer, the titanium nitride layer overlying a high dielectric constant dielectric layer disposed in a film stack, depositing an amorphous silicon capping layer having an upper surface over a titanium nitride (TiN) layer, the titanium nitride layer overlying a high dielectric constant dielectric layer disposed in a film stack, contacting the upper surface of the amorphous silicon capping layer with a nitrogen-containing gas, and annealing the film stack.

[0008]

[0008] Other and further embodiments of the present disclosure are described below.

[0009]

[0009] The embodiments of the present disclosure, summarized above and described in more detail below, can be understood by reference to the exemplary embodiments of the present disclosure, which are illustrated in the accompanying drawings. However, the accompanying drawings merely illustrate typical embodiments of the present disclosure, and therefore should not be considered as limiting the scope, as the present disclosure may admit of other equally effective embodiments. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a flow diagram of a method for forming a semiconductor device according to some embodiments of the present disclosure. [Diagram 2] 2A-2E are illustrative cross-sectional views of a substrate during different stages of the processing sequence of FIG. 1 according to some embodiments of the present disclosure. [Diagram 3] A device suitable for carrying out the method and forming a device according to the present disclosure. [Figure 4] FIG. 2 is a flow diagram of a method for forming a semiconductor structure having a reduced effective oxide thickness according to some embodiments of the present disclosure. [Diagram 5]FIG. 2 is a flow diagram of a method for forming a semiconductor structure having a reduced effective oxide thickness according to some embodiments of the present disclosure.

[0011]

[0015] For ease of understanding, the same reference numbers have been used, where possible, to designate identical elements common to the drawings. The drawings are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated in other embodiments without further detail. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012]

[0016] Embodiments of the present disclosure provide methods of forming semiconductor structures and methods of reducing the effective oxide thickness of a film stack. For example, in some embodiments, a method of forming a semiconductor structure having a scaled effective oxide thickness includes depositing an amorphous silicon capping layer having an upper surface on a titanium nitride (TiN) layer, the titanium nitride layer overlying a high-k dielectric layer disposed in the film stack, contacting the upper surface of the amorphous silicon capping layer with a nitrogen-containing gas, and annealing the film stack.

[0013]

[0017] The method of the present disclosure treats amorphous silicon (a-Si) with a nitrogen-containing gas or vapor under conditions suitable to reduce or eliminate agglomeration of the amorphous silicon during high temperature annealing. The inventors have observed that by reducing or eliminating agglomeration of the amorphous silicon during high temperature annealing, the coverage and uniformity of the high-k dielectric layer is advantageously increased. Agglomeration of the amorphous silicon during annealing can be prevented, reduced, or eliminated by treating the deposited amorphous silicon with a nitrogen-containing gas or vapor such as hydrazine prior to annealing. The inventors have observed that treating the amorphous silicon according to the present disclosure advantageously maintains the efficacy of the amorphous silicon capping layer or film in reducing the effective oxide thickness of a film stack, for example, including a high-k dielectric layer and an interfacial layer. The scaled or reduced effective oxide thickness according to the present disclosure may be suitable to obtain a desired semiconductor device or a desired film stack for use in a semiconductor device. The embodiments of the present disclosure may be used in devices that may be advantageously formed using atomic layer deposition (ALD) processes and may undergo further processing. In some embodiments, the methods of the present disclosure advantageously provide film stacks having a desired or predetermined effective oxide thickness suitable for use in fin field effect transistors (FinFETs) at the 7 nm technology node and beyond. In embodiments, the effective oxide thickness of the film stacks of the present disclosure is predetermined. For example, the desired effective oxide thickness of the film stacks of the present disclosure may be targeted to be between 8 and 9 angstroms (Å) in thickness. In embodiments, the effective oxide thickness of the film stacks of the present disclosure may be reduced by about 0.5 to 2.0 angstroms compared to a substantially similar film stack made without the methods of the present disclosure.

[0014]

[0018] FIG. 1 is a flow diagram of a method 100 for forming a semiconductor device according to some embodiments of the present disclosure. The method 100 is described below with respect to the deposition of various layers including amorphous silicon as shown in FIGS. 2A-2E. The method 100 may be performed in a suitable process chamber, such as, for example, the process chamber 16 of FIG. 3. Exemplary processing systems that may be used to perform the methods disclosed herein may include, but are not limited to, any of the ENDURA®, CENTURA®, or PRODUCER® brand processing systems available from Applied Materials, Inc., Santa Clara, Calif. Non-limiting examples of suitable cluster tools and process chambers are disclosed in commonly owned U.S. Patent No. 7,405,158, entitled "Method for Depositing a Tungsten Layer Using Atomic Layer Deposition Techniques," issued to Lai et al. on July 29, 2008. Other process chambers, including those available from other manufacturers, may also be suitably used in conjunction with the teachings provided herein.

[0015]

[0019] The method 100 is typically performed on a substrate 200 provided to a processing region of a process chamber, such as a process chamber suitable for performing cyclic deposition, such as atomic layer deposition. Although not shown in FIG. 1, in an embodiment, the substrate 200 to be processed is first loaded into and placed in a process chamber in which cyclic deposition is performed and process conditions may be adjusted (such as process chamber 16 shown in FIG. 3) and / or a process chamber suitable for annealing at high temperature. In some embodiments, as shown in FIG. 2A, the substrate 200 includes a first surface 205 and an interface layer 210 overlying the first surface 205 of the substrate 200. The interface layer 210 has a first surface 212. Although the following description is made with respect to a substantially planar substrate 200 as shown in FIGS. 2A-2E, in some embodiments, the substrate 200 may include one or more features (such as multiple trenches, vias, etc.) (not shown in FIGS. 2A-2E).

[0016]

[0020] Substrate 200 may be any suitable substrate. For example, substrate 200 may include one or more of silicon (Si), silicon oxide (SiO2), etc. In an embodiment, substrate 200 is an oxide substrate. In an embodiment, substrate 200 may include a dielectric layer or a dielectric substrate. For example, low-k materials (e.g., materials having a dielectric constant less than silicon oxide or less than about 3.9), etc., may be suitable for use herein. Additionally, substrate 200 may include additional layers of material or have one or more completed or partially completed structures or devices formed in or on substrate 200 (not shown). In an embodiment, substrate 200 may be, for example, a doped or undoped silicon substrate, a III-V compound substrate, a silicon germanium (SiGe) substrate, an epi substrate, a silicon-on-insulator (SOI) substrate, a display substrate such as a liquid crystal display (LCD), a plasma display, an electroluminescent (EL) lamp display, a light emitting diode (LED) substrate, a solar cell array, a solar panel, etc. In some embodiments, the substrate 200 can be a semiconductor wafer. In embodiments, the substrate 200 is an oxide substrate, a dielectric substrate, or a combination thereof. The substrate 200 is not limited to any particular size or shape. The substrate 200 can be a round wafer having a diameter of 200 mm, a diameter of 300 mm, or other diameter, for example, 450 mm, among others. The substrate 200 can also be any polygonal, square, rectangular, curved, or other non-circular workpiece, such as a polygonal glass substrate used in the manufacture of flat panel displays.

[0017]

[0021] As shown in FIG. 2A, the substrate 200 includes an interface layer 210 on the first side 205 of the substrate 200. In an embodiment, the interface layer 210 is directly on the first side 205. In an embodiment, the interface layer 210 includes a first side 212. In an embodiment, the interface layer 210 is deposited by any means known in the art, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), to a thickness sufficient to reduce damage between the high-k dielectric layer 220 and a silicon substrate, such as the substrate 200, or to separate the high-k dielectric layer 220 from the substrate 200, for example, about 5 Å to 20 Å thick, or about 10 Å or 10 Å thick. In an embodiment, the interface layer 210 includes silicon dioxide (SiO2), silicon oxynitride (SiON), or the like.

[0018]

[0022] Reference is now made to FIG. 2B, which illustrates the substrate 200 and the interfacial layer 210 with a high-k dielectric layer 220 on the first side 212 of the interfacial layer 210. In an embodiment, the high-k dielectric layer 220 is directly on the first side 212 of the interfacial layer 210, which is directly on the first side 205 of the substrate 200. In an embodiment, the high-k dielectric layer 220 is suitable for use in a film stack of a transistor device. In some embodiments, the high-k dielectric layer 220 may be deposited on the first side 212 of the interfacial layer 210. In an embodiment, the high-k dielectric layer 220 may be deposited to a predetermined thickness by any deposition means known in the art to form a film. In an embodiment, the high-k dielectric layer 220 is made of a material having a high dielectric constant (high-k material has a dielectric constant greater than 4.0), such as hafnium (IV) oxide (HfO2), zirconium dioxide (ZrO2), aluminum oxide (Al2O3), barium strontium titanate (BST), lead zirconate titanate (PZT), zirconium silicate (ZrSiO2), hafnium silicon dioxide (HfSiO2), tantalum dioxide (TaO2), silicon oxide (SiO2), hafnium silicate (HfSiO), etc. In an embodiment, a suitable high-k dielectric layer includes a high-k oxide grown by atomic layer deposition to form a thin film, and the high-k dielectric layer 220 has a thickness of about 10 to 30 angstroms, such as about 25 angstroms. In some embodiments, the high-k dielectric layer 220 includes or is composed of hafnium (IV) oxide (HfO2) having a thickness of about 10 to 30 angstroms, such as about 25 angstroms.

[0019]

[0023] Reference is now made to FIG. 2C, which illustrates the substrate 200, the interfacial layer 210, and the high-k dielectric layer 220 with a titanium nitride layer 230 on the first side 225 of the high-k dielectric layer 220. In an embodiment, the titanium nitride layer 230 is directly on the first side 225 of the high-k dielectric layer 220, which is directly on the first side 212 of the interfacial layer 210, which is directly on the first side 205 of the substrate 200. In an embodiment, the titanium nitride layer 230 is suitable for use in a film stack of a transistor device. In some embodiments, the titanium nitride layer 230 may be deposited on the first side 225 of the high-k dielectric layer 220. In an embodiment, the titanium nitride layer 230 may be deposited to a predetermined thickness by any deposition means known in the art to form a film. In an embodiment, the titanium nitride layer 230 is made of a substantially pure titanium nitride (TiN) material. In embodiments, suitable titanium nitride layer 230 includes a titanium nitride film grown by atomic layer deposition to a thickness of about 5 to 25 angstroms, such as 10 to 20 angstroms, or about 15 angstroms or 15 angstroms. In some embodiments, titanium nitride layer 230 includes or consists of titanium nitride having a thickness of about 10 to 20 angstroms.

[0020]

[0024] Reference is now made to FIG. 2D, which illustrates a substrate 200, an interfacial layer 210, a high-k dielectric layer 220, and a titanium nitride layer 230, along with an amorphous silicon capping layer 240 on a first side 235 of the titanium nitride layer 230. In an embodiment, the amorphous silicon capping layer 240 is directly on the first side 235 of the titanium nitride layer 230, which is directly on the high-k dielectric layer 220, the high-k dielectric layer 220 is directly on the first side 212 of the interfacial layer 210, and the interfacial layer 210 is directly on the first side 205 of the substrate 200. In an embodiment, the amorphous silicon capping layer 240 is suitable for use in forming a film stack of a transistor device. In some embodiments, the amorphous silicon capping layer 240 may be deposited on the first side 235 of the titanium nitride layer 230. In embodiments, the amorphous silicon capping layer 240 may be deposited to a predetermined thickness by any deposition means known in the art to form a film. In embodiments, the amorphous silicon capping layer 240 may be made of substantially pure amorphous silicon capping layer 240 material. In embodiments, a suitable amorphous silicon capping layer 240 may include amorphous silicon grown by atomic layer deposition to a thickness of about 20 to 50 angstroms, such as 30 to 40 angstroms, or about 35 angstroms. In some embodiments, the amorphous silicon capping layer 240 includes or consists of amorphous silicon having a thickness of about 20 to 50 angstroms.

[0021]

[0025] 1 , at 102, a method of forming a semiconductor structure with reduced effective oxide thickness includes depositing an amorphous silicon capping layer 240 having an upper surface 245 on a titanium nitride layer 230, the titanium nitride layer overlying a high-k dielectric layer 220 disposed in a film stack 260, contacting the upper surface 245 of the amorphous silicon capping layer 240 with a nitrogen-containing gas, and annealing the film stack 260. In an embodiment, the method includes contacting the upper surface 245 of the amorphous silicon capping layer 240 with a nitrogen-containing gas or vapor, at 104.

[0022]

[0026] In embodiments, contacting the top surface 245 of the amorphous silicon capping layer 240 with the nitrogen-containing gas or vapor is performed under conditions suitable to form a silicon nitride layer 250 (shown in dotted lines) on or within the amorphous silicon capping layer 240 adjacent to the top surface 245. In embodiments, the nitrogen-containing gas includes or consists of hydrazine gas or hydrazine vapor. In embodiments, the hydrazine gas or vapor is provided in an amount sufficient to form a silicon nitride layer on or within the amorphous silicon capping layer 240. In embodiments, the nitrogen-containing gas or vapor contacts the top surface 245 of the amorphous silicon capping layer 240 at a temperature of about 300 degrees Celsius to about 600 degrees Celsius. In some embodiments, the nitrogen-containing gas or vapor contacts the top surface 245 of the amorphous silicon capping layer 240 at a temperature of about 450 degrees Celsius to about 500 degrees Celsius. In some embodiments, the nitrogen-containing gas or vapor contacts the top surface 245 of the amorphous silicon capping layer 240 for about 30 seconds to about 5 minutes. In some embodiments, the nitrogen-containing gas or vapor contacts the top surface 245 of the amorphous silicon capping layer 240 under conditions where the amorphous silicon capping layer 240 has a thickness of 20 to 50 Angstroms, the titanium nitride (TiN) layer 230 has a thickness of about 10 to 20 Angstroms, and the high-k dielectric layer 220 has a thickness of about 10 to 30 Angstroms.

[0023]

[0027] In an embodiment, agglomeration of the amorphous silicon capping layer 240 during annealing may be prevented by treating the amorphous silicon capping layer 240 with hydrazine gas or vapor prior to annealing. In an embodiment, agglomeration of the amorphous silicon capping layer 240 is prevented after the amorphous silicon capping layer 240 is exposed to hydrazine vapor at 450 degrees Celsius for 2 minutes or at 500 degrees Celsius for 1 minute. In an embodiment, silicon nitride, such as SiNx (where x is an integer), may be formed on the top surface 245 of the amorphous silicon capping layer 240 after the amorphous silicon capping layer 240 is exposed to a nitrogen-containing gas, such as hydrazine. The formation of SiNx may suppress the remaining amorphous silicon capping layer 240 and prevent agglomeration of the amorphous silicon capping layer 240 during annealing. To preserve the efficacy of the amorphous silicon capping layer 240 in reducing the effective oxide thickness during annealing of the high-k dielectric layer 220, the bulk composition of the amorphous silicon capping layer 240 remains unchanged after a nitrogen-containing gas treatment, such as hydrazine, in which the nitrogen penetrates a limited portion of the amorphous silicon capping layer 240 to form, for example, a silicon nitride layer 250 (SiNx layer) on or within the amorphous silicon capping layer 240. In some embodiments, the nitrogen is present in the upper part of the nitrogen gas treated amorphous silicon capping layer 240. Thus, the efficacy of the amorphous silicon capping layer 240 in reducing the effective oxide thickness of the film stack 260 including the high-k dielectric layer 220 is unlikely to be affected.

[0024]

[0028] Returning to FIG. 1 , at 106, the method of forming a semiconductor structure with reduced effective oxide thickness includes annealing the film stack 260. In an embodiment, the annealing is performed at a temperature of about 700 to 1000 degrees Celsius. For example, the substrate 200 disposed in the process chamber 16 may be heated to a temperature of an amount of about 700 to 1000 degrees Celsius. In an embodiment of the present disclosure, the amorphous silicon capping layer 240 does not agglomerate and substantially covers the first surface 235 during the annealing. In some embodiments, following the annealing, the effective oxide thickness of the film stack including the high-k dielectric layer is reduced by about 0.5 to 2.0 Angstroms, about 0.5 to 1.5 Angstroms, for example, 2 Angstroms or 1 Angstrom. In an embodiment, the effective oxide thickness of the film stack including the high-k dielectric layer is reduced by 1 Angstrom. In embodiments, following the annealing, the effective oxide thickness of the high-k dielectric layer and the interfacial layer is reduced by about 0.5 to 2.0 Angstroms, about 0.5 to 1.5 Angstroms, e.g., 2 Angstroms or 1 Angstrom. In some embodiments, following the annealing, the method further includes etching the amorphous silicon capping layer. In some embodiments, such as those including removing or etching the amorphous silicon capping layer, after etching or removing the amorphous silicon capping layer, the effective oxide thickness of the film stack is reduced by about 0.5 to 2.0 Angstroms.

[0025]

[0029] 1 and 2E, methods of the present disclosure may include etching the amorphous silicon capping layer 240 such that the film stack 260 includes the substrate 200, the interfacial layer 210, and the high-k dielectric layer 220, with the titanium nitride layer 230 overlying the first side 225 of the high-k dielectric layer 220. In some etched embodiments, the effective oxide thickness of the high-k dielectric layer and the interfacial layer 210 is reduced by about 0.5 to 2.0 Angstroms, such as 2 Angstroms or 1 Angstrom.

[0026]

[0030] Reference is now made to FIG. 3, which illustrates a process chamber 16 suitable for deposition and annealing of layers according to the present disclosure in a single process chamber. In an embodiment, the process chamber 16 may be configured to operate in both CVD and cyclic deposition modes (ALD). One example of such a chamber is described in U.S. Patent No. 6,878,206, entitled Lid Assembly for a Processing System to Facilitate Sequential Deposition Techniques, filed on December 12, 2001 and assigned to Applied Materials, Inc. Still referring to FIG. 3, disposed within the process chamber 16 is a heater / lift assembly 46 including a support pedestal 48 connected to a support shaft 48a suitable for supporting a wafer. The support pedestal 48 is disposed between the support shaft 48a and the lid assembly 20 when the lid assembly 20 is in a closed position. The support shaft 48a extends from the support pedestal 48 away from the lid assembly 20 through a passageway formed in the housing 14. A bellows 50 is attached to a portion of the housing 14 located opposite the lid assembly 20 to prevent leakage between the support shaft 48a and the housing 14 into the process chamber 16. The heater / lift assembly 46 can be moved vertically within the process chamber 16 so that the distance between the support pedestal 48 and the lid assembly 20 can be controlled. A sensor (not shown) provides information regarding the position of the support pedestal 48 within the process chamber 16.

[0027]

[0031] The support pedestal 48 includes an embedded thermocouple 50a that can be used to monitor the temperature of the support pedestal 48. For example, the signal from the thermocouple 50a can be used in a feedback loop to control the power applied by the power supply 52 to a heater element 52a. The heater element 52a can be a resistive heater element or other heat transfer device disposed within or in contact with the support pedestal 48 that is utilized to control the temperature of the support pedestal 48. Optionally, the support pedestal 48 can be heated using a heat transfer fluid (not shown).

[0028]

[0032] The support pedestal 48 may be formed from any process compatible material, including aluminum nitride and aluminum oxide (Al2O3 or alumina), and may also be configured to hold a substrate 200 (not shown) thereon using a vacuum, i.e., the support pedestal 48 may be a vacuum chuck. As such, the support pedestal 48 may include a number of vacuum holes (not shown) arranged to be in fluid communication with a vacuum source, such as a pump system, via vacuum tubing routed through the support shaft 48a.

[0029]

[0033] The liner assembly is disposed in the process chamber 16 and includes a cylindrical portion 54 and a planar portion 56. The cylindrical portion 54 and the planar portion 56 may be formed from any suitable material, such as aluminum, ceramic, etc. The cylindrical portion 54 surrounds the support pedestal 48. The cylindrical portion 54 further includes an aperture 60 that aligns with the slit valve opening 44 located in the sidewall 14b of the housing 14 to allow passage of the substrate from the process chamber 16.

[0030]

[0034] The planar portion 56 extends transversely relative to the cylindrical portion 54 and is disposed relative to a chamber bottom 14a of the process chamber 16 that is disposed opposite the lid assembly 20. The liner assembly defines a channel 58 between the housing 14 and both the cylindrical portion 54 and the planar portion 56. Specifically, a first portion of the channel 58 is defined between the chamber bottom 14a and the planar portion 56. A second portion of the channel 58 is defined between the sidewall 14b of the housing 14 and the cylindrical portion 54. A purge gas is introduced into the channel 58.

[0031]

[0035] Located along the sidewall 14b of the process chamber 16 adjacent the lid assembly 20 is a pump channel 62. The pump channel 62 includes a plurality of apertures, one of which is shown as a first aperture 62a. The pump channel 62 includes a second aperture 62b coupled to a pump system 18 by a conduit 66. A throttle valve 18A is coupled between the pump channel 62 and the pump system 18. The pump channel 62, throttle valve 18A and pump system 18 control the amount of flow from the process chamber 16. The size, number and location of the apertures, such as the first aperture 62a, which communicate with the process chamber 16 are configured to achieve a uniform flow of gas therethrough and out of the lid assembly 20 when seated on the support pedestal 48 and substrate 200. Multiple supplies 68a, 68b, and 68c of process and / or other fluids are fluidly connected to one of the valves 32a, 32b, or 32c through a series of conduits (not shown) formed through the housing 14, the lid assembly 20, and the gas manifold 34.

[0032]

[0036] The controller 70 coordinates the operation of the various components of the system 10. The controller 70 includes a processor 72 in data communication with memory, such as a random access memory 74 and a hard disk drive 76, and communicates with at least the pump system 18, the power supply 52, and the valves 32a, 32b, and 32c. The random access memory 74 includes stored instructions that, when read by the processor 72, control the operation of the system 10 to perform the methods disclosed herein on the structures described herein within the process chamber. In some embodiments, the memory is a non-transitory computer readable medium. In embodiments, the memory, or computer readable medium of the CPU, may include one or more of a readily available memory, such as a random access memory (RAM), a read only memory (ROM), a floppy disk, a hard disk, or any other form of local or remote digital storage. In embodiments, support circuits are coupled to the CPU to support the processor in a conventional manner. These circuits include cache, power supplies, clock circuits, input / output circuits and subsystems, and the like.

[0033]

[0037] In some embodiments, any type of process fluid can be used, but an example of a process fluid is the precursor as described above, and optionally a purge fluid as described above, such as argon (Al) gas. Nitrogen (N2) can also be used as a purge gas. The chamber pressure can be in the pressure range described above, or can be in the range of 1 to 150 Torr, or 1 to 50 Torr. The support pedestal 48 is heated in the range of 300 degrees Celsius to 600 degrees Celsius so that the substrate can be maintained at a set temperature, such as a substrate at a temperature of 350 degrees Celsius to about 470 degrees Celsius, or 400 degrees Celsius to about 450 degrees Celsius. In embodiments, a process fluid, such as a precursor, can be flowed into the process chamber 16 with a carrier fluid, such as argon (Ar). However, the purge fluid can be different from the carrier fluid or precursor, the oxygen-containing gas, or the reactive gas.

[0034]

[0038] In a vapor deposition embodiment according to the present disclosure, the method includes performing an atomic layer deposition (ALD) process to deposit the substrate, the interface layer, the high-k dielectric layer, the titanium nitride layer, and the amorphous silicon capping layer 240, as described above. One cycle of ALD may include flowing a precursor into the process chamber 16 containing the substrate, purging the process chamber 16, such as pumping to remove all process fluids, and after pumping, providing a reactive gas, such as a precursor-containing gas. A subsequent purge may be performed to remove any unreacted reactive gas, precursor, or by-products thereof. After pumping, a reactive gas, such as a silicon precursor-containing gas, is provided. A subsequent purge may be performed to remove any unreacted reactive gas, precursor, or by-products thereof. In an embodiment, the ALD sequence of cycles is repeated until the layer formed has the desired properties, such as thickness, conductivity, etc. In an embodiment, the ALD sequence of cycles is repeated until the layer formed has the desired properties, such as the desired thickness, or a predetermined amount of, for example, amorphous silicon, as described above. In some embodiments, purge gas may be strategically delivered through the lower portion of passage 73 to sweep cleaning agent from gas manifold 34 and the baffle plate.

[0035]

[0039] Reference is now made to FIG. 4, which illustrates a method of forming a semiconductor structure with reduced effective oxide thickness. The method includes depositing an amorphous silicon capping layer 240 having an upper surface 245 directly over a titanium nitride (TiN) layer 230, the titanium nitride layer 230 being directly over a high-k dielectric layer 220 disposed in a film stack 260, the high-k dielectric layer 220 being directly over an interfacial layer 210 disposed in the film stack 260. In an embodiment, the method includes contacting the upper surface 245 of the amorphous silicon capping layer 240 with hydrazine gas or vapor at a temperature of about 300 degrees Celsius to about 600 degrees Celsius for about 30 seconds to about 5 minutes at 404. In an embodiment, the method includes annealing the film stack at a temperature of about 700 to 1000 degrees Celsius at 406. In an embodiment, the method includes removing the amorphous silicon capping layer 240 at 408. In embodiments, following the annealing process, the effective oxide thickness of the film stack is reduced by about 0.5 to 2 Angstroms. In embodiments, the nitrogen-containing vapor comprises hydrazine gas or vapor provided under the conditions described above. In some embodiments, the nitrogen-containing vapor contacts the top surface 245 of the amorphous silicon capping layer 240 at a temperature of about 300 degrees Celsius to about 600 degrees Celsius for about 30 seconds to about 5 minutes. In some embodiments, the annealing process is performed at a temperature of about 700 to 1000 degrees Celsius. In some embodiments, the amorphous silicon capping layer 240 has a thickness of 20 to 50 Angstroms and the high-k capping layer 220 has a thickness of about 10 to 30 Angstroms. In embodiments, the nitrogen-containing gas, including or consisting of hydrazine, contacts the top surface of the amorphous silicon capping layer at a temperature of about 300 degrees Celsius to about 600 degrees Celsius. In an embodiment, the nitrogen-containing gas comprising or consisting of hydrazine is contacted with the top surface of the amorphous silicon capping layer at a temperature of about 450 degrees Celsius to about 500 degrees Celsius. In an embodiment, the nitrogen-containing gas comprising or consisting of hydrazine is contacted with the top surface of the amorphous silicon capping layer for about 30 seconds to about 5 minutes.

[0036]

[0040] Reference is now made to FIG. 5, which illustrates a method of forming a semiconductor structure with a reduced effective oxide thickness. The method includes, in process sequence 502, depositing an amorphous silicon capping layer having an upper surface directly over a titanium nitride (TiN) layer, the titanium nitride layer being directly over a high-k dielectric layer disposed in a film stack, the high-k dielectric layer being directly over an interfacial layer disposed in the film stack. In embodiments, the method includes, in process sequence 504, contacting the upper surface of the amorphous silicon capping layer with hydrazine gas or hydrazine vapor at a temperature of about 300 degrees Celsius to about 600 degrees Celsius for about 30 seconds to about 5 minutes. In embodiments, the method includes, in process sequence 506, annealing the film stack at a temperature of about 700 to 1000 degrees Celsius. In some embodiments, the method includes, in process sequence 508, removing the amorphous silicon capping layer.

[0037]

[0041] Another embodiment of the present disclosure includes a method of forming a semiconductor structure with reduced effective oxide thickness, the method including depositing an amorphous silicon capping layer having a first surface on a first surface of a titanium nitride (TiN) layer, the titanium nitride layer overlying a first surface of a high-k dielectric layer disposed in a film stack, contacting the first surface of the amorphous silicon capping layer with hydrazine gas or vapor at a temperature of about 300 degrees Celsius to about 600 degrees Celsius for about 30 seconds to about 5 minutes, and annealing the film stack at a temperature of about 700 to 1000 degrees Celsius. The film stack may be etched to remove the amorphous silicon capping layer.

[0038]

[0042] Another embodiment of the present disclosure relates to a non-transitory computer readable medium having instructions stored thereon that, when executed, perform a method of forming a semiconductor structure with a reduced effective oxide thickness, the method including depositing an amorphous silicon capping layer having an upper surface over a titanium nitride (TiN) layer, the titanium nitride layer overlying a high-k dielectric layer disposed in a film stack; contacting the upper surface of the amorphous silicon capping layer with a nitrogen-containing gas; and annealing the film stack.

[0039]

[0043] Another embodiment of the present disclosure relates to a non-transitory computer readable medium having instructions stored thereon that, when executed, perform a method of forming a semiconductor structure with a reduced effective oxide thickness, the method including depositing an amorphous silicon capping layer having an upper surface over a titanium nitride (TiN) layer, the titanium nitride layer overlying a high-k dielectric layer disposed in a film stack; contacting the upper surface of the amorphous silicon capping layer with a nitrogen-containing gas; and annealing the film stack.

[0040]

[0044] Another embodiment of the present disclosure relates to a non-transitory computer readable medium having instructions stored thereon that, when executed, perform a method of forming a semiconductor structure with reduced effective oxide thickness, the method including depositing an amorphous silicon capping layer having a top surface directly over a titanium nitride (TiN) layer, the titanium nitride layer being directly over a high-k dielectric layer disposed in a film stack, the high-k dielectric layer being directly over an interfacial layer disposed in the film stack; contacting the top surface of the amorphous silicon capping layer with hydrazine gas or hydrazine vapor at a temperature of about 300 degrees Celsius to about 600 degrees Celsius for about 30 seconds to about 5 minutes; annealing the film stack at a temperature of about 700 to 1000 degrees Celsius; and removing the amorphous silicon capping layer.

[0041]

[0045] While the forgoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof.

Claims

1. 1. A method for forming a semiconductor structure having a reduced effective oxide thickness, comprising: depositing an amorphous silicon capping layer having an upper surface on a titanium nitride (TiN) layer, the titanium nitride layer overlying a high-k dielectric layer disposed in a film stack; contacting a top surface of the amorphous silicon capping layer with a nitrogen-containing gas to form a silicon nitride layer on the amorphous silicon capping layer; annealing the film stack; Including, The method, wherein the depositing, the contacting, and the annealing are performed in the same chamber.

2. The method of claim 1 , wherein the nitrogen-containing gas comprises hydrazine vapor.

3. 3. The method of claim 1 or 2, wherein the nitrogen-containing gas contacts the top surface of the amorphous silicon capping layer at a temperature of 450 degrees Celsius to 500 degrees Celsius.

4. 4. The method of claim 1, wherein the nitrogen-containing gas is in contact with the top surface of the amorphous silicon capping layer for 30 seconds to 5 minutes.

5. 5. The method according to claim 1, wherein the annealing is carried out at a temperature of from 700 degrees Celsius to 1000 degrees Celsius.

6. 6. The method of claim 1, further comprising etching the silicon nitride layer and the amorphous silicon capping layer following the annealing treatment.

7. A method according to any one of claims 1 to 5, further comprising etching the silicon nitride layer and the amorphous silicon capping layer, wherein said etching reduces the effective oxide thickness of the film stack by 0.5 to 2.0 angstroms.

8. The method of claim 1, wherein the depositing grows the amorphous silicon capping layer to a thickness of 20 to 50 angstroms.

9. 9. The method of claim 1, wherein the titanium nitride layer has a thickness of 10 to 20 Angstroms.

10. A method according to any one of claims 1 to 9, wherein the high dielectric constant dielectric layer before the effective oxide thickness of the film stack is reduced has a thickness of 10 to 30 angstroms.

11. 1. A method for reducing an effective oxide thickness of a film stack, comprising: depositing an amorphous silicon capping layer having an upper surface on a titanium nitride (TiN) layer, the titanium nitride layer overlying a high-k dielectric layer disposed in a film stack; contacting a top surface of the amorphous silicon capping layer with a nitrogen-containing gas to form a silicon nitride layer on the amorphous silicon capping layer; annealing the film stack; Including, The method, wherein the depositing, the contacting, and the annealing are performed in the same chamber.

12. The method of claim 11 , wherein the annealing reduces the effective oxide thickness of the film stack by 0.5 to 2 Angstroms.

13. 13. The method of claim 11 or 12, wherein the nitrogen-containing gas comprises hydrazine.

14. 1. A non-transitory computer readable medium having stored thereon instructions for causing a computer to control an apparatus for forming a semiconductor structure having a reduced effective oxide thickness, the apparatus comprising: The instructions, when executed on the computer, cause the device to: depositing an amorphous silicon capping layer having an upper surface on a titanium nitride (TiN) layer, the titanium nitride layer overlying a high-k dielectric layer disposed in a film stack; contacting a top surface of the amorphous silicon capping layer with a nitrogen-containing gas to form a silicon nitride layer on the amorphous silicon capping layer; annealing the film stack; wherein the depositing, the contacting, and the annealing are performed in the same chamber.

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