Microvia Formation Methodology for Advanced Packaging

Abstract

The present disclosure relates to microvia structures for interconnects in advanced wafer-level semiconductor packaging. The methods described herein enable the formation of high quality, low aspect ratio microvia structures with improved uniformity, thus improving bandwidth and power, and facilitating the realization of thin, small form factor semiconductor devices with high I / O density.

Description

[Technical field]

[0001] TECHNICAL FIELD

[0001] Embodiments described herein relate generally to microvia structures and methods for forming same for advanced wafer-level semiconductor packaging. [Background technology]

[0002] 2. Description of Related Art

[0002] Along with other ongoing trends in the development of miniaturized electronic devices and components, the demand for high speed processing capabilities with increased circuit density places corresponding demands on the materials, structures, and processes utilized in the manufacture of integrated circuit chips, circuit boards, and packaging structures. Accordingly, one area of ​​focus in semiconductor device development is the structure and fabrication methods of device interconnects (i.e., interconnects or interconnect structures) with reduced lateral dimensions.

[0003]

[0010] As is known, vertical interconnect access (or "VIA") is one example of an interconnect structure, and laser drilling is an established method for forming vias. Despite the trend to make vias smaller to increase interconnect density, conventional approaches to forming vias with such small diameters (e.g., 10 μm or less) may sacrifice certain quality parameters of the via to obtain the desired dimensions, especially in high volume manufacturing environments. Examples of such quality parameters generally include via morphology, uniformity, and via pad cleanliness.

[0004]

[0011] Additionally, current approaches to laser drilling vias typically rely on ultraviolet (UV) or pulsed CO2 lasers to directly drill vias in the panel. Both of these approaches require complex beam shaping optics to convert the Gaussian laser beam profile emitted by the laser source into a top-hat (i.e., flat-top) shaped beam profile, which typically cannot drill diameters below 40 μm in a consistent and cost-effective manner. Thus, masks can be used in combination with laser drilling to achieve the desired via size. However, current masking techniques require wet etching and / or laser drilling to pattern the mask, which can cause damage to the underlying layers and / or the formation of unwanted debris. Additionally, certain approaches utilize masks formed of substantially the same material as the underlying conductive layers and / or interconnects, making the mask difficult to remove during laser drilling of the vias.

[0005]

[0003] Therefore, there is a need in the art for improved methods of forming high quality small diameter vias, such as microvias. Summary of the Invention

[0006]

[0004] The present disclosure relates generally to microvia structures and methods for forming same for advanced wafer-level semiconductor packaging.

[0007] In a particular embodiment, a method is provided for forming a microvia structure in a semiconductor device. The method includes laminating a dielectric layer over the semiconductor device, depositing a metal layer over the dielectric layer, and applying, patterning, and developing a resist over the metal layer to form a trench in the layer of resist corresponding to a desired lateral dimension of the microvia structure. The method further includes etching the metal layer through the trench in the developed layer of resist to extend a trench in the metal layer and expose a portion of the dielectric layer. The method also includes laser ablating the exposed portion of the dielectric layer to form a microvia structure having the desired lateral dimension.

[0008] In a particular embodiment, a method is provided for forming a microvia structure in a semiconductor device. The method includes laminating a dielectric layer over a conductive layer of the semiconductor device, depositing a metal layer over the dielectric layer, and applying, patterning, and developing a resist over the metal layer to form a trench in the layer of resist corresponding to a desired lateral dimension of the microvia structure. The method further includes selectively etching the metal layer through the trench in the developed layer of resist to extend a trench in the metal layer and expose a portion of the dielectric layer, laser ablating the exposed portion of the dielectric layer to form a microvia structure having the desired lateral dimension, exposing the microvia structure to a cleaning process to remove debris, and selectively removing the metal layer from the dielectric layer.

[0009] In a particular embodiment, a method is provided for forming a microvia structure in a semiconductor device. The method includes: laminating a dielectric layer over a conductive layer of the semiconductor device; depositing a chromium layer over the dielectric layer; and applying, patterning, and developing a resist over the chromium layer to form a trench in the layer of resist corresponding to a desired lateral dimension of the microvia structure. The method further includes selectively etching the chromium layer through the trench in the developed layer of resist to extend a trench in the chromium layer and expose a portion of the dielectric layer; and laser ablating the exposed portion of the dielectric layer to form a microvia structure having a desired lateral dimension, the conductive layer of the semiconductor device being utilized as a laser stop. The method further includes removing the resist from the chromium layer, exposing the microvia structure to a cleaning process to remove debris, and selectively removing the chromium layer from the dielectric layer using a wet etching process. The cleaning process includes a fluorine-based dry plasma etch and a methanol-based wet clean.

[0010]

[0008] In order that the above-mentioned features of the present disclosure may be understood in detail, a more detailed description of the present disclosure briefly summarized above will be obtained by referring to the embodiments. Some embodiments are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings show only typical embodiments of the present disclosure, and therefore should not be considered as limiting the scope of the present disclosure, which may admit of other equally effective embodiments. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a flow diagram of a process for forming microvias in a semiconductor device according to embodiments described herein. [Figure 2A] 2A-2C are schematic cross-sectional views of a portion of a semiconductor device at different stages of the process shown in FIG. 1 according to embodiments described herein. [Figure 2B]2A-2D show schematic cross-sectional views of a portion of a semiconductor device at different stages of the process shown in FIG. 1 according to embodiments described herein. [Figure 2C] 2A-2D show schematic cross-sectional views of a portion of a semiconductor device at different stages of the process shown in FIG. 1 according to embodiments described herein. [Figure 2D] 2A-2D show schematic cross-sectional views of a portion of a semiconductor device at different stages of the process shown in FIG. 1 according to embodiments described herein. [Figure 2E] 2A-2D show schematic cross-sectional views of a portion of a semiconductor device at different stages of the process shown in FIG. 1 according to embodiments described herein. [Figure 2F] 2A-2D show schematic cross-sectional views of a portion of a semiconductor device at different stages of the process shown in FIG. 1 according to embodiments described herein. [Figure 2G] 2A-2D show schematic cross-sectional views of a portion of a semiconductor device at different stages of the process shown in FIG. 1 according to embodiments described herein. [Figure 2H] 2A-2D show schematic cross-sectional views of a portion of a semiconductor device at different stages of the process shown in FIG. 1 according to embodiments described herein. [Figure 2I] 2A-2D show schematic cross-sectional views of a portion of a semiconductor device at different stages of the process shown in FIG. 1 according to embodiments described herein. [Figure 2J] 2A-2D show schematic cross-sectional views of a portion of a semiconductor device at different stages of the process shown in FIG. 1 according to embodiments described herein. [Figure 3A-3B] 2A-2C are schematic cross-sectional views of micro-vias formed by the process shown in FIG. 1 according to embodiments described herein; [Figure 4] 2A and 2B illustrate schematic cross-sectional views of an exemplary semiconductor device including microvias formed by the process illustrated in FIG. 1 according to embodiments described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012]

[0013]

[0003] The embodiments of the present disclosure relate to micro-via structures and methods of forming the same for advanced wafer-level semiconductor packaging. The ongoing demand for denser and smaller package structures is driving the need for correspondingly smaller interconnects (e.g., vias). However, as circuit density increases and via dimensions decrease, via formation methods become increasingly challenging, primarily due to limitations associated with the quality and uniformity of laser drilling of narrow via structures. This can result in poor quality and non-uniform vias, which can lead to reduced performance. The methods described herein provide improved methods of forming high quality and uniform micro-via structures.

[0013]

[0014] Figure 1 illustrates a flow diagram of an exemplary method 100 for forming microvias in a semiconductor device, such as a redistribution layer (RDL) of a semiconductor package, in accordance with certain embodiments of the present disclosure. Figures 2A-2J illustrate schematic cross-sectional views of a portion of a semiconductor device 200 at different stages of the method 100 depicted in Figure 1. For clarity, therefore, Figures 1 and 2A-2J are described herein together. Although described with respect to forming a single microvia, it should be noted that the methods disclosed herein may be utilized to simultaneously or sequentially form multiple microvias or arrays in a semiconductor device.

[0014]

[0015] Generally, the method 100 begins with operation 102, corresponding to FIG. 2A, where an insulating layer 208 is deposited over the semiconductor device 200. As mentioned above, in FIGS. 2A-2J, only a portion of the semiconductor device 200 is shown, and the insulating layer 208 may be utilized to form an RDL thereon. The semiconductor device 200 may be any suitable type of semiconductor device, including, but not limited to, a 3D semiconductor package (e.g., a 3D wafer level package (WLP), a 3D system in package (SiP), a stacked integrated circuit (SIC), a 3D package on package (POP), etc.), a 2.5D interposer, a 2D semiconductor package, etc. Thus, the semiconductor device 200 may include one or more embedded active and / or passive devices (e.g., a semiconductor die, a memory die, a capacitor, an inductor, an RF device, etc.) (not shown) and one or more conductive interconnects (not shown) wired therebetween.

[0015]

[0016] 2A, the semiconductor device 200 includes a substrate 202, which may serve as a frame or core structure for the semiconductor device 200. Generally, the substrate 202 may be made of any suitable substrate material, including, but not limited to, III-V compound semiconductor materials, silicon (e.g., having a resistivity of about 1 to about 10 Ω·cm or a conductivity of about 100 W / mK), crystalline silicon (e.g., Si <100> or Si <111> ), silicon oxide (SiO2), silicon germanium (SiGe), doped or undoped silicon, undoped high resistivity silicon (e.g., float zone silicon with low dissolved oxygen content and resistivity of about 5000 to about 10000 Ω·cm), doped or undoped polysilicon, silicon nitride (Si3N4), silicon carbide (SiC) (e.g., with conductivity of about 500 W / mK), quartz, glass (e.g., borosilicate glass), sapphire or aluminum oxide (Al2O3), and / or ceramic materials. In certain embodiments, substrate 202 is a monocrystalline p-type or n-type silicon substrate. In certain embodiments, substrate 202 is a polycrystalline p-type or n-type silicon substrate. In certain embodiments, substrate 202 is a p-type or n-type silicon solar substrate.

[0016]

[0017] Substrate 202 may further have any suitable shape and / or dimensions. For example, substrate 202 may have a polygonal or circular shape. In certain embodiments, substrate 202 comprises a substantially square silicon substrate having lateral dimensions of about 120 mm to about 220 mm, e.g., about 160 mm or about 156 mm to about 166 mm, with or without chamfered edges. In certain other embodiments, substrate 202 comprises a circular silicon-containing wafer having a diameter of about 100 mm to about 450 mm, e.g., about 150 mm to about 300 mm (e.g., about 200 mm).

[0017]

[0018] Unless otherwise specified, the embodiments and examples described herein are performed on a substrate having a thickness of about 50 μm to about 1500 μm, such as about 90 μm to about 780 μm. For example, substrate 202 has a thickness of about 100 μm to about 300 μm, such as about 110 μm to about 200 μm. In another example, substrate 202 has a thickness of about 60 μm to about 180 μm, such as about 80 μm to about 120 μm.

[0018]

[0019] In certain embodiments, the semiconductor device 202 further includes an insulating layer 204 formed on the substrate 202. Generally, the insulating layer 204 may be formed of dielectric and polymeric materials, such as epoxy resins. For example, the insulating layer 204 may be formed of a ceramic filler-containing epoxy resin, such as an epoxy resin filled (e.g., containing) substantially spherical silica (SiO2) particles. As used herein, the term "spherical" refers to any circular, ellipsoidal, or spheroidal shape. For example, in certain embodiments, the ceramic filler may have an elliptical, oblong elliptical, or other similar circular shape. However, other forms are also contemplated. Other examples of ceramic fillers that may be utilized to form the dielectric film 220 include aluminum nitride (AlN), aluminum oxide (Al2O3), silicon carbide (SiC), silicon nitride (Si3N4), Sr2Ce2Ti5O, and the like. 16Ceramics, zirconium silicate (ZrSiO4), wollastonite (CaSiO3), beryllium oxide (BeO), cerium dioxide (CeO2), boron nitride (BN), calcium copper titanium oxide (CaCu3Ti4O 12 ), magnesium oxide (MgO), titanium dioxide (TiO2), zinc oxide (ZnO), etc.

[0019]

[0020] In some examples, the ceramic filler utilized to form the insulating layer 204 has particles with a size ranging from about 40 nm to about 1.5 μm, such as from about 80 nm to about 1 μm. For example, the ceramic filler utilized to form the insulating layer 204 has particles with a size ranging from about 200 nm to about 800 nm, such as from about 300 nm to about 600 nm. In certain embodiments, the ceramic filler includes particles with a size that is less than about 25% of the width or diameter of the desired patterned structures in the substrate 202, including vias for interconnects and cavities for active and / or passive devices. In certain embodiments, the ceramic filler includes particles with a size that is less than about 15% of the width or diameter of the desired patterned structures.

[0020]

[0021] In yet another embodiment, the insulating layer 204 is formed of a polyimide material, such as a photosensitive or non-photosensitive polyimide material, a polybenzoxazole (PBO) material, a silicon dioxide material, and / or a silicon nitride material.

[0021]

[0022] As further shown in FIG. 2A, the semiconductor device 202 includes a conductive layer 206 formed on the insulating layer 204. The conductive layer 206 may represent a trace layer, a wiring layer, a pad layer, or any other type of lateral interconnect structure for electrically coupling one or more active and / or passive devices. In a particular embodiment, the conductive layer 206 has a thickness between about 2 μm and about 20 μm, such as between about 3 μm and about 18 μm, such as between about 6 μm and about 18 μm. The conductive layer 206 is generally formed from one or more layers of any suitable conductive material, including, but not limited to, copper (Cu), aluminum (Al), gold (Au), nickel (Ni), silver (Ag), palladium (Pd), tin (Sn), and the like. In certain embodiments, an adhesion layer (not shown) and / or a seed layer (not shown) are formed between the surfaces of the insulating layer 204 and the conductive layer 206 to improve adhesion and inhibit diffusion of the conductive material of the conductive layer 206. For example, in certain embodiments, a molybdenum (Mo), titanium (Ti), tantalum (Ta), or titanium-tungsten (WTi) adhesion layer and / or a copper seed layer are formed between the insulating layer 204 and the conductive layer 206.

[0022]

[0023] Returning now to FIG. 1 and method 100, in operation 102, insulating layer 208 is deposited over semiconductor device 200. In certain embodiments, insulating layer 208 is substantially similar to insulating layer 204. For example, in certain embodiments, insulating layer 208 is formed of a dielectric material, such as a ceramic-filled epoxy resin, a polyimide material, a PBO material, a silicon dioxide material, and / or a silicon nitride material. However, in certain other embodiments, insulating layer 208 is formed of a different material than insulating layer 204. Generally, insulating layer 208 has a thickness between about 2 μm and about 20 μm, such as between about 4 μm and about 18 μm, such as between about 6 μm and about 14 μm.

[0023]

[0024] During lamination, the insulating layer 208 (e.g., as a film) is placed over the semiconductor device 200 and then exposed to high temperatures such that the insulating layer 208 softens and adheres to, for example, the conductive layer 206 of the semiconductor device 200. In certain embodiments, the lamination operation includes a vacuum lamination process, which may be performed in a laminator or other suitable device. In certain embodiments, the lamination operation is performed using a hot press process.

[0024]

[0025] In certain embodiments, the lamination operation is performed at a temperature between about 80° C. and about 200° C. for a period between about 5 seconds and about 90 seconds, such as between about 30 seconds and about 60 seconds. In certain embodiments, the lamination operation includes applying a pressure between about 1 psig and about 50 psig while exposing the semiconductor device 200 having the insulating layer 208 disposed thereon to a temperature between about 80° C. and about 140° C. for a period between about 5 seconds and about 90 seconds. For example, the lamination operation is performed at a pressure between about 5 psig and about 40 psig and a temperature between about 100° C. and about 120° C. for a period between about 10 seconds and about 1 minute. In some embodiments, the lamination operation is performed at a temperature of about 110° C. for a period of about 20 seconds.

[0025]

[0026] Once the insulating layer 208 is deposited on the semiconductor device 200, in operation 104 corresponding to FIG. 2B, a metal mask layer 210 is deposited on the insulating layer 208. The metal mask layer 210 may be formed of one or more suitable metals, including, but not limited to, chromium (Cr), tungsten (W), molybdenum, copper, and the like. In certain embodiments, the metal mask layer 210 is formed of a refractory metal. Generally, the metal mask layer 210 has a thickness between about 50 nm and about 500 nm, such as between about 100 nm and about 400 nm, such as between about 100 nm and about 300 nm. For example, in certain embodiments, the metal mask layer 210 has a thickness of about 200 nm. The metal mask layer 210 may be deposited on the insulating layer 208 by any suitable deposition technique, including, but not limited to, a sputtering deposition process (i.e., sputtering by PVD deposition process).

[0026]

[0027] In operation 106 and FIG. 2C, a spin-on / spray-on or dry film resist layer 212, such as photoresist, is applied, laminated, and patterned over the metal mask layer 210. In certain embodiments, the resist layer 212 is patterned by selective exposure to UV radiation to form one or more patterned regions 213. For example, in certain embodiments, the resist layer 212 is selectively exposed to UV radiation using maskless lithography, such as direct-write digital lithography. Upon patterning, in operation 108 and FIG. 2D, the resist layer 212 is developed to form one or more trenches 214 therein. As shown in FIG. 2D, in examples where the resist layer 212 is a negative photoresist, the trenches 212 are formed in areas of the resist layer 212 that were previously left unpatterned in operation 106. In examples where the resist layer 212 is a positive photoresist, the trenches 212 correspond to the patterned regions 213 formed in operation 106. In certain embodiments, the developing process is a wet process that includes exposing the resist layer 212 to a solvent. For example, the developing process may be a wet etching process that utilizes an aqueous etching process. In other examples, the film developing process may be a wet etching process that utilizes a buffered etching process that is selective to the desired material. However, any suitable wet solvent or combination of wet etchants may be used in the resist film developing process.

[0027]

[0028] As shown in FIGS. 2C-2D, the resist layer 212 is patterned and developed according to the desired shape and lateral dimensions of the microvias to be subsequently formed. Generally, the microvias have a cylindrical or circular tubular shape corresponding to the shape of the interconnects to be routed therethrough. Thus, in certain embodiments, the resist layer 212 is patterned and developed to form cylindrical trenches 214 therein to enable downstream transfer of the cylindrical pattern to the metal mask layer 210 and the insulating layer 208. However, in further embodiments, non-cylindrical or non-annular interconnects and / or vias are desired, and thus non-cylindrical trenches 214 are formed. For example, in certain embodiments, the shape of the trenches 214 formed in the resist layer 212 in operation 108 may be oval, elliptical, or polygonal.

[0028]

[0029] In operation 110 and Figure 2E, the semiconductor device 200 with the patterned and developed resist layer 212 formed thereon is exposed to an etching process to transfer the pattern of the resist layer 212 to the metal mask layer 210. Thus, trenches 214 extend into the metal mask layer 210, thus exposing the underlying insulating layer 208. As shown in Figure 2E, a portion of the resist layer 212 may also be consumed during the process.

[0029]

[0030] In certain embodiments, the etching process is a plasma-based dry etching process performed in an inductively coupled plasma (ICP) dry etching chamber. For example, in embodiments where the metal mask layer 210 is a chromium mask layer, the semiconductor device 200 may be subjected to a dry chromium selective etching process. In such embodiments, the dry etching process may utilize oxygen (O2), ammonia (NH3), nitrogen (N2), helium (He), chlorine (Cl2), and / or argon (Ar) reactive gases. For example, in certain embodiments, a reactive gas mixture of 90:5:20 Cl2:O2:Ar is utilized. The chromium selective etching process may further utilize a plasma generating power of about 200 watts (W) to about 2000 W, e.g., about 600 W, and a bias power of about 100 W to about 400 W, e.g., about 220 W, and may be performed at a pressure between about 2 millitorr (mTorr) to about 100 mTorr, e.g., about 10 mT.

[0030]

[0031] After etching the metal mask layer 210, in operation 112 and FIG. 2F, the semiconductor device 200 is exposed to a laser ablation process to ablate the portions of the insulating layer 208 exposed through the metal mask layer 210, thus forming microvias 216 therein. The laser ablation process may be performed utilizing any suitable type of laser system with adjustable laser process parameters and characteristics, including, but not limited to, laser power supply, focal beam diameter, focal height, pulse energy, pulse width, burst energy, number of pulses per burst train (e.g., a sequence of pulses separated by a desired duration), pulse frequency, burst frequency, beam spot size, and spatial beam profile (Gaussian or top hat), etc. In general, because the metal mask layer 210 protects the portions of the insulating layer 208 disposed thereunder, in operation 112 the laser system may generate a laser beam having a spot size larger than the lithographically defined holes in the metal mask layer 210.

[0031]

[0032] In certain embodiments, the laser ablation process in operation 112 is performed utilizing an ultraviolet (UV) laser, such as a femtosecond (fs) UV laser with Innoslab laser source, emitting a laser beam having a wavelength of about 180 nm to about 400 nm, e.g., about 300 nm to about 360 nm, e.g., about 345 nm or about 355 nm. In such embodiments, the UV laser can ablate the insulating layer 208 by generating a pulsed laser beam, which can be emitted at one or more fixed frequencies (e.g., 50 MHz or higher), pulse burst trains with pulse energies of about 5 nJ to about 10 nJ. Because metals such as copper are not resistant to UV laser beams, utilizing a pulse burst mode with precise energy doses between about 5-10 nJ can reduce debris formation and facilitate ablation of the insulating layer 208 with little or no damage to the underlying conductive layer 206, as compared to a continuous or continuous pulsed UV laser beam. Thus, the conductive layer 206 can act as a laser stop during the laser ablation process in operation 112. Furthermore, the UV laser conditions described above, in combination with the pre-patterned metal mask layer 210, allow for very precise via shape control, including top / bottom opening size, opening morphology, and taper between the top / bottom openings.

[0032]

[0033] In certain embodiments, the laser ablation process in operation 112 is performed utilizing a laser source operating at an infrared (IR) wavelength between about 700 nm and about 1 mm, such as a near infrared (NIR) wavelength between about 700 nm and about 2.5 μm, or a mid-infrared (mid-IR) wavelength between about 2.5 μm and about 24 μm. For example, in certain embodiments, the laser ablation process in operation 112 is performed using a laser source having a NIR to mid-IR wavelength between about 2 μm and about 3 μm. The 2-3 μm wavelength is highly selective for polymeric materials relative to metallic materials, thus allowing for a larger alignment tolerance between the emitted laser beam and the pre-patterned trenches 214 of the metal mask layer 210, since the metal mask layer 210 simply reflects the misaligned portions of the laser beam. Furthermore, due to the increased ablation efficiency of the 2-3 μm wavelength of polymeric materials, such as the insulating layer 208, and the relatively low ablation efficiency of metals, little or no damage occurs to the underlying conductive layer 206 during operation 112. In certain embodiments, the NIR or mid-IR laser is a fiber laser that creates a laser beam through one or more cascaded processes in an optical fiber. For example, in certain embodiments, the fiber laser can inject a nanosecond (ns) or picosecond (ps) seed laser beam, for example at a wavelength of about 1 μm, into a series of passive or active fibers for extended transmission in the desired IR wavelength range for nonlinear frequency conversion. In certain other embodiments, the fiber laser can pump a short-pulse, high-intensity seed laser beam, such as a fs seed laser beam, into a highly nonlinear optical medium with normal dispersion, such as a chalcogenide glass fiber. In still other embodiments, the fiber laser can utilize an erbium-doped or fluoride fiber, or other doped mid-IR fiber, emitting at a wavelength of about 3 μm.

[0033]

[0034] In embodiments where multiple microvias 216 or an array are required, the laser system may include a scanner 220, such as a single-axis or multi-axis large angle galvanometer optical scanner (e.g., a galvo scanner), to facilitate scanning one or more laser beams from a laser source across the surface of the semiconductor device 200 to form the multiple microvias 216 or array. The term "galvanometer scanner" generally refers to any type of device that can change the projection or reflection angle of one or more laser beams to sweep the one or more laser beams across the semiconductor device 200. For example, the scanner 220 may include one or more adjustable, electromechanically controlled mirrors to diverge (e.g., multiply) and / or direct the laser beam across the semiconductor device 200 during the laser ablation process in operation 112. In certain embodiments, the scanner 220 may be used to drill a single microvia 216 in the semiconductor device 200 at a time, to drill multiple microvias 216 simultaneously, or to scan a laser beam across the surface of the semiconductor device 200 to form multiple microvias 216 with some sweeping.

[0034]

[0035] In operation 114 and FIG. 2G, a resist removal process is performed to remove the resist layer 212 from the semiconductor device 200. Operation 114 may be performed before or after the laser ablation process in operation 112. In certain embodiments, the resist layer 212 is removed by one or more dry processes, such as dry etching or ashing. In certain embodiments, the resist removal process includes exposing the semiconductor device 200 to a microwave O2 plasma while maintaining the semiconductor device 200 at a temperature between about 60° C. and about 100° C., such as about 80° C., which allows the resist layer 212 to be removed without damaging the conductive layer 206 exposed through the microvias 216. Temperature is an important factor in operation 114, since using too low a temperature can significantly reduce the resist strip rate, while using too high a temperature can damage the underlying conductive layer 206.

[0035]

[0036] After resist stripping, the semiconductor device 200 is exposed to a cleaning process in operation 116 and FIG. 2H to remove unwanted debris remaining in the microvia 216 from the previous laser ablation process and to smooth the surfaces (e.g., walls) of the microvia 216 exposed to the laser drilling. The cleaning process may include any combination of dry and / or wet processes. In certain embodiments, the semiconductor device 200 is exposed to a dry etching process, such as a plasma-based dry etching process. In such embodiments, the plasma-based dry etching process may utilize O2, CF4, NH3, N2, Cl2, and / or Ar reactive gases. For example, in certain embodiments, the plasma-based dry etching process utilizes a reactive gas mixture of 50:3:5 O2:CF4:Ar, a plasma generating power of about 200 watts (W) to about 2000 W, e.g., 500 W, and a bias power of about 25 watts (W) to about 100 W, e.g., about 50 W. In further embodiments, the semiconductor device 200 is exposed to a wet process that may be used in combination with one or more dry processes. For example, in a particular embodiment, the semiconductor device 200 is exposed to a 3:1 solution of cupric chloride (CuCl2) in 5% methanol in water, which may be used in combination with a plasma-based dry etching process, such as a plasma-based dry etching process utilizing reactive fluorine gas.

[0036]

[0037] In operation 118 and FIG. 2I, the cleaned semiconductor device 200 is selectively etched to remove the metal mask layer 210. Thus, unlike some conventional methods, the metal mask layer 210 does not remain on the semiconductor device 200 during downstream interconnect formation, allowing a seed layer and / or barrier layer to be deposited directly on the insulating layer 208 prior to interconnect formation. In certain embodiments, the etching process in operation 118 is a wet etching process utilizing any suitable wet etchant or combination of wet etchants in an aqueous solution. For example, for an embodiment in which the metal mask layer 210 includes chromium, the semiconductor device 200 may be immersed in an aqueous etching solution including 50% NaOH and 33% K3[FE(CN)6] (1:3) at about room temperature (27° C.) for about 2 to about 10 minutes, such as about 3 to about 5 minutes.

[0037]

[0038] Selective etching of the metal mask layer 210 may result in the formation of an interconnect 222 within the microvia 216, as shown in FIG. 2J. The interconnect 222 may be formed on the sidewall of the microvia 216, defined by the insulating layer 208, and extending through the microvia 216 to the underlying conductive layer 206. The interconnect 222 may be deposited within the microvia 216 by any suitable method, including electroless deposition, or a combination of physical vapor deposition (PVD) and electrochemical deposition (ECD). In certain embodiments, the interconnect 222 is deposited to fill or "plug" the microvia 216, thus creating a solid or filled conductor therein. However, in certain other embodiments, the interconnect 222 is deposited only on the line surface of the microvia 216.

[0038]

[0039] The interconnects 222 may generally be formed from one or more layers of any suitable conductive material, including, but not limited to, copper (Cu), aluminum (Al), gold (Au), nickel (Ni), silver (Ag), palladium (Pd), tin (Sn), etc. In certain embodiments, as described above, an adhesion layer (not shown) and / or a seed layer (not shown) may be formed on the surfaces of the microvias 216 prior to deposition of the interconnects 222. For example, in certain embodiments, a molybdenum, titanium, tantalum, or titanium tungsten adhesion layer and / or a copper seed layer is deposited on the sidewalls of the microvias 216 prior to deposition of the interconnects 222 to improve adhesion and inhibit diffusion of the conductive material.

[0039]

[0040] 3A and 3B generally illustrate cross-sectional views of exemplary microvia structures that may be formed in a semiconductor device 200 according to certain embodiments, such as by the method 100 described above. It should be noted that only a portion of the semiconductor device 200 is shown in FIGS. 3A-3B.

[0040]

[0041] As shown in FIG. 3A, the microvia 316a is an example of a microvia formed in a redistribution layer of the semiconductor device 200, which may be a semiconductor package. Thus, the microvia 316a is shown disposed through an insulating layer 208 above the substrate 202, which further includes an insulating layer 204 and a conductive layer 206 formed thereon. Generally, the microvia 316a is formed through the entire thickness of the insulating layer 208, and thus the conductive layer 206 may be used as a laser stop during laser ablation of the microvia 316a. In certain embodiments, the microvia 316a has a height between about 2 μm and about 20 μm, which may be comparable to the thickness of the insulating layer 208. In certain embodiments, the microvia 316a may have substantially vertical sidewalls and thus a uniform diameter between about 2 μm and about 10 μm, such as between about 3 μm and about 7 μm. In certain embodiments, the ratio of the diameter of the microvia 316a to the thickness of the insulating layer 208 is between about 1:2 and about 1:1.

[0041]

[0042] In certain other embodiments, the microvia has tapered or angled sidewalls, as shown in FIG. 3A. For example, the sidewalls of the microvia 316 may have a taper angle α of about 60° to about 90°, such as about 80° to about 90°. In such embodiments, the top diameter DT of the microvia 316a is between about 2 μm to about 15 μm, such as between about 4 μm to about 12 μm, and the bottom diameter DB of the microvia 316a is between about 1 μm to about 8.5 μm, such as between about 2 μm to about 6 μm. The formation of a tapered or conical morphology may be accomplished, for example, by moving a laser beam of a laser system utilized in operation 112 in a helical (e.g., circular, corkscrew) motion relative to a central axis of the microvia 316a. The laser beam may also be angled using the motion system to form a tapered microvia 316a.

[0042]

[0043] 3B, the microvia 316b is an example of a microvia formed through the substrate 202 of the semiconductor device 200, for example extending from the first surface 303a to the second surface 303b of the substrate 202. In such an embodiment, the microvia 316b is laser ablated through the insulating layer 204 of the semiconductor device 200, which encapsulates (e.g., surrounds) the substrate 202 and passes through the through silicon via 314 formed in the substrate 202. Thus, to form the microvia 316b, prior to the method 100 described above, the through silicon via 314 must first be formed through the substrate 202 by any suitable substrate patterning method or methods, and then in operation 100, the insulating layer 204 is deposited on the substrate 202, adhering to the substrate 202 and flowing into the through silicon via 314.

[0043] In certain embodiments, the through silicon vias 314 are formed by laser ablation, for example using an IR, UV, or CO2 laser. For example, the laser utilized to ablate the through silicon vias 314 can be a ps or fsUV laser. In certain embodiments, the laser is a fs green laser. In yet other embodiments, the through silicon vias 314 are formed by a suitable etching process, for example, a dry etching process or a bead blasting process. Generally, the through silicon vias 314 can have a cylindrical or tapered morphology, as shown in FIG. 3B. Similar to the microvias 316a, the formation of tapered or conical morphology can be achieved, for example, by moving the laser beam of the laser utilized during substrate patterning in a helical (e.g., circular, corkscrew) motion relative to the central axis of the through silicon vias 314. The laser beam can also be angled using a motion system. A similar method can also be utilized to form cylindrical through silicon vias 314 with a uniform diameter.

[0044]

[0044] During the formation of the through silicon vias 314, the insulating layer 204 may be disposed over the substrate 202 and laminated, for example, in operation 102 of the method 100, thus flowing and filling the through silicon vias 314. In certain embodiments, the lamination process is a vacuum lamination process that may be performed in an autoclave or other suitable device. In certain embodiments, the lamination process is performed using a hot press process. In certain embodiments, the lamination process is performed at a temperature between about 80°C and about 140°C for a period of time between about 5 seconds and about 1.5 minutes. In such embodiments, the lamination process may be performed at a pressure between about 1 psig and about 50 psig. For example, the lamination process may be performed at a pressure between about 5 psig and about 40 psig and a temperature between about 100°C and about 120°C for a period of time between about 10 seconds and about 1 minute.

[0045] After lamination, as shown in Figure 3B, method 100 is used to form microvia 316b in a portion of insulating layer 204 that extends through through-silicon via 314. Generally, microvia 316b may have a similar lateral shape and / or dimensions as microvia 316a, such as a tapered or conical configuration.

[0046] 4 shows a schematic cross-sectional side view of an exemplary semiconductor package 400 having microvias formed by the method 100 described above, according to certain embodiments. As shown, the semiconductor package 400 includes a substrate 402, e.g., a silicon substrate, that serves as a package frame and has one or more cavities 408 and one or more through-silicon vias 414 formed therein. An insulating layer 404 is laminated on the substrate 402 and extends through the cavities 408 and through-silicon vias 414 from a first side 403a to a second side 403b of the substrate 402. One or more semiconductor dies 406 are disposed in each cavity 408 and embedded within the insulating layer 404 therein. Similarly, one or more interconnects 412 are disposed in each through-silicon via 414 and surrounded by the insulating layer 404 therein. On either side of the semiconductor package 400 is a redistribution layer 420 that is comprised of one or more redistribution interconnects 422 in electrical communication with the one or more interconnects 412. The redistribution interconnects 422 can include vertical and lateral interconnects such as traces, wires, and pads.

[0047] During the formation of the semiconductor package 400, the deposition of the insulating layer 404 causes its dielectric material to flow into and fill the through silicon vias 414. Thus, after the deposition of the insulating layer 404, vias 416a can be laser drilled in the dielectric material of the insulating layer 404 in the through silicon vias 414 to form channels or pathways for the interconnects 412 across the substrate 402, thus forming a via-in-via structure for the wiring of the interconnects 412. Similarly, after the formation of the interconnects 412, redistribution interconnects 422 can be formed on either side of the semiconductor package 400 in the redistribution vias 416b, which can also be laser drilled in the insulating layer 404. Thus, the vias 416a and redistribution vias 416b formed in the insulating layer 404 can be microvias formed by the methods described above with reference to FIGS. 1 and 2A-2J above.

[0048] In summary, the methods and microvia structures described above provide numerous advantages over methods and architectures implementing conventional via fabrication techniques for semiconductor devices, including the ability to form high quality, low aspect ratio microvia structures, which advantageously enable high density packaging architectures for advanced integrated semiconductor devices with improved performance, flexibility, and relatively low manufacturing costs compared to conventional packaging techniques.

[0049]

[0049] While the above description is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope of the disclosure, the scope of which is determined by the following claims.

Claims

1. A method for forming a microvia structure in a semiconductor device having a substrate, an insulating layer disposed on the substrate, and a conductive layer disposed on the insulating layer, comprising: depositing a dielectric layer over the conductive layer of the semiconductor device; depositing a metal mask layer over the dielectric layer; applying, patterning, and developing a resist over the metal mask layer, where developing the layer of resist forms a trench in the layer of resist corresponding to a desired lateral dimension of the microvia structure; etching the metal mask layer through the trenches in the developed layer of resist, where etching the metal mask layer extends the trenches in the metal mask layer and exposes a portion of the dielectric layer; laser ablating the exposed portions of the dielectric layer using an ultraviolet (UV) laser in a pulse burst mode providing pulses with a frequency of 50 MHz or greater and an energy of 5 nJ to 10 nJ; Including, The method of claim 1, wherein laser ablation of the exposed portions of the dielectric layer forms the microvia structure having the desired lateral dimensions and exposes the conductive layer.

2. The method of claim 1 , wherein the dielectric layer comprises an epoxy resin material having a ceramic filler.

3. The method of claim 1 , wherein the metal mask layer comprises chromium (Cr), tungsten (W), molybdenum, or copper.

4. The method of claim 3 , wherein the metal mask layer comprises chromium (Cr).

5. The method of claim 3 , wherein the metal mask layer is deposited over the dielectric layer by physical vapor deposition (PVD).

6. The method of claim 1 , wherein the resist is a photoresist and is patterned via selective exposure to UV radiation.

7. The method of claim 1 , wherein the resist is patterned using direct-write digital lithography.

8. The method of claim 1 , wherein the metal mask layer is dry etched using an oxygen-based plasma.

9. The method of claim 1 , wherein the dielectric layer is laser ablated using a near-infrared (NIR) or mid-infrared (mid-IR) laser.

10. A method for forming a microvia structure in a semiconductor device having a substrate, an insulating layer disposed on the substrate, and a conductive layer disposed on the insulating layer, comprising: depositing a dielectric layer over the conductive layer of the semiconductor device; depositing a metal mask layer over the dielectric layer; applying, patterning, and developing a resist over the metal mask layer, where developing the layer of resist forms a trench in the layer of resist corresponding to a desired lateral dimension of the microvia structure; selectively etching the metal mask layer through the trenches in the developed layer of resist, where selectively etching the metal mask layer extends the trenches in the metal mask layer and exposes a portion of the dielectric layer; laser ablating the exposed portions of the dielectric layer using an ultraviolet (UV) laser in a pulse burst mode providing pulses with a frequency of 50 MHz or greater and an energy of 5 nJ to 10 nJ, where laser ablating the exposed portions of the dielectric layer forms the microvia structure having the desired lateral dimensions and exposes the conductive layer; exposing the microvia structure to a cleaning process to remove debris; selectively removing the metal mask layer from the dielectric layer; A method comprising:

11. The method of claim 10 , wherein the metal mask layer comprises chromium (Cr).

12. The method of claim 10 , wherein the metal mask layer is deposited over the dielectric layer by physical vapor deposition (PVD).

13. The method of claim 10, wherein the resist is patterned using direct-write digital lithography.

14. The method of claim 10 , wherein the metal mask layer is selectively dry etched using an oxygen-based plasma.

15. The method of claim 10, wherein the dielectric layer is laser ablated using a near-infrared (NIR) or mid-infrared (mid-IR) laser.

16. The method of claim 10 , wherein the microvia structure has a lateral dimension between about 2 μm and about 10 μm.

17. The method of claim 10 , wherein the microvia structure has a first lateral dimension between about 2 μm and about 15 μm and a second lateral dimension between about 1 μm and about 8.5 μm.

18. A method for forming a microvia structure in a semiconductor device having a substrate, an insulating layer disposed on the substrate, and a conductive layer disposed on the insulating layer, comprising: depositing a dielectric layer over a conductive layer of the semiconductor device; depositing a chromium mask layer over the dielectric layer; applying, patterning, and developing a resist over the chrome mask layer, where developing the layer of resist forms a trench in the layer of resist corresponding to a desired lateral dimension of the microvia structure; selectively etching the chrome mask layer through the trenches in the developed layer of resist, where selectively etching the chrome mask layer extends the trenches in the chrome mask layer and exposes a portion of the dielectric layer; laser ablating the exposed portions of the dielectric layer using an ultraviolet (UV) laser in a pulse burst mode providing pulses with a frequency of 50 MHz or greater and an energy of 5 nJ to 10 nJ, where laser ablating the exposed portions of the dielectric layer forms the microvia structure having the desired lateral dimensions and exposes the conductive layer, where the conductive layer of the semiconductor device is utilized as a laser stop; removing the resist from the chrome mask layer; exposing the microvia structure to a cleaning process to remove debris, the cleaning process including a fluorine-based dry plasma etch and a methanol-based wet clean; selectively removing the chromium mask layer from the dielectric layer using a wet etching process; A method comprising:

Images