Multilayer printed circuit board and method for adjusting impedance of interlayer lines

Abstract

To provide a technique to suppress signal degradation based on impedance mismatch caused by interlayer lines without sacrificing high-density mounting.SOLUTION: It has interlayer patterns 4. A plurality of pattern layers P1 to P8 is alternately stacked with a plurality of dielectric layers D1 to D7. Interstitial via holes 3 form interlayer lines that conduct the strip lines formed in each of the two different pattern layers. Gnd vias 4 are provided in parallel along the interlayer lines. Pattern layers P2 and P7, which are adjacent to pattern layers P3 and P6 across the dielectric layers D2 and D6, where the end patterns 31 of the interlayer lines are formed, have a non-patterned area 5 where the formation of conductor patterns is prohibited at the position opposite the end patterns 31.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a technique for adjusting the impedance of an interlayer line in a multilayer printed circuit board. [Background technology]

[0002] Electronic control units (hereinafter referred to as on-board ECUs) installed in vehicles are constructed using multi-layer printed circuit boards. As on-board ECUs become more sophisticated, multi-layer printed circuit boards are becoming more and more multi-layered, requiring not only higher density wiring but also high-speed signal transmission exceeding several GHz.

[0003] Furthermore, since vehicle-mounted ECUs have strict requirements regarding radiated emissions, it is desirable to use inner layer wiring for the wiring. In the case of a build-up board, which is a type of multilayer printed circuit board, wiring between layers is performed using laser via holes (hereinafter referred to as LVHs) and interstitial via holes (hereinafter referred to as IVHs). LVHs and IVHs have lower impedance than the striplines that form the wiring patterns of each layer. In particular, IVHs have a large impedance difference with striplines, so there is concern that signal quality may deteriorate due to impedance mismatch.

[0004] Patent Document 1 proposes a method of adjusting the impedance on the stripline side by interposing multiple dielectric layers between the signal line pattern and ground pattern that form the stripline and ensuring a distance between the two. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2002-57467 A Summary of the Invention [Problem to be solved by the invention]

[0006] When considering applying the conventional technology described in Patent Document 1 to an IVH, it is conceivable to form a ground via (hereinafter, GND via) parallel to the IVH along the wiring direction of the IVH, as in multilayer printed circuit boards 100 and 101 shown in Fig. 3, and adjust the impedance of the interlayer line formed by the IVH by adjusting the distance to the GND via. In this case, the greater the distance between the IVH and the GND via, that is, the higher the impedance of the interlayer line can be in multilayer printed circuit board 101 shown in the lower part of Fig. 3 than in multilayer printed circuit board 100 shown in the upper part.

[0007] However, the area between the IVH and the GND via is a non-wiring area A where no other patterns can be formed, which causes a problem of reduced packaging density. One aspect of the present disclosure provides a technique for suppressing signal degradation due to impedance mismatch occurring in interlayer lines, without sacrificing high-density packaging. [Means for solving the problem]

[0008] One aspect of the present disclosure is a multilayer printed circuit board comprising a plurality of dielectric layers (D1-D7), a plurality of pattern layers (P1-P8), an interstitial via hole (3), and an interlayer pattern (4). The plurality of pattern layers are alternately laminated with the plurality of dielectric layers. The interstitial via hole forms an interlayer line that conducts strip lines formed in two different pattern layers. The interlayer pattern is provided in parallel along the interlayer line. A pattern layer adjacent to the pattern layer (P3, P6) on which the end pattern (31) of the interlayer line is formed, with a dielectric layer (D2, D6) sandwiched between them, is defined as a target pattern layer (P2, P7). A non-pattern area (5) in which the formation of a conductor pattern is prohibited is provided at a position facing the end pattern in the target pattern layer.

[0009] According to this configuration, the coupling between the interlayer line and the ground can be weakened by providing the non-patterned area, so that the impedance of the interlayer line can be increased without increasing the distance between the interlayer line and the interlayer pattern. As a result, the deterioration of signal quality due to impedance mismatch occurring in the interlayer line can be suppressed without sacrificing high-density packaging.

[0010] One aspect of the present disclosure is a method for adjusting impedance of an interlayer line in a multilayer printed circuit board. The multilayer printed circuit board includes a plurality of dielectric layers (D1 to D7), a plurality of pattern layers (P1 to P8), an interstitial via hole (3), and an interlayer pattern (4). The plurality of pattern layers are alternately laminated with the plurality of dielectric layers. The interstitial via hole forms an interlayer line that conducts strip lines formed in two different pattern layers. The interlayer pattern is provided in parallel along the interlayer line. A pattern layer adjacent to the pattern layer (P3, P6) on which the end pattern (31) of the interlayer line is formed, with a dielectric layer (D2, D6) sandwiched between them, is defined as a target pattern layer (P2, P7). A non-pattern area (5) in which the formation of a conductor pattern is prohibited is provided at a position facing the end pattern in the target pattern layer, thereby increasing the impedance of the interlayer line.

[0011] According to this method, it is possible to suppress deterioration of signal quality due to impedance mismatch occurring in the interlayer lines without sacrificing high-density packaging. [Brief description of the drawings]

[0012] [Figure 1] 1 is a cross-sectional view showing components of a multilayer printed circuit board. [Diagram 2] FIG. 11 is an explanatory diagram showing the effect of a non-pattern region. [Diagram 3] FIG. 1 is an explanatory diagram illustrating a problem with the conventional technology. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. [1. Configuration] The multilayer printed circuit board 1 shown in FIG. N N+1 pattern layers P1 to P N+1 In the embodiment, the case where N=7 is illustrated.

[0014] A build-up board is a board manufactured by alternately stacking dielectric layers D and pattern layers P on a core printed circuit board. In a build-up board, laser via holes (hereinafter, LVH) 2 and interstitial via holes (hereinafter, IVH) 3 are used for internal wiring between layers. Both the LVH 2 and IVH 3 are formed in parallel with the lamination of the dielectric layers D and pattern layers P.

[0015] The LVH2 is a buried via that penetrates one dielectric layer D and connects two adjacent pattern layers P with the dielectric layer D in between, and is drilled using a laser. In the multilayer printed circuit board 1, the multiple LVH2 are provided so as to penetrate one of the dielectric layers D1, D2, D6, and D7, respectively, and are formed in the dielectric layers D. i Two pattern layers P i ,P i+1 The wiring patterns formed on each of the above are electrically connected to each other.

[0016] The IVH3 is a non-penetrating via that penetrates two or more dielectric layers D to connect between multiple pattern layers P. "Non-penetrating" means that at least one end of the via is not exposed to the outermost pattern layers P1, P8. In the multilayer printed circuit board 1, the IVH3 is provided so as to penetrate D3 to D5 collectively, and provides electrical continuity between at least the wiring patterns formed on each of the pattern layers P3, P6. Furthermore, the IVH3 may be configured to be electrically connected to the wiring patterns formed on the pattern layers P4, P5.

[0017] The multilayer printed circuit board 1 includes a plurality of LVHs 2 and a plurality of IVHs 3, as well as ground vias (hereinafter, GND vias) 4 formed in parallel to the IVHs 3. The GND vias 4 are formed by conducting holes formed so as to penetrate all of the dielectric layers D after lamination of the dielectric layers D and the pattern layers P is completed, and provide mutual conduction between the ground patterns formed on each of the pattern layers P1 to P8. The distance between the IVHs 3 and the GND vias 4 paired with the IVHs 3 is set to be longer than the thickness of one dielectric layer D and shorter than the thickness of two layers, for example.

[0018] At least a wiring pattern using a strip line is formed on the pattern layers P3 and P6. The wiring patterns formed on the pattern layers P3 and P6 are connected to each other via the IVH3.

[0019] The pattern layers P2 and P7 have a ground pattern formed over almost the entire surface except for a non-pattern region 5 where pattern formation is prohibited. The non-pattern region 5 is provided in the pattern layers P2 and P7 at a position facing the end pattern 31 of the IVH 3 with the dielectric layers D2 and D6 interposed therebetween. The non-pattern region 5 has approximately the same size and shape as the end pattern 31 of the IVH 3 provided in the pattern layers P3 and P6. However, the non-pattern region 5 may be larger than the end pattern 31 of the IVH 3, or may have a different shape from the end pattern 31. The non-pattern region 5 may also be formed in a part of the area facing the end pattern 31.

[0020] The pattern layers P1 and P8 are provided with conductor patterns such as a ground pattern and a power supply pattern at least in a portion facing the end pattern 31 of the IVH 3 across the non-patterned region 5. The region between the IVH 3 and the GND via 4 is a no-wiring region A in which pattern formation is prohibited, similar to the non-patterned region 5.

[0021] [2. Response] In this embodiment, the pattern layers P2 and P7 correspond to the target pattern layers, and the GND via 4 corresponds to the interlayer pattern. [3. Effect] Since the multilayer printed circuit board 1 has a non-pattern area 5, as shown in FIG. 2, the coupling capacitance Cx generated between the end pattern 31 of the IVH 3 and a pattern arranged in a position opposite the end pattern 31 (hereinafter, the opposing pattern) is reduced compared to a conventional multilayer printed circuit board 100 which does not have the non-pattern area 5 shown in the upper part of FIG. 3.

[0022] The coupling capacitance Cx is expressed by equation (1), where S is the area of ​​the interlayer line side facing the opposing pattern (i.e., end pattern 31 of IVH 3), d is the distance between the opposing pattern and the interlayer line, and ε is the capacitance of the dielectric layer D.

[0023]

number

[0024] In the multilayer printed circuit board 1, the distance d is approximately twice as large as that in the conventional multilayer printed circuit board 100, and therefore the coupling capacitance Cx between the end pattern 31 and the opposing pattern is approximately half. Furthermore, impedance Zo of the interlayer line formed by the IVH 3 is expressed by equation (2), where L is the inductance of the IVH 3 and C is the coupling capacitance between the IVH 3 and ground. The coupling capacitance C includes the coupling capacitance between the IVH 3 and the GND via 4, in addition to the coupling capacitance Cx between the end pattern 31 and the opposing pattern.

[0025]

number

[0026] That is, by having the non-patterned area 5, the multilayer printed circuit board 1 has a smaller coupling capacitance C between the LVH 3 and ground compared to a conventional multilayer printed circuit board 100 that does not have the non-patterned area 5. As a result, the impedance Zo of the interlayer line formed by the LVH 3 increases.

[0027] [4. Effects] According to the embodiment described above in detail, the following effects are achieved. (1) By having the non-patterned region 5, the multilayer printed circuit board 1 can increase the impedance Zo of the interlayer line without increasing the distance between the interlayer line formed by the IVH 3 and the GND via 4. As a result, the impedance difference between the interlayer line and the wiring pattern (i.e., the strip line) connected to the interlayer line can be reduced, and waveform distortion caused by impedance mismatch between the interlayer line and the wiring pattern can be suppressed.

[0028] Moreover, the non-patterned area 5 only needs to be about the same size as the end pattern 31 of the IVH 3. Therefore, the non-wiring area A can be made smaller than in the conventional multilayer printed circuit board 101 shown in the lower part of Fig. 3, in which the impedance Zo of the interlayer line is adjusted by the distance between the interlayer line and the GND via 4. In other words, the impedance mismatch in the interlayer line can be suppressed without sacrificing high-density packaging.

[0029] (2) In the multilayer printed circuit board 1, the pattern layers P2 and P7 have ground patterns formed over almost the entire surfaces of the areas other than the non-patterned areas 5. This makes it possible to suppress the generation of emission noise due to radiation from the wiring patterns formed on the pattern layers P3 to P6 located inside the pattern layers P2 and P7.

[0030] 5. Other embodiments Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above-described embodiments and can be implemented in various modified forms.

[0031] (a) In the above embodiment, the non-patterned region 5 is formed only in each of the patterned layers P2, P7 adjacent to the patterned layers P3, P6 on which the end pattern 31 of the IVH 3 is formed, but this is not limited to the above. For example, the non-patterned region 5 may be formed in a plurality of patterned layers adjacent to each other with a dielectric layer interposed therebetween, thereby making the distance d between the end pattern 31 of the IVH 3 and the opposing pattern larger.

[0032] (b) In the above embodiment, the GND vias 4 are provided in parallel to the IVHs 3. However, instead of the GND vias 4, signal vias used as interlayer lines separate from the IVHs 3 may be provided.

[0033] (c) Multiple functions possessed by one component in the above embodiments may be realized by multiple components, or one function possessed by one component may be realized by multiple components. Also, multiple functions possessed by multiple components may be realized by one component, or one function realized by multiple components may be realized by one component. Also, part of the configuration of the above embodiments may be omitted. Also, at least part of the configuration of the above embodiments may be added to or substituted for the configuration of another of the above embodiments.

[0034] (3d) In addition to the above-described multilayer printed circuit board 1, the present disclosure can be realized in various forms, such as a system including the multilayer printed circuit board 1 as a component, and a method for adjusting impedance of an interlayer line. [Explanation of symbols]

[0035] 1...multilayer printed circuit board, 2...laser via hole (LVH), 3...interstitial via hole (IVH), 4...GND via, 5...non-patterned area, 31...end pattern, 31...end pattern, D1 to D7...dielectric layers, P1 to P8...pattern layers.

Claims

1. A plurality of dielectric layers (D1 to D7); A plurality of pattern layers (P1 to P8) alternately laminated with the plurality of dielectric layers; an interstitial via hole (3) forming an interlayer line for conducting striplines formed on the two different pattern layers; An interlayer pattern (4) provided in parallel along the interlayer line; Equipped with a pattern layer adjacent to the pattern layer (P3, P6) on the opposite side to the side on which the interlayer line is wired, with the dielectric layer (D2, D6) sandwiched therebetween, as a target pattern layer (P2, P7), and a non-pattern area (5) in which formation of a conductor pattern is prohibited is provided at a position facing the end pattern in the target pattern layer; a plurality of target pattern layers are present on at least one end side of the interlayer line; A conductor pattern is formed in the pattern layer (P1, P8) facing the end pattern via the non-patterned region at a position facing the end pattern. Multilayer printed circuit board.

2. 2. The multilayer printed circuit board according to claim 1, The interlayer pattern is a ground via that electrically connects ground patterns provided on each of the plurality of pattern layers. Multilayer printed circuit board.

3. 3. The multilayer printed circuit board according to claim 1, The area other than the non-pattern area of ​​the target pattern layer is a ground pattern. Multilayer printed circuit board.

4. A multilayer printed circuit board according to any one of claims 1 to 3, The target pattern layer is present at each end of the interlayer line. Multilayer printed circuit board.

5. A multilayer printed circuit board according to any one of claims 1 to 4, The non-patterned area has the same size as the end pattern. Multilayer printed circuit board.

6. A method for adjusting impedance of an interlayer line in a multilayer printed circuit board comprising a plurality of dielectric layers (D1 to D7), a plurality of pattern layers (P1 to P8) laminated alternately with the plurality of dielectric layers, an interstitial via hole (3) forming an interlayer line for conducting strip lines formed in each of two different pattern layers, and an interlayer pattern (4) provided in parallel along the interlayer line, comprising: The pattern layer adjacent to the pattern layer (P3, P6) on which the end pattern (31) of the interlayer line is formed, across the dielectric layer (D2, D6) from the side on which the interlayer line is wired, is set as a target pattern layer (P2, P7), and a non-pattern area (5) in which formation of a conductor pattern is prohibited is provided at a position facing the end pattern in the target pattern layer, and a plurality of target pattern layers are present on at least one end side of the interlayer line, and a conductor pattern is provided at a position facing the end pattern in the pattern layer (P1, P8) facing the end pattern via the non-pattern area, thereby increasing the impedance of the interlayer line. A method for adjusting impedance of interlayer lines.

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