Wiring design device for semiconductor integrated circuits and wiring design program for semiconductor integrated circuits

Abstract

To provide a wiring design device for semiconductor integrated circuits and wiring design program for semiconductor integrated circuits that can reduce the labor required for wiring processing.SOLUTION: A wiring design device for a semiconductor integrated circuit according to the present embodiment is characterized by comprising: primary parameter setting means 31 for back-wiring a via parametric cell to a power rail of an instance cell generated based on design information of the semiconductor integrated circuit and setting parameters of the wired via parametric cell; short part detection means 32 for detecting a short part where the via parametric cell crosses with the wiring in a layer above the layer of the instance cell; and shape change means 33 for updating a setting value of the via parametric cell and changing it to a new shape by cutting the backing wiring in order to remove the short part detected by the short part detection means.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a wiring design device for a semiconductor integrated circuit and a wiring design program for a semiconductor integrated circuit. [Background technology]

[0002] Patent Document 1 discloses a wiring board suitable for narrowing the pitch between lead wiring layers in a connector section that requires migration prevention, and a manufacturing method thereof. For this purpose, the wiring board includes a flexible insulating substrate that constitutes a connector terminal section having an insertion edge in a direction intersecting with the connector insertion direction into an external connector, and first and second lead wiring layers having a silver component and formed on the insulating substrate surface of the connector terminal section in an arrangement pattern parallel to the insertion direction. The wiring board also includes first and second electrode terminal layers that cover and cover the upper surfaces and side edges of each tip on the insertion edge side, respectively, and an insulating protective layer for migration prevention that covers and covers the upper surfaces and side edges of each lead wiring layer other than the tips. Here, the first and second electrode terminal layers are arranged in a distant relationship with each other with respect to the insertion edge.

[0003] In addition, the existence of an insulating protective layer sufficiently prevents electrical shorts between the lead wiring layers and ensures insulation, and the design of the spacing is highly flexible, and the wiring layer width is not subject to significant dimensional constraints, so that a larger width can be ensured for the same pitch compared to the prior art. As a result, the internal resistance of the lead wiring layer can be reduced, the current capacity can be increased, and it is easy to accommodate narrowing of the wiring pitch P.

[0004] Patent Document 2 discloses a wiring board for flip-chip connecting a semiconductor integrated circuit, which can maintain a gap between the flip-chip connected semiconductor integrated circuit and the board, and can effectively prevent short circuits on the side walls. In this wiring board, a flip-chip connection part is formed by a convex part formed of a conductor on the insulating resin layer surface and an electrode pattern formed on the convex part, all side surfaces of the convex part are covered with an insulating material, and an insulating material is formed on the insulating resin layer surface thinner than the convex part.

[0005] Patent Document 3 discloses an automatic wiring method for semiconductor integrated circuits that has a function of estimating the signal wiring delay of the signal to be wired, and in particular a function of predicting the wiring length of each signal based on the placement result since actual wiring has not been performed at this stage. This method further has a function of calculating the delay due to wiring based on the wiring length, and in particular a function of calculating the delay assuming the worst case, although various methods are possible for these predictions and calculation methods.

[0006] The method of Patent Document 3 also has a function for extracting target wiring in descending order of delay in order to process wiring with the greatest difficulty from the standpoint of reducing delay, and a function for switching between wiring methods to select the automatic wiring method to be used in order to prevent unnecessary execution, since automatic wiring that takes wiring delay into account requires much longer calculation time than wiring that does not.

[0007] In the case of multi-layer wiring, in order to avoid a situation where the same layer is assigned to wirings that cross at the same point, a function is provided to move one of the shorted wiring layers to another wiring layer. This wiring layer change function evaluates the effect of the wiring layer change on signal delays and switches the signal wiring that will have the least effect to another layer.

[0008] Moreover, the invention of Patent Document 3 uses a method of completing the wiring by appropriately repeating the following steps: first, determining a path that connects two appropriate terminal pairs; and second, determining a path that connects a point on a path already determined in a previous step to another terminal or a point on another path already determined.

[0009] In particular, in the second stage, when selecting one point on an already determined route as a branch point, a configuration is adopted in which the center point of the route is calculated and a branch point is selected within a certain distance from the center point. Alternatively, in the second stage, a cost is set to the branch point that increases with distance from the center point on the already determined route, and a branch point is selected so that the sum of the length of a wiring route newly generated between the branch points with the set cost and the cost is minimized.

[0010] With the above means, the delay estimation function for each signal and the function of extracting the nets to be wired in descending order of delay amount enable the nets to be wired, which are difficult to comply with the constraints on signal delay, to be wired at an early stage with a high degree of freedom. Meanwhile, the delay prediction estimation function and the function of switching the wiring method depending on the estimated wiring delay amount distinguish between signals that require special measures regarding signal delay and those that do not, thereby reducing the number of times wiring that takes into account signal delay, which takes a lot of processing time, and saving processing time.

[0011] Generally, when performing multi-layer wiring using an automatic wiring program, the wiring direction assigned to each wiring layer is fixed. When three or more wiring layers are available, it becomes possible to assign multiple wiring layers to the same direction. However, each wiring layer has its own electrical characteristics such as electrical resistance and capacitance, and the signal propagation delay is different. Therefore, by assigning to wiring layers with small propagation delays first, the propagation delay of the wiring can be reduced.

[0012] In a method of wiring according to the priority allocation direction of wiring layers that determines the priority direction of wiring layers, when there are multiple wiring layers that can be allocated, the function of preferentially allocating wiring layers with small signal delays has the effect of minimizing delays in wiring as much as possible. Furthermore, this increases the probability that the resulting wiring satisfies delay constraints.

[0013] In addition, when converting wiring layers to resolve a short circuit in a temporary wiring, the effect on signal delay of the change in electrical parameters corresponding to the change in wiring layer of both wirings is calculated, and the function of avoiding a short circuit by changing the wiring layer that constitutes the wiring of the signal that is less affected makes it possible to minimize the wiring delay that increases due to the work of avoiding the short circuit. [Prior art documents] [Patent documents]

[0014] [Patent Document 1] JP 2009-147130 A [Patent Document 2] JP 2015-018945 A [Patent Document 3] Japanese Patent Application Publication No. 6-283602

[0015] As described above, various techniques have been developed to prevent short circuits in wiring in semiconductor integrated circuits and the like, but these do not cover designs to prevent short circuits in power supply rails.

[0016] In semiconductor integrated circuits, in order to reduce the resistance of the power supply wiring, a wiring layer and a via hole are stacked on the power supply rail laid in each block cell to form a backing wiring. In this case, if there is a signal line that crosses the backing wiring at right angles, it is necessary to divide the backing wiring side to avoid wiring shorts. However, this work is done manually, and there is a problem that it takes a lot of time and effort to divide the via cells. Summary of the Invention [Problem to be solved by the invention]

[0017] The present invention has been made in consideration of the problems in the conventional wiring design of semiconductor integrated circuits as described above, and an object of the present invention is to provide a wiring design device for semiconductor integrated circuits and a wiring design program for semiconductor integrated circuits that can lead to a reduction in the number of steps in the wiring processing process. [Means for solving the problem]

[0018] The wiring design device for a semiconductor integrated circuit according to this embodiment is characterized by comprising: a primary parameter setting means for back-wiring a via parametric cell to a power rail of an instance cell generated based on design information of the semiconductor integrated circuit and setting parameters of the wired via parametric cell; a short circuit part detection means for detecting a short circuit part where the via parametric cell crosses with wiring in a layer above the layer of the instance cell; and a shape modification means for updating the setting value of the via parametric cell and modifying it to a new shape in which the back-wiring is cut in order to remove the short circuit part detected by the short circuit part detection means.

[0019] The wiring design device for a semiconductor integrated circuit according to this embodiment includes a short circuit part coordinate detection means for detecting the coordinate values ​​of the short circuit part detected by the short circuit part detection means, and a second parameter setting means for setting parameters of a new via parametric cell based on the coordinate values ​​of the short circuit part detected by the short circuit part coordinate detection means, and is characterized in that the shape modification means changes the backing wiring to a new shape by cutting it based on the parameters set by the second parameter setting means.

[0020] In the wiring design device for a semiconductor integrated circuit according to this embodiment, the power supply rails are composed of a first power supply rail that supplies a voltage to the circuit and a second power supply rail that supplies a ground potential, and the wiring in the layer above the layer of the instance cell is wiring that crosses the first power supply rail and the second power supply rail.

[0021] In the wiring design device for a semiconductor integrated circuit according to this embodiment, the layer above the layer of the instance cell has multiple layers, and the short circuit detection means, the shape modification means, the short circuit coordinate detection means, and the secondary parameter setting means perform processing for the wiring of each layer.

[0022] In the wiring design apparatus for a semiconductor integrated circuit according to this embodiment, the vias of the via parametric cell are formed in a plurality of rows and a plurality of columns.

[0023] The wiring design device for a semiconductor integrated circuit according to this embodiment is characterized in that one or more upper layer wirings that cross the via parametric cell can be placed on each layer.

[0024] The wiring design program for a semiconductor integrated circuit according to this embodiment is characterized in that it causes a computer to function as a primary parameter setting means for backing-wiring a via parametric cell to a power rail of an instance cell generated based on design information of the semiconductor integrated circuit and setting parameters of the wired via parametric cell, a short circuit portion detection means for detecting a short circuit portion where the via parametric cell crosses with wiring in a layer above the layer of the instance cell, and a shape modification means for updating the setting value of the via parametric cell and modifying it to a new shape in which the backing wiring is cut in order to remove the short circuit portion detected by the short circuit portion detection means.

[0025] In the wiring design program for a semiconductor integrated circuit according to this embodiment, the computer is further made to function as a short circuit portion coordinate detection means for detecting the coordinate values ​​of the short circuit portion detected by the short circuit portion detection means, and a second parameter setting means for setting parameters of a new via parametric cell based on the coordinate values ​​of the short circuit portion detected by the short circuit portion coordinate detection means, and is made to function as the shape change means for changing the backing wiring to a new shape by cutting it based on the parameters set by the second parameter setting means.

[0026] In the wiring design program for a semiconductor integrated circuit according to this embodiment, the power supply rails are composed of a first power supply rail that supplies a voltage to the circuit and a second power supply rail that supplies a ground potential, and the wiring in a layer above the layer of the instance cell is wiring that crosses the first power supply rail and the second power supply rail.

[0027] In the program for wiring design of a semiconductor integrated circuit according to this embodiment, the layer above the layer of the instance cell has multiple layers, and the short circuit detection means, the shape modification means, the short circuit coordinate detection means, and the secondary parameter setting means perform processing for the wiring of each layer.

[0028] In the wiring design program for a semiconductor integrated circuit according to this embodiment, the vias of the via parametric cell are formed in a plurality of rows and a plurality of columns.

[0029] The wiring design program for a semiconductor integrated circuit according to this embodiment is characterized in that one or more upper layer wirings that cross the via parametric cell can be placed on each layer. [Brief description of the drawings]

[0030] [Figure 1] FIG. 1 is a block diagram of a computer constituting an apparatus for designing wiring for a semiconductor integrated circuit according to an embodiment of the present invention. [Diagram 2]FIG. 2 is a block diagram showing each unit for realizing a wiring design program for a semiconductor integrated circuit according to an embodiment of the present invention. [Diagram 3] 4 is a flowchart showing an operation of the wiring design apparatus for a semiconductor integrated circuit according to the embodiment of the present invention. [Figure 4] 2 is a diagram showing an example of an instance cell generated based on design information of a semiconductor integrated circuit according to the embodiment of the present invention; [Diagram 5] FIG. 1 is a schematic diagram showing a state where via parametric cells are back-wired to the power rails of instance cells generated based on design information of a semiconductor integrated circuit according to this embodiment of the present invention. [Figure 6] FIG. 13 is an enlarged view of a main portion when a via parametric cell is backed with wiring for a power rail of an instance cell generated based on design information of a semiconductor integrated circuit according to this embodiment of the present invention. [Figure 7] FIG. 6 is a schematic diagram showing the state in which upper layer wiring has been added from the state shown in FIG. 5. [Figure 8] FIG. 8 is a schematic diagram showing a state in which the setting values ​​of the via parametric cell are updated and the backing wiring is cut to change the shape from the state shown in FIG. 7 to a new shape in order to remove the short circuit portion detected by the short circuit portion detection means. [Figure 9] FIG. 9 is an enlarged view of a main part of FIG. 8. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] Hereinafter, a wiring design device and a wiring design program for a semiconductor integrated circuit according to an embodiment of the present invention will be described with reference to the accompanying drawings. In each drawing, the same components are given the same reference numerals and duplicated explanations will be omitted.

[0032] The wiring design device for a semiconductor integrated circuit according to the embodiment of the present invention having the above configuration can be configured using a computer, as shown in Fig. 1. That is, a CPU 10 configures the wiring design device for a semiconductor integrated circuit using programs and data in a main memory 11. An external storage interface 13, an input interface 14, a display interface 15, and a network interface 16 are connected to the CPU 10 via a bus 12.

[0033] An external storage device 23 is connected to the external storage interface 13. The external storage device 23 stores programs and data for the operation of the wiring design device for semiconductor integrated circuits, which can be read out and used by the CPU 10 in the main memory 11 as appropriate. For this reason, the external storage device 23 stores programs for implementing each means of the wiring design device for semiconductor integrated circuits, which will be described later. An input device 24 such as a keyboard or a touch panel and a pointing device 22 such as a mouse are connected to the input interface 14. A display device 25 having a screen such as an LCD is connected to the display interface 15, and the display device 25 realizes the display of images and the like required for the wiring design device for semiconductor integrated circuits. A network is connected to the network interface 16, and the wiring design device for semiconductor integrated circuits can import data and the like to be used for wiring design. As described above, an input device 24 such as a keyboard for inputting data and commands and a pointing device 22 such as a mouse are connected to the input interface 14, so that the wiring design device for semiconductor integrated circuits can perform the necessary operations and processes by operating the input device 24 and the mouse 22.

[0034] The external storage device 23 stores various means for implementing a wiring design program for a semiconductor integrated circuit, as shown in Fig. 2. These means are composed of a first parameter setting means 31, a short circuit portion detection means 32, a shape modification means 33, a short circuit portion coordinate detection means 34, and a second parameter setting means 35.

[0035] The wiring design device for a semiconductor integrated circuit according to this embodiment operates according to a program corresponding to the flowchart shown in Fig. 3. Therefore, the operation will be described below based on this flowchart. First, information on the placement and wiring of elements and layout generated based on design information of the semiconductor integrated circuit related to the design target is retrieved from, for example, the external storage device 23, and verification is started (S11).

[0036] Next, a via parametric cell is back-wired to the power rail of the instance cell generated based on the design information of the semiconductor integrated circuit, and parameters of the wired via parametric cell are set (S12). This step S12 can be executed by the first parameter setting means 31. The design information of the semiconductor integrated circuit of this embodiment can be stored in the external storage device 23 in advance as described above, or can be obtained from a predetermined device or the like via the network interface 16 and stored in the external storage device 23.

[0037] An instance cell generated based on the design information of the semiconductor integrated circuit of this embodiment is, for example, as shown in Fig. 4. That is, Fig. 4 shows a circuit in which two pairs of inverters are arranged, each of which has a drain 42 of a PMOS transistor 41 and a source 44 of an NMOS transistor 43 connected to each other. A line connected to the source of the PMOS transistor 41 is connected to a power supply rail 51 with potential (VDD), and a line connected to the drain of the NMOS transistor 43 is connected to a power supply rail 52 with earth potential (VSS).

[0038] A schematic diagram of the via parametric cell 61 (62) backing the power rail 51 (52) is shown in FIG. 5, and an enlarged view of the main part is shown in FIG. 6. The parameters set at this time are <1> ~ <8> The parameters are shown in the upper part of Fig. 6 and the contents are shown in the right frame of Fig. 6. <1> indicates a row, and the parameter <2> indicates a column. In the example of Fig. 6, the vias 63 are shown in 2 rows x 4 columns, but in reality the number of columns reaches about 1000. Therefore, it is understood that it is extremely inefficient to manually prevent short circuits for each via 63. Also, in Fig. 5, only one row of via parametric cells 61 (62) for the power rail 51 (52) is shown.

[0039] Parameters <3> is the hole width, and the parameter <4> is the hole spacing, and the parameter <5> is the X-direction perimeter width of Layer 1 (Layer1 Enclosure X), and the parameter <6> is the Y-direction perimeter width of layer 1 (Layer1 Enclosure Y), and the parameter <7> is the X-direction perimeter width of Layer 2 (Layer2 Enclosure X), and the parameter <8> is the Y-direction perimeter width of layer 2 (Layer2 Enclosure Y).

[0040] In the next process of the device according to this embodiment, the process proceeds to step S13 in Fig. 3, where wiring 47 is performed in the upper layer of the layer of the instance cell, and short sites SR1 and SR2 of the via parametric cells 61 and 62 are detected (S13). This step S13 is performed by the short site detection means 32. Fig. 7 shows a state in which wiring 47 in the upper layer has been performed from the state in Fig. 5. The short sites SR1 and SR2 are generated in the power rails 51 and 52. At this time, the short site coordinate detection means 34 detects the coordinate values ​​of the short sites SR1 and SR2 detected by the short site detection means 32.

[0041] In step S14 following step S13, the parameters of the via parametric cells 61A, 61B, 62A, and 62B are set as shown in FIG. 8 based on the coordinate values ​​of the short-circuited regions SR1 and SR2 detected above (S14). That is, the secondary parameter setting means 35 updates the set values ​​of the via parametric cells to remove the short-circuited regions based on the coordinate values ​​of the short-circuited regions SR1 and SR2 detected by the short-circuited region coordinate detection means 34, and sets parameters so that the backing wiring is cut into a new shape (61A (62A), 61B (62B)). This process is performed by the secondary parameter setting means 35. In this embodiment, as shown in FIG. 9, the parameters of the via parametric cell 61A (62A) and the coordinates (Layer1 Cut Coords) of the cut position of the via parametric cell 61B (62B) are set. <9> is set (Figure 9).

[0042] Specifically, the semiconductor integrated circuit to be designed is represented by the XY coordinates in FIG. 7, and the coordinate values ​​of the short sites SR1 and SR2 are the coordinate values ​​based on these XY coordinates. In contrast, the positions in the via parametric cell are represented by the xy coordinates shown in FIG. 6 and FIG. 9. For this reason, in the above step S14, the coordinate values ​​of the short sites SR1 and SR2 in the XY coordinates are converted into coordinate values ​​in the xy coordinates. In this example, the coordinate values ​​of the via parametric cells backed by wiring to the two power rails 51 and 52 are expressed by different coordinate values, so that conversion to coordinate values ​​based on the respective coordinates is performed. Note that the conversion formulas and the like are created for each system and are publicly known, so they will not be described in detail here.

[0043] Next, in step S15, in order to remove the short-circuited regions SR1 and SR2 detected by the short-circuited region detection means 32, the setting values ​​of the via parametric cell are updated and changed to new shapes 61A (62A), 61B (62B) in which the backing wiring is cut (S15). This process is performed by the shape modification means 33. In practice, the shape modification means 33 updates the setting values ​​of the via parametric cell and changes to new shapes 61A (62A), 61B (62B) in which the backing wiring is cut, based on the parameters set by the secondary parameter setting means 35, in order to remove the short-circuited regions. As a result, the via parametric cell is changed from the state shown in FIG. 7 or FIG. 6 to the state shown in FIG. 8 or FIG. 9. In other words, as shown in FIG. 8 or FIG. 9, the parameters <9> The backing wiring is cut at the position of the coordinates (Layer1 Cut Coords) indicated by and divided into via parametric cells 61A (62A) and 61B (62B). Thus, by changing the via parametric cell to a new shape, wiring shorts are avoided.

[0044] After the above process is completed, it is checked whether any changes have been made to the wiring route in the design (S16), and if the answer is YES, the process returns to step S13 to continue. If the process branches to NO in step S16, the process ends. [Explanation of symbols]

[0045] 10 CPU 11 Main Memory 12 Bus 13 External memory interface 14 Input Interface 15 Display Interface 16 Network Interfaces 22 Pointing Device 23 External storage device 24 Input Devices 25 Display device 31 Primary parameter setting means 32 Means for detecting short circuit 33 Shape change means 34 Short circuit area coordinate detection means 35 Secondary parameter setting means 41 PMOS transistor 42 Drain 43 NMOS transistor 44 Source 47 Wiring 51 Power Rail 52 Power Rail 61 Via Parametric Cell 61A Via Parametric Cell 61B Via Parametric Cell 62 Via Parametric Cell 62A Via Parametric Cell 62B Via Parametric Cell 63 Via SR1, SR2 short site

Claims

1. a first parameter setting means for backwiring a via parametric cell to a power rail of an instance cell generated based on design information of a semiconductor integrated circuit, and setting parameters of the wired via parametric cell; a short circuit portion detection means for detecting a short circuit portion where a wiring in a layer above the layer of the instance cell and the via parametric cell cross each other; a shape changing means for changing a setting value of a via parametric cell to a new shape by cutting a backing wiring in order to remove the short-circuit portion detected by the short-circuit portion detecting means; 1. A wiring design device for a semiconductor integrated circuit comprising:

2. a short circuit part coordinate detection means for detecting a coordinate value of the short circuit part detected by the short circuit part detection means; a second parameter setting means for setting parameters of a new via parametric cell based on the coordinate values ​​of the short circuit portion detected by the short circuit portion coordinate detection means; Equipped with 2. The wiring design device for a semiconductor integrated circuit according to claim 1, wherein said shape changing means changes said backing wiring to a new shape by cutting said backing wiring based on the parameters set by said secondary parameter setting means.

3. 3. The wiring design device for a semiconductor integrated circuit according to claim 1, wherein the power supply rail is composed of a first power supply rail that provides a voltage to a circuit and a second power supply rail that provides a ground potential, and wiring in a layer above the layer of the instance cell is wiring that crosses the first power supply rail and the second power supply rail.

4. 3. The wiring design device for a semiconductor integrated circuit according to claim 2, wherein a layer above the layer of the instance cell includes a plurality of layers, and the short circuit detection means, the shape modification means, the short circuit coordinate detection means, and the secondary parameter setting means perform processing for the wiring of each layer.

5. 2. The wiring design device for a semiconductor integrated circuit according to claim 1, wherein the vias of the via parametric cell are formed in a plurality of rows and a plurality of columns.

6. 2. The wiring design device for a semiconductor integrated circuit according to claim 1, wherein one or more upper layer wirings crossing said via parametric cell can be arranged on each layer.

7. Computer, a first parameter setting means for back-wiring a via parametric cell to a power rail of an instance cell generated based on design information of the semiconductor integrated circuit, and setting parameters of the wired via parametric cell; a short circuit portion detection means for detecting a short circuit portion where a wiring in a layer above the layer of the instance cell crosses the via parametric cell; a shape changing means for changing a setting value of a via parametric cell to a new shape by cutting a backing wiring in order to remove the short-circuit portion detected by the short-circuit portion detecting means; 4. A wiring design program for a semiconductor integrated circuit, comprising:

8. The computer further comprises: a short circuit part coordinate detection means for detecting a coordinate value of the short circuit part detected by the short circuit part detection means; a second parameter setting means for setting parameters of a new via parametric cell based on the coordinate values ​​of the short circuit portion detected by the short circuit portion coordinate detection means; Function as a 8. The wiring design program for a semiconductor integrated circuit according to claim 7, wherein the computer is caused to function as the shape changing means so as to change the backing wiring to a new shape by cutting the backing wiring based on the parameters set by the second parameter setting means.

9. 9. The wiring design program for a semiconductor integrated circuit according to claim 7 or 8, wherein the power supply rail is composed of a first power supply rail that provides a voltage to a circuit and a second power supply rail that provides a ground potential, and the wiring in a layer above the layer of the instance cell is wiring that crosses the first power supply rail and the second power supply rail.

10. 9. The program for wiring design of a semiconductor integrated circuit according to claim 8, wherein a layer above the layer of the instance cell is a plurality of layers, and the short circuit detection means, the shape modification means, the short circuit coordinate detection means, and the secondary parameter setting means perform processing for wiring in each layer.

11. 8. The wiring design program for a semiconductor integrated circuit according to claim 7, wherein the vias of the via parametric cell are formed in a plurality of rows and a plurality of columns.

12. 8. The wiring design program for a semiconductor integrated circuit according to claim 7, wherein one or more upper layer wirings crossing the via parametric cell can be arranged on each layer.

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