High-bandwidth IJTAG via high-speed parallel bus

Abstract

The system in the circuit includes a first network configurable to transmit data in parallel within the circuit, the first network comprising a circuit block interface device, each of the circuit block interface devices coupled to a port of one of the circuit blocks in the circuit, a plurality of second networks, each of the plurality of second networks configurable to transmit data serially with one of the circuit blocks, a third network configurable to transmit data serially within the circuit when coupled to the plurality of second networks, and a plurality of network switching interface devices.

Description

[Technical field]

[0001] Related inventions This application claims the benefit of U.S. Provisional Patent Application No. 63 / 067,534, filed Aug. 19, 2020, by Jean-Francois Cote et al., which is incorporated by reference in its entirety.

[0002] The techniques disclosed herein relate to the fields of integrated circuit design, verification, manufacturing and testing. Various implementations of the disclosed techniques are particularly useful for increasing the bandwidth of in-circuit serial networks. [Background technology]

[0003] The number of functional units in semiconductor devices continues to increase significantly as the integration of functions into a single semiconductor device continues. A functional unit may be a sensor for temperature or voltage, a clock control circuit such as a phase-locked loop (PLL), a scan configuration controller, or an entire built-in self-test (BIST) engine for memory or logic testing. Accessing, controlling, observing, or in more general terms "executing" these numerous functional units presents a challenge to the designer. Summary of the Invention [Problem to be solved by the invention]

[0004] Traditionally, functional units are daisy-chained with one serial access network. This leads to numerous scan operations to shift data bits in and out of these functional blocks. To reduce the access time, a reconfigurable scan network can be employed to replace the traditional serial access network. Based on the specific program operations of special elements of the access network, parts of the reconfigurable scan network can move in and out of the scan path. A typical reconfigurable scan network compliant with IEEE 1687-2014 and IEEE 1149.1-2013 is called an IJTAG network.

[0005] The actively reconfigurable IJTAG network minimizes the number of shift operations required to exercise a desired functional unit, such as setting all aspects of a circuit's test mode.As device complexity increases and the amount of diagnostic data that needs to be extracted grows, the slow speed and serial nature of the IJTAG scan network becomes a bottleneck, lengthening test times.

[0006] Attempts have been made to increase the speed of shifting by introducing clock gaps around the transition of the control (clock stretching) or by matching stages on the scan path and adding pipeline stages to the control signals. Unfortunately, these two techniques are mutually exclusive. These solutions help to reach shift speeds in the low 100MHz range, but the increased bandwidth is still an order of magnitude lower than required due to the serial nature of the solution and the two edge timings used when crossing clock domains.

[0007] Support for the IEEE 1687-2014 standard which uses a multi-chain scan interface, but wiring many scan chains across physical block boundaries is costly, very cumbersome, and incompatible with modern core-based design flows. [Means for solving the problem]

[0008] Various aspects of the disclosed technology relate to increasing the bandwidth of serial networks. In one aspect, a system in a circuit includes a first network configured to serially transmit data in the circuit, the first network comprising circuit block interface devices, each of the circuit block interface devices coupled to a port of one of the circuit blocks in the circuit, a plurality of second networks, each of the plurality of second networks configured to serially transmit data to one of the circuit blocks in the circuit, a third network configured to serially transmit data in the circuit when the circuit is connected to the plurality of second networks, and a plurality of network switching interface devices, each of the plurality of network switching interface devices configured to couple either the first network or the third network to one of the plurality of second networks based on a control signal stored in each of the plurality of interface devices.

[0009] The control signals stored in each of the plurality of interface devices may be updated using the third network when the third network is coupled to one of the plurality of second networks, or using the first network when the first network is coupled to one of the plurality of second networks.

[0010] The multiple second networks may be configured to be coupled to the first network in a daisy chain mode, a parallel mode, a broadcast mode, or any combination thereof.

[0011] The first network may operate at a clock frequency that is a multiple (greater than one) of the clock frequency at which the multiple second networks operate, and the multiple second networks may be coupled to the first network in a timeslot multiplexing mode.

[0012] A second network of the plurality of second networks may comprise a section configurable to transmit data in parallel, the section being configurable to be coupled to the first network in parallel.

[0013] One or more of the plurality of second networks may use a clock stretching technique to increase the shift rate.

[0014] The third network and the plurality of second networks may be compliant with the IEEE 1687 standard (IJTAG, Internal Joint Test Action Group).

[0015] The first network may further include a multiplexing device, a pipeline device, or both, and the multiplexing device is configurable to modify the data streaming path of the first network based on further control data transmittable to the multiplexing device via a plurality of second networks coupled to either the first network or the third network.

[0016] Each of the plurality of second networks includes a configuration interface device, the configuration interface device is coupled to one of the circuit block interface devices, configuration data for the configuration interface device is transmittable over each of the plurality of networks coupled to either the first network or the third network, the configuration data including data determining whether a circuit block interface device of a circuit block is operational and data determining what portions of the data transmitted to the first network are to be captured, replaced, or captured and replaced by each of the operational circuit block interface devices.

[0017] The circuit block interface device may comprise a register and clock signal generation logic, the first network comprises a data channel and is configurable to transmit a plurality of data packets in succession, each of the plurality of data packets having a plurality of bits, each of the plurality of bits being assigned to one of the circuit blocks for which the circuit block interface device is activated, and a number of the plurality of bits is equal to or greater than a number of data channels used to transmit the plurality of data packets. Each of the plurality of data packets may include one or more bits of a test pattern or a compressed test pattern for testing one or more of the circuit blocks, and the clock signal generation logic in the circuit block interface device coupled to a port of one of the circuit blocks may be configurable to generate a clock signal for scan-based testing, and the port of one of the circuit blocks may include inputs and outputs of a scan chain, inputs and outputs of one or more test controllers, or a combination thereof, each of the one or more test controllers comprising a decompressor and a compactor.

[0018] In another aspect, there are one or more non-transitory computer-readable media storing computer-executable instructions for causing a computer to perform a method, the method including generating the above-described system in a circuit design.

[0019] In yet another aspect, a method for testing a circuit includes transmitting network configuration data over a third network coupled to a plurality of second networks, the third network configured to transmit data serially within the circuit, each of the plurality of second networks configured to transmit data to one of the circuit blocks of the circuit, the network configuration data including first network switching interface control data for a plurality of network switching interface devices, the first network switching interface control data operable to operate each of the plurality of second networks to isolate one of the plurality of second networks from the third network and to isolate one of the plurality of second networks from the first network. a first network coupled to a plurality of second networks, the first network configured to transmit data in parallel to the circuit; and transmitting setup data over the first network coupled to a plurality of second networks, the setup data including test setup data for the circuit blocks, network setup data for communication between the first network and the circuit blocks, and second network switching interface control data for the plurality of network switching interface devices, the second network switching interface control data operating the plurality of network switching interface devices to isolate one of the plurality of second networks from the first network and to couple said one of the plurality of second networks to a third network. and transmitting test data to the circuit block via the first network.

[0020] The method may further comprise transmitting interface enabling data over a third network coupled to the plurality of second networks to enable an interface device between the first network and the circuit block prior to transmitting the test data.

[0021] The network configuration data may further include network reconfiguration data for the plurality of multiplexing devices, the network reconfiguration data causing the first network to bypass zero, one, or multiple circuit blocks.

[0022] Particular inventive aspects are set out in the accompanying independent and dependent claims. Features from the dependent claims may be combined with features of the independent claims and with features of other dependent claims as appropriate and not merely as explicitly set out in the claims.

[0023] Specific objectives and advantages of various inventive aspects have been described herein above. Of course, it should be understood that not necessarily all such objectives or advantages will be achieved in accordance with any particular embodiment of the disclosed technology. Thus, for example, one skilled in the art will recognize that the disclosed technology may be embodied or performed in a manner that achieves or optimizes one advantage or group of advantages as taught herein, without necessarily achieving other objectives or advantages as taught herein. [Brief description of the drawings]

[0024] [Figure 1] Figure 1 shows an example of an IJTAG network. [Diagram 2] Figure 2 shows an example of a data streaming system in circuitry, where a serial network is used to set up the core interface for communication with a parallel data streaming network. [Diagram 3]FIG. 3 shows an example of bit allocation of the data channels of the parallel data streaming network in FIG. [Figure 4] FIG. 4 illustrates an example of a circuit block interface device, such as the first interface device in FIG. 2, implemented in accordance with various embodiments of the disclosed technology. [Diagram 5] FIG. 5 illustrates an example of a pipeline apparatus implemented in accordance with various embodiments of the disclosed technology. [Figure 6] FIG. 6 illustrates an example of a multiplexing device implemented in accordance with various embodiments of the disclosed technology. [Figure 7] FIG. 7 illustrates an example of a system utilizing a data streaming network to increase serial network bandwidth implemented in accordance with various embodiments of the disclosed technology. [Figure 8] FIG. 8 illustrates an example of a network switching interface device according to various embodiments of the disclosed technology. [Figure 9] FIG. 9 illustrates an example detailed block diagram of a network switching interface device in accordance with various embodiments of the disclosed technology. [Figure 10] FIG. 10 illustrates an example of a data streaming network coupled to three local serial networks in a daisy-chain mode in accordance with various embodiments of the disclosed technology. [Figure 11] FIG. 11 shows an example of a TAP state machine that complies with the IEEE 1149.1-2013 standard. [Figure 12] FIG. 12 shows a table illustrating an example of some bits of the scan / storage element of FIG. 10 over 19 successive clock cycles. [Figure 13] FIG. 13 illustrates an example of a data streaming network coupled to three local serial networks in broadcast mode in accordance with various embodiments of the disclosed technology. [Figure 14]FIG. 14 illustrates an example of a data streaming network coupled in a parallel mode to two local serial networks in accordance with various embodiments of the disclosed technology. [Figure 15] FIG. 15 illustrates an example of a data streaming network coupled to two local serial networks in a time slot multiplexing mode in accordance with various embodiments of the disclosed technology. [Figure 16] FIG. 16 illustrates an example of a memory BIST (Built-In Self-Test) section of a local network that can be configured to be coupled in parallel to a data streaming network (first network) in accordance with various embodiments of the disclosed technology. [Figure 17] FIG. 17 illustrates a flow chart illustrating a process of setting up a circuit test over a high bandwidth serial network enabled by a data streaming network implemented in accordance with various examples of the disclosed technology. [Figure 18] FIG. 18 shows several example clock and control signal waveforms illustrating a clock stretching technique for increasing the shift speed of an IJTAG network implemented in accordance with various embodiments of the disclosed technology. [Figure 19] FIG. 19 illustrates a programmable computer system in which various embodiments of the disclosed technology may be employed. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] Various aspects of the disclosed technology relate to increasing the bandwidth of a serial network in a circuit. In the following description, numerous details are set forth for purposes of explanation. However, one of ordinary skill in the art will understand that the disclosed technology can be practiced without the use of these specific details. In other instances, well-known features have not been described in detail to avoid obscuring the technology disclosed herein.

[0026] Detailed descriptions of methods or devices sometimes use terms such as "transmit" and "enable" to describe the functionality / structure of the disclosed method or device. Such terms are at a high level of abstraction. The actual operations or functionality / structure that correspond to these terms will vary depending on the specific implementation and will be readily discernible by those skilled in the art. Additionally, those skilled in the art will appreciate that the term "coupled" means "directly or indirectly connected."

[0027] Although the operations of the disclosed methods are described in a particular order for convenient presentation, it should be understood that this manner of description encompasses rearrangements, unless a particular ordering is required by specific language set forth below. For example, operations described as sequentially may in some cases be rearranged or performed simultaneously. Moreover, for simplicity, the disclosed flow charts and block diagrams do not typically show the various ways in which particular methods are used in conjunction with other methods.

[0028] Reconfigurable Scan Network Reconfigurable scan networks compliant with IEEE 1687-2014 (IJTAG) provide, among other things, built-in test and access to test setups for manufacturing test. Figure 1 shows an example of an IJTAG network 100. In the IJTAG network 100, a Segment Insertion Bit (SIB) 123 switches between two multiple access paths between a Test Data Input (TDI) port 115 and a Test Data Output (TDO) port 117 belonging to a Test Access Port (TAP) 110. The short access path connects the SIB 123 directly to the SIB 121, while the long access path connects the SIB 123 to the SIB 121 via two Test Data Registers (TDRs) 135 and 136. A ScanMux (multiplexer) 140 selects one of the two scan segments of the access network 100 (one via TDR 133 and the other via TDR 134) based on the received control data. To access these two scan segments, SIBs 121 and 122 must be programmed accordingly. The scan path can also reach SIB 122 directly from TDR 131, bypassing TDRs 132, 133 and 134.

[0029] As shown in FIG. 1, reconfigurable scan network programmable configuration elements such as SIBs 121, 122, and 123 and ScanMux 140 in scan network 100 allow dynamic configuration of the access network to bring specific functional blocks within the scope of the access network. These programmable components can be programmed by shifting configuration data into shift flip-flops of control registers and latching the shifted bits into parallel latches therein. The functional blocks of the circuit are controlled by TDRs 131-136. This dynamic access network configuration minimizes the number of shift operations required to operate the desired functional blocks.

[0030] An additional benefit of such a reconfigurable scan network derives from the ability to configure the access network according to power and clock domains. For example, placing a SIB in front of a power domain ensures that parts of the access network outside this power domain remain operational even when the power domain is switched off. In a similar way, hierarchical design entities can be brought within and outside the scope of the access network, enabling bypass of all functional objects within each design hierarchical entity.

[0031] Data Streaming Networks As integrated circuits grow to contain billions of transistors, it is virtually impossible to design them flat without partitioning them. Electronic Design Automation (EDA) tools cannot handle them efficiently. In addition, there is a significant reuse of intellectual property (IP) from one design to another. Large designs, known as Systems-On-A-Chip (SOC), contain many "cores" that are used as building blocks (also called circuit blocks). Each core is typically designed and verified separately first, and then integrated with other cores to form the entire SOC. This is called hierarchical design. Ideally, much of the design and validation work is done at the core level, making them smaller and more manageable, while integration and chip-level validation are done at the top level. All the work done at the core level can also be done earlier if working on the cores. As the SOCs come together and approach the tape-out deadline, they are taken off the critical path.

[0032] As designs have grown, the number of levels of core hierarchy has grown as well. Hierarchical designs started with two levels of hierarchy: the core level and the chip / top level. Cores are first integrated into larger sized cores or subsystems, and then integrated into chips. This represents three levels of core hierarchy. Some larger designs have even more levels of core hierarchy.

[0033] Just as designs employ hierarchical design to manage complexity, so does scan testing. In a hierarchical test methodology, scan chains and compression logic are inserted into every core. Test patterns are generated and verified at the core level to test most of the logic within the core. Patterns from multiple cores are then retargeted or mapped to the top level. They are also merged with retargeted patterns for other cores that are being tested simultaneously. In addition to delaying the patterns generated to test most of the content of each core, test pattern generation is performed at the next level down to test peripheral logic between cores, as well as that level's logic involved in integrating the cores. If this higher level is not the chip level, those patterns must also be retargeted to the chip level.

[0034] Although the same test pattern generation and retargeting methodology logic applies recursively regardless of the level of hierarchy, planning and design for test (DFT) becomes more complex with additional levels of hierarchy when using traditional scan access methods.

[0035] Planning and implementing hierarchical scan test in a SOC presents several challenges, most of which are related to providing access to scan channels in the cores. A scan channel is a channel that connects to the inputs / outputs of a scan chain, to the inputs / outputs of a test controller for test compression, or a combination of both. When retargeting and merging core-level patterns to the top level, typically a subset of cores are tested at any given time for two reasons. First, power dissipation may not allow all cores to be tested simultaneously. Second, the limited number of chip-level inputs / outputs (I / Os, or ports) does not allow access to all core-level channels simultaneously.

[0036] Any group of cores to be tested simultaneously must have their channel inputs and outputs connected to different chip-level I / O when employing a traditional point-to-point scan access method (sometimes called a star or switch topology). Typically, there are more core-level channels of chip-level I / O available for scan, so pin availability limits the number of cores that can be tested simultaneously, and therefore the number of groups (test sessions). Each top-level I / O can be connected to a different core-level pin for each group. As the number of cores increases and the amount of chip-level I / O available for scan test decreases, fewer cores can be directly accessed by the chip-level I / O and tested simultaneously.

[0037] A relatively recent trend in SOC design, called tile-based layout, adds further complexities and constraints to the DFT architecture. In tile-based design, virtually all logic and routing is done within the cores, not at the top level. Cores abut each other when integrated into the chip with connections flowing from one core to the next. Connections between cores must pass through cores between cores. Logic that is logically at the top level must be pushed into the cores and designed as part of the cores.

[0038] To overcome the test access challenge, we proposed a generic packet-based core access architecture. In this architecture, each parallel word contains the address of the core (or group of cores) to which the information is destined, an opcode indicating what to do with that data, and the actual payload. This architecture works for both heterogeneous and homogeneous cores. For homogeneous cores, it supports efficient broadcast of stimuli and accumulation of expected values ​​(good machine response), on-chip comparison, and pass / fail data so that multiple homogeneous cores can be tested in near-constant time. However, this architecture is not efficient due to its significant overhead in every parallel word. Non-payload information, i.e., address and opcode, occupies a constant number of bits. Very narrow buses would not be able to support this architecture.

[0039] Another packet-based core access architecture reserves all streamed packets for the actual payload and employs a separate serial network to set up the core interface for communication with the parallel data streaming network. FIG. 2 shows an example of such a data streaming system 200 in a circuit. The data streaming system 200 comprises a first network 220 and a second network 230. The first network 220 comprises a first data channel 227 (first data bus) and a first interface device 225 (also called a circuit block interface device). The second network 230 comprises one or more second data channels 237 (second data bus) and a second interface device 235. The first interface devices 225 comprise registers and clock signal generation logic. Each of the first interface devices 225 is coupled to a port of one of the circuit blocks 210 in the circuit 200. Also, each of the first interface devices 225 is coupled to one of the second interface devices 235. The inputs and outputs of the first data channel 227 can be connected to some chip-level I / O (GPIO pads). The inputs and outputs of one or more second data channels 237 can also be connected to some other chip-level I / O (GPIO pads). Although only one first network 220 and one second network 230 are shown in FIG. 2, a circuit can have multiple first networks 220 and one or more second networks 230.

[0040] The first data channel in the first network 220 may be formed by a chain of flip-flops, acting as a pipeline stage. Some of these flip-flops are in the first interface device 225. The first network 220 is configurable to transmit a plurality of data packets in succession, each of the plurality of data packets having m bits, each of the m bits being assigned to one of the circuit blocks 210 preconfigured in active mode. The second network 230 is configurable to transmit configuration data to the first interface devices. The configuration data includes data for determining whether a first interface device in the first interface device 230 is activated or not, and data for determining a bit or bits of each of the plurality of data packets to be captured, replaced, or captured, replaced and replaced by each of the activated first interface devices. The second network 230 may comply with the IEEE 1687 standard (IJTAG, Internal Joint Test Action Group).

[0041] The active mode of the circuit block may be a mode for testing or a mode for loading / unloading data, where m is equal to or greater than the number of first data channels 225 used to carry the plurality of data packets. The total number of first data channels for a manufactured circuit is typically fixed, but the number of first data channels used to transport the plurality of data packets may be less than the total number. For example, a setup for wafer testing may not require all of the first data channels 225, while a setup for testing the same circuit in a system may utilize all of the first data channels 225.

[0042] Assume that the number of initial data channels used to transport data packets is n. The first network 220 transports data packets at a rate of one n-bit word per clock cycle, and if m is greater than n, then according to various embodiments of the disclosed technology, the bit allocation to the circuit blocks 210 in the active mode for a particular n-bit word (bus word) is repeated every LCM(m,n) / n clock cycles, where LCM(m,n) is the least common multiple of m and n. In some bit allocations, the bits of each of the multiple data packets are divided into bit blocks, each bit of the bit block being adjacent to each other except for the bits at the two ends of the block, and each of the bit blocks is assigned to one of the circuit blocks pre-configured in the active mode. Each of the first interface devices activated can be configured to track the position of its data bits within each bus word.

[0043] FIG. 3 shows an example of bit allocation for the first data channel 225 used to transfer data packets. In this example, two circuit blocks (core A and core B) are driven through the first network - exchanging data in the first network. One of them loads / unloads 4 bits per shift cycle of the circuit block, and the other loads / unloads 5 bits. Thus, the size of each data packet is 9 bits. In the figure, "AI" means the data bits of core A, and "BI" means the data bits of core B. To shift two circuit blocks once, 9 bits (m=9) need to be sent out. The number of first data channels used for data streaming is 8. That is, the width of the bus that transmits the data is 8 bits (n=8). Thus, the position of the 9-bit packet in each 8-bit bus word rotates with each packet to use each bit of each bus word without using any unnecessary padding. As a result, the packet starts at the same bus bit position every 9 clock cycles. That is, the same bit allocation is repeated every 9 clock cycles. Furthermore, each data packet is divided into two bit blocks. For example, data packet 310 in FIG. 3 is divided into a bit block consisting of AI64-AI60 and a bit block consisting of BI60-BI63.

[0044] Data packets can be as wide as needed and occupy as many bus words as needed. The internal channel requirements (9 bits in the example shown in Figure 3) are decoupled from the scan pins available at the chip level (8 x 2 I / O for scan in this case). If the packet is wider than the bus and occupies multiple bus words, the circuit blocks can be shifted less frequently than once per bus shift cycle, but still drive all the circuit blocks required. The scan bus can usually shift data at a higher rate than the circuit blocks can shift internally, so that the circuit blocks can continue to be shifted at their maximum rate without having to shift every bus clock cycle. The bus (first data channel) can be reprogrammed to reduce its active width to not exceed the number of bits in the packet when the packet size (m) is smaller than the physical bus width (n).

[0045] The system for streaming data in a circuit implemented according to various embodiments of the disclosed technology can be used to send out different types of data in a circuit, such as data to be stored in a memory circuit and data for circuit testing. As mentioned above, hierarchical designs are widely used at present. Packet-based streaming based on the disclosed technology can greatly improve test efficiency and flexibility for SOC designs. Each data packet comprises one or more bits of a test pattern or a compressed test pattern to test one or more of the circuit blocks. As shown in FIG. 3, each data packet can include bits of multiple test patterns for testing different circuit blocks.

[0046] FIG. 4 shows an example of a first interface device (circuit block interface device) 400. The first interface device 400 has a number of static registers 410 labeled as IJTAG static registers. The number of static registers 410 are programmed (set) before streaming begins. IJTAG or other access mechanisms can be used to send data for programming. When the interface device 400 is powered up, bits in a bus word received from the bus in 420 are selected and sent to the scan_in port 430 while bits received from the scan_out port 440 are added to the bus word before being forwarded via the bus_out 450 of the interface device 400. Data bits in a word belonging to a given core can be rotated when the packet width is not a multiple of the bus width, so the interface device 400 can use a shifter to access the rights bits. Additionally, bits in a packet going to a core can be spread across multiple bus words, so it may be necessary to collect the data over multiple bus clock cycles before one shift cycle in the core can occur. The same happens with unloaded data. The data unloaded from one cycle of the core is inserted into a packet. The data may occupy a portion of a bus word, an entire bus word, or bits spanning multiple bus words. The interface device 400 has a clock generation circuit 470 for generating edt_clock 475 and shift_cap_clock 480. A finite state machine 490 (FSM) is used to generate the scan_en 492 and edt_update 495 signals. When the interface device 400 is not activated, the original bus word bypasses the internal logic and is selected by the multiplexer 460 for output. As such, the interface device 400 acts as a pipeline stage within the first network.

[0047] Referring to FIG. 2, the first network 220 may further include a multiplexer, a pipeliner, or both. FIG. 5 illustrates an example of a pipeliner 500 that may be implemented according to various embodiments of the disclosed technology. The pipeliner 500 may be used to meet timing requirements. If there is a long route between two cores, or between a core and a chip-level I / O, the propagation delay through that route may hinder the ability to operate the bus at a high frequency. To reduce the length of the route that data propagates within one cycle, one or more pipeliners may be inserted. Once data starts propagating through the first network 220 and the nodes in the network are filled with data, there is no loss of throughput due to the presence of additional nodes such as those pipeline stages. Their presence may slightly increase latency at the beginning of test application.

[0048] FIG. 6 illustrates an example of a multiplexer 600 that can be implemented according to various embodiments of the disclosed technology. The multiplexer 600 can select which of two predecessor nodes to connect to its output. It can serve the same purpose as a Segment Insertion Bit (SIB) node in the IJTAG standard. Such a node allows parts of the network to be included in the network or bypassed when inactive. This enables, among other things, 1) improving efficiency by bypassing parts of the network when they are not in use, 2) improving operational flexibility by allowing, for example, to power cores that include inactive sections of the network without disrupting the operation of the active sections of the network, 3) bypassing parts of the network when that section of the network has a manufacturing defect without disabling the entire network, and 4) allowing the use of the entirety of a wider width by linking different width sections of the network when the smaller width section is bypassed.

[0049] An architecture for utilizing data streaming networks to increase serial network bandwidth FIG. 7 illustrates an example of a system 700 that utilizes a data streaming network to increase serial network bandwidth implemented according to various embodiments of the disclosed technology. The system 700 includes a first network 710 (data streaming network) that can be configured to transmit data in parallel within a circuit. The first network 710 includes circuit block interface devices (not shown). Each of the circuit block interface devices is coupled to one port of a circuit block within the circuit. FIG. 4 illustrates an example of a circuit block interface device. The first network 710 can be configured to transmit test data into the circuit blocks and transmit test response data out of the circuit blocks through the circuit block interface devices. FIG. 7 illustrates that the circuit includes three circuit blocks: circuit block 750, circuit block 755, and circuit block 757.

[0050] The first network 710 may be implemented using two packet-based core access systems described above, such as the data streaming system 200 shown in Figure 2. Similar to the data streaming system 200, the first network 710 may be reconfigurable to allow one or more circuit blocks to be bypassed for data streaming. To achieve configurability, a device such as the multiplexing device 600 shown in Figure 6 may be employed.

[0051] The system 700 also includes a plurality of second networks, including second networks 720, 725, and 727, and a third network 730. Each of the plurality of second networks is configurable to serially transmit data within one of the circuit blocks in the circuit. As shown in FIG. 7, the second networks 720, 725, and 727 are located within circuit blocks 750, 755, and 757, respectively. The third network 730 is configurable to serially transmit data within the circuit while coupled to the plurality of second networks. The plurality of second networks and the third network 730 may be reconfigurable. Conventionally, the second networks 720, 725, and 727 are permanently coupled to the third network 730 to form a single network used, for example, for test setup. An example of such a network is the IJTAG network.

[0052] The system 700 further comprises a plurality of network switching interface devices, such as the network switching interface devices 740, 745 and 747 shown in FIG. 7. Each of the plurality of network switching interface devices is configurable to couple either the first network 710 or the third network 730 to one of a plurality of second networks based on control signals stored in each of the plurality of interface devices. For example, the network switching interface device 740 can enable the second network 720 to be coupled to either the first network 710 or the third network 730. The first network 710 is inherently parallel and can operate at a much higher frequency than the serial network formed by the combination of the third network 730 and the plurality of second networks. Thus, the ability to couple the first network 710 to the second networks 720, 725 and 727 can significantly increase the bandwidth for transmitting data in and out of the circuit blocks 750, 755 and 757 for devices served by the second networks 720, 725 and 727.

[0053] 8 illustrates an example of a network switching interface device 800 according to various embodiments of the disclosed technology. The network switching interface device 800 is configured to couple a local network 820 (second network) to either a serial network 830 (third network) or a parallel network 810 (first network) based on a control signal stored in a register 840. The control signal stored in the register 840 can be updated using the serial network 830 when the serial network 830 is coupled to the local network 820, or using the parallel network 810 when the parallel network 810 is coupled to the local network 820. Thus, access to the local network 820 via either the parallel network 810 or the serial network 830 can be actively changed.

[0054] FIG. 9 illustrates an example of a detailed block diagram of a network switching interface device 900 according to various embodiments of the disclosed technology. The network switching interface device 900 is configured to couple a local IJTAG network 920 (second network) to either a serial network 930 (third network) or a parallel network 910 (first network) depending on a control bit stored in a SIH enable register 950. The control bit stored in the SIH enable register 950 can be updated via either the first network 910 or the third network 930 depending on the bit stored before the update operation. The first network 910 has eight data channels SiN-SoN (N=0-7). Here, the data channels Si0-So0 are used to transmit a TMS signal (tms) when the local IJTAG network 920 is coupled to the first network 910. The TMS (Test Mode Select) signal is a control signal provided by a TAP controller compliant with JTAG (Joint Test Action Group, IEEE 1149.1). The network switching interface device 900 can use the TMS signal to drive a finite state machine (FSM) 949 that controls the shift, capture and update operations of the data registers. The other seven data channels SiN-SoN (N=1-7) can be used to transmit data in and out of the local IJTAG network 920 when the local IJTAG network 920 is coupled to the first network 910.

[0055] The network switching interface device 900 is configured with two registers 940 and 945 for the first network 910. Each of the registers 940 and 945 may include eight flip-flops, one for each data channel of the first network 910. The two flip-flops in the registers 940 and 945 for each channel are connected in series to function as two pipeline stages for the first network 910.

[0056] The network switching interface device 900 also includes a multiplexer device 947, a host SIB 960, a configuration SIB 970, a broadcast control unit 980, and a configuration unit 990. The multiplexer device 947 is configured to select one of seven data channels SiN-SoN (N=1-7) coupled to the local IJTAG network 920. The host SIB 960 and the configuration SIB 970 are typical IJTAG segment insertion bit devices as shown in FIG. 1. The host SIB 960 determines whether the local IJTAG network 920 is bypassed. The configuration SIB 970 determines whether the configuration unit 990 should be bypassed. Configuration unit 990 is configured to store control bits including those determining at which clock cycle (stored in register 991) local IJTAG network 920 receives data from the data channel of first network 910 (stored in register 992) and representing the ratio between the global clock frequency and the local clock frequency (stored in register 993). Broadcast control unit 980 is configured to store control bits for output from local IJTAG network 920 in a broadcast mode described below.

[0057] When a data streaming network (e.g., the first network 710 in FIG. 7) is coupled to a local serial network (e.g., the second network 720, 725, and 727 in FIG. 7), at least three coupling modes can be used. FIG. 10 illustrates an example of a data streaming network 1010 coupled to three local serial networks 1020, 1030, and 1040 in a daisy-chain mode, according to various embodiments of the disclosed technology. The data streaming network 1010 has eight data channels. The right-most data channel 1060 is configured to transmit a TMS signal, and the second-rightmost data channel 1050 is configured to transmit data in and out of the three local serial networks 1020, 1030, and 1040. Each of the three local serial networks 1020, 1030, and 1040 has a 2-bit shift element (1025, 1035, and 1045). Each of the three 2-bit shift elements 1025, 1035, and 1045 is coupled in parallel to a storage element (latch element) (1027, 1037, and 1047). In the daisy-chain mode, the data bits shifted in the data channel 1050 are shifted into the local serial network when the local serial network is selected based on the TSM bits shifted in the data channel 1060. The daisy-chain mode can also be such that the data bits captured by the local serial network are shifted back into the data channel 1050 based on the TSM bits shifted in the data channel 1060.

[0058] FIG. 11 shows an example of a TAP state machine 1100 that complies with the IEEE 1149.1-2013 standard. The TAP state machine 1100 advances on test clock (TCK) edges, with the value of the Test Mode Select (TMS) pin controlling the operation. Assuming the TAP state machine 1100 starts with a test logic reset, the test clock moves so that when TMS=0, the TAP state machine 1100 enters the Run Test / Idle state, and then when TMS=1, the TAP state machine 1100 enters the Select IR state, which allows it to enter either the Data Register path 1110 or the Instruction Register path 1120. The Data Register path 1110 includes three important states: Capture-DR, Shift-DR, and Update-DR. In the Capture-DR state, the shift elements of the data register load the data bits present on their parallel inputs. In the Shift-DR state, the shift elements of the data register shift the data bits along the scan path from TDI to TDO. In the Update-DR state, the data bits in the shift elements of the data register are latched into the storage elements of the data register.

[0059] FIG. 12 shows a table 1200 illustrating an example of some bits of the scan / storage element of FIG. 10 over 19 consecutive clock cycles (0-18). The TMS row shows the state change sequence of the TAP state machine of the local serial network 1020 as follows: Run-Test / Idol(1)→Select-DR-Scan(0)→Capture-DR(0)→Shift-DR(0)→Shift-DR(0)→Shift-DR(0)→Shift-DR(0)→Shift-DR(0)→Shift-DR(0)→Shift-DR(1)→Exit1-DR(1)→Update-DR(1)→Select-DR-Scan(0)→Capture-DR(0)→Shift-DR(0)→Shift-DR(0)→Shift-DR(0)→Shift-DR(0)→Shift-DR(0)→Shift-DR(0). Here, the numbers in parentheses are the TMS values. The 2-bit shift element 1025 captures C5 and C4 in clock cycle 4 and shifts these values ​​out subsequently. Similarly, the 2-bit shift element 1035 captures and shifts out C3 and C2, and the 2-bit shift element 1045 captures and shifts out C1 and C0. The sequence of "C0 C1 C2 C3 C4 C5" is finally shifted out through the data streaming network 1010. Meanwhile, S5 and S4 are shifted into the 2-bit shift element 1025 and then latched into the storage element 1027 in clock cycle 12, S3 and S2 are shifted into the 2-bit shift element 1035 and then latched into the storage element 1037 in clock cycle 16, and S1 and S0 are shifted into the 2-bit shift element 1045 and then latched into the storage element 1047 in clock cycle 18.

[0060] 13 illustrates an example of a data streaming network 1310 coupled to three local serial networks 1320, 1330, and 1340 in broadcast mode in accordance with various embodiments of the disclosed technology. Similar to the setup illustrated in FIG. 10, a right-most data channel 1360 of the data streaming network 1310 is configured to transmit a TMS signal, and a second right-most data channel 1350 is configured to transmit data to the three local serial networks 1320, 1330, and 1340. However, unlike the daisy-chain mode, the local serial networks in broadcast mode typically receive and latch the same data bits (S1 and S0 of the local serial networks 1320, 1330, and 1340, respectively, versus S1 and S0 of the local serial network 1040, S3 and S2 of the local serial network 1030, and S5 and S4 of the local serial network 1020). Furthermore, only the last local serial network 1340 captures and shifts out data bits via the data streaming network 1310. The state change sequence of the TAP state machine is Run-Test / Idle(0) → Run-Test / Idle(1) → Select-DR-Scan(0) → Capture-DR(0) → Shift-DR(0) → Shift-DR (1) → Exit1-DR(1) → Update-DR(0) → Run-Test / Idle.

[0061] FIG. 14 illustrates an example of a data streaming network 1410 coupled to two local serial networks 1420 and 1430 in a parallel mode according to various embodiments of the disclosed technology. In this setup, a data channel 1440 is configured to transmit data to and from the local serial network 1420, and another data channel 1450 is configured to transmit data to and from the local serial network 1430. The above three modes (daisy-chain mode, broadcast mode, and parallel mode) can be used alone or in any combination according to various embodiments of the disclosed technology. For example, some local networks are coupled to the data streaming network in a broadcast mode, and the remaining local networks are coupled to the data streaming network in a daisy-chain mode via different data channels of the data streaming network.

[0062] FIG. 15 shows an example of a data streaming network 1510 coupled to two local serial networks 1520 and 1530 in a time slot multiplexing mode according to various embodiments of the disclosed technology. The data streaming network can usually operate in the high 100 MHz range, while the IJTAG network often operates at 20 MHz due to various limitations. Using some techniques such as clock stretching around some extra clock cycles, the IJTAG network can operate in the low 100 MHz range. To match the local IJTAG network, the data streaming network can operate at a reduced clock speed. If more bandwidth is required, the time slot multiplexing mode can be used. In the example shown in FIG. 15, the data streaming network 1510 is assumed to operate at 400 MHz, while the local serial networks 1520 and 1530 are assumed to operate at 100 MHz. The local serial networks 1520 and 1530 can be preconfigured to scan 1 bit out of every 4 bits scanned by the data streaming network 1510. The specific position of every 4 bits scanned in (called phase) can be programmed as well. In the setup shown in FIG. 15, the phase is the same for the two local serial networks 1520 and 1530. The two local serial networks 1520 and 1530 can operate in daisy chain mode or broadcast mode. To use multiple phases for multiple local networks, the local networks can be coupled to the data streaming network 1510 in parallel mode, i.e., coupled to multiple data channels of the data streaming network 1510, as shown in FIG. 13.

[0063] The local network transmits data primarily serially. In some circumstances, the local network may include a section configurable to transmit data in parallel. This section can be coupled to the data streaming network in parallel. FIG. 16 shows an example of a memory BIST (built-in self test) section 1610 of a local network 1620 configurable to be coupled to a data streaming network 1630 (first network) in parallel, according to various embodiments of the disclosed technology. The network switching interface device 1640 has two devices 1645 and 1647. When the device 1645 couples the local network 1620 to a third network 1650, the memory BIST section 1610 can be accessed via the coupled serial network. When the device 1647 couples the local network 1620 to the data streaming network 1630, the device 1647 can couple the memory BIST section 1610 to the data streaming network 1630 in parallel, i.e., to multiple data channels of the data streaming network 1630. This allows multiple memory BIST controllers to be accessed simultaneously, further increasing bandwidth.

[0064] FIG. 17 shows a flowchart 1700 illustrating a process of setting up a circuit test over a high bandwidth serial network enabled by a data streaming network implemented according to various examples of the disclosed technology. For ease of understanding, a method for setting up a circuit test over a high bandwidth serial network enabled by a data streaming network employed according to various embodiments of the disclosed technology will be described with reference to the system 700 of FIG. 7 and the flowchart 1700 shown in FIG. 17. However, it should be understood that alternative implementations of a system utilizing a data streaming network to increase the bandwidth of the serial network may be used to perform the method for setting up a circuit test over a high bandwidth serial network enabled by a data streaming network illustrated by the flowchart 1700 according to various embodiments of the disclosed technology. Similarly, the system 700 may be employed to implement other methods for setting up a circuit test over a high bandwidth serial network enabled by a data streaming network according to various embodiments of the disclosed technology.

[0065] In operation 1710 of the flowchart 1700, network configuration data is transmitted over a third network 730 coupled to a plurality of second networks including second networks 720, 725, and 727. The network configuration data includes first network switching interface control data for a plurality of network switching interface devices including network switching interface devices 740, 745, and 747. The first network switching interface control data enables each of the plurality of network switching interface devices to disconnect one of the plurality of second networks from the third network 730 and couple one of the plurality of second networks to the first network 710. The network configuration data may further include network reconfiguration data for a plurality of multiplexing devices. The network reconfiguration data enables the first network 710 to bypass one or more of the circuit blocks. The plurality of second networks are reconfigurable and initially configured to enable the plurality of network switching interface devices and to bypass most devices other than the multiplexing devices, possibly. As a result, data transmission is not significantly slowed down despite the third network 730 being used.

[0066] In operation 1720, the setup data is transmitted over the first network 710, which is coupled to a plurality of second networks, including the second networks 720, 725, and 727. The setup data includes test setup data for the circuit blocks, network configuration data for communication between the first network and the circuit blocks, and second network switching interface control data for a plurality of network switching interface devices. The test setup data may include data for configuring various test controllers, on-chip clock controllers, phase-locked loop (PLL) clock generators, or any combination thereof. The network configuration data may be used to configure devices such as the circuit block interface devices (e.g., the first interface device 225 shown in FIG. 2). The speed of data transmission is significantly increased over the first network 710 as compared to the third network 730, especially considering the amount of data transmitted. The second network switching interface control data enables each of the plurality of network switching interface devices to, after setup, disconnect one of the plurality of second networks from the first network 710 and couple one of the plurality of second networks to the third network 730.

[0067] Optionally, in operation 1730, interface enable data is sent over a third network 730 coupled to the plurality of second networks to enable circuit block interface devices in the first network 710 and then send the test data. To ensure proper operation of some types of the first network 710, the first network 710 should be idled before the circuit block interface devices are turned on.

[0068] In operation 1740, the test data is transmitted to the circuit block via the first network 710. The circuit block may then be tested.

[0069] The disclosed technique allows local networks within a circuit block to not only benefit from the parallelism and high speed capabilities of the data streaming network within the circuit, but also to increase their own operating speed by using clock stretching techniques while being pipelined. FIG. 18 shows example waveforms of some clock and control signals illustrating the clock stretching technique. To meet the timing requirements of some clock control signals, the clocks of the IJTAG network usually run slower than 100 MHz. However, this limitation can be significantly mitigated by increasing the clock frequency when the control signals are not transitioning. As FIG. 18 shows, the ToCaptureEn signal 1810 and the ToShiftEn signal 1820 are transitioning between the Capture DR state 1850 and the ShiftDR state 1860 immediately following the Capture DR state 1850, and the ToShiftEn signal 1820 and the ToUpdateEn signal 1830 are transitioning between the Exit DR state 1870 and the Update DR state 1880. Thus, the tck_stretched clock signal 1840 only needs to be stretched for four states. In the figure, it has been stretched to run at a three hour slower speed. Note that Figure 18 is only an example, and the clock can be stretched to run at a faster or slower speed than that shown in the figure.

[0070] Stretching the global clock 1070 in FIG. 10 is infeasible because the local serial networks 1020, 1030, and 1040 are pipelined and do not change to the same state at the same time. On the other hand, the locally generated clocks for these local serial networks 1020, 1030, and 1040 can be stretched for the Capture DR state, the Shift DR state immediately following the Capture DR state, the Exit1 DR state, and the Update DR state during the execution of the global clock 1070. As a result, each local serial network can operate at a shift rate of 200 MHz or more with various implementations of the disclosed techniques, which is much faster than typical IJTAG networks in larger circuits. A register 995 in the configuration unit 990 in FIG. 9 can be used to store control signals that determine the number of clock cycles to be stretched for those four states.

[0071] Exemplary Computing Environment Some embodiments of the disclosed techniques related to generating a system of streaming data in a circuit design can be implemented through the execution of software instructions by a computing device, such as a programmable computer. FIG. 19 shows an illustrative example of such a programmable computer (computing device 1901). As seen in this figure, computing device 1901 includes a computing unit 1903 with a processing unit 1905 and a system memory 1907. Processing unit 1905 is any type of programmable electronic device for executing software instructions, but is conventionally a microprocessor. System memory 1907 may include both read-only memory 1909 and random access memory 1911. As will be appreciated by those skilled in the art, both read-only memory 1909 and random access memory 1911 can store software instructions for execution by processing unit 1905.

[0072] The processing unit 1905 and the system memory 1907 are connected, directly or indirectly, to one or more peripheral devices through a bus 1913 or alternative communication structure. For example, the processing unit 1905 or the system memory 1907 are connected, directly or indirectly, to one or more additional memory storage devices, such as a "hard" magnetic disk drive 1915, a removable magnetic disk drive 1917, an optical disk drive 1919, or a flash memory card 1921. The processing unit 1905 and the system memory 1907 are also connected, directly or indirectly, to one or more input devices 1923 and one or more output devices 1925. The input devices 1923 can include, for example, a keyboard, a pointing device (such as a mouse, touch pad, stylus, trackball, or joystick), a scanner, a camera, and a microphone. The output devices 1925 can include, for example, a monitor display, a printer, and speakers. Depending on the various implementations of computer 1901, one or more of peripherals 1915-1925 may be housed internally with computing unit 1903. Alternatively, one or more of peripherals 1915-1925 may be external to the housing for computing unit 1903 and connected to bus 1913, for example, via a Universal Serial Bus (USB) connection.

[0073] In some implementations, the computing unit 1903 may be directly or indirectly connected to one or more network interfaces 1927 for communicating with other devices constituting a network. The network interfaces 1927 convert data and control signals from the computing unit 1903 into network messages according to one or more communication protocols, such as the Transmission Control Protocol and the Internet Protocol. Additionally, the interfaces 1927 may employ any suitable connection agent (or combination of agents) for connecting to a network, including, for example, a wireless transceiver, a modem, or an Ethernet connection. Such network interfaces and protocols are well known in the art and therefore will not be discussed in further detail herein.

[0074] It should be understood that computer 1901 is illustrated by way of example only, and not by way of limitation. Various embodiments of the disclosed technology may be implemented using one or more computing devices that include the configuration elements of computer 1901 shown in Figure 19, including only a subset of the configuration elements shown in Figure 19, or including alternative combinations of configuration elements including configuration elements not shown in Figure 19. For example, various embodiments of the disclosed technology may be implemented using a multi-processor computer, multiple single- and / or multi-processor computers arranged in a network, or some combination of both.

[0075] conclusion Although the disclosed technology has been described with respect to specific examples including presently preferred modes for carrying out the disclosed technology, those skilled in the art will appreciate that there are numerous variations and permutations of the above-described systems and techniques that fall within the spirit and scope of the disclosed technology as set forth in the appended claims. For example, while the data streaming network shown in Figure 2 has been employed to illustrate the disclosed technology, it should be understood that other parallel networks can be utilized to increase the bandwidth of the serial network.

Claims

1. A system in a circuit comprising: a first network configured to transmit data in parallel within the circuit, the first network comprising circuit block interface devices, each of the circuit block interface devices coupled to a port of one of the circuit blocks within the circuit; a plurality of second networks, each of the plurality of second networks configured to transmit data serially to one of the circuit blocks in the circuit; a third network configured to serially transmit data within said circuit when said circuit is connected to said plurality of second networks; a plurality of network switching interface devices, each of the plurality of network switching interface devices configured to couple either the first network or the third network to one of the plurality of second networks based on control signals stored in each of the plurality of network switching interface devices; A system equipped with

2. The control signal stored in each of the plurality of network switching interface devices comprises: using the third network when the third network is coupled to the one of the plurality of second networks; or using the first network when the first network is coupled to the one of the plurality of second networks; It is updatable, The system of claim 1 .

3. 2. The system of claim 1, wherein the plurality of second networks are configured to be coupled to the first network in a daisy-chain mode, a parallel mode, a broadcasting mode, or a combination thereof.

4. the first network operates at a clock frequency that is a multiple (greater than one) of a clock frequency at which the plurality of second networks operate; the plurality of second networks are coupled to the first network in a time slot multiplexing mode; The system of claim 1 .

5. 2. The system of claim 1, wherein a second network of the plurality of second networks includes a section configured to transmit data in parallel that is configured to be coupled to the first network in parallel.

6. 2. The system of claim 1, wherein one or more of the plurality of second networks employ a clock stretching technique that increases a clock frequency when the control signal is not transitioning to increase a shift speed.

7. The system of claim 1, wherein the third network and the plurality of second networks are combined to form a single IJTAG network used for test configuration in accordance with the IEEE 1687 standard (IJTAG, Internal Joint Test Action Group) developed in 2014.

8. the first network further comprises a multiplexing device; the multiplexing device is configured to modify a data streaming path of the first network based on the control signal transmittable to the multiplexing device via the first network or the plurality of second networks coupled to the third network; The system of claim 1 .

9. each of the plurality of second networks includes a configuration interface device; the configuration interface unit is coupled to one of the circuit block interface units; configuration data for the configuration interface device is transmittable over the respective one of the plurality of second networks coupled to either the first network or the third network; the configuration data includes data determining whether a circuit block interface device of the circuit block is operational and data determining which portions of data transmitted to the first network are to be captured, replaced, or both captured and replaced by each of the circuit block interface devices that is operational; The system of claim 1 .

10. the circuit block interface device includes a register and a clock signal generation logic; the first network includes a data channel and is configured to transmit a plurality of data packets in succession; each of the plurality of data packets having a plurality of bits; each of the plurality of bits being assigned to one of the circuit blocks in which the circuit block interface device is operating; the number of bits is equal to or greater than the number of data channels used to transmit the data packets; The system of claim 1 .

11. each of the plurality of data packets includes one or more bits of a test pattern or a compressed test pattern for testing one or more of the circuit blocks; the clock signal generation logic of a circuit block interface device coupled to a port of one of the circuit blocks is configured to generate a clock signal for scan-based testing; the ports of one of the circuit blocks include inputs and outputs of a scan chain, inputs and outputs of one or more test controllers, or a combination thereof; each of the one or more test controllers includes an expander and a compactor; The system of claim 10.

12. 1. A method for testing a circuit, comprising: transmitting network configuration data over a third network coupled to the plurality of second networks, the third network is configured to transmit data serially within the circuit; each of the plurality of second networks is configured to transmit data to one of the circuit blocks of the circuit; the network configuration data includes first network switching interface control data for a plurality of network switching interface devices; the first network switching interface control data operates each of the plurality of second networks to decouple one of the plurality of second networks from the third network and to couple the one of the plurality of second networks to a first network; the first network is configured to transmit data in parallel within the circuit; Steps and transmitting setup data over the first network coupled to the plurality of second networks; the setup data includes test setup data for the circuit block, network setup data for communication between the first network and the circuit block, and second network switching interface control data for the plurality of network switching interface devices; the second network switching interface control data operates the plurality of network switching interface devices to isolate one of the plurality of second networks from the first network and to couple the one of the plurality of second networks to the third network. Steps and transmitting test data to the circuit block via the first network; The method includes:

13. 13. The method of claim 12, wherein the network configuration data further comprises network reconfiguration data for a plurality of multiplexing devices, the network reconfiguration data causing the first network to bypass one or more of the circuit blocks.

14. 13. The method of claim 12, further comprising the step of transmitting interface enabling data over the third network coupled to the plurality of second networks, activating a circuit block interface device between the first network and the circuit block prior to the step of transmitting the test data.

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