Multilayer wiring board and method for manufacturing the same

Abstract

To provide a multilayer wiring board and a method for manufacturing the same with high connection reliability by reducing delamination at the resin / via layer resin interface of the trench layer due to warpage and internal stress during heating in the method of forming multilayer wiring layers on a support substrate and mounting them on an FC-BGA substrate.SOLUTION: In a wiring board including a via layer 18 in which vias are formed and a trench layer 19 formed with lands and wiring on the via layer, on the sides and bottom of conductive portions of the trench layer and via layer, and on concave sides formed by making the lands and wiring, which are conductors of the trench layer, less thick than the non-conductive portions, at least a seed adhesion layer is present. A chemical adhesion layer is formed between the trench layer and the via layer 29 adjacent to the trench layer.SELECTED DRAWING: Figure 15

Description

[Technical field]

[0001] The present invention relates to a multilayer wiring board and a method for manufacturing the multilayer wiring board. [Background technology]

[0002] In recent years, as semiconductor devices have become faster and more highly integrated, there is a demand for narrower pitches for the connecting terminals with the semiconductor elements and finer wiring within the board for FC-BGA (Flip Chip-Ball Grid Array) boards on which semiconductor elements are mounted. On the other hand, there is a demand for connecting terminals with almost the same pitch as before for connecting FC-BGA boards to motherboards. In order to accommodate the narrower pitch of the connecting terminals with semiconductor elements and the accompanying finer wiring within the FC-BGA substrate, a technology has been adopted in which a multilayer wiring substrate containing fine wiring, also known as an interposer, is placed between the FC-BGA substrate and the semiconductor element. One of them is silicon interposer technology, in which an interposer is formed on a silicon wafer using semiconductor circuit manufacturing technology. Also, a method has been developed in which an interposer is directly fabricated on an FC-BGA substrate, rather than being formed on a silicon wafer. This is a method in which the surface of the FC-BGA substrate is flattened by CMP (Chemical Mechanical Polishing) or the like, and a multilayer wiring substrate that will become the interposer is directly formed on the FC-BGA substrate. This method is disclosed in Patent Document 1. Furthermore, there is a method in which an interposer (multilayer wiring board) is formed on a support such as a glass substrate, and then this is mounted on an FC-BGA substrate, and the support is then peeled off to form a narrow-pitch multilayer wiring board on the FC-BGA substrate. This method is disclosed in Patent Document 2. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2014-225671 A [Patent Document 2] International Publication No. 2018 / 047861 Summary of the Invention [Problem to be solved by the invention]

[0004] Silicon interposers are made from silicon wafers using equipment for front-end semiconductor manufacturing processes, making them suitable for forming fine wiring layers. However, silicon wafers are limited in shape and size, and only a small number of interposers can be made from a single wafer. In addition, the manufacturing equipment is expensive, making the interposers expensive. In addition, because silicon wafers are semiconductors, there is also the problem of degradation of transmission characteristics.

[0005] In addition, in the method of flattening the surface of the FC-BGA substrate and forming multiple wiring layers on it to serve as an interposer, the deterioration of transmission characteristics seen in silicon interposers is small, but there are issues with the overall low manufacturing yield due to problems with the manufacturing yield of the FC-BGA substrate itself and the high difficulty of forming fine wiring on the FC-BGA substrate. Furthermore, there are also issues with mounting semiconductor elements due to warping and distortion of the FC-BGA substrate.

[0006] Furthermore, in a method in which a multilayer wiring board is formed on a support such as a glass substrate, and then the support is peeled off after the multilayer wiring board is placed on an FC-BGA substrate, a semi-additive method is often used when forming a multilayer wiring layer on the support. However, the insulating resin layer used in the semi-additive method does not contain a filler, and tends to have a lower elastic modulus and a larger CTE (coefficient of thermal expansion) than the underfill layer and solder resist layer that contain a filler used in the subsequent process.

[0007] Therefore, regardless of which method is used, only the insulating resin layer may deform significantly when heated, causing the board to warp. In addition, if stress is generated inside the wiring layer, it may cause peeling of the internal conductor layer such as the fine wiring layer, cracks starting from the peeled area, or delamination at the interface between the layers that form the wiring layer, making it difficult to ensure connection reliability.

[0008] SUMMARY OF THE PRESENT DISCLOSURE The present invention has been made in consideration of the above problems, and has an object to provide a multilayer wiring board that is resistant to warping of the board and stress within the wiring layers, and a method for manufacturing the multilayer wiring board. [Means for solving the problem]

[0009] In order to solve the above problems, one representative multilayer wiring board of the present invention is a multilayer wiring board having two or more wiring layers, the wiring layers including a first layer including a first conductor portion and a first non-conductor portion, and a second layer including a second conductor portion and a second non-conductor portion, The second layer has a different thickness between a region where the second conductor portion is disposed and a region where the second conductor portion is not disposed, and has an uneven upper surface.

[0010] In addition, one of the representative methods for producing a multilayer wiring board of the present invention is 1) forming a pattern of the first non-conductor portion; 2) forming a pattern of the second non-conductor portion above the pattern of the first non-conductor portion; 3) sequentially providing a seed adhesion layer and a seed layer on side and bottom surfaces of the first non-conductive portion pattern and the second non-conductive portion pattern; 4) forming a conductive material on the seed layer to form a first conductor portion and a second conductor portion; 5) forming an uneven shape on the surface of the second conductor by varying the thickness between an area where the second conductor is disposed and an area where the second conductor is not disposed on the surface of the second conductor; 6) Steps 1) to 5) are repeated for the number of desired wiring layers. Effect of the Invention

[0011] According to the present invention, it is possible to provide a multilayer wiring board that is resistant to warping of the board and stress inside the wiring layers, and a manufacturing method thereof. Problems, configurations and effects other than those described above will become apparent from the following description of the embodiments. [Brief description of the drawings]

[0012] [Figure 1] 1 is a cross-sectional view showing a state in which a multilayer wiring board and an FC-BGA board are joined and a semiconductor element is mounted. [Diagram 2] 1 is a cross-sectional view showing a state in which a release layer, a photosensitive resin layer pattern, a seed adhesion layer, a seed layer, and a conductor layer are formed above a support. [Diagram 3] FIG. 2 is a cross-sectional view showing a state in which a first layer pattern is formed after surface polishing. [Figure 4] FIG. 2 is a cross-sectional view showing a state in which a second layer pattern is formed on an upper surface of a first layer pattern. [Diagram 5] FIG. 2 is a cross-sectional view showing a state in which a seed adhesion layer is formed. [Figure 6] 1 is a cross-sectional view showing a state in which a seed layer is formed on a seed adhesion layer. [Figure 7] FIG. 2 is a cross-sectional view showing a state in which a conductor layer is formed on a seed layer. [Figure 8] FIG. 11 is a cross-sectional view showing a state in which the conductor layer and the seed layer have been removed by CMP (chemical mechanical polishing). [Figure 9] 11 is a cross-sectional view showing a state in which an uneven shape is formed on the surface of a second conductor. FIG. [Figure 10] FIG. 4 is a cross-sectional view showing a state in which a chemical adhesion layer is formed. [Figure 11] FIG. 13 is a cross-sectional view showing a state in which a multilayer wiring is formed by repeating the steps shown in FIGS. [Figure 12] 1 is a cross-sectional view showing a state in which a photosensitive resin layer, a seed adhesion layer, a seed layer, and a resist pattern are formed on the upper surface of a chemical adhesion layer, and a conductor layer is formed. FIG. [Figure 13]FIG. 4 is a cross-sectional view showing a state in which a solder resist layer is formed. [Figure 14] 1 is a cross-sectional view showing a state in which a surface treatment layer and a solder joint are formed and a wiring board on a support is completed. FIG. [Figure 15] FIG. 4 is an enlarged detailed cross-sectional view of a surrounding portion in the present embodiment. [Figure 16] FIG. 11 is an enlarged detailed cross-sectional view of a surrounding portion in a comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, an example of a multilayer wiring board according to one embodiment of the present invention and a manufacturing process thereof will be described with reference to FIGS. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc., differ from the actual ones. Therefore, the specific thickness and dimensions should be determined by taking into consideration the following explanation. Furthermore, it goes without saying that the drawings include parts whose dimensional relationships and ratios differ from one another. It should also be noted that in some drawings, the same part may be shown upside down.

[0014] In addition, the embodiments shown below are merely examples of devices and methods for embodying the technical idea of ​​the present invention, and the technical idea of ​​the present invention does not specify the materials, shapes, structures, arrangements, etc. of the components to those described below. The technical idea of ​​the present invention can be modified in various ways within the technical scope defined by the claims.

[0015] In this disclosure, the term "surface" may refer not only to the surface of a plate-shaped member, but also to the interface of a layer contained in the plate-shaped member that is approximately parallel to the surface of the plate-shaped member. Additionally, the terms "upper surface" and "lower surface" refer to the surface shown at the top or bottom of a drawing of a plate-shaped member or a layer contained in the plate-shaped member. The term "side surface" refers to a surface of a plate-like member or a layer included in a plate-like member, or a portion of the thickness of a layer. Furthermore, a part of a surface and a side surface may be collectively referred to as an "end portion." In addition, "upper" refers to the vertically upward direction when a plate-like member or layer is placed horizontally. Furthermore, "upper" and its opposite, "lower", are sometimes referred to as the "Z-axis direction", and the horizontal direction is sometimes referred to as the "X-axis direction" or the "Y-axis direction". Additionally, the terms "planar shape" and "plan view" refer to the shape of a surface or layer when viewed from above. Furthermore, the terms "cross-sectional shape" and "cross-sectional view" refer to the shape of a plate-like member or layer when cut in a specific direction and viewed from the horizontal direction. Furthermore, the term "central portion" refers to the central portion other than the peripheral portion of the surface or layer, and the term "toward the center" refers to the direction from the peripheral portion of the surface or layer toward the center of the planar shape of the surface or layer.

[0016] The multilayer wiring board 30 of this embodiment can be connected to a semiconductor element on a first surface, and can be connected to another wiring board on a second surface. First, as shown in FIG. 1, a semiconductor device 16 manufactured using the multilayer wiring board 30 of this embodiment will be described in its entirety. In FIG. 1, a semiconductor element 17 is bonded to the upper surface of a multilayer wiring board 30 , and an FC-BGA substrate 14 is bonded to the lower surface of the multilayer wiring board 30 .

[0017] The semiconductor element 17 is joined to the multilayer wiring board 30 at solder joints 25, and then sealed and fixed with sealing resin 26. The multilayer wiring board 30 is joined to the FC-BGA substrate 14 at solder joints 27, and then sealed and fixed with sealing resin 28.

[0018] As described below, the multilayer wiring board 30 is formed above the support 1 with a release layer 2 interposed therebetween, and after being bonded to the FC-BGA substrate 14 together with the support 1, the support 1 is peeled off and removed by the release layer.

[0019] The semiconductor element 17 may be joined to the multilayer wiring board 30 after the multilayer wiring board 30 is joined to the FC-BGA substrate 14, or may be joined to the multilayer wiring board 30 before the multilayer wiring board 30 is joined to the FC-BGA substrate 14. In the following description of the embodiment, a form in which the semiconductor element 17 is joined to the multilayer wiring board 30 after the multilayer wiring board 30 is joined to the FC-BGA substrate 14 will be described. Next, the configuration of the multilayer wiring board 30 and a manufacturing method thereof will be described with reference to FIGS. FIG. 2 is a cross-sectional view showing a state in which a release layer 2, a photosensitive resin layer 3, a seed adhesion layer 4, a seed layer 5, and a conductor layer 6 are formed above a support. The steps for obtaining the configuration shown in FIG. 2 will be described below in order.

[0020] (1) Formation of a release layer 2 on the upper surface of a support 1 First, a release layer 2 is formed on one surface of a support 1 . The support 1 is advantageously light-transmitting since light may be irradiated onto the peeling layer 2 through the support 1, and rectangular glass, for example, may be used. Rectangular glass is suitable for large size, and glass has excellent flatness and high rigidity, making it suitable for forming a fine pattern on the support. In addition, glass has a small CTE and is resistant to distortion, and is therefore excellent in ensuring pattern placement accuracy and flatness. When glass is used as the support 1, the thickness of the glass is preferably large in order to suppress the occurrence of warping in the manufacturing process, and is, for example, 0.7 mm or more, and preferably 1.1 mm or more.

[0021] Furthermore, the CTE of the glass is preferably 3 ppm or more and 15 ppm or less, and from the viewpoint of compatibility with the CTE of the FC-BGA substrate 14 and the semiconductor element 17, it is more preferably about 9 ppm. On the other hand, in cases where light transmittance is not required for the support 1 when peeling off the support 1, for example, when a resin that foams when heated is used for the peel-off layer 2, the support 1 can be made of a material with less distortion, such as metal or ceramics. In the following, an embodiment of the present invention will be described taking as an example a case where a resin that absorbs UV light and becomes peelable is used as the release layer 2, and glass is used as the support 1.

[0022] The release layer 2 may be made of, for example, a resin that becomes peelable by absorbing light such as UV light and generating heat or by being altered, or a resin that becomes peelable by foaming due to heat. Furthermore, the release layer 2 may contain additives such as a photodecomposition accelerator, a light absorber, a sensitizer, and a filler.

[0023] Furthermore, the release layer 2 may be composed of multiple layers, and for example, for the purpose of protecting the multilayer wiring layer formed on the support 1, a protective layer may be further provided on the release layer 2, or a layer for improving adhesion to the support 1 may be provided under the release layer 2. Furthermore, a laser light reflecting layer or a metal layer may be provided between the release layer 2 and the multilayer wiring layer, and the configuration is not limited to this embodiment. In addition, when a resin that can be peeled off by light such as UV light, for example laser light, is used as the peeling layer 2, if the support 1 is translucent, the direction in which light is irradiated onto the peeling layer 2 may be the side opposite to the side on which the peeling layer 2 is provided.

[0024] (2) Forming a photosensitive resin layer 3 on the upper surface of the release layer 2 After a release layer 2 is formed on the upper surface of the support 1, a photosensitive resin layer 3 is formed on the upper surface of the release layer 2. In this embodiment, for example, a photosensitive epoxy resin is used as the photosensitive resin layer 3, and this is formed by a spin coating method. Photosensitive epoxy resin can be cured at a relatively low temperature and shrinks little due to curing after formation, so it is excellent for the subsequent formation of fine patterns.

[0025] (3) Patterning of the photosensitive resin layer 3 Next, openings are provided in the photosensitive resin layer 3 by photolithography. The openings may be subjected to plasma treatment in order to remove residues from development. The thickness of the photosensitive resin layer 3 is set according to the thickness of the conductor layer to be formed in the openings, and in one embodiment of the present invention, the thickness is set to, for example, 7 μm. The shape of the openings in plan view is set according to the pitch and shape of the bonding electrodes of the semiconductor element, and in one embodiment of the present invention, the openings have a diameter of 25 μm and are formed at a pitch of 55 μm.

[0026] (4) Formation of seed adhesion layer 4 and seed layer 5 Next, the seed adhesion layer 4 and the seed layer 5 are formed in a vacuum. The seed adhesion layer 4 is a layer that improves the adhesion of the seed layer 5 to the photosensitive resin layer 3 and prevents the seed layer 5 from peeling off. The seed layer 5 acts as a power supply layer for electrolytic plating in forming wiring. The seed adhesion layer 4 and the seed layer 5 are formed by, for example, a sputtering method or a vapor deposition method, and may be made of, for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO, IZO, AZO, ZnO, PZT, TiN, Cu3N4, Cu alloy, or a combination of a plurality of these. In the present invention, taking into consideration the electrical characteristics, ease of manufacture, and cost, a titanium layer is used as the seed adhesion layer 4, followed by a copper layer as the seed layer 5, which are formed in sequence by sputtering. The total thickness of the titanium and copper layers is preferably 1 μm or less as a power supply layer for electrolytic plating. In one embodiment of the present invention, Ti: 50 nm, Cu: 300 nm are formed.

[0027] 2, a conductor layer 6 is formed above the seed layer 5 by electrolytic plating. The conductor layer 6 serves as an electrode for bonding to the semiconductor element 17. Examples of electrolytic plating include nickel electrolytic plating, copper electrolytic plating, chromium electrolytic plating, Pd electrolytic plating, gold electrolytic plating, rhodium electrolytic plating, and iridium electrolytic plating. Of these, copper electrolytic plating is preferable because it is simple, inexpensive, and has good electrical conductivity. The thickness of the electrolytic copper plating is desirably 1 μm or more from the viewpoint of solder bonding, and 30 μm or less from the viewpoint of productivity, since this portion serves as an electrode for bonding to the semiconductor element 17. In one embodiment of the present invention, Cu: 9 μm is formed in the openings of the photosensitive resin layer 3, and Cu: 2 μm is formed on the upper part of the photosensitive resin layer 3.

[0028] Next, the following steps are carried out to obtain the configuration of FIG. (6) Polishing of Conductive Layer 6 2, the copper layer of the conductor layer 6 is polished by CMP (chemical mechanical polishing) or the like to remove the conductor layer 6 and the seed layer 5. The polishing is performed so that the seed adhesion layer 4 and the conductor layer 6 become the surface. In one embodiment of the present invention, Cu: 2 μm of the conductor layer 6 formed on the upper surface of the photosensitive resin layer 3 and Cu: 300 nm of the seed layer 5 are removed by polishing.

[0029] (7) Polishing of the seed adhesion layer 4 and the photosensitive resin layer 3 Next, polishing such as CMP processing is performed again to remove the seed adhesion layer 4 and a part of the photosensitive resin layer 3. In polishing the different materials of the seed adhesion layer 4 and the photosensitive resin layer 3, the effectiveness of chemical polishing is low, and physical polishing with an abrasive is dominant. In order to simplify the process, the same method as the polishing of the conductor layer 6 and the seed layer 5 described above may be used, or the polishing method may be changed depending on the material type of the seed adhesion layer 4 and the photosensitive resin layer 3 for the purpose of improving the efficiency of polishing. The conductor layer 6 remaining after polishing serves as an electrode for bonding to the semiconductor element 17.

[0030] (8) Formation of the first layer Next, as shown in Fig. 3, a first layer 18 is provided on the polished surface. The first layer 18 has a first conductor portion and a first non-conductor portion 31, and the first non-conductor portion 31 of the first layer can be formed from a patterned photosensitive resin. The first conductor portion of the first layer can be provided by forming a conductor in a first opening portion (corresponding to the via portion 20) of the first layer 18 in a later process. Since this first conductor portion functions as a via portion, the first layer is sometimes referred to as a via layer. The thickness of the first layer 18 is set according to the thickness of the via, which is the first conductor portion to be formed in the first opening, and in one embodiment of the present invention, is formed to be, for example, 2 μm. The shape of the first opening in plan view is set from the viewpoint of connection with conductor layer 6, and in one embodiment of the present invention, an opening shape of, for example, φ10 μm is formed. This first opening has the shape of a part of a via portion connecting upper and lower layers of a multilayer wiring.

[0031] (9) Formation of the second layer Next, as shown in Fig. 4, a second layer 19 is provided on the upper surface of the first layer 18. The second layer 19 has a second conductor portion and a second non-conductor portion 32, and the second non-conductor portion 32 can be formed of a patterned photosensitive resin. The pattern of the second non-conductor portion 32 defines at least the circuit wiring portion 22 of the multilayer wiring, and also defines a land portion 21 connected to the via portion above the via portion 20 formed in the first opening of the first layer 18. The second layer 19 is sometimes referred to as a trench layer. The thickness of the second layer 19 is set according to the thickness of the conductive layer formed in the opening of the second non-conductor portion 32, and is set to, for example, 2 μm in one embodiment of the present invention. The shape of the opening for the land portion in plan view is set from the viewpoint of the connectivity of the laminate, and is formed surrounding the outside of the first opening of the first layer 18. In one embodiment of the present invention, an opening shape of, for example, φ25 μm is formed. As described above, the first non-conductor 31 and the second non-conductor 32 may be formed in two steps, that is, a step of forming a first layer and a step of forming a second layer, or may be formed simultaneously in one step. When they are formed simultaneously in one step, for example, a non-conductive layer (photosensitive resin, etc.) having a thickness equal to the combined thickness of the first non-conductor portion and the second non-conductor portion is formed, and then the amount of exposure to each area is adjusted according to the shapes of the first non-conductor portion 31 and the second non-conductor portion 32, and development is performed, thereby simultaneously forming a step structure as shown in FIG.

[0032] (10) Formation of seed adhesion layer 4 and seed layer 5 5 and 6, a seed adhesion layer 4 and a seed layer 5 are formed in a vacuum. In one embodiment of the present invention, Ti: 50 nm and Cu: 300 nm are formed. As a result, a seed adhesion layer is formed on the bottom surfaces (in this embodiment, the surfaces on which the semiconductor element is mounted) and side surfaces of the via portions 20 and the circuit wiring portions 22.

[0033] (11) Formation of Conductive Layer 6 7, a conductor layer 6 is formed by electrolytic plating. The conductor layer 6 becomes a via / land portion 23 in which the via portion 20 and the land portion 21 are integrated, and a circuit wiring portion 22. Examples of electrolytic plating include nickel electrolytic plating, copper electrolytic plating, chromium electrolytic plating, Pd electrolytic plating, gold electrolytic plating, rhodium electrolytic plating, and iridium electrolytic plating. Of these, copper electrolytic plating is preferable because it is simple, inexpensive, and has good electrical conductivity. The thickness of the electrolytic copper plating is desirably 0.5 μm or more from the viewpoint of the electrical resistance of the circuit wiring portion 22, and 30 μm or less from the viewpoint of productivity. In this embodiment, Cu:6 μm is formed in the double opening formed by the first non-conductor portion 31 and the second non-conductor portion 32, Cu:4 μm is formed in the single opening of the second non-conductor portion 32, and Cu:2 μm is formed on the upper part of the second non-conductor portion 32.

[0034] (12) Surface polishing Next, as shown in FIG. 8, the conductive layer 6 and the seed layer 5 are removed by polishing using a CMP (chemical mechanical polishing) process or the like.

[0035] (13) Removal of seed adhesion layer 4 and second non-conductor portion 32 Next, polishing is performed again by CMP (chemical mechanical polishing) or the like to remove the seed adhesion layer 4 and the second non-conductor portion 32. The conductor layer 6 remaining after CMP becomes the conductor portion of the via / land portion 23 and the circuit wiring portion 22. In one embodiment of the present invention, Cu: 2 μm of the conductor layer 6 above the second non-conductor portion 32 and Cu: 300 nm of the seed layer 5 are removed by polishing.

[0036] (14) Formation of irregularities in the second layer Next, as shown in FIG. 9, a second layer is formed having an uneven upper surface and a different thickness between the area where the second conductor portion (via / land portion 23) is arranged and the area where the second conductor portion is not arranged. One method for forming such an uneven shape in the second layer is to etch the via / land portion 23 and the conductor layer 6 and seed layer 5 of the circuit wiring portion 22. The etching amount is preferably within a range of 0.1 to 1.5 μm. At this time, a chemical solution is used that etches the seed layer 5 and the conductor layer 6 but does not etch the seed adhesion layer 4. In one embodiment of the present invention, etching of 0.5 μm was performed using a sulfuric acid / hydrogen peroxide based etching solution. In addition to the above, other methods for forming an uneven shape on the second layer include etching the second non-conductor portion to reduce its thickness, or raising the second conductor portion or the second non-conductor portion to form an uneven portion on the surface of the second layer.

[0037] (15) Formation of chemical adhesion layer Next, as shown in Fig. 10, a chemical adhesion layer 24 is formed. The chemical adhesion layer 24 is a layer that improves adhesion between the second layer 19 and a first layer 29 (Fig. 11) formed directly on the second layer 19, and is a layer that prevents peeling of the first layer (via layer formed directly on the trench layer 19) 28 formed directly on the second layer 19. The chemical adhesion layer 24 is a film that chemically improves the adhesion between, for example, the conductor layer 6 (Cu) and the photosensitive resin layer 3, the photosensitive resin layer 3 and the photosensitive resin layer 3, and the seed adhesion layer 4 and the photosensitive resin layer 3, and examples of the chemical adhesion layer 24 include a silane coupling agent and a compound containing triazine. The chemical adhesion layer 24 may be formed over the entire surface between the first layer 29 and the second layer 19, or may be formed only partially. As a result, one wiring layer consisting of the first and second layers is formed.

[0038] (16) Formation of multi-layer wiring by repeating the process As shown in Fig. 11, a multilayer wiring board is formed by repeating the steps of Fig. 3 to Fig. 10. In this embodiment, an example in which two wiring layers are formed is shown. It is to be noted that the chemical adhesion layer 24 directly below the via / land portion 23 may be removed. In one embodiment of the present invention, two wiring layers are formed, and the chemical adhesion layer 24 directly below the via / land portion 23 is removed by plasma.

[0039] The steps for forming electrodes for bonding to the FC-BGA substrate 14 up to obtaining the configuration shown in FIG. 12 will be described below in order. (17) Formation of photosensitive resin layer A photosensitive resin layer 3 is formed on the upper surface of the chemical adhesion layer 24 formed in FIG.

[0040] (16) Formation of seed adhesion layer 4 and seed layer 5 Next, in a vacuum, the seed adhesion layer 4 and the seed layer 5 are formed. Before the seed adhesion layer 4 is formed, the chemical adhesion layer 24 immediately below the via portion 20 is removed by plasma.

[0041] (17) Formation of conductor layer (for solder connection) 6 Next, a resist pattern 7 is formed. After that, a conductor layer 6 is formed by electrolytic plating. The conductor layer 6 becomes an electrode for bonding to the FC-BGA substrate 14. The thickness of the electrolytic copper plating is desirably 1 μm or more from the viewpoint of solder bonding, and 30 μm or less from the viewpoint of productivity. In this embodiment, Cu: 9 μm is formed in the opening of the photosensitive resin layer 3, and Cu: 7 μm is formed on the upper part of the photosensitive resin layer 3. In this way, the configuration shown in FIG. 12 can be obtained.

[0042] Next, the steps up to the completion of the wiring board on the support body shown in FIG. 14 will be described in order. (18) Removal of resist pattern After obtaining the structure shown in FIG. 12, the resist pattern 7 is removed. Then, the unnecessary seed adhesion layer 4 and seed layer 5 are etched away using the conductor layer 6 as an etching mask. The conductor layer 6 remaining on the surface in this state becomes an electrode for bonding with the FC-BGA substrate 14. (19) Formation of solder resist 8 13, solder resist 8 is formed between the conductor layers for solder connection. The solder resist 8 is exposed to light and developed so as to cover the photosensitive resin layer 3, and is formed to have openings through which the conductor layer 6 is exposed. Incidentally, for example, an insulating resin such as an epoxy resin or an acrylic resin can be used as the material of the solder resist 8. In the embodiment of the present invention, a photosensitive epoxy resin containing a filler is used as the solder resist layer 8.

[0043] (20) Formation of Surface Treatment Layer 9 Next, a surface treatment layer 9 is provided to prevent oxidation of the surface of the conductor layer 6 and to improve the wettability of the solder bumps. In the embodiment of the present invention, electroless Ni / Pd / Au plating is formed as the surface treatment layer 9. Note that an OSP (Organic Soiderability Preservative, a surface treatment using a water-soluble preflux) film may be formed on the surface treatment layer 9. Alternatively, electroless tin plating, electroless Ni / Au plating, etc. may be appropriately selected depending on the application.

[0044] (21) Formation of solder joints Next, a solder material is placed on the surface treatment layer 9, and then melted, cooled, and fixed to obtain a joint of solder 10. This completes the multilayer wiring board 11 on the support as shown in FIG.

[0045] The multilayer wiring board 11 on the support body thus completed is bonded to the FC-BGA substrate 14, and the bonded portion is then sealed with an underfill layer. The underfill layer is made of, for example, one of epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and maleimide resin, or a mixture of two or more of these resins, to which a filler such as silica, titanium oxide, aluminum oxide, magnesium oxide, or zinc oxide is added. The underfill layer is formed by filling with a liquid resin.

[0046] Next, the release layer 2 is irradiated with a laser beam, making it possible to remove the support 1. Next, the release layer 2, the seed adhesion layer 4, and the seed layer 5 are removed.

[0047] Thereafter, a semiconductor element 17 is mounted to complete the semiconductor device 16 shown in Fig. 1. At this time, prior to mounting the semiconductor element 17, a surface treatment such as electroless Ni / Pd / Au plating, OSP, electroless tin plating, electroless Ni / Au plating, etc. may be performed on the conductor layer 6 exposed on the surface to prevent oxidation and improve the wettability of the solder bumps. In this manner, the semiconductor device 16 is completed.

[0048] <Verification of effectiveness> Next, the effects of using the configuration of the multilayer wiring board 30 and the manufacturing method thereof as described above will be described with reference to FIG. 15 showing an example of this embodiment and FIG. 16 showing a comparative example.

[0049] This embodiment will be described with reference to Fig. 15. In this embodiment, the circuit wiring portion 22, the via / land portion 23, and the bonding electrode pad portion with the semiconductor element of the multilayer wiring board 11 on the support are patterned (so-called damascene method) by polishing such as CMP (chemical mechanical polishing), so that the seed adhesion layer 4 can be disposed between the conductive layer 6 and the photosensitive resin layer 3 on the side surfaces of the circuit wiring portion 22, the via / land portion 23, and the bonding electrode pad portion with the semiconductor element, as shown in Fig. 15. Moreover, the multilayer wiring board 11 on the support is turned upside down and bonded to the FC-BGA board 14, and then the support 1 is removed to obtain the multilayer wiring board 30. Therefore, in the circuit wiring section 22 and the via / land section 23, the seed adhesion layer 4 can be disposed on the top surface and side surface, and in the bonding electrode pad section with the semiconductor element, the seed adhesion layer 4 can be disposed on the side surface.

[0050] As described above, in the conductor layer 6 of the circuit wiring portion 22 and the via / land portion 23, the seed adhesion layer 4 can be arranged on the upper surface and side surfaces, and in the conductor layer 6 of the bonding electrode pad portion with the semiconductor element, the seed adhesion layer 4 is arranged on the side surfaces, thereby improving adhesion with the photosensitive resin layer 3 and making it possible to prevent peeling.

[0051] Furthermore, in this substrate configuration, the conductor layer 6 and seed layer 5 of the via / land portion 23 and the circuit wiring portion 22 are etched to make the land portion 21 and the circuit wiring portion 22, which are conductors of the trench layer, thinner than the non-conductor portions. This makes the interface between the second layer (trench layer) 19 and the first layer (via layer) 29 an uneven surface, and creates a resin / resin interface on the side surfaces, thereby reducing internal stress in the wiring layer of the substrate when heated.

[0052] Furthermore, by forming a chemical adhesion layer 24 on the entire or part of the conductor upper surface of the second layer (trench layer) 19 and between the non-conductor portion of the trench layer, the exposed seed adhesion layer 4, and the via layer 29 directly below the trench layer, the adhesion between the second layer (trench layer) 19 and the first layer (via layer) 29 can be improved, and delamination at the resin interface of the trench layer / resin of the via layer due to thermal warping or internal stress during mounting can be improved.

[0053] In the above configuration, the following three types of examples were verified. In <Example 1>, (14) the formation of projections and recesses in the second layer was carried out, and (15) the formation of a chemical adhesion layer was not carried out. In addition, in <Example 2>, (14) the formation of projections and recesses in the second layer was performed by etching to a depth of 1.0 μm, and (15) no chemical adhesion layer was formed. In addition, in <Example 3>, (14) the formation of projections and recesses in the second layer was carried out, and (15) the formation of a chemical adhesion layer was not carried out.

[0054] In the above-mentioned Examples 1 to 3, the opening diameter of the via portion 20 was set to 10 μm, and the opening diameter of the land portion 21 was set to 20 μm, and a via connection reliability test was performed.

[0055] The via connection reliability was tested according to the following conditions, and the pass criteria were a resistance change rate of within ±3% and no cracks or delamination. Standard: JESD22-A106B(Condition D) Temperature: -65℃ / 5min ⇒ Room temperature / 1min ⇒ 150℃ / 5min Cycles: 500 cycles

[0056] <Comparative Example> A comparative example will be described with reference to Fig. 16. In the comparative example, the via / land portion 23 and the conductor layer 6 and seed layer 5 of the circuit wiring portion 22 were not etched, and the chemical adhesion layer 24 was not formed between the conductor upper surface of the second layer (trench layer) 19 and the non-conductor portion of the second layer and the first layer (via layer) 29 immediately below the second layer.

[0057] <Confirmation of action and effect> The results of the via connection reliability test for the above-mentioned Examples 1 to 3 which are the embodiments of the present invention and the Comparative Example are shown in Table 1. By making the interface between the second layer (trench layer) 19 and the first layer (via layer) 29 according to the embodiments of the present invention have an uneven surface shape and increasing the amount of etching, the stress on the resin of the trench layer / resin interface of the via layer is reduced and the adhesion is improved, so that sufficient via connection reliability can be ensured.

[0058] Furthermore, it was shown that, even without increasing the amount of etching, by forming a chemical adhesion layer 24 on the entire or part of the conductor top surface of the second layer (trench layer) 19 and between the non-conductor portion of the trench layer and the exposed seed adhesion layer 4 and the adjacent via layer, it is possible to reduce stress at the resin interface of the trench layer / resin of the via layer and improve adhesion, thereby ensuring the reliability of the via connection.

[0059] [Table 1]

[0060] The above-described embodiment is merely an example, and it goes without saying that other specific details such as structure can be modified as appropriate. [Explanation of symbols]

[0061] 1 Support 2. Peel layer 3 Photosensitive resin layer 4 Seed adhesion layer 5 Seed layer 6 Conductor Layer 7 Resist Pattern 8 Solder resist layer 9 Surface treatment layer 10 Solder 11 Multilayer wiring board on support 14 FC-BGA board 16 Semiconductor Devices 17 Semiconductor elements 18 1st layer 19 2nd layer 20 Via section 21 Land Department 22 Circuit wiring section 23 Via / Land Section 24 Chemical Adhesion Layer 29 A first layer formed directly above the second layer 19 30 Multilayer wiring board 31 First non-conductor 32 Second non-conductor 33 First conductor 34 Second conductor section

Claims

1. A multilayer wiring board having two or more wiring layers, the wiring layers including a first layer including a first conductor portion and a first non-conductor portion, and a second layer including a second conductor portion and a second non-conductor portion, the second layer has a thickness in a region where the second conductor portion is disposed that is smaller by 0.1 to 1.5 μm than a thickness in a region where the second conductor portion is not disposed, and has an upper surface that has an uneven shape; An interface is formed between a side surface of a second non-conductive layer on the upper surface of the second layer and a side surface of a first non-conductive layer on the lower surface of the first layer directly above the second layer. A multilayer wiring board comprising:

2. 2. The multilayer wiring board according to claim 1, A seed adhesion layer is formed on the side surface and / or bottom surface of the first conductor portion and the second conductor portion. A multilayer wiring board comprising:

3. 3. The multilayer wiring board according to claim 1, A chemical adhesion layer is disposed between the wiring layers. A multilayer wiring board comprising:

4. The multilayer wiring board according to any one of claims 1 to 3, the first layer is a via layer, the first conductor portion is a via, the second layer is a trench layer, and the second conductor portion is a land and a circuit wiring, The land is connected to the via. A multilayer wiring board comprising:

5. A method for manufacturing a multilayer wiring board having two or more wiring layers, the wiring layers including a first layer including a first conductor portion and a first non-conductor portion, and a second layer including a second conductor portion and a second non-conductor portion, comprising: 1) forming a pattern of the first non-conductor portion and a pattern of the second non-conductor portion; 2) providing a seed adhesion layer and a seed layer sequentially on side and bottom surfaces of the first non-conductor pattern and the second non-conductor pattern; 3) forming a conductive material on the seed layer to form a first conductor portion and a second conductor portion; 4) forming a step in which a thickness of a region of the second layer where the second conductor portion is disposed is made smaller by 0.1 to 1.5 μm than a thickness of a region where the second conductor portion is not disposed, and forming an uneven shape on the upper surface of the second layer; 5) repeating steps 1) to 4) for a desired number of wiring layers; and having A method for manufacturing a multilayer wiring board, which creates an interface between a side surface of a second non-conductive layer on the upper surface of the second layer and a side surface of a first non-conductive layer on the lower surface of the first layer directly above the second layer.

6. 6. The method for manufacturing a multilayer wiring board according to claim 5, wherein the step of forming an uneven shape on the upper surface of the second layer is a step of removing the surface of the region where the second conductor portion is disposed.

4. A method for manufacturing a multilayer wiring board comprising the steps of:

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