Oscillator circuit, oscillator, and method for controlling oscillator circuit

Abstract

To provide an oscillation circuit that, even if a vibrator to be connected has a variation in its characteristics, can reduce the possibility of abnormal oscillation, an oscillator, and a method for controlling an oscillation circuit.SOLUTION: In an oscillator 1, an oscillation circuit 2 has a control circuit 40 and a circuit for oscillation 10. The control circuit 40 controls the circuit for oscillation 10. The circuit for oscillation 10 has a normal operation mode for oscillating in a state in which a negative resistance value becomes a first value, and a start-up mode continuing until the circuit for oscillation suspending the oscillation makes a transition to the normal operation mode. In the start-up mode, the control circuit 40 controls such that the negative resistance value increases from a second value smaller than the first value.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to an oscillator circuit, an oscillator, and a method for controlling an oscillator circuit. [Background technology]

[0002] Patent Document 1 describes an oscillation circuit that is provided with a control circuit that increases the load capacitance of the oscillation circuit only at oscillation startup, thereby making the growth coefficient of the main vibration at oscillation startup larger than the growth coefficient of the spurious vibration. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Utility Model Application Publication No. 62-109511 Summary of the Invention [Problem to be solved by the invention]

[0004] However, when the load capacitance is different at startup and other times, as in the oscillator circuit described in Patent Document 1, there is a risk that normal oscillation cannot be guaranteed due to variations in the characteristics of the oscillator. In other words, if an oscillator is used that does not resonate with either the main vibration or the secondary vibration such as spurious vibration at the load capacitance at the time of oscillation startup, but resonates with either the main vibration or the secondary vibration at the load capacitance during normal operation, there is a risk of abnormal oscillation. [Means for solving the problem]

[0005] One aspect of the oscillator circuit according to the present invention is an oscillation circuit connected to the oscillator; A control circuit for controlling the oscillation circuit, a normal operation mode in which the oscillation circuit oscillates in a state in which the negative resistance value is a first value; a startup mode from a state in which the oscillation circuit stops oscillating to a state in which the normal operation mode is transitioned to; The control circuit includes: In the start-up mode, the negative resistance value is controlled to increase from a second value smaller than the first value.

[0006] One aspect of the oscillator according to the present invention is An embodiment of the oscillator circuit; The vibrator.

[0007] One aspect of a method for controlling an oscillator circuit according to the present invention includes: A method for controlling an oscillation circuit, comprising: an oscillation circuit connected to a vibrator, the oscillation circuit having a normal operation mode in which the oscillation circuit oscillates with a first negative resistance value; and a startup mode in which the oscillation circuit transitions from a state in which oscillation has stopped to the normal operation mode, the method comprising: In the start-up mode, the negative resistance value is controlled to increase from a second value smaller than the first value. [Brief description of the drawings]

[0008] [Figure 1] FIG. 2 is a perspective view of the oscillator according to the embodiment. [Diagram 2] FIG. 2 is a cross-sectional view of the oscillator according to the embodiment. [Diagram 3] FIG. [Figure 4] FIG. 2 is a functional block diagram of an oscillator according to the first embodiment. [Diagram 5] FIG. 2 is a diagram showing a configuration example of an oscillation circuit. [Figure 6] FIG. 4 is a diagram showing an example of the configuration of a variable current source. [Figure 7] FIG. 4 is a diagram showing an example of current adjustment data. [Figure 8] FIG. 11 is a diagram showing an example of capacity adjustment data. [Figure 9] FIG. 13 is a diagram showing another example of the configuration of a variable capacitance circuit. [Figure 10] FIG. 4 is a waveform diagram showing an example of a sequence in the first embodiment. [Figure 11] FIG. 4 is a waveform diagram showing another example of the sequence in the first embodiment. [Figure 12]FIG. 11 is a flowchart showing an example of a procedure of a method for controlling an oscillation circuit. [Figure 13] FIG. 4 is a flowchart showing an example of a procedure of a start-up process in the first embodiment. [Figure 14] FIG. 11 is a flowchart showing another example of the procedure of the start-up process in the first embodiment. [Figure 15] FIG. 11 is a waveform diagram showing an example of a sequence in the second embodiment. [Figure 16] FIG. 11 is a flowchart showing an example of a procedure of a start-up process in the second embodiment. [Figure 17] FIG. 13 is a diagram showing an example of the configuration of a voltage control circuit according to a third embodiment. [Figure 18] FIG. 13 is a waveform diagram showing an example of a sequence in the third embodiment. [Figure 19] FIG. 11 is a flowchart showing an example of a procedure of a start-up process in the third embodiment. [Figure 20] FIG. 13 is a waveform diagram showing an example of a sequence in the fourth embodiment. [Figure 21] FIG. 13 is a flowchart showing an example of a procedure of a start-up process in the fourth embodiment. [Figure 22] FIG. 13 is a functional block diagram of an oscillator according to a fifth embodiment. [Diagram 23] FIG. 4 is a diagram showing a configuration example of an oscillation detection circuit. [Figure 24] FIG. 13 is a waveform diagram showing an example of a sequence in the fifth embodiment. [Diagram 25] FIG. 13 is a flowchart showing an example of a procedure of a start-up process in the fifth embodiment. [Figure 26] FIG. 13 is a diagram showing an example of the configuration of a control circuit according to a sixth embodiment. [Figure 27] FIG. 4 is a diagram showing an example of the configuration of a delay circuit. [Figure 28] FIG. 4 is a diagram showing an example of a waveform of each bit of current adjustment data. [Figure 29] FIG. 23 is a diagram showing an example of the configuration of a variable current source according to the seventh embodiment. [Diagram 30] FIG. 23 is a diagram showing an example of current adjustment data in the seventh embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Preferred embodiments of the present invention will be described in detail below with reference to the drawings. Note that the embodiments described below do not unduly limit the contents of the present invention described in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0010] 1. First embodiment 1-1. Oscillator configuration Fig. 1, Fig. 2 and Fig. 3 are diagrams showing an example of the structure of an oscillator 1 according to this embodiment. Fig. 1 is a perspective view of the oscillator 1. Fig. 2 is a cross-sectional view taken along line AA in Fig. 1. Fig. 3 is a bottom view of the oscillator 1.

[0011] As shown in FIG. 1, FIG. 2, and FIG. 3, the oscillator 1 includes an oscillation circuit 2, a vibrator 3, a package 4, a lid 5, and a plurality of external terminals 6. In this embodiment, the vibrator 3 is a quartz crystal vibrator using quartz crystal as a substrate material, such as an AT-cut quartz crystal vibrator or a tuning fork-type quartz crystal vibrator. The vibrator 3 may be a SAW (Surface Acoustic Wave) resonator or a MEMS (Micro Electro Mechanical Systems) vibrator. SAW is an abbreviation for Surface Acoustic Wave. MEMS is an abbreviation for Micro Electro Mechanical Systems. In addition to quartz crystal, piezoelectric materials such as piezoelectric single crystals such as lithium tantalate and lithium niobate, piezoelectric ceramics such as lead zirconate titanate, silicon semiconductor materials, etc. may be used as the substrate material of the vibrator 3. The vibrator 3 may be excited by a piezoelectric effect or by electrostatic driving using Coulomb force. In this embodiment, the oscillation circuit 2 is realized by a one-chip integrated circuit. However, at least a part of the oscillator circuit 2 may be composed of discrete components.

[0012] The package 4 accommodates the oscillation circuit 2 and the vibrator 3 in the same space. Specifically, the package 4 is provided with a recess, and the recess is covered with a lid 5 to form an accommodation chamber 7. Inside the package 4 or on the surface of the recess, wiring (not shown) is provided for electrically connecting two terminals of the oscillation circuit 2, specifically, the XI terminal and the XO terminal in FIG. 4 described later, to two excitation electrodes 3a, 3b of the vibrator 3. Also, inside the package 4 or on the surface of the recess, wiring (not shown) is provided for electrically connecting each terminal of the oscillation circuit 2 to each external terminal 6 provided on the bottom surface of the package 4. The package 4 is not limited to a configuration in which the oscillation circuit 2 and the vibrator 3 are accommodated in the same space. For example, the package 4 may be a so-called H-shaped package in which the oscillation circuit 2 is mounted on one side of a substrate of the package and the vibrator 3 is mounted on the other side.

[0013] The oscillator 3 has metallic excitation electrodes 3a, 3b on its front and back surfaces, respectively, and oscillates at a desired frequency according to the shape and mass of the oscillator 3 including the excitation electrodes 3a, 3b.

[0014] 3, the oscillator 1 of this embodiment has four external terminals 6 provided on its bottom surface, specifically, on the back surface of the package 4: an external terminal VDD1 which is a power supply terminal, an external terminal VSS1 which is a ground terminal, an external terminal VC1 which is a terminal to which a signal for controlling the frequency of the oscillation circuit 2 is input, and an external terminal OUT1 which is an output terminal from which an oscillation signal is output. A power supply voltage is supplied to the external terminal VDD1, and the external terminal VSS1 is grounded.

[0015] 4 is a functional block diagram of the oscillator 1 of the first embodiment. As shown in FIG. 4, the oscillator 1 of the present embodiment includes an oscillation circuit 2 and a vibrator 3. The oscillation circuit 2 has a VDD terminal, a VSS terminal, an OUT terminal, a VC terminal, an XI terminal, and an XO terminal as external connection terminals. The VDD terminal, the VSS terminal, the OUT terminal, and the VC terminal are electrically connected to the external terminals VDD1, VSS1, OUT1, and VC1, which are the four external terminals 6 of the oscillator 1 shown in FIG. 3, respectively. The XI terminal is electrically connected to an excitation electrode 3a which is one end of the vibrator 3, and the XO terminal is electrically connected to an excitation electrode 3b which is the other end of the vibrator 3.

[0016] In this embodiment, the oscillator circuit 2 includes an oscillation circuit 10, a power supply circuit 20, a power-on reset circuit 30, a control circuit 40, a reference voltage generating circuit 50, an output circuit 60, and a memory circuit 70. Note that the oscillator circuit 2 may be configured such that some of these elements are omitted or modified, or other elements are added.

[0017] The power supply circuit 20 generates various voltages including the power supply voltage Vdd for the logic circuit 42 based on the external power supply voltage input from the external terminal VDD1 and supplied via the VDD terminal, and supplies the generated various voltages to each circuit. In addition, the ground voltage Vss is supplied to each circuit via the VSS terminal.

[0018] When power is applied to the oscillator 1, the power supply voltage Vdd output from the power supply circuit 20 rises from 0V to a predetermined voltage value. When the power supply voltage Vdd reaches a predetermined threshold voltage, the power-on reset circuit 30 generates a power-on reset signal POR that remains at a high level for a certain period of time. The power-on reset signal POR initializes the logic circuit 42 to a desired state. When the power-on reset signal POR changes from a high level to a low level, the logic circuit 42 starts operating.

[0019] The oscillation circuit 10 is a circuit that is connected to the vibrator 3 via the XI terminal and the XO terminal, amplifies a signal output from the vibrator 3 using an amplifier element, and supplies the amplified signal to the vibrator 3 to oscillate the vibrator 3. The amplifier element may be, for example, a bipolar transistor, a MOS transistor, or a CMOS inverter. MOS is an abbreviation for Metal Oxide Semiconductor. CMOS is an abbreviation for Complementary Metal Oxide Semiconductor. The oscillation circuit 10 adjusts the oscillation frequency to a target frequency based on various setting signals supplied from the logic circuit 42.

[0020] The output circuit 60 buffers the oscillation signal CK output by the oscillation circuit 10 and outputs it. The oscillation signal CKO output from the output circuit 60 is output to the outside of the oscillator 1 via the OUT terminal and the external terminal OUT1. The output circuit 60 may output a differential oscillation signal. That is, the output circuit 60 may output an oscillation signal XCKO in which the polarity of the oscillation signal CKO is inverted, together with the oscillation signal CKO. In this case, the oscillation circuit 2 further includes an XOUT terminal for outputting the oscillation signal XCKO, and the oscillator 1 further includes an external terminal XOUT1 for outputting the oscillation signal XCKO.

[0021] The control circuit 40 controls the oscillation circuit 10. In this embodiment, the control circuit 40 includes a voltage control circuit 41 and a logic circuit .

[0022] The voltage control circuit 41 generates a control voltage for changing the oscillation frequency of the oscillation circuit 10 in accordance with the voltage level of a frequency control signal supplied from the external terminal VC1 via the VC terminal, and supplies the control voltage to the oscillation circuit 10. That is, the frequency of the oscillation signal CKO output from the external terminal OUT1 changes in accordance with the voltage level of the frequency control signal input from the external terminal VC1.

[0023] The logic circuit 42 outputs an oscillation enable signal en_osc to the oscillation circuit 10 to control the operation of the oscillation circuit 10. Specifically, the logic circuit 42 makes the oscillation circuit 10 oscillate by setting the oscillation enable signal en_osc to a high level, and stops the oscillation of the oscillation circuit 10 by setting the oscillation enable signal en_osc to a low level. The logic circuit 42 also outputs various setting signals to the oscillation circuit 10 to control the oscillation frequency of the oscillation circuit 10. Furthermore, the logic circuit 42 outputs an output enable signal en_out to the output circuit 60 to control the operation of the output circuit 60. Specifically, the logic circuit 42 controls the output circuit 60 to output the oscillation signal CKO by setting the output enable signal en_out to a high level, and controls the output circuit 60 to stop outputting the oscillation signal CKO by setting the output enable signal en_out to a low level.

[0024] The reference voltage generating circuit 50 generates various reference voltages based on the voltage output from the power supply circuit 20 and outputs them to the oscillation circuit 10 .

[0025] The memory circuit 70 is a circuit for storing various information, and includes a nonvolatile memory 71 and a register 72. The nonvolatile memory 71 may be, for example, a FAMOS, a MONOS type memory, an EEPROM, or the like. FAMOS is an abbreviation for Floating gate Avalanche injection Metal Oxide Semiconductor. MONOS is an abbreviation for Metal Oxide Nitride Oxide Silicon. EEPROM is an abbreviation for Electrically Erasable Programmable Read-Only Memory. In the manufacturing process of the oscillator 1, various information is stored in the nonvolatile memory 71. When the oscillator 1 is powered on, the various information stored in the nonvolatile memory 71 is transferred to the register 72, and the various information stored in the register 72 is appropriately supplied to each circuit. For example, the information for adjusting the oscillation frequency transferred from the nonvolatile memory 71 to the register 72 is supplied to the oscillation circuit 10 as various setting signals via the logic circuit 42. The information for adjusting the oscillation frequency is current adjustment data and capacitance adjustment data, which will be described later.

[0026] 1-2. Configuration of the oscillation circuit Fig. 5 is a diagram showing a configuration example of the oscillation circuit 10. In the example of Fig. 5, the oscillation circuit 10 includes an amplifier element 11, a variable current source 12, a resistor 13, a variable capacitance circuit 14, a variable capacitance circuit 15, a variable capacitance circuit 16, and a variable capacitance circuit 17. The oscillation circuit 10 also includes ten CMOS inverters 100, 101, 102, 103, 104, 110, 111, 112, 113, and 114.

[0027] The amplifying element 11 is an NPN bipolar transistor, with its base terminal connected to the XI terminal, its collector terminal connected to the XO terminal, and its emitter terminal grounded. A resistor 13 is connected between the base terminal and the collector terminal of the amplifying element 11. An oscillation stage current Iosc is supplied to the collector terminal of the amplifying element 11 from a variable current source 12, and a signal at the collector terminal is output as an oscillation signal CK. A MOS transistor or a CMOS inverter may be used as the amplifying element 11.

[0028] The variable current source 12 generates an oscillation stage current Iosc having a magnitude according to 5-bit current adjustment data trimI[4:0] as a setting signal supplied from the logic circuit 42, based on the voltage Vreg generated by the reference voltage generation circuit 50. Then, the variable current source 12 supplies the oscillation stage current Iosc to the amplifying element 11. Note that the number of bits of the current adjustment data trimI is not limited to 5.

[0029] Fig. 6 is a diagram showing an example of the configuration of the variable current source 12. In the example of Fig. 6, the variable current source 12 includes six current sources 120, 121, 122, 123, 124, and 130, five switch elements 125, 126, 127, 128, and 129, and two P-channel MOS transistors 131 and 132.

[0030] 5. The gate and drain of the P-channel MOS transistor 131 are connected to each other, and a voltage Vreg is supplied to the source of the P-channel MOS transistor 132. The gate of the P-channel MOS transistor 132 is connected to the gate of the P-channel MOS transistor 131, a voltage Vreg is supplied to the source of the P-channel MOS transistor 132, and a drain of the P-channel MOS transistor 132 is connected to the collector of the amplifying element 11 of FIG.

[0031] The current source 130 has one end connected to the drain of the P-channel MOS transistor 131 and the other end grounded, and outputs a constant bias current I bOne end of the current source 120 is connected to the drain of the P-channel MOS transistor 131 via the switch element 125, and the other end is grounded. When the switch element 125 is in a conductive state, a constant current I0 flows. One end of the current source 121 is connected to the drain of the P-channel MOS transistor 131 via the switch element 126, and the other end is grounded. When the switch element 126 is in a conductive state, a current twice as large as I0 flows. One end of the current source 122 is connected to the drain of the P-channel MOS transistor 131 via the switch element 127, and the other end is grounded. When the switch element 127 is in a conductive state, a current four times as large as I0 flows. One end of the current source 123 is connected to the drain of the P-channel MOS transistor 131 via the switch element 128, and the other end is grounded. When the switch element 128 is in a conductive state, a current eight times as large as I0 flows. One end of the current source 124 is connected to the drain of a P-channel MOS transistor 131 via a switch element 129, and the other end is grounded, and a current 16 times larger than I0 flows when the switch element 129 is in a conductive state. For example, the current sources 120, 121, 122, 123, 124, and 130 may be configured using depletion-type N-channel MOS transistors or may be configured using current mirror circuits.

[0032] The switch element 125 receives data trimI[0] of bit 0 of the current adjustment data trimI[4:0] at a control terminal, and is conductive when data trimI[0] is at a high level and is non-conductive when data trimI[0] is at a low level. The switch element 126 receives data trimI[1] of bit 1 of the current adjustment data trimI[4:0] at a control terminal, and is conductive when data trimI[1] is at a high level and is non-conductive when data trimI[1] is at a low level. The switch element 127 receives data trimI[2] of bit 2 of the current adjustment data trimI[4:0] at a control terminal, and is conductive when data trimI[2] is at a high level and is non-conductive when data trimI[2] is at a low level. The switch element 128 receives data trimI[3] of bit 3 of the current adjustment data trimI[4:0] at a control terminal, and is conductive when the data trimI[3] is at a high level and is non-conductive when the data trimI[3] is at a low level. The switch element 129 receives data trimI[4] of bit 4 of the current adjustment data trimI[4:0] at a control terminal, and is conductive when the data trimI[4] is at a high level and is non-conductive when the data trimI[4] is at a low level. For example, the switch elements 125, 126, 127, 128, and 129 may be N-channel MOS transistors or transmission gates.

[0033] 7 is a diagram showing the relationship between the value of the current adjustment data trimI[4:0] expressed in decimal and the value of each bit of the current adjustment data trimI[4:0] expressed in binary. Each bit of 0 corresponds to a low level, and each bit of 1 corresponds to a high level. For example, if the current adjustment data trimI[4:0] is 1, bit 0 is 1, and bits 1, 2, 3, and 4 are 0. Therefore, the switch element 125 is conductive and a current I0 flows through the current source 120. Also, for example, if the current adjustment data trimI[4:0] is 2, bit 1 is 1, and bits 0, 2, 3, and 4 are 0. Therefore, the switch element 126 is conductive and a current twice as large as the current I0 flows through the current source 121.

[0034] A bias current I b A current flows between the source and drain of the P-channel MOS transistor 131, the sum of the currents flowing through the current sources 120, 121, 122, 123, and 124 and the current I0 flows between the source and drain of the P-channel MOS transistor 131 and the current I1 flows between the source and drain of the P-channel MOS transistor 131 and the current I2 ... b In addition, for example, when the current adjustment data trimI[4:0] is 1, a current twice the current I0 flows through the current source 121, and the currents flowing through the current sources 120, 122, 123, and 124 are zero. Therefore, a bias current I b A current obtained by adding twice the current I0 to the current I1 flows. Then, a current mirror circuit formed by two P-channel MOS transistors 131, 132 causes a current that is a predetermined multiple of the current flowing between the source and drain of the P-channel MOS transistor 131 to flow between the source and drain of the P-channel MOS transistor 132. This current is supplied to the amplifying element 11 as the oscillation stage current Iosc. Therefore, the magnitude of the oscillation stage current Iosc changes according to the value of the current adjustment data trimI[4:0]. Specifically, the larger the value of the current adjustment data trimI[4:0], the larger the oscillation stage current Iosc.

[0035] In the manufacturing process of the oscillator 1, the value of the current adjustment data trimI[4:0] for adjusting the oscillation stage current Iosc to a desired value according to the resonance frequency of the resonator 3 is written to the non-volatile memory 71.

[0036] Returning to the explanation of FIG. 5, the CMOS inverter 100 outputs data trimCN1[0] obtained by logically inverting data trimC1[0] of bit 0 of the 5-bit capacitance adjustment data trimC1[4:0] as a setting signal supplied from the logic circuit 42. The CMOS inverter 101 outputs data trimCN1[1] obtained by logically inverting data trimC1[1] of bit 1 of the capacitance adjustment data trimC1[4:0]. The CMOS inverter 102 outputs data trimCN1[2] obtained by logically inverting data trimC1[2] of bit 2 of the capacitance adjustment data trimC1[4:0]. The CMOS inverter 103 outputs data trimCN1[3] obtained by logically inverting data trimC1[3] of bit 3 of the capacitance adjustment data trimC1[4:0]. The CMOS inverter 104 outputs data trimCN1[4] obtained by logically inverting data trimC1[4] of bit 4 of the capacitance adjustment data trimC1[4:0].

[0037] The variable capacitance circuit 14 is a capacitance circuit having a capacitance value C1 that corresponds to capacitance adjustment data trimCN1[4:0] obtained by logically inverting each bit of the capacitance adjustment data trimC1[4:0] by CMOS inverters 100, 101, 102, 103, and 104. The variable capacitance circuit 14 includes five capacitance elements 140, 141, 142, 143, and 144, and five switch elements 145, 146, 147, 148, and 149.

[0038] The capacitance element 140 has one end connected to the XI terminal and the other end grounded via the switch element 145, and its capacitance value is C0. The capacitance element 141 has one end connected to the XI terminal and the other end grounded via the switch element 146, and its capacitance value is twice as large as C0. The capacitance element 142 has one end connected to the XI terminal and the other end grounded via the switch element 147, and its capacitance value is four times as large as C0. The capacitance element 143 has one end connected to the XI terminal and the other end grounded via the switch element 148, and its capacitance value is eight times as large as C0. The capacitance element 144 has one end connected to the XI terminal and the other end grounded via the switch element 149, and its capacitance value is sixteen times as large as C0. For example, the capacitance elements 140, 141, 142, 143, and 144 may be MIM type capacitance elements using metal for two electrodes, or may be PIP type capacitance elements using polysilicon for two electrodes. MIM is an abbreviation for Metal Insulator Metal, and PIP is an abbreviation for Poly Insulator Poly.

[0039] The switch element 145 receives data trimCN1[0] of bit 0 of the capacitance adjustment data trimCN1[4:0] at its control terminal, and is conductive when the data trimCN1[0] is at a high level, and is non-conductive when the data trimCN1[0] is at a low level. The switch element 146 receives data trimCN1[1] of bit 1 of the capacitance adjustment data trimCN1[4:0] at its control terminal, and is conductive when the data trimCN1[1] is at a high level, and is non-conductive when the data trimCN1[1] is at a low level. The switch element 147 receives data trimCN1[2] of bit 2 of the capacitance adjustment data trimCN1[4:0] at its control terminal, and is conductive when the data trimCN1[2] is at a high level, and is non-conductive when the data trimCN1[2] is at a low level. The switch element 148 receives data trimCN1[3] of bit 3 of the capacitance adjustment data trimCN1[4:0] at a control terminal, and is conductive when the data trimCN1[3] is at a high level, and is non-conductive when the data trimCN1[3] is at a low level. The switch element 149 receives data trimCN1[4] of bit 4 of the capacitance adjustment data trimCN1[4:0] at a control terminal, and is conductive when the data trimCN1[4] is at a high level, and is non-conductive when the data trimCN1[4] is at a low level. For example, the switch elements 145, 146, 147, 148, and 149 may be N-channel MOS transistors or transmission gates.

[0040] FIG. 8 is a diagram showing the relationship between the value of the capacitance adjustment data trimC1[4:0] expressed in decimal and the value of each bit of the capacitance adjustment data trimCN1[4:0] obtained by logically inverting the capacitance adjustment data trimC1[4:0] expressed in binary. A 0 in each bit corresponds to a low level, and a 1 in each bit corresponds to a high level. For example, if the capacitance adjustment data trimC1[4:0] is 1, bits 1, 2, 3, and 4 of the capacitance adjustment data trimCN1[4:0] are 1, and bit 0 is 0. Therefore, the switch elements 146, 147, 148, and 149 are conductive, and the other ends of the capacitance elements 141, 142, 143, and 144 are grounded. Also, for example, if the capacitance adjustment data trimC1[4:0] is 2, bits 0, 2, 3, and 4 of the capacitance adjustment data trimCN1[4:0] are 1, and bit 1 is 0. Therefore, the switch elements 145, 147, 148, and 149 are rendered conductive, and the other ends of the capacitance elements 140, 142, 143, and 144 are grounded.

[0041] The capacitance value C1 of the variable capacitance circuit 14 is the sum of the capacitance values ​​of the capacitance elements 140, 141, 142, 143, and 144 whose other ends are grounded by each of the switch elements 145, 146, 147, 148, and 149 being conductive. For example, when the capacitance adjustment data trimC1[4:0] is 1, the other ends of the capacitance elements 141, 142, 143, and 144 are grounded and the other end of the capacitance element 140 is not grounded, so that the capacitance value C1 of the variable capacitance circuit 14 is 2C0+4C0+8C0+16C0=30C0. Also, for example, when the capacitance adjustment data trimC1[4:0] is 2, the other end of each of the capacitance elements 140, 142, 143, and 144 is grounded, and the other end of the capacitance element 141 is not grounded, so that the capacitance value C1 of the variable capacitance circuit 14 is C0+4C0+8C0+16C0=29C0. In this manner, the capacitance value C1 of the variable capacitance circuit 14 changes according to the value of the capacitance adjustment data trimC1[4:0]. Specifically, the larger the value of the capacitance adjustment data trimC1[4:0], the smaller the capacitance value C1 of the variable capacitance circuit 14.

[0042] The CMOS inverter 110 outputs data trimCN2[0] obtained by logically inverting data trimC2[0] of bit 0 of the 5-bit capacitance adjustment data trimC2[4:0] as a setting signal supplied from the logic circuit 42. The CMOS inverter 111 outputs data trimCN2[1] obtained by logically inverting data trimC2[1] of bit 1 of the capacitance adjustment data trimC2[4:0]. The CMOS inverter 112 outputs data trimCN2[2] obtained by logically inverting data trimC2[2] of bit 2 of the capacitance adjustment data trimC2[4:0]. The CMOS inverter 113 outputs data trimCN2[3] obtained by logically inverting data trimC2[3] of bit 3 of the capacitance adjustment data trimC2[4:0]. The CMOS inverter 114 outputs data trimCN2[4] obtained by logically inverting data trimC2[4] of bit 4 of the capacitance adjustment data trimC2[4:0].

[0043] The variable capacitance circuit 15 is a capacitance circuit having a capacitance value C2 whose magnitude corresponds to capacitance adjustment data trimCN2[4:0] obtained by logically inverting each bit of the capacitance adjustment data trimC2[4:0] by CMOS inverters 110, 111, 112, 113, and 114. The variable capacitance circuit 15 includes five capacitance elements 150, 151, 152, 153, and 154, and five switch elements 155, 156, 157, 158, and 159.

[0044] Capacitance element 150 has one end connected to the XO terminal and the other end grounded via switch element 155, and its capacitance value is C0. Capacitance element 151 has one end connected to the XO terminal and the other end grounded via switch element 156, and its capacitance value is twice C0. Capacitance element 152 has one end connected to the XO terminal and the other end grounded via switch element 157, and its capacitance value is four times C0. Capacitance element 153 has one end connected to the XO terminal and the other end grounded via switch element 158, and its capacitance value is eight times C0. Capacitance element 154 has one end connected to the XO terminal and the other end grounded via switch element 159, and its capacitance value is 16 times C0. For example, the capacitive elements 150, 151, 152, 153, and 154 may be MIM type capacitive elements using metal for two electrodes, or PIP type capacitive elements using polysilicon for two electrodes. MIM is an abbreviation for Metal Insulator Metal. Also, PIP is an abbreviation for Poly Insulator Poly.

[0045] The switch element 155 receives data trimCN2[0] of bit 0 of the capacitance adjustment data trimCN2[4:0] at its control terminal, and is conductive when the data trimCN2[0] is at a high level, and is non-conductive when the data trimCN2[0] is at a low level. The switch element 156 receives data trimCN2[1] of bit 1 of the capacitance adjustment data trimCN2[4:0] at its control terminal, and is conductive when the data trimCN2[1] is at a high level, and is non-conductive when the data trimCN2[1] is at a low level. The switch element 157 receives data trimCN2[2] of bit 2 of the capacitance adjustment data trimCN2[4:0] at its control terminal, and is conductive when the data trimCN2[2] is at a high level, and is non-conductive when the data trimCN2[2] is at a low level. The switch element 158 ​​receives data trimCN2[3] of bit 3 of the capacitance adjustment data trimCN2[4:0] at its control terminal, and is conductive when the data trimCN2[3] is at a high level, and is non-conductive when the data trimCN2[3] is at a low level. The switch element 159 receives data trimCN2[4] of bit 4 of the capacitance adjustment data trimCN2[4:0] at its control terminal, and is conductive when the data trimCN2[4] is at a high level, and is non-conductive when the data trimCN2[4] is at a low level. For example, the switch elements 155, 156, 157, 158, and 159 may be N-channel MOS transistors or transmission gates.

[0046] The relationship between the value of the capacitance adjustment data trimC2[4:0] expressed in decimal and the value of each bit of the capacitance adjustment data trimCN2[4:0] obtained by logically inverting the capacitance adjustment data trimC2[4:0] expressed in binary is the same as the relationship between the value of the capacitance adjustment data trimC1[4:0] expressed in decimal and the value of each bit of the capacitance adjustment data trimCN1[4:0] expressed in binary shown in Fig. 8, so that the illustration is omitted. For example, if the capacitance adjustment data trimC2[4:0] is 1, bits 1, 2, 3, and 4 of the capacitance adjustment data trimCN2[4:0] are 1, and bit 0 is 0. Therefore, the switch elements 156, 157, 158, and 159 are conductive, and the other ends of the capacitance elements 151, 152, 153, and 154 are grounded. Also, for example, if the capacitance adjustment data trimC2[4:0] is 2, then bits 0, 2, 3, and 4 of the capacitance adjustment data trimCN2[4:0] are 1, and bit 1 is 0. Therefore, the switch elements 155, 157, 158, and 159 are conductive, and the other ends of the capacitance elements 150, 152, 153, and 154 are grounded.

[0047] The capacitance value C2 of the variable capacitance circuit 15 is the sum of the capacitance values ​​of the capacitance elements 150, 151, 152, 153, and 154 whose other ends are grounded by each of the switch elements 155, 156, 157, 158, and 159 being conductive. For example, when the capacitance adjustment data trimC2[4:0] is 1, the other ends of the capacitance elements 151, 152, 153, and 154 are grounded and the other end of the capacitance element 150 is not grounded, so that the capacitance value C2 of the variable capacitance circuit 15 is 2C0+4C0+8C0+16C0=30C0. Also, for example, when the capacitance adjustment data trimC2[4:0] is 2, the other end of each of the capacitance elements 150, 152, 153, and 154 is grounded, and the other end of the capacitance element 151 is not grounded, so that the capacitance value C2 of the variable capacitance circuit 15 is C0+4C0+8C0+16C0=29C0. In this manner, the capacitance value C2 of the variable capacitance circuit 15 changes according to the value of the capacitance adjustment data trimC2[4:0]. Specifically, the larger the value of the capacitance adjustment data trimC2[4:0], the smaller the capacitance value C2 of the variable capacitance circuit 15.

[0048] The variable capacitance circuit 14 is connected to the excitation electrode 3a of the resonator 3 via the XI terminal, and the variable capacitance circuit 15 is connected to the excitation electrode 3b of the resonator 3 via the XO terminal. That is, the variable capacitance circuits 14 and 15 are connected to a node connected to the resonator 3 and become part of the load capacitance of the resonator 3. In the manufacturing process of the oscillator 1, values ​​of capacitance adjustment data trimC1[4:0], trimC2[4:0] for adjusting the frequency of the oscillation signal CK output from the oscillation circuit 10 to a target frequency are written to the nonvolatile memory 71.

[0049] The variable capacitance circuit 16 is a capacitance circuit having a capacitance value C3 whose magnitude corresponds to the control voltage Vcnt1 supplied from the voltage control circuit 41. The variable capacitance circuit 16 includes a variable capacitance element 160. For example, the variable capacitance element 160 is a varactor in which the source and drain of an NMOS transistor are connected, the gate of the NMOS transistor is connected to the XI terminal, the ground voltage Vss is supplied to the back gate, and the control voltage Vcnt1 is supplied to the source and drain. The larger the control voltage Vcnt1, the smaller the capacitance value C3 of the variable capacitance circuit 16.

[0050] The variable capacitance circuit 17 is a capacitance circuit having a capacitance value C4 whose magnitude corresponds to the control voltage Vcnt2 supplied from the voltage control circuit 41. The variable capacitance circuit 17 includes a variable capacitance element 170. For example, the variable capacitance element 170 is a varactor in which the source and drain of an NMOS transistor are connected, the gate of the NMOS transistor is connected to the XO terminal, the ground voltage Vss is supplied to the back gate, and the control voltage Vcnt2 is supplied to the source and drain. The larger the control voltage Vcnt2 is, the smaller the capacitance value C4 of the variable capacitance circuit 17 becomes.

[0051] FIG. 9 is a diagram showing another configuration example of the variable capacitance circuits 16 and 17. In the example of FIG. 9, the variable capacitance circuit 16 includes n variable capacitance elements 161-1 to 161-n, n capacitance elements 162-1 to 162-n, and n capacitance elements 163-1 to 163-n. n is an integer of 2 or more. For each integer i between 1 and n, the variable capacitance element 161-i is a varactor in which the source and drain of an NMOS transistor are connected, the source and drain of the NMOS transistor are connected to an XI terminal via a capacitance element 163-i, the back gate is supplied with a ground voltage Vss, and the gate is grounded via a capacitance element 162-i. In addition, the gate of the NMOS transistor is supplied with a reference voltage Vref1-i generated by the reference voltage generating circuit 50, and the source and drain are supplied with a control voltage Vcnt1. The larger the control voltage Vcnt1 is, the smaller the capacitance value C3 of the variable capacitance circuit 16 becomes.

[0052] The variable capacitance circuit 17 includes n variable capacitance elements 171-1 to 171-n, n capacitance elements 172-1 to 172-n, and n capacitance elements 173-1 to 173-n. n is an integer equal to or greater than 2. For each integer i between 1 and n, the variable capacitance element 171-i is a varactor in which the source and drain of an NMOS transistor are connected, the source and drain of the NMOS transistor are connected to an XI terminal via a capacitance element 173-i, the back gate is supplied with a ground voltage Vss, and the gate is grounded via a capacitance element 172-i. The gate of the NMOS transistor is supplied with a reference voltage Vref2-i generated by the reference voltage generating circuit 50, and the source and drain are supplied with a control voltage Vcnt2. The larger the control voltage Vcnt2 is, the smaller the capacitance value C4 of the variable capacitance circuit 17 becomes.

[0053] In both of FIG. 5 and FIG. 9, the variable capacitance circuit 16 is connected to the excitation electrode 3a of the vibrator 3 via the XI terminal, and the variable capacitance circuit 17 is connected to the excitation electrode 3b of the vibrator 3 via the XO terminal. That is, the variable capacitance circuits 16 and 17 are connected to a node connected to the vibrator 3 and become part of the load capacitance of the vibrator 3. The capacitance values ​​C3 and C4 of the variable capacitance circuits 16 and 17 change according to the control voltages Vcnt1 and Vcnt2, respectively, and the control voltages Vcnt1 and Vcnt2 change according to the voltage level of a frequency control signal input from the external terminal VC1 via the VC terminal. Therefore, the oscillation frequency of the oscillation circuit 10 can be changed by the frequency control signal input from the external terminal VC1. In this way, in this embodiment, the voltage control circuit 41 generates the control voltages Vcnt1 and Vcnt2 according to the voltage level of the frequency control signal input from the external terminal VC1, but the voltage control circuit 41 may be a temperature compensation circuit and the control voltages Vcnt1 and Vcnt2 may be temperature compensation voltages.

[0054] In addition, in Figure 5, the circuit for stopping oscillation when the oscillation enable signal en_osc is at a low level is omitted, but the circuit may be, for example, a switch circuit that cuts off the supply of oscillation stage current Iosc to the amplifier element 11 when the oscillation enable signal en_osc is at a low level.

[0055] 1-3. Startup sequence In this embodiment, the oscillation circuit 2 has a plurality of operation modes including a normal operation mode and a startup mode. The normal operation mode is an operation mode in which the oscillation circuit 10 oscillates in a state in which the negative resistance value |nR|, which is the absolute value of the negative resistance, is a predetermined first value |nR1|. The startup mode is an operation mode from a state in which the oscillation circuit 10 stops oscillating until it transitions to the normal operation mode. The startup mode is, for example, an operation mode from when the oscillator 1 is powered on until it transitions to the normal operation mode. In addition, if the oscillation circuit 2 has a standby mode as an operation mode in which the oscillation circuit 10 stops oscillating while the oscillator 1 is powered on, the operation mode from when the standby mode transitions to the normal operation mode is also the startup mode.

[0056] In this embodiment, the vibrator 3 is a quartz crystal vibrator and can resonate with the main vibration or the secondary vibration. When the polarization of the X-axis, Y-axis, and Z-axis of the vibration are illustrated, the Y-axis and Z-axis are cosine waves, and the vibration mode is expressed as (pqr) if the number of peaks is p, q, and r, respectively. For example, when the vibrator 3 is an AT-cut quartz crystal vibrator, the main vibration is a thickness main vibration with a vibration mode of (1.0.0). This thickness main vibration is a pure shear vibration with only displacement in the X-axis direction, and has a certain polarization in the Z-axis direction. In addition, for example, the secondary vibration is a thickness secondary vibration with a vibration mode of (3.1.0), (5.1.0), or (7.1.0). This thickness secondary vibration is a shear vibration only in the X-axis direction, but has an odd number of sinusoidal polarizations in the X-axis direction, and the signs of adjacent extreme values ​​are opposite to each other. Alternatively, the secondary vibration may be a thickness secondary vibration having a vibration mode of (1.1.1) or (1.1.2). This thickness secondary vibration is close to the thickness primary vibration and is between the thickness primary vibration and the thickness secondary vibration having a vibration mode of (3.1.0), (5.1.0) or (7.1.0), and has one sinusoidal polarization in the X-axis direction and one or two cosine-shaped polarizations in the Z-axis direction, with adjacent extreme values ​​having opposite signs. Alternatively, the secondary vibration may be a secondary vibration due to a high-order contour vibration having a vibration mode of (21.0.0). This secondary vibration due to a high-order contour vibration has an odd number of sinusoidal polarizations in the X-axis direction, with adjacent extreme values ​​having opposite signs, and has an almost constant polarization in the Z-axis direction. Alternatively, the secondary vibration may be a secondary vibration due to a high-order contour vibration having a vibration mode of (0.0.33). The secondary vibration caused by this high-order contour vibration has an odd number of sinusoidal polarizations in the Z-axis direction, with adjacent extreme values ​​having opposite signs, and has a substantially constant polarization in the X-axis direction. Alternatively, the secondary vibration may be a secondary vibration caused by a high-order contour vibration having a vibration mode of (40.1.0), (42.1.0), or (12.1.0). The secondary vibration caused by this high-order contour vibration has an odd number of sinusoidal polarizations in the X-axis direction, with adjacent extreme values ​​having opposite signs.

[0057] The value of the series resistance under load when the vibrator 3 resonates with the main vibration, R Lm is the value of the series resistance under load R when the vibrator 3 resonates with the secondary vibration. LsIn other words, the vibration with the smallest value of the series resistance under load is the main vibration. In the normal operation mode, if the vibrator 3 resonates with the main vibration, the oscillation circuit 10 oscillates normally and an oscillation signal CK of the target frequency is obtained, but if the vibrator 3 resonates with the secondary vibration, the oscillation circuit 10 oscillates abnormally and an oscillation signal CK of the target frequency is not obtained. In the normal operation mode, in order to stably oscillate the oscillation circuit 10 with the main vibration, the negative resistance value |nR| is set to R Lm Specifically, the logic circuit 42 of the control circuit 40 supplies the current adjustment data trimI[4:0] and the capacitance adjustment data trimC1[4:0], trimC2[4:0] transferred from the nonvolatile memory 71 to the register 72 to the oscillation circuit 10, and controls the negative resistance value |nR| of the oscillation circuit 10 to be the first value |nR1| determined by the current adjustment data trimI[4:0] and the capacitance adjustment data trimC1[4:0], trimC2[4:0].

[0058] However, the first value |nR1| is Lm is sufficiently larger than R Ls Then, the first value |nR1| becomes larger than R Ls Therefore, if the negative resistance value |nR| is set to the first value |nR1| immediately after the oscillation of the oscillation circuit 10 has stopped, the resonator 3 may resonate with the secondary vibration under some conditions, and the oscillation circuit 10 may oscillate abnormally. Therefore, in this embodiment, in order to reduce the possibility of the oscillation circuit 10 oscillating abnormally, the logic circuit 42 of the control circuit 40 controls the negative resistance value |nR| of the oscillation circuit 10 in the startup mode so as to increase from a second value |nR2| that is smaller than the first value |nR1|.

[0059] Here, as described above, the first value |nR1| is the value R of the loaded series resistance when the vibrator 3 resonates with the main vibration. Lm The value of the series resistance under load R when the vibrator 3 resonates with the secondary vibration is greater than LsThe second value |nR2| is at least the value R of the loaded series resistance when the vibrator 3 resonates with the secondary vibration. Ls The second value |nR2| is the negative resistance value at which the vibrator 3 cannot resonate with the secondary vibration. The second value |nR2| is the value R of the loaded series resistance when the vibrator 3 resonates with the primary vibration. Lm For example, even when the variation in the characteristics of the resonator 3 connected to the oscillation circuit 2 is taken into consideration, the second value |nR2| can be reliably set to R Ls The second value |nR2| is set to R so that it is smaller than Lm It may be smaller than.

[0060] In this manner, in the present embodiment, the logic circuit 42 controls the negative resistance value |nR| of the oscillation circuit 10 in the startup mode so as to increase it from the second value |nR2| at which the vibrator 3 cannot resonate at least in the secondary vibration. This ensures that the negative resistance value |nR| Lm Greater than and R Ls In this state, the vibrator 3 can resonate with the primary vibration but cannot resonate with the secondary vibration. Therefore, the vibrator 3 resonates with the primary vibration before resonating with the secondary vibration, and the oscillation circuit 10 oscillates normally based on the resonance with the primary vibration.

[0061] In the oscillation circuit 10 shown in FIG. 5, the mutual conductance of the amplifier element 11 is g m The capacitance value connected to the XI terminal is C XI The capacitance value connected to the XO pin is C XO If the oscillation frequency of the oscillation circuit 10 is f=ω / 2π, the theoretical formula for the negative resistance value |nR| of the oscillation circuit 10 is given by formula (1).

[0062]

number

[0063] In addition, the mutual conductance of the amplifier element 11 is g mis expressed by equation (2), where q is the charge of an electron, k is the Boltzmann constant, and T is the absolute temperature.

[0064]

number

[0065] From equation (1), the mutual conductance of the amplifying element 11 is g m In equation (2), q, k, and T are constants, so the larger the oscillation stage current Iosc, the larger the mutual conductance g m Therefore, the larger the oscillation stage current Iosc is, the larger the negative resistance value |nR| becomes.

[0066] Therefore, in this embodiment, the logic circuit 42 of the control circuit 40 increases the negative resistance value |nR| of the oscillation circuit 10 from the second value |nR2| by increasing the value of the oscillation stage current Iosc in the startup mode. Specifically, the logic circuit 42 controls the negative resistance value |nR| to increase in a stepwise manner by changing the value of the current adjustment data trimI[4:0] output to the oscillation circuit 10 in the startup mode to increase the value of the oscillation stage current Iosc in a stepwise manner.

[0067] Fig. 10 is a waveform diagram showing an example of a sequence in which the oscillator circuit 2 transitions to a normal operation mode after power is applied to the oscillator circuit 2. In the example of Fig. 10, when power is applied to the oscillator 1, a reset period T1 starts, the power supply voltage Vdd rises from 0V to a predetermined voltage value, the power-on reset signal POR changes from a low level to a high level, and the logic circuit 42 is initialized. Thereafter, the power-on reset signal POR changes from a high level to a low level, ending the reset period T1 and starting a memory load period T2.

[0068] In the memory load period T2, various pieces of information stored in the nonvolatile memory 71 are transferred to the register 72. After this transfer is completed, the logic circuit 42 changes the oscillation enable signal en_osc from low level to high level, thereby ending the memory load period T2 and starting the startup period T3.

[0069] In the startup period T3, the logic circuit 42 increases the current adjustment data trimI[4:0] stepwise by an arbitrary value from the start value to the end value, and the value of the oscillation stage current Iosc increases stepwise accordingly. The start value and end value of the current adjustment data trimI[4:0] may be set to an arbitrary value by being written in advance to the non-volatile memory 71, for example. In the example of FIG. 10, the logic circuit 42 increases the current adjustment data trimI[4:0] stepwise by 1 in sequence from the start value of 0, and the value of the oscillation stage current Iosc increases stepwise accordingly. b As a result, during the startup period T3, the negative resistance value |nR| of the oscillation circuit 10 increases stepwise from the second value |nR2|. Lm Greater than and R Ls When the amplitude of the current I_xtal exceeds a predetermined threshold, a pulse is generated in the oscillation signal CK. After that, the current adjustment data trimI[4:0] continues to increase, and the negative resistance value |nR| becomes equal to or larger than R. Ls However, at that point, the oscillation of the oscillation circuit 10 due to the resonance of the main vibration of the vibrator 3 has grown sufficiently, so that the resonance of the secondary vibration of the vibrator 3 does not occur. When the current adjustment data trimI[4:0] further increases and reaches the end value of 31, the value of the oscillation stage current Iosc becomes I b+31I0. Thereafter, the logic circuit 42 changes the value of the current adjustment data trimI[4:0] stepwise by any value from the end value to the set value in the normal operation mode. In the example of FIG. 10, the logic circuit 42 decreases the value of the current adjustment data trimI[4:0] stepwise by 1 from the end value of 31, and when the set value of the current adjustment data trimI[4:0] in the normal operation mode reaches 20, which is the value transferred to the register 72 in the memory load period T2, the value of the oscillation stage current Iosc becomes I b +20I0, and the negative resistance value |nR| becomes the first value |nR1|. Then, the logic circuit 42 holds the value of the current adjustment data trimI[4:0] at 20 and changes the output enable signal en_out from low level to high level, thereby ending the startup period T3 and starting the normal operation period T4.

[0070] During the normal operation period T4, since the output enable signal en_out is at a high level, the oscillation signal CK is buffered and a pulse is generated in the oscillation signal CKO.

[0071] 10, the operation mode in the startup period T3 is the startup mode, and the operation mode in the normal operation period T4 is the normal operation mode, or the operation mode in the reset period T1, the memory load period T2, and the startup period T3 is the startup mode.

[0072] 10, the logic circuit 42 increases the current adjustment data trimI[4:0] from the minimum value to the maximum value in the startup mode, and then decreases it to the set value in the normal operation mode, so that the startup period T3 is long. In contrast, other sequences in which the startup period T3 is shortened are also possible.

[0073] FIG. 11 is a waveform diagram showing another example of a sequence in which the oscillation circuit 2 is powered on and then transitions to the normal operation mode. In the example of FIG. 11, during the startup period T3, the logic circuit 42 increases the current adjustment data trimI[4:0] stepwise by any value from the start value to the set value in the normal operation mode, and the value of the oscillation stage current Iosc increases stepwise accordingly. The start value of the current adjustment data trimI[4:0] may be set to any value by, for example, being written in advance to the non-volatile memory 71. In the example of FIG. 11, the logic circuit 42 increases the current adjustment data trimI[4:0] stepwise by one from the start value of 0 to the set value in the normal operation mode of 20, and the value of the oscillation stage current Iosc increases stepwise accordingly. b From I b +20I0 by I0. As a result, during the startup period T3, the negative resistance value |nR| of the oscillation circuit 10 increases in a stepwise manner from the second value |nR2| to the first value |nR1|. Then, the logic circuit 42 holds the value of the current adjustment data trimI[4:0] at 20 and changes the output enable signal en_out from low level to high level, thereby ending the startup period T3 and starting the normal operation period T4.

[0074] 11, the logic circuit 42 does not need to increase the current adjustment data trimI[4:0] from the start value to the end value, and therefore the startup period T3 is shortened. Also, in the example of FIG. 11, the first value |nR1|, which is the setting value of the negative resistance value |nR| in the normal operation mode, is equal to or greater than the maximum value of the negative resistance value |nR| in the startup period T3. In other words, since the negative resistance value |nR| does not become larger than the first value |nR1| in the startup period T3, the negative resistance value |nR| becomes equal to or greater than the value R of the loaded series resistance when the vibrator 3 resonates in the secondary vibration. Ls Therefore, the time during which the value becomes larger than the maximum vibration frequency is short, and resonance in the secondary vibration of the vibrator 3 is less likely to occur.

[0075] 11, the operation mode in the startup period T3 is the startup mode, and the operation mode in the normal operation period T4 is the normal operation mode, or the operation mode in the reset period T1, the memory load period T2, and the startup period T3 is the startup mode.

[0076] 1-4.How to control the oscillation circuit Fig. 12 is a flow chart showing an example of the procedure of the control method of the oscillation circuit 2. As shown in Fig. 12, when the oscillator 1 is powered on, the oscillation circuit 2 first performs a reset step S1. Specifically, in the reset step S1, the power-on reset circuit 30 changes the power-on reset signal POR from a low level to a high level to initialize the logic circuit 42. Then, the power-on reset circuit 30 changes the power-on reset signal POR from a high level to a low level, and the reset step S1 ends. The period of the reset step S1 corresponds to the reset period T1 in Fig. 10 or 11.

[0077] Next, the oscillation circuit 2 performs a memory load step S2. Specifically, in the memory load step S2, the memory circuit 70 transfers various pieces of information stored in the nonvolatile memory 71 to the register 72. After the transfer is completed, the logic circuit 42 sets the oscillation enable signal en_osc to a high level, and the memory load step S2 ends. The period of the memory load step S2 corresponds to the memory load period T2 in FIG. 10 or FIG. 11.

[0078] Next, the oscillation circuit 2 performs a startup step S3. Specifically, in the startup step S3, the logic circuit 42 sets the oscillation enable signal en_osc to a high level and controls the negative resistance value |nR| of the oscillation circuit 10 to increase from a second value |nR2| that is smaller than the first value |nR1|. Then, the logic circuit 42 changes the output enable signal en_out from a low level to a high level, and the startup step S3 ends. The period of the startup step S3 corresponds to the startup period T3 in FIG. 10 or FIG. 11.

[0079] Finally, the oscillation circuit 2 performs a normal operation step S4. Specifically, in the normal operation step S4, the oscillation circuit 10 oscillates with its negative resistance value |nR| being a second value |nR2|, and the oscillation signal CKO output from the output circuit 60 is output from the external terminal OUT1 of the oscillator 1 via the OUT terminal. The period of the normal operation step S4 corresponds to the normal operation period T4 in FIG. 10 or FIG. 11.

[0080] The operation mode in the startup step S3 is the startup mode, and the operation mode in the normal operation step S4 is the normal operation mode. Alternatively, the operation mode in the reset step S1, the memory load step S2, and the startup step S3 is the startup mode.

[0081] Fig. 13 is a flow chart showing an example of the procedure of the startup step S3 of Fig. 12 in the first embodiment. The procedure shown in Fig. 13 corresponds to the operation in the startup period T3 of Fig. 10. As shown in Fig. 13, first, in step S31, the logic circuit 42 sets the current adjustment data trimI[4:0] to a starting value. In the example of Fig. 10, the starting value is 0. By setting the current adjustment data trimI[4:0] to the starting value, the negative resistance value |nR| of the oscillation circuit 10 becomes a second value |nR2|.

[0082] Next, when a predetermined time has elapsed in step S32, in step S33, the logic circuit 42 determines whether or not the value of the current adjustment data trimI[4:0] matches the end value. In the example of FIG.

[0083] If the value of the current adjustment data trimI[4:0] does not match the end value in step S33, the logic circuit 42 changes the value of the current adjustment data trimI[4:0] to increase the oscillation stage current Iosc in step S34.

[0084] Steps S32, S33, and S34 are repeated until the value of the current adjustment data trimI[4:0] matches the end value, and when the value of the current adjustment data trimI[4:0] matches the end value, in step S35, the logic circuit 42 changes the current adjustment data trimI[4:0] to the set value in the normal operation mode.

[0085] Then, in step S36, the logic circuit 42 sets the output enable signal en_out to a high level, and the startup step S3 ends.

[0086] Fig. 14 is a flow chart showing another example of the procedure of the startup step S3 of Fig. 12 in the first embodiment. The procedure shown in Fig. 14 corresponds to the operation in the startup period T3 of Fig. 11. As shown in Fig. 14, first, in step S101, the logic circuit 42 sets the current adjustment data trimI[4:0] to a start value. In the example of Fig. 11, the start value is 0. By setting the current adjustment data trimI[4:0] to the start value, the negative resistance value |nR| of the oscillation circuit 10 becomes a second value |nR2|.

[0087] Next, when a predetermined time has elapsed in step S102, in step S103, the logic circuit 42 determines whether the value of the current adjustment data trimI[4:0] matches the set value in the normal operation mode. The set value of the current adjustment data trimI[4:0] in the normal operation mode is the value stored in the non-volatile memory 71.

[0088] If in step S103 the value of the current adjustment data trimI[4:0] does not match the set value in the normal operation mode, in step S104 the logic circuit 42 changes the value of the current adjustment data trimI[4:0] to increase the oscillation stage current Iosc.

[0089] Then, steps S102, S103, and S104 are repeated until the value of the current adjustment data trimI[4:0] matches the set value in the normal operation mode, and when the value of the current adjustment data trimI[4:0] matches the set value in the normal operation mode, in step S105, the logic circuit 42 sets the output enable signal en_out to a high level, and the startup step S3 is completed.

[0090] 1-5.Effects In the oscillator 1 of the first embodiment described above, in the oscillation circuit 2, in a startup mode from a state in which the oscillation circuit 10 stops oscillating to a normal operation mode in which the oscillation circuit 10 oscillates with the negative resistance value |nR| of the oscillation circuit 10 at a first value |nR1|, the negative resistance value |nR| of the oscillation circuit 10 increases from a second value |nR2| smaller than the first value |nR1|. Lm is the value of the series resistance under load when the vibrator 3 resonates with the secondary vibration, R Ls Since the negative resistance value |nR| of the oscillation circuit 10 is smaller than the second value |nR2|, the negative resistance value |nR| of the oscillation circuit 10 increases from the second value |nR2| to R Lm Greater than and R Ls Therefore, in the startup mode, the oscillation based on the resonance in the main vibration of the vibrator 3 grows before the oscillation based on the resonance in the secondary vibration of the vibrator 3. Therefore, according to the oscillator 1 of the first embodiment, the risk of abnormal oscillation can be reduced even if the characteristics of the vibrator 3 vary.

[0091] In particular, in the oscillator 1 of the first embodiment, in the startup mode, by increasing the value of the oscillation stage current Iosc, the negative resistance value |nR| of the oscillation circuit 10 gradually increases in a stepwise manner from the second value |nR2|. Lm Greater than and R Ls The time during which the value becomes smaller than 10 ...

[0092] Furthermore, according to the oscillator 1 of the first embodiment, the variable current source 12 for setting the oscillation stage current Iosc to a desired value according to the resonant frequency of the resonator 3 in the normal operation mode can also be used to increase the negative resistance value |nR| of the oscillation circuit 10 in the startup mode.

[0093] 2. Second embodiment In the following, for the oscillator 1 of the second embodiment, the same reference numerals are used for configurations similar to those of the first embodiment, the description of the same parts as those of the first embodiment is omitted or simplified, and differences from the first embodiment are mainly described.

[0094] The configuration of the oscillator 1 of the second embodiment is the same as that of Fig. 1 to Fig. 4, and therefore illustration and description thereof will be omitted. Also, the configuration of the oscillation circuit 10 in the second embodiment is the same as that of Fig. 5, and therefore illustration and description thereof will be omitted. The oscillator 1 of the second embodiment differs from the oscillator 1 of the first embodiment in the operation in the startup mode.

[0095] From the above equation (1), the capacitance value C XI ,C XO The smaller at least one of the capacitance values ​​C1, C2 of the variable capacitance circuits 14, 15 is made, the larger the negative resistance value |nR| becomes. Therefore, in the second embodiment, the logic circuit 42 of the control circuit 40 increases the negative resistance value |nR| of the oscillation circuit 10 from the second value |nR2| by decreasing at least one of the capacitance values ​​C1, C2 of the variable capacitance circuits 14, 15 in the startup mode. Specifically, the logic circuit 42 changes at least one of the capacitance adjustment data trimC1[4:0], trimC2[4:0] output to the oscillation circuit 10 in the startup mode to increase at least one of the capacitance values ​​C1, C2 of the variable capacitance circuits 14, 15 in a stepwise manner, thereby controlling the negative resistance value |nR| to increase in a stepwise manner.

[0096] Other configurations of the oscillator 1 of the second embodiment are similar to those of the first embodiment, and therefore illustrations and descriptions thereof will be omitted.

[0097] Fig. 15 is a waveform diagram showing an example of a sequence in which the oscillator circuit 2 transitions to a normal operation mode after power is applied to the oscillator circuit 2 in the second embodiment. In the example of Fig. 15, when power is applied to the oscillator 1, a reset period T1 starts, the power supply voltage Vdd rises from 0V to a predetermined voltage value, the power-on reset signal POR changes from a low level to a high level, and the logic circuit 42 is initialized. Thereafter, the power-on reset signal POR changes from a high level to a low level, ending the reset period T1 and starting a memory load period T2.

[0098] In the memory load period T2, various pieces of information stored in the nonvolatile memory 71 are transferred to the register 72. After this transfer is completed, the logic circuit 42 changes the oscillation enable signal en_osc from low level to high level, thereby ending the memory load period T2 and starting the startup period T3.

[0099] In the startup period T3, the logic circuit 42 increases the capacitance adjustment data trimC1[4:0], trimC2[4:0] stepwise by an arbitrary value from the start value to the set value in the normal operation mode, and the capacitance values ​​C1, C2 increase stepwise accordingly. The start values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] may be set to an arbitrary value by, for example, being written in advance to the non-volatile memory 71. In the example of FIG. 15, the logic circuit 42 increases the capacitance adjustment data trimC1[4:0], trimC2[4:0] stepwise by 1 from the start value of 0, and the capacitance values ​​C1, C2 decrease stepwise from 31C0, respectively. As a result, in the startup period T3, the negative resistance value |nR| of the oscillation circuit 10 increases stepwise from the second value |nR2|. When the negative resistance value |nR| Lm Greater than and R LsWhen the amplitude of the current I_xtal exceeds a predetermined threshold, a pulse is generated in the oscillation signal CK. After that, the capacitance adjustment data trimC1[4:0], trimC2[4:0] continue to increase, and the negative resistance value |nR| becomes equal to or larger than R. Ls However, at that point, the oscillation of the oscillation circuit 10 due to the resonance with the main vibration of the vibrator 3 has grown sufficiently, so that resonance with the secondary vibration of the vibrator 3 does not occur. When the capacitance adjustment data trimC1[4:0], trimC2[4:0] further increase and reach 20, which is the value transferred to the register 72 in the memory load period T2, the capacitance values ​​C1, C2 each become 11C0, and the negative resistance value |nR| becomes the first value |nR1|. Then, the logic circuit 42 holds the values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] at 20 and changes the output enable signal en_out from low level to high level, thereby ending the startup period T3 and starting the normal operation period T4.

[0100] During the normal operation period T4, since the output enable signal en_out is at a high level, the oscillation signal CK is buffered and a pulse is generated in the oscillation signal CKO.

[0101] In addition, during the startup period T3, both capacitance values ​​C1 and C2 are decreased by increasing both capacitance adjustment data trimC1[4:0] and trimC2[4:0], but it is also possible to fix one of the capacitance values ​​C1 and C2 and decrease the other by fixing one of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] and increasing the other.

[0102] 15, the first value |nR1|, which is the set value of the negative resistance value |nR| in the normal operation mode, is equal to or greater than the maximum value of the negative resistance value |nR| in the startup period T3. In other words, in the startup period T3, the negative resistance value |nR| does not become larger than the first value |nR1|, so that the negative resistance value |nR| is equal to or smaller than the value R of the loaded series resistance when the vibrator 3 resonates in the secondary vibration. LsTherefore, the time during which the value becomes larger than the maximum vibration frequency is short, and resonance in the secondary vibration of the vibrator 3 is less likely to occur.

[0103] 15, the operation mode in the startup period T3 is the startup mode, and the operation mode in the normal operation period T4 is the normal operation mode. Alternatively, the operation mode in the reset period T1, the memory load period T2, and the startup period T3 is the startup mode.

[0104] Although the sequence is not shown, during the startup period T3, the logic circuit 42 may increase at least one of the capacity adjustment data trimC1[4:0], trimC2[4:0] stepwise by any value from the start value to the end value, and then decrease it stepwise by any value to the set value in the normal operation mode.

[0105] A flow chart showing the procedure of the control method of the oscillation circuit 2 in the second embodiment is the same as that in Fig. 12, and therefore the illustration and description thereof will be omitted. However, in the second embodiment, the procedure of the start-up step S3 in Fig. 12 is different from that in the first embodiment.

[0106] 16 is a flow chart showing an example of the procedure of the startup process S3 of FIG. 12 in the second embodiment. The procedure shown in FIG. 16 corresponds to the operation in the startup period T3 of FIG. 15. As shown in FIG. 16, first, in step S201, the logic circuit 42 sets the capacitance adjustment data trimC1[4:0], trimC2[4:0] to start values. In the example of FIG. 15, both start values ​​are 0. By setting the capacitance adjustment data trimC1[4:0], trimC2[4:0] to start values, the negative resistance value |nR| of the oscillation circuit 10 becomes the second value |nR2|.

[0107] Next, when a predetermined time has elapsed in step S202, in step S203, the logic circuit 42 determines whether or not the values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] match the set values ​​in the normal operation mode. The set values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] in the normal operation mode are values ​​stored in the non-volatile memory 71.

[0108] If, in step S203, the values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] do not match the set values ​​in the normal operating mode, in step S204, the logic circuit 42 changes the values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] to reduce the capacitance values ​​C1, C2.

[0109] Then, steps S202, S203, and S204 are repeated until the values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] match the set values ​​in the normal operation mode. When the values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] match the set values ​​in the normal operation mode, in step S205, the logic circuit 42 sets the output enable signal en_out to a high level, and the startup step S3 is completed.

[0110] Alternatively, the logic circuit 42 may fix one of the capacitance adjustment data trimC1[4:0], trimC2[4:0] and change the other, thereby fixing one of the capacitance values ​​C1, C2 and decreasing the other.

[0111] In the oscillator 1 of the second embodiment described above, in the startup mode, the capacitance values ​​C1 and C2 of the variable capacitance circuits 14 and 15 are reduced, so that the negative resistance value |nR| of the oscillation circuit 10 gradually increases in a stepwise manner from the second value |nR2|. Therefore, the value R of the loaded series resistance when the vibrator 3 resonates with the main vibration is Lm The value of the series resistance under load R when the vibrator 3 resonates with the secondary vibration is greater than LsThe time during which the value becomes smaller than 10 ...

[0112] Furthermore, according to the oscillator 1 of the second embodiment, the variable capacitance circuits 14, 15 for setting the oscillation frequency of the oscillation circuit 10 to a target frequency in the normal operation mode can also be used to increase the negative resistance value |nR| of the oscillation circuit 10 in the startup mode.

[0113] 3. Third embodiment Hereinafter, for the oscillator 1 of the third embodiment, the same symbols will be used for configurations similar to any of the above embodiments, and descriptions of similarities with any of the above embodiments will be omitted or simplified, and mainly the differences from any of the above embodiments will be described.

[0114] The configuration of the oscillator 1 of the third embodiment is the same as that of Fig. 1 to Fig. 4, and therefore illustration and description thereof will be omitted. Also, the configuration of the oscillation circuit 10 in the third embodiment is the same as that of Fig. 5, and therefore illustration and description thereof will be omitted. The oscillator 1 of the third embodiment differs from the oscillator 1 of each of the above embodiments in operation in the startup mode.

[0115] From the above equation (1), the capacitance value C XI ,C XO The smaller at least one of them is, the larger the negative resistance value |nR| becomes. Therefore, in the third embodiment, the voltage control circuit 41 of the control circuit 40 increases the negative resistance value |nR| of the oscillation circuit 10 from the second value |nR2| by decreasing at least one of the capacitance values ​​C3, C4 of the variable capacitance circuits 16, 17 in the startup mode. Specifically, the voltage control circuit 41 changes the value of at least one of the control voltages Vcnt1, Vcnt2 output to the oscillation circuit 10 in the startup mode to continuously increase at least one of the capacitance values ​​C3, C4 of the variable capacitance circuits 16, 17, thereby controlling the negative resistance value |nR| to continuously increase.

[0116] 17 is a diagram showing an example of the configuration of a voltage control circuit 41 in the third embodiment. As shown in FIG. 17, the voltage control circuit 41 includes a control voltage generation circuit 200, a filter circuit 210, a switch circuit 220, a filter circuit 230, a switch circuit 240, a resistor 250, and a resistor 260.

[0117] In the normal operation mode, the control voltage generation circuit 200 generates control voltages Vcnt1X, Vcnt2X for changing the oscillation frequency of the oscillation circuit 10 in accordance with the voltage level of a frequency control signal supplied from the external terminal VC1 via the VC terminal. In addition, in the startup mode, the control voltage generation circuit 200 outputs the control voltages Vcnt1X, Vcnt2X in accordance with the control from the logic circuit 42. The control voltage Vcnt1X is input to the filter circuit 210, and the control voltage Vcnt2X is input to the filter circuit 230.

[0118] The filter circuit 210 is a low-pass filter circuit including a resistor 211 and a capacitive element 212, and outputs a control voltage Vcnt1f that has a gentle rise or fall of the control voltage Vcnt1.

[0119] The switch circuit 220 selects and outputs the control voltage Vcnt1X in the normal operation mode, and selects and outputs the control voltage Vcnt1f in the startup mode, in accordance with control from the logic circuit 42. The voltage output from the switch circuit 220 is supplied to the variable capacitance circuit 16 in FIG. 5 via a resistor 250 as the control voltage Vcnt1.

[0120] The filter circuit 230 is a low-pass filter circuit including a resistor 231 and a capacitive element 232, and outputs a control voltage Vcnt2f that has a gentle rise or fall of the control voltage Vcnt2.

[0121] The switch circuit 240 selects and outputs the control voltage Vcnt2X in the normal operation mode, and selects and outputs the control voltage Vcnt2f in the startup mode, in accordance with control from the logic circuit 42. The voltage output from the switch circuit 240 is supplied to the variable capacitance circuit 17 in FIG. 5 via a resistor 260 as the control voltage Vcnt2.

[0122] The other configuration of the oscillator 1 of the third embodiment is similar to that of the above-described embodiments, and therefore illustration and description thereof will be omitted.

[0123] Fig. 18 is a waveform diagram showing an example of a sequence in which the oscillator circuit 2 is powered on and then transitions to a normal operation mode in the third embodiment. In the example of Fig. 18, when the oscillator 1 is powered on, a reset period T1 starts, the power supply voltage Vdd rises from 0V to a predetermined voltage value, the power-on reset signal POR changes from a low level to a high level, and the logic circuit 42 is initialized. Thereafter, the power-on reset signal POR changes from a high level to a low level, ending the reset period T1 and starting a memory load period T2.

[0124] In the memory load period T2, various pieces of information stored in the nonvolatile memory 71 are transferred to the register 72. After this transfer is completed, the logic circuit 42 changes the oscillation enable signal en_osc from low level to high level, thereby ending the memory load period T2 and starting the startup period T3.

[0125] In the startup period T3, under the control of the logic circuit 42, the control voltage generation circuit 200 in the voltage control circuit 41 sets the control voltages Vcnt1X and Vcnt2X to the start values ​​V start to the end value V endto the start-up period T3, and the switch circuits 220, 240 select and output the control voltages Vcnt1f, Vcnt2f output from the filter circuits 210, 230. This causes the control voltages Vcnt1, Vcnt2 to rise more gently, and the control voltages Vcnt1, Vcnt2 increase continuously, with the capacitance values ​​C3, C4 decreasing continuously accordingly. As a result, during the start-up period T3, the negative resistance value |nR| of the oscillation circuit 10 increases continuously from the second value |nR2|. When the negative resistance value |nR| Lm Greater than and R Ls When |nR| is smaller than the threshold value, the vibrator 3 starts to resonate with the main vibration, and the amplitude of the current I_xtal output from the vibrator 3 increases. Then, when the amplitude of the current I_xtal exceeds a predetermined threshold value, a pulse is generated in the oscillation signal CK. After that, the control voltages Vcnt1 and Vcnt2 continue to increase, and the negative resistance value |nR| Ls However, at this point, the oscillation of the oscillation circuit 10 due to the resonance of the main vibration of the vibrator 3 has grown sufficiently, so that the resonance of the secondary vibration of the vibrator 3 does not occur. The control voltages Vcnt1 and Vcnt2 further increase to the final value V end When the end value V reaches the predetermined value, the capacitance values ​​C3 and C4 become predetermined values, and the negative resistance value |nR| becomes the first value |nR1|. For example, end may be the voltage value of the frequency control signal input from the VC terminal. The logic circuit 42 changes the output enable signal en_out from low level to high level, whereby the startup period T3 ends and the normal operation period T4 begins. start or the end value V end may be set to an arbitrary value by being written in advance to the non-volatile memory 71, for example.

[0126] During the normal operation period T4, since the output enable signal en_out is at a high level, the oscillation signal CK is buffered and a pulse is generated in the oscillation signal CKO.

[0127] In addition, during the start-up period T3, both of the capacitance values ​​C3 and C4 are decreased by increasing both of the control voltages Vcnt1 and Vcnt2, but it is also possible to fix one of the capacitance values ​​C3 and C4 and decrease the other by fixing one of the control voltages Vcnt1 and Vcnt2 and increasing the other.

[0128] 18, the operation mode in the startup period T3 is the startup mode, and the operation mode in the normal operation period T4 is the normal operation mode. Alternatively, the operation mode in the reset period T1, the memory load period T2, and the startup period T3 is the startup mode.

[0129] Although the sequence is not shown, in the start-up period T3, at least one of the control voltages Vcnt1 and Vcnt2 is set to the start value V start to the end value V end After continuously increasing to the end value V end For example, the minimum and maximum values ​​of the variable range of the control voltages Vcnt1 and Vcnt2 may be set to a starting value V start and the end value V end It is also possible to use the following.

[0130] The flowchart showing the procedure of the control method of the oscillation circuit 2 in the third embodiment is the same as that in Fig. 12, and therefore the illustration and description thereof will be omitted. However, in the third embodiment, the procedure of the start-up step S3 in Fig. 12 is different from the above-mentioned embodiments.

[0131] Fig. 19 is a flow chart showing an example of the procedure of the start-up step S3 of Fig. 12 in the third embodiment. The procedure shown in Fig. 19 corresponds to the operation in the start-up period T3 of Fig. 18. As shown in Fig. 19, first, in step S301, the logic circuit 42 sets the switch circuits 220, 240 of the voltage control circuit 41 to select the output voltages of the filter circuits 210, 230.

[0132] Next, in step S302, the logic circuit 42 causes the control voltage generating circuit 200 of the voltage control circuit 41 to set the control voltages Vcnt1X and Vcnt2X to the starting value V start to the end value V end As a result, the control voltages Vcnt1 and Vcnt2 change continuously from the start value to the end value.

[0133] Then, when the predetermined time has elapsed in step S303, the logic circuit 42 sets the output enable signal en_out to a high level in step S304, and the startup step S3 ends. For example, the predetermined time is when the control voltages Vcnt1 and Vcnt2 are at the start value V start to the end value V end and is appropriately determined based on the time constants of the filter circuits 210 and 230.

[0134] Alternatively, the logic circuit 42 may fix one of the control voltages Vcnt1X, Vcnt2X and change the other, thereby fixing one of the capacitance values ​​C1, C2 and decreasing the other.

[0135] In the oscillator 1 of the third embodiment described above, in the startup mode, the capacitance values ​​C3 and C4 of the variable capacitance circuits 16 and 17 are reduced, so that the negative resistance value |nR| of the oscillation circuit 10 is continuously and gradually increased from the second value |nR2|. Therefore, the value R of the loaded series resistance when the vibrator 3 resonates with the main vibration is Lm The value of the series resistance under load R when the vibrator 3 resonates with the secondary vibration is greater than Ls The time during which the value becomes smaller than 10 ...

[0136] Furthermore, according to the oscillator 1 of the third embodiment, the variable capacitance circuits 16, 17 for changing the oscillation frequency of the oscillation circuit 10 by a frequency control signal input from the external terminal VC1 in the normal operation mode can also be used to increase the negative resistance value |nR| of the oscillation circuit 10 in the startup mode.

[0137] 4. Fourth embodiment Hereinafter, for the oscillator 1 of the fourth embodiment, the same symbols will be used for configurations similar to any of the above embodiments, and descriptions similar to any of the above embodiments will be omitted or simplified, and mainly the differences from any of the above embodiments will be described.

[0138] The configuration of the oscillator 1 of the fourth embodiment is the same as that of Fig. 1 to Fig. 4, and therefore illustration and description thereof will be omitted. Also, the configuration of the oscillation circuit 10 in the fourth embodiment is the same as that of Fig. 5, and therefore illustration and description thereof will be omitted. The oscillator 1 of the fourth embodiment differs from the oscillator 1 of each of the above embodiments in operation in the startup mode.

[0139] In the fourth embodiment, in the startup mode, the logic circuit 42 of the control circuit 40 increases the value of the oscillation stage current Iosc and decreases at least one of the capacitance values ​​C1, C2 of the variable capacitance circuits 14, 15, thereby increasing the negative resistance value |nR| from the second value |nR2|. For example, in the startup mode, the logic circuit 42 may repeatedly perform control to increase the value of the oscillation stage current Iosc from the third value to a fourth value greater than the third value without changing the capacitance values ​​C1, C2 of the variable capacitance circuits 14, 15, and then decrease at least one of the capacitance values ​​C1, C2 and change the value of the oscillation stage current Iosc to the third value. For example, in the startup mode, the logic circuit 42 first holds at least one of the capacitance adjustment data trimC1[4:0], trimC2[4:0] to be output to the oscillation circuit 10 at a starting value, and changes the value of the current adjustment data trimI[4:0] to be output to the oscillation circuit 10 from the starting value to the ending value to increase the value of the oscillation stage current Iosc in a stepwise manner from the third value to the fourth value, thereby controlling the negative resistance value |nR| to increase in a stepwise manner. Next, the logic circuit 42 changes the value of the current adjustment data trimI[4:0] to the start value, and then changes and holds at least one of the values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] to decrease at least one of the capacitance values ​​C1, C2 by one step, and changes the value of the current adjustment data trimI[4:0] from the start value to the end value to increase the value of the oscillation stage current Iosc in a stepwise manner from the third value to the fourth value, thereby controlling so that the negative resistance value |nR| increases in a stepwise manner. The logic circuit 42 repeats the same control while changing at least one of the values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0]. Finally, the logic circuit 42 changes the value of the current adjustment data trimI[4:0] to the start value, and then changes and holds at least one of the values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] to the end value, thereby decreasing the capacitance values ​​C1 and C2 by one step, and changes the value of the current adjustment data trimI[4:0] from the start value to the end value, thereby increasing the value of the oscillation stage current Iosc in steps from the third value to the fourth value, thereby controlling the negative resistance value |nR| to increase in steps.

[0140] The other configuration of the oscillator 1 of the fourth embodiment is similar to that of the above-described embodiments, and therefore illustration and description thereof will be omitted.

[0141] Fig. 20 is a waveform diagram showing another example of a sequence in which the oscillator circuit 2 transitions to a normal operation mode after power is applied to the oscillator circuit 2 in the fourth embodiment. In the example of Fig. 20, when power is applied to the oscillator 1, a reset period T1 starts, the power supply voltage Vdd rises from 0V to a predetermined voltage value, the power-on reset signal POR changes from a low level to a high level, and the logic circuit 42 is initialized. Thereafter, the power-on reset signal POR changes from a high level to a low level, ending the reset period T1 and starting the memory load period T2.

[0142] In the memory load period T2, various pieces of information stored in the nonvolatile memory 71 are transferred to the register 72. After this transfer is completed, the logic circuit 42 changes the oscillation enable signal en_osc from low level to high level, thereby ending the memory load period T2 and starting the startup period T3.

[0143] In the start-up period T3, the logic circuit 42 first sets and holds the capacitance adjustment data trimC1[4:0] and trimC2[4:0] to their respective start values, and increases the current adjustment data trimI[4:0] stepwise from the start value to the end value by an arbitrary value, and accordingly, the value of the oscillation stage current Iosc increases stepwise. The start values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] and the start and end values ​​of the current adjustment data trimI[4:0] may be set to arbitrary values ​​by being written in advance to the non-volatile memory 71, for example. In the example of FIG. 20, the logic circuit 42 sets and holds the capacitance adjustment data trimC1[4:0] and trimC2[4:0] to their respective start values ​​of 0, and increases the current adjustment data trimI[4:0] stepwise by 1 from the start value of 0 to the end value of 31. As a result, when the capacitances C1 and C2 are each 31C0, the oscillation stage current Iosc becomes the third value Ib The fourth value, I b The negative resistance value |nR| of the oscillation circuit 10 increases in a stepwise manner from the second value |nR2| to +31I0.

[0144] Next, the logic circuit 42 changes the current adjustment data trimI[4:0] to the starting value of 0, and then increases the values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] by an arbitrary value. In the example of FIG. 20, the values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] are each set to 1, which is a value obtained by increasing the value by 1 from 0, and are maintained, and the current adjustment data trimI[4:0] is again increased stepwise by 1 from the starting value of 0 to the ending value of 31. As a result, with the capacitance values ​​C1, C2 each reduced to 30C0, the oscillation stage current Iosc increases to a third value I b The fourth value, I b The negative resistance value |nR| of the oscillation circuit 10 increases stepwise to +31I0.

[0145] Next, the logic circuit 42 changes the current adjustment data trimI[4:0] to the starting value of 0, and then increases the values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] by an arbitrary value. In the example of Fig. 20, the values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] are each set to and held at 2, which is a value obtained by increasing the value by 1 from 1, and the current adjustment data trimI[4:0] is again increased stepwise by 1 from the starting value of 0 to the ending value of 31. As a result, with the capacitance values ​​C1, C2 each reduced to 29C0, the oscillation stage current Iosc increases to a third value I b The fourth value, I b +31I0, the negative resistance value |nR| of the oscillation circuit 10 increases in a stepwise manner. Lm Greater than and R LsWhen the amplitude of the current I_xtal exceeds a predetermined threshold, a pulse is generated in the oscillation signal CK. After that, the capacitance adjustment data trimC1[4:0], trimC2[4:0] continue to increase, and the negative resistance value |nR| becomes equal to or larger than R. Ls However, at this point in time, the oscillation of the oscillation circuit 10 due to the resonance with the main vibration of the vibrator 3 has grown sufficiently, so that resonance with the secondary vibration of the vibrator 3 does not occur.

[0146] Thereafter, when the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] reach the end value of 31 and the value of the current adjustment data trimI[4:0] reaches the end value of 31, the logic circuit 42 changes the value of the current adjustment data trimI[4:0] stepwise by any value from the end value to the set value in the normal operation mode. The end values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] may be set to any value by being written in advance to the non-volatile memory 71, for example. In the example of FIG. 20, the logic circuit 42 decreases the value of the current adjustment data trimI[4:0] stepwise by 1 from the end value of 31. Then, when the value of the current adjustment data trimI[4:0] reaches 24, which is the value transferred to the register 72 in the memory load period T2, the logic circuit 42 holds the value of the current adjustment data trimI[4:0] at 24 and sets the value of the oscillation stage current Iosc to I b+24I0. Furthermore, the logic circuit 42 changes the values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] stepwise by any value from the end value to the set value in the normal operation mode. In the example of FIG. 20, the logic circuit 42 decreases the values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] stepwise by 1 from the end value of 31. Then, when the values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] reach 26, which is the value transferred to the register 72 during the memory load period T2, the logic circuit 42 holds the values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] at 26, and the capacitance values ​​C1, C2 become 5C0. The value of the oscillation stage current Iosc is I b The capacitance value C1 and the capacitance value C2 each become +24I0 and 5C0, so that the negative resistance value |nR| becomes the first value |nR1|. Then, the logic circuit 42 changes the output enable signal en_out from a low level to a high level, whereby the startup period T3 ends and the normal operation period T4 begins.

[0147] During the normal operation period T4, since the output enable signal en_out is at a high level, the oscillation signal CK is buffered and a pulse is generated in the oscillation signal CKO.

[0148] In addition, during the startup period T3, both capacitance values ​​C1 and C2 are decreased by increasing both capacitance adjustment data trimC1[4:0] and trimC2[4:0], but it is also possible to fix one of the capacitance values ​​C1 and C2 and decrease the other by fixing one of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] and increasing the other.

[0149] 20, the operation mode in the startup period T3 is the startup mode, and the operation mode in the normal operation period T4 is the normal operation mode, or the operation mode in the reset period T1, the memory load period T2, and the startup period T3 is the startup mode.

[0150] Although the sequence is not illustrated, in order to shorten the startup period T3, when the values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] reach any preset end values ​​and the value of the current adjustment data trimI[4:0] reaches its end value, the logic circuit 42 may reduce the value of the current adjustment data trimI[4:0] to the set value in the normal operation mode and end the startup period T3. For example, the end values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] may be the set values ​​in the normal operation mode.

[0151] The flowchart showing the procedure of the control method of the oscillation circuit 2 in the fourth embodiment is the same as that in Fig. 12, and therefore the illustration and description thereof will be omitted. However, in the fourth embodiment, the procedure of the start-up step S3 in Fig. 12 is different from each of the above embodiments.

[0152] FIG. 21 is a flow chart showing an example of the procedure of the startup process S3 of FIG. 12 in the fourth embodiment. The procedure shown in FIG. 21 corresponds to the operation of the startup period T3 of FIG. 20. As shown in FIG. 21, first, in step S401, the logic circuit 42 sets the current adjustment data trimI[4:0] and the capacitance adjustment data trimC1[4:0], trimC2[4:0] to the start value. In the example of FIG. 20, the start value of the current adjustment data trimI[4:0] is 0, and the start values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] are 0. By setting the current adjustment data trimI[4:0] and the capacitance adjustment data trimC1[4:0], trimC2[4:0] to the start value, the negative resistance value |nR| of the oscillation circuit 10 becomes the second value |nR2|.

[0153] Next, when a predetermined time has elapsed in step S402, in step S403, the logic circuit 42 determines whether the value of the current adjustment data trimI[4:0] matches the end value. In the example of FIG. 20, the end value of the current adjustment data trimI[4:0] is 31.

[0154] If the value of the current adjustment data trimI[4:0] does not match the end value in step S403, the logic circuit 42 changes the value of the current adjustment data trimI[4:0] to increase the oscillation stage current Iosc in step S404.

[0155] Steps S402, S403, and S404 are repeated until the value of the current adjustment data trimI[4:0] matches the end value, and when the value of the current adjustment data trimI[4:0] matches the end value, in step S405, the logic circuit 42 determines whether the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] each match the end value. In the example of FIG. 20, the end values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] are both 31.

[0156] If the values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] do not match the end value in step S405, the logic circuit 42 sets the current adjustment data trimI[4:0] to the start value in step S406. Furthermore, in step S407, the logic circuit 42 changes the values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] to decrease the capacitance values ​​C1, C2, respectively.

[0157] Steps S402, S403, S404, S405, S406, and S407 are repeated until the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] match the end values, and when the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] match the end values, in step S408, the logic circuit 42 changes the current adjustment data trimI[4:0] to the set value in the normal operation mode. Furthermore, in step S409, the logic circuit 42 changes the capacitance adjustment data trimC1[4:0] and trimC2[4:0] to the set value in the normal operation mode.

[0158] Then, in step S410, the logic circuit 42 sets the output enable signal en_out to a high level, and the startup step S3 ends.

[0159] Alternatively, the logic circuit 42 may fix one of the capacitance adjustment data trimC1[4:0], trimC2[4:0] and change the other, thereby fixing one of the capacitance values ​​C1, C2 and decreasing the other.

[0160] In the oscillator 1 of the fourth embodiment described above, in the startup mode, the value of the oscillation stage current Iosc is increased and the capacitance values ​​C1 and C2 of the variable capacitance circuits 14 and 15 are decreased, so that the negative resistance value |nR| of the oscillation circuit 10 gradually increases in a stepwise manner from the second value |nR2|. Therefore, the value R of the loaded series resistance when the vibrator 3 resonates with the main vibration Lm The value of the series resistance under load R when the vibrator 3 resonates with the secondary vibration is greater than Ls The time during which the value becomes smaller than 10 ...

[0161] In particular, in the oscillator 1 of the fourth embodiment, the logic circuit 42 repeatedly controls to increase the value of the oscillation stage current Iosc from the third value to the fourth value while changing the capacitance values ​​C1, C2 of the variable capacitance circuits 14, 15. Therefore, according to the oscillator 1 of the fourth embodiment, it is possible to reduce the risk that the oscillation circuit 10 does not oscillate because the capacitance values ​​C1, C2 of the variable capacitance circuits 14, 15 are too large or the value of the oscillation stage current Iosc is too small. Furthermore, after the logic circuit 42 increases the value of the oscillation stage current Iosc from the third value to the fourth value, it changes the value of the oscillation stage current Iosc to the third value before decreasing the capacitance values ​​C1, C2, thereby reducing the risk that the negative resistance value |nR| increases rapidly when the capacitance values ​​C1, C2 are decreased, causing the vibrator 3 to resonate in the secondary vibration.

[0162] Furthermore, according to the oscillator 1 of the fourth embodiment, the variable current source 12 for setting the oscillation stage current Iosc to a desired value corresponding to the resonant frequency of the resonator 3 in the normal operation mode and the variable capacitance circuits 14, 15 for setting the oscillation frequency of the oscillation circuit 10 to a target frequency can also be used to increase the negative resistance value |nR| of the oscillation circuit 10 in the startup mode.

[0163] 5. Fifth embodiment Hereinafter, for the oscillator 1 of the fifth embodiment, the same symbols will be used for configurations similar to any of the above embodiments, and descriptions of similarities with any of the above embodiments will be omitted or simplified, and mainly the differences from any of the above embodiments will be described.

[0164] The structure of the oscillator 1 of the fifth embodiment is similar to that shown in FIGS. 1 to 3, and therefore illustration and description thereof will be omitted.

[0165] Fig. 22 is a functional block diagram of an oscillator 1 of the fifth embodiment. As shown in Fig. 22, the oscillator 1 of the fifth embodiment includes an oscillation circuit 2 and a resonator 3, similar to the above-mentioned embodiments. The oscillation circuit 2 includes an oscillation circuit 10, a power supply circuit 20, a power-on reset circuit 30, a control circuit 40, a reference voltage generating circuit 50, an output circuit 60, and a memory circuit 70, similar to the above-mentioned embodiments, but further includes an oscillation detection circuit 80, unlike the above-mentioned embodiments. Note that the oscillation circuit 2 may be configured such that some of these elements are omitted or modified, or other elements are added.

[0166] In the startup mode, the oscillation detection circuit 80 detects that the signal output from the vibrator 3 has a predetermined amplitude or more, and outputs a detection signal DET.

[0167] The logic circuit 42 of the control circuit 40 sets the negative resistance value |nR| of the oscillation circuit 10 to a first value |nR1| based on the detection signal DET.

[0168] Fig. 23 is a diagram showing a configuration example of the oscillation detection circuit 80. In the example of Fig. 23, the oscillation detection circuit 80 includes a current source 300, three capacitance elements 301, 314, and 315, three variable resistors 302, 303, and 304, six N-channel MOS transistors 305, 306, 307, 308, 309, and 313, a comparator 310, and two CMOS inverters 311 and 312.

[0169] The current source 300 has one end supplied with a voltage Vreg and the other end connected to the drain of an N-channel MOS transistor 305 .

[0170] The gate of the N-channel MOS transistor 305 is connected to the gate of the N-channel MOS transistor 307 and the gate of the N-channel MOS transistor 309, and the sources of the N-channel MOS transistors 305, 307, and 309 are grounded.

[0171] The drain of the N-channel MOS transistor 307 is connected to the source of the N-channel MOS transistor 306 , and the drain of the N-channel MOS transistor 309 is connected to the source of the N-channel MOS transistor 308 .

[0172] The variable resistor 304 has one end supplied with a voltage Vreg and the other end connected to one end of the variable resistor 303. The other end of the variable resistor 303 is connected to one end of the variable resistor 302, and the other end of the variable resistor 302 is grounded.

[0173] One end of the capacitance element 301 is connected to the XI terminal, and the other end is connected to the other end of the variable resistor 303, one end of the variable resistor 302, and the gate of the N-channel MOS transistor 306. A signal output from the vibrator 3 is input to the XI terminal.

[0174] The gate of the N-channel MOS transistor 308 is connected to the other end of the variable resistor 304 and one end of the variable resistor 303, and a voltage Vreg is supplied to each drain of the N-channel MOS transistors 306 and 308.

[0175] The comparator 310 has an inverting input terminal connected to the source of the N-channel MOS transistor 308 and one end of the capacitive element 315, and a non-inverting input terminal connected to the source of the N-channel MOS transistor 306 and one end of the capacitive element 314. The other end of the capacitive element 314 and the other end of the capacitive element 315 are grounded.

[0176] The output terminal of the comparator 310 is connected to the input terminal of a CMOS inverter 311 and the gate of an N-channel MOS transistor 313, and the output terminal of the CMOS inverter 311 is connected to the input terminal of a CMOS inverter 312. The source and drain of the N-channel MOS transistor 313 are connected to one end and the other end of the variable resistor 303, respectively.

[0177] In the oscillation detection circuit 80 thus configured, a voltage V2=Vreg×(R1+R2) / (R1+R2+R3) obtained by dividing the voltage Vreg by the variable resistors 302, 303, and 304 is input to the gate of the N-channel MOS transistor 306. R1, R2, and R3 are the resistance values ​​of the variable resistors 302, 303, and 304, respectively. A voltage V1 is input to the gate of the N-channel MOS transistor 306, which is the sum of the voltage Vreg×R1 / (R1+R2+R3) obtained by dividing the voltage Vreg by the variable resistors 302, 303, and 304 and the AC component of the signal input from the XI terminal, from which the DC component has been removed by the capacitance element 301. Therefore, a voltage V2-V gs2 is input, and the non-inverting input terminal of the comparator 310 has a voltage V1-V gs1 is entered. V gs1 is the gate-source voltage of the N-channel MOS transistor 306, and V gs2 is the gate-source voltage of the N-channel MOS transistor 308.

[0178] Comparator 310 calculates the voltage V1-V gs1 is the voltage V2-Vgs2 When the voltage is lower than V1-V gs1 is the voltage V2-V gs2 , the comparator 310 outputs a high-level signal when the voltage V1-V is higher than the threshold voltage V2. The output signal of the comparator 310 has its logic level inverted by a CMOS inverter 311, and is further inverted by a CMOS inverter 312. The output signal of the CMOS inverter 312 is output to the logic circuit 42 as the detection signal DET, so that the logic level of the detection signal DET is the same as that of the output signal of the comparator 310. Therefore, the detection signal DET is gs1 is the voltage V2-V gs2 When the voltage is lower than V1-V gs1 is the voltage V2-V gs2 When the voltage V1-V2 is higher than the threshold voltage V1, the amplitude of the signal output from the oscillator 3 and input from the XI terminal is zero at the start of the startup mode. gs1 is the voltage V2-V gs2 As the amplitude of the signal input from the XI terminal increases, the capacitance elements 314 and 315 suppress instantaneous voltage fluctuations while the voltage V1-V gs1 The DC level of the voltage V1-V gs1 is the voltage V2-V gs2 When the voltage V1 becomes higher than the voltage V2, the output signal of the comparator 310 changes to a high level, and the detection signal DET also changes to a high level. When the detection signal DET changes from a low level to a high level, the logic circuit 42 sets the negative resistance value |nR| of the oscillation circuit 10 to a first value |nR1|. When the output signal of the comparator 310 becomes a high level, the drain-source of the N-channel MOS transistor 313 becomes conductive, the difference between the voltage V1 and the voltage V2 disappears, the output signal of the comparator 310 maintains a high level, and the detection signal DET also maintains a high level.

[0179] According to this oscillation detection circuit 80, the voltages V1 and V2 are determined by the ratio, not the absolute values ​​of the variable resistors 302, 303, and 304, but the absolute values ​​of the resistance values ​​R1, R2, and R3. Therefore, the error in the voltages V1 and V2 caused by the manufacturing errors of the variable resistors 302, 303, and 304 is small, and the amplitude of the signal output from the vibrator 3 can be detected with high accuracy.

[0180] The other configuration of the oscillator 1 of the fifth embodiment is similar to that of the above-described embodiments, and therefore illustration and description thereof will be omitted.

[0181] Fig. 24 is a waveform diagram showing another example of a sequence in which the oscillator circuit 2 transitions to a normal operation mode after power is applied to the oscillator circuit 2 in the fifth embodiment. In the example of Fig. 24, when power is applied to the oscillator 1, a reset period T1 starts, the power supply voltage Vdd rises from 0V to a predetermined voltage value, the power-on reset signal POR changes from a low level to a high level, and the logic circuit 42 is initialized. Thereafter, the power-on reset signal POR changes from a high level to a low level, ending the reset period T1 and starting the memory load period T2.

[0182] In the memory load period T2, various pieces of information stored in the nonvolatile memory 71 are transferred to the register 72. After this transfer is completed, the logic circuit 42 changes the oscillation enable signal en_osc from low level to high level, thereby ending the memory load period T2 and starting the startup period T3.

[0183] In the start-up period T3, the logic circuit 42 first sets and holds the capacitance adjustment data trimC1[4:0] and trimC2[4:0] to their respective start values, and increases the current adjustment data trimI[4:0] stepwise from the start value to the end value by an arbitrary value, and accordingly, the value of the oscillation stage current Iosc increases stepwise. The start values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] and the start and end values ​​of the current adjustment data trimI[4:0] may be set to arbitrary values ​​by being written in advance to the non-volatile memory 71, for example. In the example of FIG. 24, the logic circuit 42 sets and holds the capacitance adjustment data trimC1[4:0] and trimC2[4:0] to their respective start values ​​of 0, and increases the current adjustment data trimI[4:0] stepwise by 1 from the start value of 0 to the end value of 31. As a result, when the capacitances C1 and C2 are each 31C0, the oscillation stage current Iosc becomes the third value I b The fourth value, I b The negative resistance value |nR| of the oscillation circuit 10 increases in a stepwise manner from the second value |nR2| to +31I0.

[0184] Next, the logic circuit 42 changes the current adjustment data trimI[4:0] to the starting value of 0, and then increases the values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] by an arbitrary value. In the example of Fig. 24, the values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] are each set to 1, which is a value obtained by increasing the value by 1 from 0, and are maintained, and the current adjustment data trimI[4:0] is again increased stepwise by 1 from the starting value of 0 to the ending value of 31. As a result, with the capacitance values ​​C1, C2 each reduced to 30C0, the oscillation stage current Iosc reaches a third value I b The fourth value, I b The negative resistance value |nR| of the oscillation circuit 10 increases stepwise to +31I0.

[0185] Next, the logic circuit 42 changes the current adjustment data trimI[4:0] to the starting value of 0, and then increases the values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] by an arbitrary value. In the example of Fig. 24, the values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] are each set to and held at 2, which is a value obtained by increasing the value by 1 from 1, and the current adjustment data trimI[4:0] is again increased stepwise by 1 from the starting value of 0 to the ending value of 31. As a result, with the capacitance values ​​C1, C2 each reduced to 29C0, the oscillation stage current Iosc reaches a third value I b The fourth value, I b +31I0, the negative resistance value |nR| of the oscillation circuit 10 increases in a stepwise manner. Lm Greater than and R Ls When the amplitude of the current I_xtal output from the vibrator 3 exceeds a predetermined threshold, a pulse is generated in the oscillation signal CK. When the amplitude of the current I_xtal output from the vibrator 3 reaches a predetermined value, for example, when the value of the current adjustment data trimI[4:0] is 9 and the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] are both 2, the detection signal DET changes from low level to high level.

[0186] Next, in response to the detection signal DET going to high level, the logic circuit 42 changes the value of the current adjustment data trimI[4:0] stepwise by any value up to the set value in the normal operation mode. In the example of FIG. 24, since the value of the current adjustment data trimI[4:0] is 9 when the detection signal DET goes to high level, the logic circuit 42 increases the value of the current adjustment data trimI[4:0] from 9 stepwise by 1. Then, when the value of the current adjustment data trimI[4:0] reaches 24, which is the value transferred to the register 72 in the memory load period T2, the logic circuit 42 holds the value of the current adjustment data trimI[4:0] at 24, and increases the value of the oscillation stage current Iosc to I b+24I0. Furthermore, the logic circuit 42 changes the values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] stepwise by an arbitrary value up to the set value in the normal operation mode. In the example of FIG. 24, the values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] are each 2 when the detection signal DET becomes high level, so the logic circuit 42 increases the values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] stepwise by 1 from 2. Then, when the values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] reach 26, which is the value transferred to the register 72 during the memory load period T2, the logic circuit 42 holds the values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] at 26, and the capacitance values ​​C1, C2 become 5C0. The value of the oscillation stage current Iosc is I b +24I0, and the capacitance values ​​C1 and C2 each become 5C0, so that the negative resistance value |nR| becomes the first value |nR1|. Ls However, at that point in time, the oscillation of the oscillation circuit 10 due to the resonance with the main vibration of the vibrator 3 has grown sufficiently, so that resonance with the secondary vibration of the vibrator 3 does not occur. Then, the logic circuit 42 changes the output enable signal en_out from low level to high level, thereby ending the startup period T3 and starting the normal operation period T4.

[0187] During the normal operation period T4, since the output enable signal en_out is at a high level, the oscillation signal CK is buffered and a pulse is generated in the oscillation signal CKO.

[0188] In addition, during the startup period T3, both capacitance values ​​C1 and C2 are decreased by increasing both capacitance adjustment data trimC1[4:0] and trimC2[4:0], but it is also possible to fix one of the capacitance values ​​C1 and C2 and decrease the other by fixing one of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] and increasing the other.

[0189] 24, the operation mode in the startup period T3 is the startup mode, and the operation mode in the normal operation period T4 is the normal operation mode. Alternatively, the operation mode in the reset period T1, the memory load period T2, and the startup period T3 is the startup mode.

[0190] The flowchart showing the procedure of the control method of the oscillation circuit 2 in the fifth embodiment is the same as that in Fig. 12, and therefore the illustration and description thereof will be omitted. However, in the fifth embodiment, the procedure of the start-up step S3 in Fig. 12 is different from each of the above embodiments.

[0191] FIG. 25 is a flow chart showing an example of the procedure of the startup process S3 of FIG. 12 in the fifth embodiment. The procedure shown in FIG. 25 corresponds to the operation of the startup period T3 of FIG. 24. As shown in FIG. 25, first, in step S501, the logic circuit 42 sets the current adjustment data trimI[4:0] and the capacitance adjustment data trimC1[4:0], trimC2[4:0] to the start value. In the example of FIG. 24, the start value of the current adjustment data trimI[4:0] is 0, and the start values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] are 0. By setting the current adjustment data trimI[4:0] and the capacitance adjustment data trimC1[4:0], trimC2[4:0] to the start value, the negative resistance value |nR| of the oscillation circuit 10 becomes the second value |nR2|.

[0192] Next, when a predetermined time has elapsed in step S502, if the detection signal DET is at a low level in step S503, the logic circuit 42 determines in step S504 whether the value of the current adjustment data trimI[4:0] matches the end value. In the example of FIG. 24, the end value of the current adjustment data trimI[4:0] is 31.

[0193] If the value of the current adjustment data trimI[4:0] does not match the end value in step S504, the logic circuit 42 changes the value of the current adjustment data trimI[4:0] to increase the oscillation stage current Iosc in step S505.

[0194] As long as the detection signal DET is at a low level in step S503, steps S502, S504, and S505 are repeated until the value of the current adjustment data trimI[4:0] matches the end value, and when the value of the current adjustment data trimI[4:0] matches the end value, in step S506, the logic circuit 42 determines whether the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] each match the end value. In the example of FIG. 24, the end values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] are both 31.

[0195] If the values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] do not match the end value in step S506, the logic circuit 42 sets the current adjustment data trimI[4:0] to the start value in step S507. Furthermore, in step S508, the logic circuit 42 changes the values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] to decrease the capacitance values ​​C1, C2, respectively.

[0196] As long as the detection signal DET is at a low level in step S503, steps S502, S504, S505, S506, S507, and S508 are repeated until the values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] match the end value.

[0197] If the detection signal DET is at a high level in step S503, or if the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] match the end value in step S506, the logic circuit 42 changes the current adjustment data trimI[4:0] to the set value in the normal operation mode in step S509. Furthermore, in step S510, the logic circuit 42 changes the capacitance adjustment data trimC1[4:0] and trimC2[4:0] to the set value in the normal operation mode.

[0198] Then, in step S511, the logic circuit 42 sets the output enable signal en_out to a high level, and the startup step S3 ends.

[0199] Alternatively, the logic circuit 42 may fix one of the capacitance adjustment data trimC1[4:0], trimC2[4:0] and change the other, thereby fixing one of the capacitance values ​​C1, C2 and decreasing the other.

[0200] 24 and 25 correspond to a sequence and a flowchart in the case where an oscillation detection circuit 80 is added to the oscillator 1 of the fourth embodiment. Although illustration of the sequence and the flowchart is omitted, the oscillation detection circuit 80 may be added to the oscillator 1 of the first to third embodiments.

[0201] In the oscillator 1 of the fifth embodiment described above, when the oscillation detection circuit 80 detects that the signal output from the vibrator 3 has reached a predetermined amplitude or greater in the startup mode, the negative resistance value |nR| is set to the first value |nR1| and the mode transitions to the normal operation mode, thereby shortening the startup time.

[0202] 6. Sixth embodiment In the following, for the oscillator 1 of the sixth embodiment, the same symbols are used for configurations that are similar to any of the above embodiments, and descriptions that are similar to any of the above embodiments are omitted or simplified, and the description will mainly focus on the differences from any of the above embodiments.

[0203] The configuration of the oscillator 1 in the sixth embodiment is the same as that in Fig. 1 to Fig. 4, and therefore illustration and description thereof will be omitted. Also, the configuration of the oscillation circuit 10 in the fourth embodiment is the same as that in Fig. 5, and therefore illustration and description thereof will be omitted.

[0204] In each of the above embodiments, in the startup mode, the negative resistance value |nR| of the oscillation circuit 10 is controlled based on weighted multi-bit control data output from the control circuit 40.

[0205] For example, in the first or fourth embodiment, in the startup mode, the negative resistance value |nR| is controlled by the current adjustment data trimI[4:0], which is control data in which the larger the bit, the greater the weight. For example, when the logic level of trimI[0] is inverted, the oscillation stage current Iosc increases or decreases by I0, whereas when the logic level of trimI[4] is inverted, the oscillation stage current Iosc increases or decreases by 16×I0. Therefore, for example, when the current adjustment data trimI[4:0] changes from 15 to 16, if trimI[4] changes from high level to low level before trimI[0], trimI[1], trimI[2], and trimI[3] each change from high level to low level, the oscillation stage current Iosc instantaneously increases by 16×I0. As a result, the negative resistance value |nR| is the value R of the loaded series resistance when the vibrator 3 resonates with the secondary vibration. Ls If it becomes larger than this, there is an increased risk that the oscillator 3 will resonate with the secondary vibration and cause abnormal oscillation.

[0206] Also, in the second or fourth embodiment, for example, in the startup mode, the negative resistance value |nR| is controlled by the capacitance adjustment data trimC1[4:0], trimC2[4:0], which are control data in which the larger the bit, the greater the weight. For example, when the logic levels of trimC1[0], trimC2[0] are inverted, the capacitance values ​​C1, C2 each increase or decrease by C0, whereas when the logic levels of trimC1[4], trimC2[4] are inverted, the capacitance values ​​C1, C2 each increase or decrease by 16×C0. Therefore, for example, when the capacitance adjustment data trimC1[4:0] and trimC2[4:0] change from 15 to 16, if trimC1[4] changes from high to low before trimC1[0], trimC1[1], trimC1[2], and trimC1[3] each change from high to low, the capacitance value C1 will instantaneously increase by 16×C0. As a result, the negative resistance value |nR| Ls If it is larger than , there is a higher risk that the oscillator 3 will resonate with the secondary vibration and cause abnormal oscillation. The same can be said for the capacitance adjustment data trimC2[4:0].

[0207] Therefore, in the sixth embodiment, in order to reduce the risk of abnormal oscillation, the control circuit 40 is configured so that the control data for controlling the negative resistance value |nR| of the oscillation circuit 10 in the startup mode changes logic level more quickly for bits with lower weighting.

[0208] Fig. 26 is a diagram showing a configuration example of the control circuit 40 in the sixth embodiment. Fig. 26 shows a configuration example of the control circuit 40 in the case where the control data for controlling the negative resistance value |nR| of the oscillation circuit 10 in the startup mode is the current adjustment data trimI[4:0]. In the example of Fig. 26, the control circuit 40 includes a logic circuit 42 and ten delay circuits 411, 421, 422, 431, 432, 433, 441, 442, 443, and 444. As in each of the above embodiments, the control circuit 40 also includes a voltage control circuit 41, but this is omitted in Fig. 26.

[0209] The logic circuit 42 outputs the current adjustment data trimIX[4:0]. trimIX[0] is output as trimI[0]. trimIX[1] is output as trimI[1] after propagating through the delay circuit 411. trimIX[2] is output as trimI[2] after propagating through the delay circuits 421 and 422. trimIX[3] is output as trimI[3] after propagating through the delay circuits 431, 432, and 433. trimIX[4] is output as trimI[4] after propagating through the delay circuits 441, 442, 443, and 444.

[0210] The delay circuits 411, 421, 422, 431, 432, 433, 441, 442, 443, and 444 are, for example, circuits in which four CMOS inverters 401, 402, 403, and 404 are connected in series, as shown in Fig. 27. Note that the number of CMOS inverters is not limited to four, and may be any even number.

[0211] 28 is a diagram showing an example of the waveform of each bit of the current adjustment data trimIX[4:0], trimI[4:0]. In the example of FIG. 28, the waveform of each bit when the current adjustment data trimIX[4:0] changes from 15 to 16 is shown.

[0212] 28, the logic levels of the bits of the current adjustment data trimIX[4:0] change simultaneously at time t1. Specifically, trimIX[0], trimIX[1], trimIX[2], and trimIX[3] change from high to low, and trimIX[4] changes from low to high.

[0213] Since trimIX[0] is output as trimI[0] without propagating through the delay circuit, trimI[0] changes from high level to low level at time t1. In addition, the low level of trimIX[1] propagates through the delay circuit 411 after time t1, and trimI[1] changes from high level to low level at time t2. In addition, the low level of trimIX[2] propagates through the delay circuits 421 and 422 after time t1, and trimI[2] changes from high level to low level at time t3. In addition, the low level of trimIX[3] propagates through the delay circuits 431, 432, and 433 after time t1, and trimI[3] changes from high level to low level at time t4. Furthermore, after time t1, the high level of trimIX[4] propagates through the delay circuits 441, 442, 443, and 444, and at time t5, trimI[4] then changes from low to high.

[0214] In this way, the logic level of the current adjustment data trimI[4:0] output to the oscillation circuit 10 changes in the order of trimI[0], trimI[1], trimI[2], trimI[3], and trimI[4], i.e., the lower the weight of the bit, the faster the bit changes.

[0215] Although not shown, the control circuit 40 when the control data for controlling the negative resistance value |nR| of the oscillation circuit 10 in the startup mode is the capacitance adjustment data trimC1[4:0], trimC2[4:0] is also configured in the same manner as in FIG. 26.

[0216] The other configuration of the oscillator 1 of the sixth embodiment is similar to that of the above-described embodiments, and therefore illustration and description thereof will be omitted.

[0217] In the oscillator 1 of the sixth embodiment described above, when increasing the negative resistance value |nR| of the oscillation circuit 10 in the startup mode, the logic level of the current adjustment data trimI[4:0] and the capacitance adjustment data trimC1[4:0], trimC2[4:0] changes faster as the weighting of the bit decreases. Therefore, according to the oscillator 1 of the sixth embodiment, when increasing the negative resistance value |nR| of the oscillation circuit 10, the negative resistance value |nR| does not increase suddenly transiently, so that the risk of abnormal oscillation due to the growth of oscillation based on the resonance in the secondary vibration of the vibrator 3 is reduced.

[0218] 7. Seventh embodiment In the following, for the oscillator 1 of the seventh embodiment, the same symbols are used for configurations that are similar to any of the above embodiments, and descriptions that are similar to any of the above embodiments are omitted or simplified, and the description will mainly focus on the differences from any of the above embodiments.

[0219] The configuration of the oscillator 1 of the seventh embodiment is similar to that shown in FIGS. 1 to 4, and therefore illustration and description thereof will be omitted.

[0220] In each of the above-described embodiments, in the startup mode, the negative resistance value |nR| of the oscillation circuit 10 is controlled based on weighted multi-bit control data output from the control circuit 40. Therefore, as described above, except for the sixth embodiment, there is an increased risk that the vibrator 3 resonates with the secondary vibration and abnormal oscillation occurs.

[0221] Therefore, in the seventh embodiment, in order to reduce the risk of abnormal oscillation, in the startup mode, the negative resistance value |nR| of the oscillation circuit 10 is controlled based on unweighted multi-bit control data output from the control circuit 40. The unweighted multi-bit control data may be data represented by a thermometer code.

[0222] For example, in the startup mode, the oscillation stage current Iosc output from the variable current source 12 of the oscillation circuit 10 may be controlled based on the unweighted 32-bit current adjustment data trimI[31:0] to control the negative resistance value |nR|. Also, for example, in the startup mode, the capacitance values ​​C1 and C2 of the variable capacitance circuits 14 and 15 of the oscillation circuit 10 may be controlled based on the unweighted 32-bit capacitance adjustment data trimC1[31:0] and trimC2[31:0] to control the negative resistance value |nR|.

[0223] Fig. 29 is a diagram showing an example of the configuration of the variable current source 12 controlled by unweighted 32-bit current adjustment data trimI[31:0]. In the example of Fig. 29, the variable current source 12 includes a current source 135, 32 current sources 136-0 to 136-31, 32 switch elements 137-0 to 137-31, and two P-channel MOS transistors 133 and 134.

[0224] 5. The gate and drain of the P-channel MOS transistor 133 are connected, and a voltage Vreg is supplied to the source. The gate of the P-channel MOS transistor 134 is connected to the gate of the P-channel MOS transistor 133, a voltage Vreg is supplied to the source, and a drain is connected to the collector of the amplifying element 11 in FIG.

[0225] The current source 135 has one end connected to the drain of the P-channel MOS transistor 133 and the other end grounded, and outputs a constant bias current I bflows. For each integer i between 0 and 31, one end of the current source 136-i is connected to the drain of the P-channel MOS transistor 133 via the switch element 137-i, and the other end is grounded, and a constant current I0 flows when the switch element 137-i is in a conductive state. For example, the current sources 135, 136-0 to 136-31 may be configured using depletion-type N-channel MOS transistors or may be configured using a current mirror circuit.

[0226] For each integer i between 0 and 31, the switch element 137-i receives data trimI[i] of bit i of the current adjustment data trimI[31:0] at its control terminal, and becomes conductive when data trimI[i] is at a high level and becomes non-conductive when data trimI[i] is at a low level. For example, the switch elements 137-0 to 137-31 may be N-channel MOS transistors or transmission gates.

[0227] 30 is a diagram showing the relationship between the value of each bit of the current adjustment data trimI[31:0] and the value of the oscillation stage current Iosc output from the variable current source 12 shown in FIG. 29. A value of 0 for each bit corresponds to a low level, and a value of 1 for each bit corresponds to a high level. For example, when bit 0 of the current adjustment data trimI[31:0] is 1 and bits 1 to 31 are 0, only the switch element 137-0 is conductive and the oscillation stage current Iosc=I b +I0. For example, when bits 0 and 1 of the current adjustment data trimI[31:0] are 1 and bits 2 to 31 are 0, only the two switch elements 137-0 and 137-1 are conductive, and the oscillation stage current Iosc=I b In general, if the number of bits whose value is 1 among the 32 bits of the current adjustment data trimI[31:0] is N and the number of bits whose value is 0 is 32-N, then the oscillation stage current Iosc=I b+N×I0. In the code shown in Fig. 30, the values ​​of bits 0 to 31 are all 0, or the values ​​of bits 0 to 31 are all 1, or, for any integer j between 0 and 30, the values ​​of bits 0 to j are all 1 and the values ​​of bits j+1 to 31 are all 0. This type of code is called a thermometer code.

[0228] Although not shown, in the startup mode, when the capacitance values ​​C1, C2 of the variable capacitance circuits 14, 15 of the oscillation circuit 10 are controlled based on the unweighted 32-bit capacitance adjustment data trimC1[31:0], trimC2[31:0], the codes of the variable capacitance circuits 14, 15 and the capacitance adjustment data trimC1[31:0], trimC2[31:0] are also configured in the same manner as in Figures 29 and 30.

[0229] The other configuration of the oscillator 1 of the seventh embodiment is similar to that of the above-described embodiments, and therefore illustration and description thereof will be omitted.

[0230] In the oscillator 1 of the seventh embodiment described above, when the negative resistance value |nR| of the oscillation circuit 10 is increased in the startup mode, the current adjustment data trimI[31:0] and the capacitance adjustment data trimC1[31:0], trimC2[31:0] are unweighted data, for example, data represented by a thermometer code. Therefore, according to the oscillator 1 of the seventh embodiment, when the negative resistance value |nR| of the oscillation circuit 10 is increased, the negative resistance value |nR| does not increase suddenly transiently, so that the risk of abnormal oscillation due to the growth of oscillation based on resonance in the secondary vibration of the vibrator 3 is reduced.

[0231] 8. Variations In the oscillator 1 of the first or fourth embodiment described above, the logic circuit 42 controls the negative resistance value |nR| to increase in steps in the startup mode by increasing the value of the oscillation stage current Iosc in steps, but it may also control the negative resistance value |nR| to increase continuously by increasing the value of the oscillation stage current Iosc continuously.

[0232] Furthermore, in the oscillator 1 of the second or fourth embodiment described above, the logic circuit 42 controls the negative resistance value |nR| to increase in a step-like manner in the startup mode by increasing at least one of the capacitance values ​​C1, C2 of the variable capacitance circuits 14, 15 in a step-like manner, but it may also control the negative resistance value |nR| to increase continuously by continuously increasing at least one of the capacitance values ​​C1, C2 of the variable capacitance circuits 14, 15.

[0233] Further, the oscillator 1 in each of the above embodiments is an oscillator having a frequency control function such as a VCXO (Voltage Controlled Crystal Oscillator), but may be an oscillator having a temperature compensation function such as a TCXO (Temperature Compensated Crystal Oscillator), an oscillator having a temperature compensation function and a frequency control function such as a VC-TCXO (Voltage Controlled Temperature Compensated Crystal Oscillator), a simple oscillator without a temperature compensation function and a frequency control function such as a SPXO (Simple Packaged Crystal Oscillator), or an oscillator having a temperature control function such as an OCXO (Oven Controlled Crystal Oscillator). VCXO is an abbreviation for Voltage Controlled Crystal Oscillator. TCXO is an abbreviation for Temperature Compensated Crystal Oscillator. VC-TCXO is an abbreviation for Voltage Controlled Temperature Compensated Crystal Oscillator. SPXO is an abbreviation for Simple Packaged Crystal Oscillator. OCXO is an abbreviation for Oven Controlled Crystal Oscillator. When the oscillator 1 is an oscillator having a temperature compensation function or an oscillator having a temperature compensation function and a frequency control function, in the startup mode, the temperature compensation circuit may increase the negative resistance value by decreasing the capacitance value of the variable capacitance circuit.

[0234] The present invention is not limited to the present embodiment, and various modifications are possible within the scope of the present invention.

[0235] The above-described embodiment and modifications are merely examples, and the present invention is not limited to these. For example, the embodiments and modifications can be appropriately combined.

[0236] The present invention includes configurations that are substantially the same as the configurations described in the embodiments, for example, configurations with the same functions, methods, and results, or configurations with the same purpose and effects. The present invention also includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. The present invention also includes configurations that achieve the same effects as the configurations described in the embodiments, or configurations that can achieve the same purpose. The present invention also includes configurations in which publicly known technology is added to the configurations described in the embodiments.

[0237] The following can be derived from the above-described embodiment and modifications.

[0238] One aspect of the oscillator circuit is an oscillation circuit connected to the oscillator; A control circuit for controlling the oscillation circuit, a normal operation mode in which the oscillation circuit oscillates in a state in which the negative resistance value is a first value; a startup mode from a state in which the oscillation circuit stops oscillating to a state in which the normal operation mode is transitioned to; The control circuit includes: In the start-up mode, the negative resistance value is controlled to increase from a second value smaller than the first value.

[0239] In this oscillation circuit, in a startup mode from a state where the oscillation circuit stops oscillating to a normal operation mode where the oscillation circuit oscillates with the negative resistance value of the oscillation circuit at a first value, the negative resistance value of the oscillation circuit increases from a second value smaller than the first value. Lmis the value of the series resistance under load when the vibrator resonates with the secondary vibration, R Ls is smaller than the second value, the negative resistance of the oscillation circuit increases from the second value to R Lm Greater than and R Ls Therefore, in the startup mode, the oscillation based on the resonance of the main vibration of the vibrator grows before the oscillation based on the resonance of the secondary vibration of the vibrator. Therefore, with this oscillation circuit, it is possible to reduce the risk of abnormal oscillation even if there is variation in the characteristics of the vibrators connected.

[0240] In one embodiment of the oscillator circuit, The control circuit includes: In the start-up mode, the negative resistance value may be controlled to increase in a stepwise manner.

[0241] In this oscillator circuit, in the start-up mode, the negative resistance value of the oscillation circuit increases in a stepwise manner from the second value, so that R Lm Greater than and R Ls The time during which the value of the oscillation frequency becomes smaller than the value of the oscillation frequency becomes longer. Therefore, the oscillation based on the resonance of the main vibration of the vibrator grows before the oscillation based on the resonance of the secondary vibration of the vibrator. Therefore, with this oscillator circuit, the risk of abnormal oscillation can be reduced even if there is variation in the characteristics of the vibrators connected to it.

[0242] In one embodiment of the oscillator circuit, The control circuit includes: In the start-up mode, the negative resistance value may be controlled to increase continuously.

[0243] In this oscillator circuit, in the start-up mode, the negative resistance value of the oscillation circuit increases continuously from the second value, so that R Lm Greater than and R LsThe time during which the value of the oscillation frequency becomes smaller than the value of the oscillation frequency becomes longer. Therefore, the oscillation based on the resonance of the main vibration of the vibrator grows before the oscillation based on the resonance of the secondary vibration of the vibrator. Therefore, with this oscillator circuit, the risk of abnormal oscillation can be reduced even if there is variation in the characteristics of the vibrators connected to it.

[0244] In one embodiment of the oscillator circuit, The first value may be equal to or greater than a maximum value of the negative resistance value in the startup mode.

[0245] According to this oscillation circuit, in the start-up mode, the negative resistance value of the oscillation circuit does not become larger than the first value, so that the negative resistance value of the oscillation circuit is equal to the value R of the loaded series resistance when the vibrator resonates with the secondary vibration. Ls The time during which the value is greater than the maximum vibration frequency is short, and resonance in the secondary vibration of the oscillator is less likely to occur.

[0246] In one embodiment of the oscillator circuit, the oscillation circuit includes an amplifying element and a variable current source that supplies a current to the amplifying element; The control circuit may increase the negative resistance value by increasing the value of the current in the startup mode.

[0247] According to this oscillation circuit, for example, a variable current source for adjusting the current supplied to the amplifying element in the normal operation mode to a desired value corresponding to the resonant frequency of the vibrator can also be used to increase the negative resistance value of the oscillation circuit in the startup mode.

[0248] In one embodiment of the oscillator circuit, the oscillation circuit includes a variable capacitance circuit connected to a node connected to the oscillator, In the startup mode, the control circuit may increase the negative resistance value by decreasing a capacitance value of the variable capacitance circuit.

[0249] According to this oscillator circuit, for example, the variable capacitance circuit for adjusting the oscillation frequency of the oscillation circuit to a target frequency in the normal operation mode can also be used to increase the negative resistance value of the oscillation circuit in the startup mode.

[0250] In one embodiment of the oscillator circuit, the oscillation circuit includes an amplifying element, a variable current source that supplies a current to the amplifying element, and a variable capacitance circuit that is connected to a node that is connected to the vibrator; In the startup mode, the control circuit may increase the negative resistance value by increasing the current value and decreasing the capacitance value of the variable capacitance circuit.

[0251] According to this oscillation circuit, for example, a variable current source for adjusting the current supplied to the amplifying element to a desired value corresponding to the resonant frequency of the vibrator in the normal operation mode and a variable capacitance circuit for adjusting the oscillation frequency of the oscillation circuit to a target frequency can be used to increase the negative resistance value of the oscillation circuit in the startup mode. Also, according to this oscillation circuit, since the value of the current supplied to the amplifying element is increased and the capacitance value of the variable capacitance circuit is decreased in the startup mode, it is possible to reduce the risk that the oscillation circuit will not oscillate due to the capacitance value of the variable capacitance circuit being too large or the value of the current supplied to the amplifying element being too small.

[0252] In one embodiment of the oscillator circuit, In the startup mode, the control circuit may repeatedly perform control to increase the value of the current from a third value to a fourth value greater than the third value without changing the capacitance value, and then decrease the capacitance value and change the value of the current to the third value.

[0253] According to this oscillation circuit, in the startup mode, the control circuit repeatedly increases the value of the current supplied to the amplifying element from a third value to an upper limit value while changing the capacitance value of the variable capacitance circuit, thereby reducing the risk that the capacitance value of the variable capacitance circuit is too large or the value of the current supplied to the amplifying element is too small, causing the oscillation circuit to not oscillate. Furthermore, in this oscillation circuit, the control circuit increases the value of the current supplied to the amplifying element from the third value to a fourth value, and then changes the value of the current supplied to the amplifying element to the third value before decreasing the capacitance value of the variable capacitance circuit, thereby reducing the risk that the negative resistance value increases rapidly when the capacitance value of the variable capacitance circuit is decreased, causing the vibrator to resonate in the secondary vibration.

[0254] One aspect of the oscillator circuit is an oscillation detection circuit that detects when the signal output from the vibrator reaches or exceeds a predetermined amplitude in the startup mode and outputs a detection signal; The control circuit may set the negative resistance value to the first value based on the detection signal.

[0255] According to this oscillator circuit, when the oscillation circuit oscillates in the startup mode, the negative resistance value is set to the first value and the mode transitions to the normal operation mode, thereby shortening the startup time.

[0256] In one embodiment of the oscillator circuit, the negative resistance value is controlled based on weighted multi-bit control data; The control data may have a logic level that changes more quickly for a bit with a smaller weight.

[0257] According to this oscillator circuit, when the negative resistance value of the oscillation circuit is increased, there is no sudden, transient increase in the negative resistance value, reducing the risk of abnormal oscillation due to the growth of oscillation based on resonance in the secondary vibration of the vibrator.

[0258] In one embodiment of the oscillator circuit, The negative resistance value may be controlled based on unweighted multi-bit control data.

[0259] According to this oscillator circuit, when the negative resistance value of the oscillation circuit is increased, there is no sudden, transient increase in the negative resistance value, reducing the risk of abnormal oscillation due to the growth of oscillation based on resonance in the secondary vibration of the vibrator.

[0260] In one embodiment of the oscillator circuit, The control data may be data represented by a thermometer code.

[0261] One embodiment of the oscillator is An embodiment of the oscillator circuit; The vibrator.

[0262] In this oscillator, in a startup mode in which the oscillation circuit stops oscillating and transitions to a normal operation mode in which the oscillation circuit oscillates with the negative resistance value of the oscillation circuit at a first value, the negative resistance value of the oscillation circuit increases from a second value smaller than the first value. Lm is the value of the series resistance under load when the vibrator resonates with the secondary vibration, R Ls is smaller than the second value, the negative resistance of the oscillation circuit increases from the second value to R Lm Greater than and R Ls Therefore, in the startup mode, the oscillation based on the resonance of the main vibration of the vibrator grows before the oscillation based on the resonance of the secondary vibration of the vibrator. Therefore, according to this oscillator, the risk of abnormal oscillation can be reduced even if the characteristics of the vibrator vary.

[0263] One aspect of a method for controlling an oscillator circuit includes: A method for controlling an oscillation circuit, comprising: an oscillation circuit connected to a vibrator, the oscillation circuit having a normal operation mode in which the oscillation circuit oscillates with a first negative resistance value; and a startup mode in which the oscillation circuit transitions from a state in which oscillation has stopped to the normal operation mode, the method comprising: In the start-up mode, the negative resistance value is controlled to increase from a second value smaller than the first value.

[0264] In this control method for an oscillation circuit, in a startup mode from a state in which the oscillation circuit stops oscillating to a normal operation mode in which the oscillation circuit oscillates with the negative resistance value of the oscillation circuit at a first value, the negative resistance value of the oscillation circuit increases from a second value smaller than the first value. Lm is the value of the series resistance under load when the vibrator resonates with the secondary vibration, R Ls is smaller than the second value, the negative resistance of the oscillation circuit increases from the second value to R Lm Greater than and R Ls Therefore, in the startup mode, the oscillation based on the resonance of the main vibration of the vibrator grows before the oscillation based on the resonance of the secondary vibration of the vibrator. Therefore, according to this control method of the oscillation circuit, it is possible to reduce the risk of abnormal oscillation even if there is variation in the characteristics of the vibrators connected. [Explanation of symbols]

[0265] 1...oscillator, 2...oscillating circuit, 3...vibrator, 3a...excitation electrode, 3b...excitation electrode, 4...package, 5...lid, 6...external terminal, 7...accommodation chamber, 10...oscillation circuit, 11...amplifying element, 12...variable current source, 13...resistor, 14...variable capacitance circuit, 15...variable capacitance circuit, 16...variable capacitance circuit, 17...variable capacitance circuit, 20...power supply circuit, 30...power-on reset circuit, 40...control circuit, 41...voltage control circuit, 42...logic circuit, 50...reference voltage generating circuit, 60...output circuit, 70...memory circuit, 71...non-volatile memory, 72...register, 80...oscillation detection circuit, 10 0,101,102,103,104,110,111,112,113,114...CMOS inverter, 120,121,122,123,124...current source, 125,126,127,128,129...switching element, 130...current source, 131,132...P-channel MOS transistor, 133,134...P-channel MOS transistor, 135...current source, 136-0 to 136-31...current source, 137-0 to 137-31...switching element, 140,141,142,143,144...capacitive element, 145,146,147,148,149...s switch elements, 150, 151, 152, 153, 154...capacitance elements, 155, 156, 157, 158, 159...switch elements, 160...variable capacitance element, 161-1 to 161-n...variable capacitance elements, 162-1 to 162-n...capacitance elements, 163-1 to 163-n...capacitance elements, 170...variable capacitance element, 171-1 to 171-n...variable capacitance elements, 172-1 to 172-n...capacitance elements, 173-1 to 173-n...capacitance elements, 200...control voltage generation circuit, 210...filter circuit, 211...resistor, 212...capacitance element, 220...switch circuit, 230...filter circuit , 231 ... resistor, 232 ... capacitor, 240 ... switch circuit, 250 ... resistor, 260 ... resistor, 300 ... current source, 301 ... capacitor, 302, 303, 304 ... variable resistor, 305, 306, 307, 308, 309 ... N-channel MOS transistor, 310 ... comparator, 311, 312 ... CMOS inverter, 313 ... N-channel MOS transistor, 314, 315 ... capacitor, 401, 402, 403, 404 ... CMOS inverter, 411, 421, 422, 431, 432, 433, 441, 442, 443, 444 ... delay circuit

Claims

1. an oscillation circuit connected to the oscillator; A control circuit for controlling the oscillation circuit, a normal operation mode in which the oscillation circuit oscillates in a state in which the negative resistance value is a first value; The operation mode from when the power is turned on until the transition to the normal operation mode, or standby a startup mode, which is an operation mode from the startup mode to the normal operation mode; death, The oscillation circuit includes an amplifier element, a variable current source that supplies a current to the amplifier element, and a a variable capacitance circuit connected to a node connected to the actuator, The control circuit includes: In the start-up mode, the value of the current is changed to a third value without changing the capacitance value of the variable capacitance circuit. When the capacitance value is increased from the first value to a fourth value greater than the third value, and then the capacitance value is decreased, By repeatedly performing control to change the value of the current to the third value, and controlling the resistance to increase from a second value less than the first value.

2. The control circuit includes: In the start-up mode, the negative resistance value is controlled to increase stepwise.

2. The oscillator circuit according to claim 1.

3. The control circuit includes: In the start-up mode, the negative resistance value is controlled to increase continuously.

2. The oscillator circuit according to claim 1.

4. the first value is equal to or greater than a maximum value of the negative resistance in the startup mode.

4. The oscillator circuit according to claim 1 .

5. In the start-up mode, the signal output from the vibrator reaches a predetermined amplitude or more. and an oscillation detection circuit for detecting the oscillation and outputting a detection signal, The control circuit sets the negative resistance value to the first value based on the detection signal.

5. An oscillator circuit as claimed in claim 1 .

6. the negative resistance value is controlled based on weighted multi-bit control data; 2. The control data according to claim 1, wherein the logic level of a bit having a smaller weight changes earlier.

6. An oscillator circuit according to claim 5.

7. The negative resistance value is controlled based on unweighted multi-bit control data.

7. An oscillator circuit according to claim 1.

8. 8. The oscillator according to claim 7, wherein the control data is data represented by a thermometer code. circuit.

9. An oscillator circuit according to any one of claims 1 to 8; An oscillator comprising the vibrator.

10. an amplifier element connected to the vibrator; a variable current source for supplying a current to the amplifier element; a variable capacitance circuit connected to a node connected to the actuator, The oscillation circuit has a normal operation mode in which the negative resistance value oscillates at a first value, and a second operation mode in which the negative resistance value oscillates at a first value after the power is turned on. The operation mode from the standby mode to the normal operation mode, or from the standby mode to the normal operation mode. A control method for an oscillation circuit having a start-up mode which is an operation mode until the operation mode is changed to the start-up mode. It is a law, In the start-up mode, the value of the current is changed to a third value without changing the capacitance value of the variable capacitance circuit. When the capacitance value is increased from the first value to a fourth value greater than the third value, and then the capacitance value is decreased, By repeatedly performing control to change the value of the current to the third value, and controlling the oscillation circuit so that the resistance increases from a second value smaller than the first value. method.

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