Patterning of metal oxide resists by electric field induced post-exposure bake.

Abstract

A method of processing a substrate is described. The method includes forming a metal-containing resist layer on a substrate, patterning the metal-containing resist layer, and performing a post-exposure bake on the metal-containing resist layer. The post-exposure bake on the metal-containing resist layer is a field-guided post-exposure bake operation and includes the use of an electric field to guide ions or charged species in the metal-containing resist layer. The field-guided post-exposure bake operation can be combined with a post-development field-guided bake operation.

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate generally to methods and apparatus for processing substrates. More particularly, the present disclosure is directed to methods and apparatus for enhancing profile control of metal oxide resists. [Background technology]

[0002] Integrated circuits have evolved into complex devices that may contain millions of components (e.g., transistors, capacitors, and resistors) on a single chip. Photolithography is a process that can be used to form components on a chip. In general, the process of photolithography includes several basic steps. First, a layer of photoresist is formed on a substrate. Chemically amplified photoresists typically include a resist resin and a photoacid generator. The photoacid generator, when exposed to electromagnetic radiation in a subsequent exposure step, changes the solubility of the photoresist in the development process. The electromagnetic radiation may have any suitable wavelength, such as, for example, a 193 nm ArF laser, extreme ultraviolet light (also known as EUV), or may be an electron beam, ion beam, or other suitable electromagnetic radiation source.

[0003] In the exposure step, a photomask or reticle is used to selectively expose certain areas of the substrate to electromagnetic radiation. Other exposure methods include maskless exposure methods. Exposure to light decomposes the photoacid generator, which generates acid and creates an acid latent image in the resist resin. After exposure, the substrate is heated in a post-exposure bake process. During the post-exposure bake process, the acid generated by the photoacid generator reacts with the resist resin and changes the solubility of the resist during the subsequent development process.

[0004] After the post-exposure bake, the substrate, particularly the photoresist layer, is developed and rinsed to produce a patterned mask. Depending on the type of photoresist used, the areas of the substrate exposed to electromagnetic radiation are either resistant to removal or susceptible to removal. After development and rinsing, the pattern of the mask is transferred to the substrate using a wet or dry etching process.

[0005] The evolution of chip design is continually seeking faster circuits and greater circuit density. The demand for higher circuit density typically utilizes shrinking dimensions of integrated circuit components. As the dimensions of integrated circuit components shrink, more elements can be placed in a given area on a semiconductor integrated circuit. Thus, in lithography processes, ever smaller features are transferred onto the substrate to meet advanced chip design specifications, and lithography transfers them precisely and accurately without damage. To transfer features precisely and accurately onto the substrate, high-resolution lithography utilizes light sources that provide shorter wavelength radiation. Short wavelengths help reduce the minimum size that can be printed on a substrate or wafer. However, short wavelength lithography has problems such as reduced throughput, increased line edge roughness, reduced resist sensitivity, and / or increased nanopattern defects due to line bridging / breaking.

[0006] Electrode assemblies are utilized to generate electric fields before and after the exposure process and transfer the electric fields to a photoresist layer deposited on a substrate to modify the chemical properties of the portions of the photoresist layer through which the electromagnetic radiation penetrates, in order to improve the exposure / development resolution of lithography. However, it is difficult to reduce the print size on a substrate using current photoresist materials and bake processes.

[0007] Therefore, there is a need for an improved method for patterning resist on a substrate. Summary of the Invention

[0008] In one embodiment, a method for processing a film stack is described. The method includes forming a metal-containing resist layer on a substrate, patterning the metal-containing resist layer, and performing a post-exposure bake process after patterning the metal-containing resist layer. The metal-containing resist layer is one of a metal-doped resist layer or a metal oxide resist layer. The patterning of the metal-containing resist layer forms a plurality of unexposed portions of the metal-containing resist layer and a plurality of exposed portions of the metal-containing resist layer. An electric field is applied across the metal-containing resist layer perpendicular to a major plane of the substrate to process the plurality of exposed portions of the metal-containing resist layer.

[0009] In another embodiment, a method for processing a film stack includes forming a metal-containing resist layer on a substrate, patterning the metal-containing resist layer, and performing a post-exposure bake process after patterning the metal-containing resist layer. The metal-containing resist layer includes metal nanoparticles or metal oxide nanoparticles. The patterning of the metal-containing resist layer forms a plurality of unexposed portions of the metal-containing resist layer and a plurality of exposed portions of the metal-containing resist layer. The post-exposure bake process is performed by heating the substrate to about 150° C. to about 300° C. and applying a first electric field across the metal-containing resist layer.

[0010] In yet another embodiment, a method for treating a substrate includes forming a metal-containing resist layer on a substrate, baking the metal-containing resist layer, and patterning the baked metal-containing resist layer, where a post-exposure bake process is performed after the patterning of the metal-containing resist layer, the substrate is developed using a wet or dry development process after the post-exposure bake process is performed, and a post-development bake is performed after the development of the substrate. The metal-containing resist layer includes metal oxide nanoparticles or metal nanoparticles. The baked metal-containing resist layer is patterned to form a plurality of unexposed portions of the metal-containing resist layer and a plurality of exposed portions of the metal-containing resist layer. The post-exposure bake process includes heating the substrate to about 80° C. to about 300° C. and applying a first electric field perpendicular to the major surface of the substrate across the metal oxide resist layer. The post-development bake includes heating the substrate and applying a second electric field perpendicular to the major surface of the substrate across the metal-containing resist layer.

[0011] So that the above-mentioned features of the present disclosure can be understood in detail, a more particular description of the present disclosure, briefly summarized above, can be had by reference to embodiments, some of which are illustrated in the accompanying drawings, in which it is noted, however, that the accompanying drawings depict only exemplary embodiments and therefore should not be considered as limiting the scope of the present disclosure, which may admit of other equally effective embodiments. [Brief description of the drawings]

[0012] [Figure 1] 1 is a schematic top view of a substrate processing system, according to one embodiment; [Diagram 2] 2 is a schematic cross-sectional view of a processing module in the substrate processing system of FIG. 1, according to one embodiment; [Figure 3A] 1A-1C are cross-sectional views of a film stack deposited on a substrate at various stages of substrate processing; [Figure 3B] 1A-1C are cross-sectional views of a film stack deposited on a substrate at various stages of substrate processing; [Figure 3C] 1A-1C are cross-sectional views of a film stack deposited on a substrate at various stages of substrate processing; [Figure 3D] 1A-1C are cross-sectional views of a film stack deposited on a substrate at various stages of substrate processing; [Figure 3E] 1A-1C are cross-sectional views of a film stack deposited on a substrate at various stages of substrate processing; [Figure 3F] 1A-1C are cross-sectional views of a film stack deposited on a substrate at various stages of substrate processing; [Figure 3G] 1A-1C are cross-sectional views of a film stack deposited on a substrate at various stages of substrate processing; [Figure 4] FIG. 3B is a flow diagram of a method for processing a membrane stack according to the sequence shown in FIGS. 3A-3G. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] To facilitate understanding, wherever possible, like reference numerals are used to designate like elements common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0014] The present disclosure generally relates to methods and apparatus for enhancing profile control of metal oxide resists. The methods and apparatus disclosed herein help to reduce line edge / width roughness, eliminate pattern bridging / breaking line defects, and improve exposure resolution in photolithography processes for semiconductor processing applications.

[0015] Metal oxide photoresists can achieve smaller line spacing on semiconductor substrates compared to conventional photoacid resists. Performing at least one field-guided bake on metal oxide photoresists has been shown to improve edge smoothness, material properties of lines formed on the substrate, and dose sensitivity while simultaneously reducing linewidth roughness, providing a wider depth-of-focus process window while using metal oxide photoresists. The field-guided bake can be performed both before and after development of the substrate, the first field-guided bake being a post-exposure field-guided bake and the second field-guided bake being a post-development field-guided bake. Using both the first and second field-guided bakes on metal oxide photoresists further improves dose sensitivity and reduces linewidth roughness.

[0016] As described herein, a "substrate" or "substrate surface" generally refers to any substrate surface on which processing is performed. Processing includes deposition, etching, and other methods utilized during semiconductor processing. For example, substrate surfaces that may be processed include silicon, silicon oxide, doped silicon, silicon germanium, germanium, gallium arsenide, glass, sapphire, and any other materials, such as metals, metal nitrides, metal alloys, and other conductive or semiconductive materials, depending on the application. Substrates or substrate surfaces that may be processed also include conductive materials, such as silicon dioxide, silicon nitride, organosilicates, and carbon-doped silicon oxide or silicon nitride materials. The substrate itself is not limited to a particular size or shape. Although the embodiments described herein are made with reference to generally circular 200 mm or 300 mm substrates, other shapes, such as polygonal, square, rectangular, curved, or other non-circular workpieces, may also be utilized in accordance with the embodiments described herein.

[0017] FIG. 1 shows a schematic plan view of a substrate processing system 100. The substrate processing system 100 is used to process semiconductor substrates by performing various processes on the substrates. The substrate processing system 100 described herein includes a transfer chamber 110, a number of processing chambers 130a-130d, load lock chambers 120a, 120b, and a factory interface (FI) 140. The FI 140 is shown coupled with several front opening unified pods (FOUPs) 150. The processing chambers 130a-d and the load lock chambers 120a, 120b are coupled to the transfer chamber 110. The transfer chamber 110 includes a robot 115 that moves substrates between the processing chambers 130a-d and the load lock chambers 120a, 120b.

[0018] The load lock chambers 120a, 120b are coupled between the FI 140 and the transfer chamber 110. The FI 140 receives a FOUP 150 coupled to the opposite side of the load lock chambers 120a, 120b. The load lock chambers 120a, 120b include a substrate support 135 disposed therein, which is used to facilitate substrate exchange between the robot 115 of the transfer chamber 110 and the robot 108 of the FI 140. The transfer chamber 110 includes a transfer robot 115 disposed therein. The substrate support 135 holds a substrate when the load lock chambers 120a, 120b are pumped down to the vacuum level of the transfer chamber 110 or vented to the pressure of the FI 140 (usually atmospheric pressure).

[0019] Each processing chamber 130a-d includes a substrate transfer port 125 disposed adjacent to the transfer chamber 110 through which substrates enter and exit the processing chambers 130a-d via the robot 115. The substrate transfer port 125 may be sealable using a slit valve (not shown) to isolate substrates disposed in each of the processing chambers 130a-d from the transfer chamber 110.

[0020] It is contemplated that system 100 may have more or less processing chambers than the four processing chambers 130a-d shown in FIG. 1. Additionally, the locations of processing chambers 130a-d may differ from the locations shown. Although system 100 shows processing chambers 130a-d coupled to transfer chamber 110 in a cluster tool arrangement, system 100 may alternatively have processing chambers 130a-d arranged in-line, batch, linear, or other suitable manner. Processing chambers 130a-d may be configured as etch chambers, lithography exposure chambers, deposition or spin-coating chambers, bake chambers, annealing chambers, or other types of semiconductor processing chambers. Alternatively, lithography exposure chambers, deposition chambers, and bake chambers are located on separate tools and substrates are transferred between the tools.

[0021] Figure 2 shows a schematic cross-sectional view of a processing chamber 130a of the substrate processing system 100 shown in Figure 1. In some embodiments, the processing chamber 130a may be an independent, stand-alone processing chamber, which will be described in more detail below and may be used for pre-exposure bake, post-exposure bake, and / or other processing steps.

[0022] The processing chamber 130a includes chamber walls 202, an electrode assembly 216, and a substrate support assembly 238. The chamber walls 202 include sidewalls 206, a lid assembly 210, and a bottom 208. The chamber walls 202 partially enclose a processing volume 212. The processing volume 212 is accessed through a substrate transfer port 125 (shown in FIG. 1 ) configured to facilitate movement of a substrate 200 from the transfer chamber 110 into and out of the processing chamber 130a by the robot 115.

[0023] A pumping port 214 may be disposed through one of the lid assembly 210, sidewalls 206, or bottom 208 of the processing chamber 130a to connect the processing volume 212 to an exhaust system. The exhaust system includes various vacuum pumping components such as a vacuum pump, a foreline, a throttle valve, etc. The exhaust system is utilized to control the pressure within the processing volume 212 and to evacuate any gases and / or processing by-products from the processing chamber 130a.

[0024] The process chamber 130a is coupled to one or more sources 204 for supplying one or more process gases to the process volume 212. In the embodiments described herein, the source 204 is configured to supply an inert gas, such as argon (Ar), helium (He), xenon (XE), or neon (He). The source 204 may also supply one of oxygen (O2) or steam (H2O).

[0025] The substrate support assembly 238 is centrally disposed within the processing chamber 130a. The substrate support assembly 238 supports the substrate 200 during processing. The substrate support assembly 238 may include a body 224 that encapsulates at least one embedded heater 232. In some embodiments, the substrate support assembly 238 may be an electrostatic chuck. A heater 232, such as a resistive element, is disposed within the substrate support assembly 238. The heater 232 controllably heats the substrate support assembly 238 and the substrate 200 positioned thereon to a predetermined processing temperature. The heater 232 is configured to rapidly increase the temperature of the substrate 200 to precisely control the temperature of the substrate 200. In some embodiments, the heater 232 is connected to a power source 274. The power source 274, and therefore the temperature of the substrate 200, is controlled by the controller 175. Alternatively or additionally, the power source 274 may apply power to the substrate support assembly 238. The power source 274 may be configured similarly to the power source 270 discussed below. Additionally, it should be noted that the heater 232 may be located in other locations of the processing chamber 130a, such as on the chamber walls, a chamber liner, an edge ring surrounding the substrate, the chamber ceiling, etc., as needed to provide thermal energy to the substrate 200 disposed on the substrate support assembly 238.

[0026] Generally, the substrate support assembly 238 has a first surface 234 and a second surface 226. The first surface 234 is opposite the second surface 226. The first surface 234 is configured to support a substrate 200. A stem 242 is coupled to the second surface 226. The substrate 200 can be any type of substrate, such as a dielectric substrate, a glass substrate, a semiconductor substrate, or a conductive substrate. The first surface 234 of the substrate support assembly 238 is separated from the electrode assembly 216 by a distance d in the z-direction. The stem 242 is coupled to a lift system (not shown) for moving the substrate support assembly 238 between an elevated processing position (shown in FIG. 2 ) and a lowered substrate transfer position. The lift system can accurately and precisely control the z-direction position of the substrate support assembly 238 and the substrate 200 disposed thereon. In some embodiments, the lift system may be configured to move the substrate support assembly 238 and the substrate 200 disposed thereon in the x-direction, the y-direction, or both the x- and y-directions. The stem 242 further provides a conduit for electrical and thermocouple leads between the substrate support assembly 238 and other components of the processing chamber 130a. A bellows 246 is coupled to the substrate support assembly 238 to provide a vacuum seal between the processing volume 212 and the atmosphere outside the processing chamber 130a and to facilitate movement of the substrate support assembly 238 in the z-direction.

[0027] The lid assembly 210 may optionally include an inlet 280 through which gas provided by the source 204 may flow into the processing chamber 130a. The source 204 may optionally controllably pressurize the processing volume 212 with gas, such as nitrogen, argon, helium, other gases, or combinations thereof. The gas from the source 204 may create a controlled environment within the processing volume 212 of the processing chamber 130a. The inlet 280 may be located in other parts of the processing chamber 130a. Optionally, an actuator 290 may be coupled between the lid assembly 210 and the electrode assembly 216. The actuator 290 is configured to move the electrode assembly 216 in one or more of the x, y, and z directions. The actuator 290 allows the distance d to be adjusted.

[0028] The electrode assembly 216 includes at least an electrode 258. As shown, the electrode 258 is coupled to a power supply 270. In some embodiments, the electrode 258 is coupled to ground and the power supply 274 that supplies power to the substrate support 238 is a bipolar power supply that switches between a positive bias and a negative bias. The electrode assembly 216 is configured to generate an electric field perpendicular to the first surface 234 of the substrate support assembly 238. For example, the electrode assembly 216 can be configured to generate an electric field in the z or -z direction.

[0029] The power source 270 is configured to supply, for example, between about 1 V and about 100 kV to the electrode assembly 216 to generate an electric field having a strength between about 0.1 MV / m and about 100 MV / m. In some embodiments, the power source 274 may also be configured to supply power to the electrode assembly 216. In some embodiments, either or both of the power source 270 or the power source 274 are pulsed direct current (DC) power supplies. The pulsed DC wave may be from a half-wave rectifier or a full-wave rectifier. The AC / DC power may have a frequency between about 1 Hz and 1 MHz. The duty cycle of the pulsed DC power may be between about 5% and about 95%, for example between about 20% and about 60%. In some embodiments, the duty cycle of the pulsed DC power may be between about 20% and about 40%. In other embodiments, the duty cycle of the pulsed DC power may be about 60%. The rise and fall times of the pulsed DC power can be between about 1 ns and about 1000 ns, for example, between about 10 ns and about 500 ns. In other embodiments, the rise and fall times of the pulsed DC power can be between about 10 ns and about 100 ns. In some embodiments, the rise and fall times of the pulsed DC power can be about 500 ns. In some embodiments, either or both of the power source 270 or the power source 274 are alternating current (AC) power supplies. The AC power supplies can have frequencies between about 1 Hz and 1 MHz. The AC power supplies are configured to provide a peak value of about 1 V to about 100 kV to the electrode assembly 216. In other embodiments, either or both of the power source 270 or the power source 274 are DC power supplies.

[0030] In some embodiments, the voltage or power provided by either or both of the power supplies 270 and 274 may use an AC / DC offset. The AC / DC offset may be, for example, between about 0% and about 75% of the applied voltage, such as between about 5% and about 60% of the applied voltage. In some embodiments, the electrode 258 is pulsed negatively while the substrate support assembly 238 is also pulsed negatively. In these embodiments, the power supplied to the electrode 258 and the substrate support assembly 238 is synchronized but offset in time. For example, the electrode 258 may be in a "1" power state while the substrate support assembly is in a "zero" power state, and then the substrate support assembly 238 may be in a "zero" power state while the electrode 258 is in the "zero" power state.

[0031] In some embodiments, one or more magnets 296 can be positioned within the processing chamber 130a. In the embodiment shown in FIG. 1, the magnets 296 are coupled to the inner surface of the sidewall 206. In other embodiments, the magnets 296 can be positioned at other locations within the processing chamber 130a or outside the processing chamber 130a. The magnets 296 can be, for example, permanent magnets or electromagnets. Exemplary permanent magnets include ceramic magnets and rare earth magnets. In embodiments where the magnets 296 are electromagnets, the magnets 296 can be coupled to a power source (not shown). The magnets 296 are configured to generate a magnetic field in a direction perpendicular or parallel to the direction of the electric field lines generated by the electrode assembly 216 at the first surface 234 of the substrate support assembly 238.

[0032] 3A-3G are cross-sectional views of a film stack 300 deposited on a substrate 200 during various stages of a method 400 for forming a film stack. A flow diagram of the method 400 is shown in FIG. 4. At least a portion of the method 400 is performed in one or more of the processing chambers 130a-d of FIG. 1, such as the processing chamber 130a of FIG. 2. The method 400 is stored as instructions accessible by a memory of the controller 175. The controller 175 provides instructions to at least one of the substrate processing system 100 and the processing chamber 130a to perform the method 400. As shown in FIG. 3A, the film stack 300 deposited on the substrate 200 includes a device layer 304 deposited on top of the substrate 200 and an underlayer layer 306 deposited on top of the device layer 304. The device layer 304 may be one or more semiconductor devices and may include multiple layers or features therein. The underlayer 306 covers and protects the device layer 304. Alternatively, in some embodiments, the underlayer 306 is a hard mask layer. The top surface 308 of the underlayer 306 is a flat surface that is deposited on the opposite side of the underlayer 306 from the device layer 304.

[0033] The underlayer 306 includes one or more additives, such as an acid agent (e.g., a photoacid generator (PAG) or acid catalyst), a base agent, an adhesion promoter, or a photosensitive component. The one or more additives may be deposited in an organic solvent or a resin and / or an inorganic matrix material. Suitable examples of acid agents, including a photoacid generator (PAG) and / or an acid catalyst, may be selected from the group consisting of sulfonic acids (e.g., p-toluenesulfonic acid, styrenesulfonic acid), sulfonates (e.g., pyridinium p-toluenesulfonate, pyridinium trifluoromethanesulfonate, pyridinium 3-nitrobenzenesulfonate), and mixtures thereof. Suitable organic solvents may include homopolymers or higher order polymers that include two or more repeat units and a polymer backbone. Suitable examples of organic solvents include, but are not limited to, propylene glycol methyl ether acetate (PGMEA), ethyl lactate (EL), propylene glycol methyl ether (PGME), propylene glycol n-propyl ether (PnP), cyclohexanone, acetone, gamma butyrolactone (GBL), and mixtures thereof. The underlayer 306 can also be deposited using one of chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) operations. The underlayer 306 formed by one of CVD, PVD, or ALD operations has a similar composition to the underlayer 306 described above.

[0034] In one example, the underlayer 306 provides active acidic, basic, electronic, ionic, or ionic / non-ionic species during a lithographic exposure process, a pre-exposure bake process, or a post-exposure bake process.

[0035] In embodiments where the underlayer 306 is a hardmask layer, the hardmask layer can be a spin-on or CVD / PVD / ALD deposited layer made from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, amorphous carbon, doped amorphous carbon, TEOS oxide, USG, SOG, organosilicon, oxide-containing materials titanium nitride, titanium oxynitride, combinations thereof, and the like.

[0036] The method 400 begins at operation 402 by depositing a metal-containing resist layer 310 on the film stack 300, as shown in FIG. 3B. In one example, the metal-containing resist layer 310 is deposited by spin coating. In another example, the metal-containing resist layer 310 is deposited by a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process. The metal-containing resist layer 310 is formed on the top surface 308 of the underlayer 306. The metal-containing resist layer 310 is either a metal oxide resist layer or a metal-doped resist layer. Then, using the metal oxide resist layer, the metal-containing resist layer 310 includes metal oxide nanoparticles and one or more ligands bound to the metal oxide nanoparticles. The metal oxide nanoparticles act as a core to which the ligands bind. The metal oxide and the ligands form a Lewis acid / Lewis base pair and associate with each other in the metal-containing resist layer 310. The metal-containing resist layer 310 can further include other materials, such as a polymer resist. In embodiments in which the metal-containing resist layer 310 is deposited by a CVD or ALD process, the metal oxide nanoparticles and attached ligands form substantially all of the metal-containing resist layer 310.

[0037] In an embodiment where the metal oxide nanoparticles and ligands are deposited as part of the metal-containing resist layer 310 with the polymer resist, the metal oxide nanoparticles and corresponding ligands in the metal-containing resist layer 310 have a percent composition of about 5% to about 30%, such as about 10% to about 25%, such as about 15% to about 25% of the metal-containing resist layer 310. The metal oxide in the metal oxide resist layer 310 can be one or a combination of tin (IV) oxide (SnO2), titanium dioxide (TiO2), zirconium dioxide (ZrO2), hafnium dioxide (HfO2), indium (III) oxide (In2O3), or zinc oxide (ZnO). The metal oxide is formed as nanoparticles in the metal-containing resist layer 310. The use of nanoparticles as the metal oxide allows for improved association of the metal oxide particles with the ligands, improving the results of the subsequent field guided bake operation. The size of each metal oxide nanoparticle is less than about 25 nm wide, such as less than about 20 nm wide, such as less than about 15 nm wide, such as less than about 10 nm wide. The small size of each metal oxide nanoparticle helps to enable improved resolution during exposure and post-exposure bake operations. Other metal oxides are contemplated but are not disclosed herein.

[0038] The ligands in the metal-containing resist layer 310 are organic ligands, such as hydroxide (-OH), carbon monoxide (-CO), nitrous acid (NO2), 1 ), Carbonic acid (CO3 -2 ), or oxalic acid (COO) 2- 2 or a combination thereof. Other ligands can also be utilized. Smaller ligands are utilized to improve resolution during exposure and post-exposure bake operations. The ligands and metal oxides are selected to allow for controlled dissociation of the metal oxide nanoparticles and ligands within a portion of the metal-containing resist layer 310 during lithographic exposure and subsequent post-exposure bake operations. In addition, the ligands and metal oxides are selected for high absorptivity at extreme ultraviolet wavelengths.

[0039] When the metal-containing resist layer is spin-coated onto the film stack 300 during operation 402 of method 400, the metal oxide and ligand are deposited as a resin or disposed within a separate resin or solution. The film stack 300 may be immersed in the resin or solution, or a stream of the resin or solution may be dispensed onto the top surface 308 of the underlayer 306 while the film stack 300 is rotated about a central axis, causing the resin or solution to spread along the top surface of the film stack 300.

[0040] In embodiments where the metal-containing resist layer 310 is deposited using chemical vapor deposition (CVD) or atomic layer deposition (ALD) during operation 402 of method 400, the metal oxide and ligand may be deposited by introducing a first precursor that includes the metal oxide and a second precursor that includes the ligand. The precursor flows of the first precursor and the second precursor may be mixed to form a metal oxide material or an organometallic material. The mixing of the first precursor and the second precursor is performed simultaneously with the deposition of the metal oxide resist layer 310.

[0041] In some embodiments, the metal-containing resist layer 310 is a resist layer having a metal dopant disposed therein. The resist layer can be a polymer resist. The metal dopant can be one or a combination of tin (Sn), titanium (Ti), zirconium (Zr), hafnium (Hf), indium (In), or zinc (Zn). The metal dopant is formed as nanoparticles within the resist layer 310. The use of the metal nanoparticle dopant improves the results of a subsequent field guided bake operation. The size of each metal nanoparticle is less than about 25 nm wide, such as less than about 20 nm wide, such as less than about 15 nm wide, such as less than about 10 nm wide. The small size of each metal nanoparticle helps enable improved resolution during exposure and post-exposure bake operations. Other metal nanoparticle compositions are contemplated but are not disclosed herein.

[0042] The resist layer components of the metal-containing resist layer 310 include one or more additives, such as an acid agent (e.g., a photoacid generator (PAG) or acid catalyst), a base agent, an adhesion promoter, or a photosensitive component. The one or more additives may be deposited in an organic solvent or a resin and / or an inorganic matrix material. Suitable examples of acid agents, including photoacid generators (PAG) and / or acid catalysts, may be selected from the group consisting of sulfonic acids (e.g., p-toluenesulfonic acid, styrenesulfonic acid), sulfonates (e.g., pyridinium p-toluenesulfonate, pyridinium trifluoromethanesulfonate, pyridinium 3-nitrobenzenesulfonate), and mixtures thereof. Suitable organic solvents may include homopolymers or higher order polymers comprising two or more repeat units and a polymer backbone. Suitable examples of organic solvents include, but are not limited to, propylene glycol methyl ether acetate (PGMEA), ethyl lactate (EL), propylene glycol methyl ether (PGME), propylene glycol n-propyl ether (PnP), cyclohexanone, acetone, gamma butyrolactone (GBL), and mixtures thereof. The resist layer may also be deposited using one of chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) operations. The resist layer may be formed by one of CVD, PVD, or ALD operations and is of similar composition to the resist layers described above.

[0043] In an embodiment in which the metal-containing resist layer 310 is deposited using CVD or ALD during operation 402 of method 400, the metal nanoparticles are deposited by introducing a first precursor containing the metal nanoparticles and one or more second precursors that form a photoresist material. The precursor flows of the first precursor and the second precursor can be mixed to form a metal-doped resist layer. The mixing of the first precursor and the second precursor occurs simultaneously with the deposition of the metal oxide resist layer 310. In an embodiment in which the metal nanoparticles are deposited as part of the metal-containing resist layer 310 with a polymer resist, the metal nanoparticles in the metal-containing resist layer 310 have a percent composition of about 5% to about 30%, such as about 10% to about 25%, such as about 15% to about 25% of the metal-containing resist layer 310.

[0044] The suggested processing conditions utilized during method 400 may be utilized in embodiments employing either a metal oxide resist layer or a metal doped resist layer, and thus, similar expose and bake operations may be performed with any of the metal oxide resist layer or metal doped resist layer embodiments described herein.

[0045] In operation 404, the film stack 300 with the metal-containing resist layer 310 deposited thereon is subjected to a baking operation 404, as shown in FIG. 3C. Baking the film stack 300 includes heating the metal-containing resist layer 310 to a temperature of about 80° C. to about 300° C., such as about 80° C. to about 250° C., such as about 100° C. to about 250° C. Baking the film stack 300 may be performed in the same processing chamber as the formation of the metal-containing resist layer 310, or in a different processing chamber. Baking the film stack 300 hardens the metal-containing resist layer 310 and forms a baked metal-containing resist layer 312 from the metal-containing resist layer 310. The baked metal-containing resist layer 312 is a solid layer and is rigid.

[0046] In operation 406, the baked metal-containing resist layer 312 deposited on the film stack 300 is exposed to radiation, as shown in FIG. 3D. The exposure operation 406 occurs in a lithography processing chamber, which may be one of chambers 130c-d or other suitable chamber. The film stack 300 is exposed to radiation to pattern the baked metal-containing resist layer 312. Patterning the baked metal-containing resist layer 312 includes forming a plurality of unexposed portions 312a and a plurality of exposed portions 312b from the baked metal-containing resist layer 312. The unexposed portions 312a are not exposed to radiation and therefore remain substantially the same as the baked metal-containing resist layer 312. The exposed portions 312b are exposed to radiation at a frequency and intensity that dissociates the metal oxide nanoparticles from the ligands. Dissociation of the metal oxide nanoparticles and the ligands results in the formation of a Lewis acid separated from the metal oxide and a Lewis base from the ligand. The exposed portions 312b may be further cross-linked by exposure to radiation. Thus, the physical and chemical properties of the exposed portions 312b change differently than the unexposed portions 312a. As described herein, the baked metal-containing resist layer 312 is a positive resist layer. However, in some embodiments, exposing a portion of the baked metal-containing resist layer 312 to radiation may release the cross-links in the exposed portions 312b, and the baked metal-containing resist layer 312 functions as a negative resist layer.

[0047] The exposure operation 406 includes exposing the exposed portions 312b to radiation, such as UV light radiation. In the embodiments described herein, the exposed portions 312b are exposed to radiation having a wavelength of about 5 nm to about 400 nm, such as about 5 nm to about 20 nm, such as about 10 nm to about 14 nm. The UV light radiation is extreme ultraviolet light (EUV light). The extreme ultraviolet light enables dissociation of metal oxides and ligands in the exposed portions 312b.

[0048] After operation 406, the exposed film stack 300 is subjected to a post-exposure field-guided bake operation 408, as shown in FIG. 3E. The post-exposure field-guided bake operation 408 can be performed in a processing chamber similar to the processing chamber 130a shown in FIG. 2, or in another suitable processing chamber. The post-exposure field-guided bake operation 408 includes heating the film stack 300 and applying an electric field to the film stack and the baked metal-containing resist layer 312 such that the electric field interacts with the non-exposed portions 312a and the exposed portions 312b of the baked metal-containing resist layer 312. The electric field interacts with the Lewis acid and Lewis base formed by the dissociated metal oxide and ligands, as well as any additional ions disposed within the baked metal-containing resist layer 312. The electric field can crosslink the metal oxide nanoparticles and ligands in the exposed portions 312b. The electric field is applied between the electrode 258 and the first surface 234 of the substrate support assembly 238.

[0049] When a post-exposure field-guided bake operation 408 is performed, the distribution and drift of ligands and other ions in the baked metal-containing resist layer 312 is controlled by an electric field. The electric field is oriented approximately perpendicular to the top surface of the film stack 300, such as approximately perpendicular to the top surface 308 of the underlayer 306 of the substrate 200. The electric field can also be described as being oriented perpendicular or perpendicular to the major surface of the substrate. The major surface of the substrate may be referred to as the wafer surface. The major surface is oriented along the diameter of the substrate 200. The major surface may be perpendicular to the top surface 308 of the underlayer 306 or the top surface of the film stack 300. The major surface is oriented along the length of the substrate. The electric field controls the direction of the reaction of the metal oxides with the ligands to prevent diffusion of the dissociated metal oxides and ligands into the unexposed portions 312a. During the post-exposure field-guided bake operation 408, the exposed portions 312b are converted into a plurality of baked exposed portions 314. The post-baked exposed portions 314 have greater cross-linking and the line edge roughness is reduced due to the movement of charged particles parallel to the electric field in the baked metal-containing resist layer 312 during the post-exposure field-guided bake operation 408. Thus, the electric field helps improve the photoresist line edge roughness, line critical dimension uniformity, and dose sensitivity.

[0050] In some embodiments, the electric field can be controlled to be oriented in different directions, such as parallel to the top surface 308 of the underlayer 306 or parallel to the major surface. The electric field has a strength across the film stack 300 of about 100 MV / m to about 2000 MV / m. The electric field is induced by a voltage difference between the electrode 258 and the first surface 234 of the substrate support assembly 238 of about 0 V to about 4000 V, e.g., about 10 V to about 4000 V, e.g., about 100 V to about 4000 V. Alternatively, a current of about 10 μA to about 1 A may be applied to the electrode 258.

[0051] During the post-exposure field-guided bake operation 408, the substrate 200 and film stack 300 are heated to a temperature of about 100° C. to about 300° C., for example, about 100° C. to about 250° C., for example, about 150° C. to about 250° C., for example, about 175° C. to about 250° C. Performing the field-guided bake operation 408 at a temperature above 100° C. improves stochasticity and crosslinking in the exposed portions 312b. As the temperature increases during the post-exposure field-guided bake operation 408, for example, toward about 250° C., such as about 150° C., the mobility of dissociated ligands and other charged ions increases in the exposed portions 312b. The post-exposure field-guided bake operation 408 is further performed at a pressure of about 100 mTorr to about 800 Torr, for example, about 100 mTorr to about 760 Torr, for example, about 1 Torr to about 600 Torr.

[0052] The post-exposure field-guided bake operation 408 can be either a dry process or a wet process. In an example where the post-exposure field-guided bake operation 408 is a dry process, the medium in the processing volume 212 is a gas. The gas can be an inert gas, such as one or a combination of argon (Ar), helium (He), xenon (XE), neon (He), nitrogen (N2), or ambient air. In some embodiments, the processing volume 212 is under vacuum and no gas flows into the processing volume 212 during the post-exposure field-guided bake operation 408. In other embodiments, the gas includes carbon dioxide (CO2), oxygen (O2), or steam (H2O). The steam is kept in a gaseous state and does not condense at the temperature and pressure in the processing chamber 130a. In an example where the post-exposure field-guided bake operation 408 is a wet process, the medium in the processing volume is a liquid or a slurry. Possible media include carbon-based liquids or deionized liquid water.

[0053] In a developing operation 410, the film stack 300 is subjected to a wet or dry developing process, as shown in FIG. 3F. Optionally, the developing operation 410 can also include an area-selective ALD process. An area-selective ALD process can be used to selectively deposit a layer on one of the unexposed portions 312a or the exposed portions 312b. Area-selective ALD can deposit a separate hard mask layer on the baked metal-containing resist layer 312. Area-selective ALD selectively deposits due to the different surface properties of each of the unexposed portions 312a and the exposed portions 312b.

[0054] Specifically, FIG. 3F illustrates the film stack after development of the film stack 300. The development is configured to remove either the unexposed portion 312a or the exposed portion 312b. Whether the unexposed portion 312b or the exposed portion 312b is removed depends at least in part on whether the development process is configured to be a positive or negative development process. In a positive tone development process, the baked exposed portion 314 is removed leaving the unexposed portion 312f as shown in FIG. 3F. In a negative tone development process, the baked exposed portion 314 is left while the unexposed portion is removed (not shown). The baked metal-containing resist layer 312 is processed using a wet or dry etch. The wet or dry etch is performed in a separate chamber from the processing chamber 130a in which the post-exposure field guided bake operation 408 is performed. As shown herein, etching is performed to remove at least a portion of the baked exposed portions 314 and form a plurality of openings 316 between each of the non-exposed portions 312a. Thus, the sidewalls 318 of each of the non-exposed portions 312a are exposed, forming the openings 316 in the baked metal-containing resist layer 312. When the baked exposed portions 314 are completely removed, the top surface 308 of the underlayer 306 is exposed, forming the bottom surface of the openings 316. Alternatively, the non-exposed portions 312a of the baked metal-containing resist layer 312 can be removed by wet or dry development.

[0055] The dry development can be an anisotropic etching process, such as a selective etching process. The film stack 300 may be exposed to a plasma or other thermal process to remove the unexposed portions 312a or the post-bake exposed portions 314.

[0056] Wet development can include applying a solvent or other liquid configured to remove one of the post-baked exposed portions 314 or the non-exposed portions 312a. The solvent removes at least a portion of one of the post-baked exposed portions 314 or the non-exposed portions 312a.

[0057] Area-selective ALD is not shown in FIG. 3F but can be performed if it is desired to form an area-selective hard mask. Area-selective ALD is performed to selectively deposit a metal or metal oxide on one of the baked exposed portions 314 or the unexposed portions 312a. Area-selective ALD deposits a metal or metal oxide only on one of the baked exposed portions 314 or the unexposed portions 312a and is therefore selective to areas of the baked metal-containing resist layer 312 having a predetermined surface quality.

[0058] After performing the develop operation 410, an optional post-develop field guided bake or anneal, such as a post-develop field guided bake / anneal process, is performed in operation 412. The optional post-develop field guided bake or anneal is performed to improve edge smoothness and improve material properties of the remaining portion of the baked metal-containing resist layer 312 by improving cross-linking within the baked metal-containing resist layer 312. The post-develop field guided bake operation 412 can be performed using process conditions similar to those described for the post-exposure field guided bake operation 408. The temperature during the post-develop field guided bake operation 412 is from about 100° C. to about 300° C., such as from about 100° C. to about 250° C., such as from about 150° C. to about 250° C., such as from about 175° C. to about 250° C. The pressure during the post develop field guide bake operation 412 is from about 100 mTorr to about 800 Torr, such as from about 100 mTorr to about 760 Torr, such as from about 100 mTorr to about 600 Torr.

[0059] In some embodiments, one or both of the post exposure field guided bake operation 408 and the post development field guided bake / anneal operation 412 are performed at superatmospheric pressure. The superatmospheric pressure is from about 760 Torr to about 1500 Torr, such as from about 760 Torr to about 1200 Torr. Superatmospheric pressure has been shown to improve crosslinking and reduce bake times. Thus, in some embodiments, the pressure during the post exposure field guided bake operation 408 and / or the post development field guided bake / anneal operation 412 is from about 100 mTorr to about 1200 Torr.

[0060] The electric field applied to the film stack 300 during the post develop field guided bake / anneal operation 412 is similar to the electric field applied during the post exposure field guided bake operation 408. The electric field has a strength of about 100 MV / m to about 2000 MV / m across the film stack 300 during the post develop field guided bake / anneal operation 412, 512. The electric field is generated by a voltage difference between the electrode 258 and the first surface 234 of the substrate support assembly 238 of about 0 V to about 4000 V, e.g., about 10 V to about 4000 V, e.g., about 100 V to about 4000 V. Alternatively, a current can be applied to the electrode 258, resulting in a current of about 10 μA to about 1 A.

[0061] The post-develop field-guided bake operation 412 can be either a dry process or a wet process. In an operation where the post-develop field-guided bake operation 412 is a dry process, the medium in the processing volume 212 is a gas. The gas can be an inert gas, such as one or a combination of argon (Ar), helium (He), xenon (XE), or neon (He). In other embodiments, the gas includes oxygen (O2) or steam (H2O). In an operation where the post-develop field-guided bake operation 412 is a wet process, the medium in the processing volume is a liquid or a slurry. Possible media include fluorocarbon-based liquids or hydrocarbon-based fluids such as oil. Deionized liquid water can also serve as a medium.

[0062] After the development 410, and optionally after a second post-develop field guide bake operation 412, an etching operation 414 is performed, as shown in FIG. 3G. The etching operation 414 includes etching at least a portion of the underlayer 306 through the openings 316 in the baked metal-containing resist layer 312. The etching operation 414 can be any suitable dry or wet etching process. Etching the underlayer 306 forms a plurality of underlayer openings 320 formed through the underlayer 306. Each of the underlayer openings 320 has sidewalls 322 and a bottom formed by a top surface 324 of the device layer 304.

[0063] A drying or cleaning operation (not shown) may also be performed either during or after the method 400 described herein. The drying or cleaning operation may include any suitable drying or cleaning process.

[0064] The methods described herein allow for improved dose sensitivity and reduced linewidth roughness when using metal-containing resist layers. The field guide post-exposure bake process impacts ion and charged particle drift in the metal-containing resist layer. Improving patterning resist sensitivity, linewidth roughness, and line edge roughness allows for smaller and more uniform features on the film stack 300. Thus, smaller linewidths can be utilized while reducing the impact of linewidth roughness on device yield.

[0065] While the forgoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof, which scope is determined by the following claims.

Claims

1. 1. A method for patterning a resist on a substrate, comprising: forming a metal-containing resist layer on a substrate, the metal-containing resist layer being one of a metal-doped resist layer or a metal oxide resist layer, the metal-containing resist layer comprising: A photoresist layer; metal nanoparticles in the photoresist layer, each metal nanoparticle having a size of less than about 25 nm in width; forming a metal-containing resist layer having patterning the metal-containing resist layer to form a plurality of unexposed portions of the metal-containing resist layer and a plurality of exposed portions of the metal-containing resist layer; and performing a post-exposure bake process after patterning the metal-containing resist layer, wherein an electric field generated by a voltage difference of about 100V to about 4000V between a substrate support and an electrode is applied across the metal-containing resist layer and perpendicular to a major surface of the substrate through an inert gas in contact with the metal-containing resist layer to treat the plurality of exposed portions of the metal-containing resist layer; A method comprising:

2. forming the metal-containing resist layer on the substrate comprises depositing the metal-containing resist layer by spin coating, CVD, or ALD; baking the metal-containing resist layer prior to patterning the metal-containing resist layer; and developing said metal-containing resist layer using a wet or dry development process after performing said post-exposure bake process. The method of claim 1 further comprising:

3. The substrate is a device layer disposed over the substrate; and an underlayer deposited on top of the device layer and below the metal-containing resist layer; The method of claim 1 , comprising:

4. the metal-containing resist layer is the metal oxide resist layer, and the metal nanoparticles comprising metal oxide nanoparticles, and Ligands bound to said metal oxide nanoparticles The method of claim 1 , comprising:

5. 5. The method of claim 4, wherein the metal-containing resist layer comprises one or a combination of tin (IV) oxide, titanium dioxide, zirconium dioxide, hafnium dioxide, indium (III) oxide, and zinc oxide.

6. 10. The method of claim 1, wherein the metal nanoparticles of the metal-containing resist layer have a percent composition of the metal-containing resist layer of about 5% to about 30%.

7. The method of claim 6 , wherein the metal-containing resist layer comprises one or a combination of tin, titanium, zirconium, hafnium, indium, or zinc.

8. 10. The method of claim 1, wherein the post-exposure bake process is carried out at a temperature of about 100°C to about 300°C.

9. 9. The method of claim 8, wherein the post-exposure bake process is performed at a pressure of about 100 mTorr to about 1200 Torr.

10. A method for patterning a resist on a substrate, comprising the steps of: forming a metal-containing resist layer on a substrate, the metal-containing resist layer comprising metal nanoparticles or metal oxide nanoparticles having a width of less than about 25 nm; patterning the metal-containing resist layer to form a plurality of unexposed portions of the metal-containing resist layer and a plurality of exposed portions of the metal-containing resist layer; and performing a post-exposure bake process after patterning the metal-containing resist layer by heating the substrate to about 150° C. to about 300° C. and applying a first electric field generated by a voltage difference of about 100 V to about 4000 V between a substrate support and an electrode through an inert gas in contact with the metal-containing resist layer across the metal-containing resist layer and perpendicular to a major surface of the substrate to treat the plurality of unexposed portions of the metal-containing resist layer. A method comprising:

11. baking the metal-containing resist layer prior to patterning the metal-containing resist layer; and developing said metal-containing resist layer using a wet or dry development process after performing said post-exposure bake process. The method of claim 10 further comprising:

12. heating the substrate to about 150° C. to about 250° C. after developing the metal-containing resist layer and applying a second electric field across the metal-containing resist layer perpendicular to a major surface of the substrate. The method of claim 11 further comprising:

13. The method of claim 11 , wherein developing the substrate comprises etching at least a portion of the exposed portions of the metal-containing resist layer.

14. performing said post-exposure bake process; maintaining a volume in which the substrate is processed at a pressure between about 100 mTorr and about 1200 Torr; The method of claim 10 further comprising:

15. forming the metal-containing resist layer on the substrate, spin-coating the metal-containing resist layer on the substrate; The method of claim 10 further comprising:

16. forming the metal-containing resist layer on the substrate, depositing said metal-containing resist layer by a chemical vapor deposition process or an atomic layer deposition process. The method of claim 10 further comprising:

17. 1. A method for processing a substrate, comprising: forming a metal-containing resist layer on a substrate, the metal-containing resist layer comprising metal oxide nanoparticles or metal nanoparticles disposed in the metal-containing resist layer and having a width of less than about 25 nm; baking the metal-containing resist layer; patterning the baked metal-containing resist layer to form a plurality of unexposed portions of the metal-containing resist layer and a plurality of exposed portions of the metal-containing resist layer; performing a post-exposure bake process after patterning the metal-containing resist layer by heating the substrate to about 80° C. to about 300° C. and applying a first electric field generated by a voltage difference of about 100 V to about 4000 V between a substrate support and an electrode through an inert gas in contact with the metal-containing resist layer across the metal-containing resist layer and perpendicular to a major surface of the substrate to treat the plurality of unexposed portions of the metal-containing resist layer; developing the substrate using a wet or dry development process after performing the post-exposure bake process; and performing a post-development bake after developing the substrate by heating the substrate and applying a second electric field across the metal-containing resist layer perpendicular to a major surface of the substrate. A method comprising:

18. Developing the substrate removing at least a portion of the exposed portions of the metal-containing resist layer; 20. The method of claim 17, comprising:

19. Developing the substrate Performing an area-selective atomic layer deposition process 20. The method of claim 17, further comprising:

20. patterning the metal-containing resist layer exposing the exposed portion of the metal-containing resist layer to radiation having a wavelength of about 5 nm to about 20 nm.

20. The method of claim 17, further comprising:

21. The method of claim 1, wherein a current of about 10 μA to about 1 A flows from the electrode to the substrate support during the post-exposure bake process.

22. The method of claim 1, further comprising performing a wet development process after the post-exposure bake process.

Images