Semiconductor device manufacturing method

Abstract

To provide a method for manufacturing semiconductor devices that can properly cut a hexagonal crystal structure from two different directions.SOLUTION: A method for manufacturing a semiconductor device includes the steps of preparing a hexagonal crystal structure, cutting the crystal structure in the m-axis direction of the hexagonal crystal to form a first cut section, and cutting the crystal structure in the a-axis direction of the hexagonal crystal to form a second cut section that crosses the first cut section.SELECTED DRAWING: Figure 25A

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a wafer processing method for cutting out a plurality of devices from a single wafer. The wafer is made of silicon carbide (SiC), gallium nitride (GaN), lithium tantalate (LT), lithium niobate (LN), or the like. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-100255 A Summary of the Invention [Problem to be solved by the invention]

[0004] A crystal structure made of hexagonal crystals has different physical properties depending on the crystal plane and crystal direction. For example, a crystal structure made of hexagonal crystals has the physical property that it is easy to crack along the arrangement direction of the nearest atoms (hereinafter simply referred to as the "nearest atom direction"), but is difficult to crack along the intersecting direction intersecting the nearest atom direction (hereinafter simply referred to as the "intersecting direction of the nearest atom direction").

[0005] The present inventors have conducted extensive research into a process of cutting a crystal structure along a nearest-neighbor atom direction and then cutting the crystal structure along a direction intersecting the nearest-neighbor atom direction, and have found that in the second cutting process, a protruding portion protruding along the nearest-neighbor atom direction is formed at the cut portion of the crystal structure.

[0006] In particular, this protuberance tends to occur at the connection between the cut portion formed in the first cutting step and the cut portion formed in the second cutting step. In the second cutting step, the crystal structure is cut in a direction in which the atomic arrangement is discontinuous with respect to the nearest atom direction. It is therefore believed that a force that maintains the atomic arrangement in the crystal structure acts, forming a protuberance along the nearest atom direction at the cut portion.

[0007] An embodiment of the present invention provides a method for manufacturing a semiconductor device that can appropriately cut a hexagonal crystal structure from two different directions. [Means for solving the problem]

[0008] One embodiment of the present invention provides a method for manufacturing a semiconductor device, including the steps of preparing a hexagonal crystal structure, cutting the crystal structure in an m-axis direction of the hexagonal crystal to form a first cut portion, and cutting the crystal structure in an a-axis direction of the hexagonal crystal to form a second cut portion that intersects the first cut portion.

[0009] According to this crystal cutting method, the crystal structure is cut along the m-axis direction, which is a direction intersecting the nearest-neighbor atom direction, in the step of forming the first cut portion, and the crystal structure is cut along the a-axis direction, which is the nearest-neighbor atom direction, in the step of forming the second cut portion.

[0010] In the step of forming the first cut portion, the uncut crystal structure is cut, so that the stress on the crystal structure does not become discontinuous. This makes it possible to suppress the occurrence of protrusions in the first cut portion. On the other hand, in the step of forming the second cut portion, the crystal structure is cut in a direction intersecting the nearest atom direction, so that the stress on the crystal structure becomes discontinuous. However, in the step of forming the second cut portion, stress is applied to the crystal structure along the nearest atom direction, and the crystal structure is cut along the nearest atom direction.

[0011] This makes it possible to suppress the generation of protrusions in the second cut portion, thereby improving the flatness of the first cut portion and the second cut portion, thereby providing a method for manufacturing a semiconductor device that can appropriately cut a hexagonal crystal structure from two different directions.

[0012] One embodiment of the present invention provides a crystal cutting method including: a step of preparing a crystal structure made of a hexagonal crystal; a first cutting step of cutting the crystal structure along a [1-100] direction of the hexagonal crystal to form a first cut portion in the crystal structure; and a second cutting step of cutting the crystal structure along a [11-20] direction of the hexagonal crystal to form a second cut portion in the crystal structure that intersects with the first cut portion.

[0013] According to this crystal cutting method, the crystal structure is cut in a first cutting step along the [1-100] direction that intersects with the nearest-neighbor atomic direction, and in a second cutting step, the crystal structure is cut in the [11-20] direction that is the nearest-neighbor atomic direction.

[0014] In the first cutting step, an uncut crystal structure is cut, so that the stress on the crystal structure does not become discontinuous. This makes it possible to suppress the occurrence of protrusions at the first cut portion. On the other hand, in the second cutting step, the crystal structure is cut in a direction intersecting the nearest atom direction, so that the stress on the crystal structure becomes discontinuous. However, in the second cutting step, stress is applied to the crystal structure along the nearest atom direction, and the crystal structure is cut along the nearest atom direction.

[0015] This makes it possible to suppress the occurrence of protrusions in the second cut portion, thereby improving the flatness of the first cut portion and the second cut portion, and thus provides a crystal cutting method that can appropriately cut a crystal structure made of hexagonal crystals from two different directions.

[0016] One embodiment of the present invention provides a crystal cutting method including the steps of: preparing a SiC crystal structure made of a hexagonal crystal; a first cutting step of cutting the SiC crystal structure along a [1-100] direction of the hexagonal crystal to form a first cut portion in the SiC crystal structure; and a second cutting step of cutting the SiC crystal structure along a [11-20] direction of the hexagonal crystal to form a second cut portion in the SiC crystal structure that intersects with the first cut portion.

[0017] According to this crystal cutting method, the SiC crystal structure is cut in a first cutting step along the [1-100] direction, which is a direction intersecting the nearest neighbor atomic direction, and in a second cutting step, the SiC crystal structure is cut in the [11-20] direction, which is the nearest neighbor atomic direction.

[0018] In the first cutting step, the uncut SiC crystal structure is cut, so that the stress on the SiC crystal structure does not become discontinuous. This makes it possible to suppress the occurrence of protuberances in the first cut portion. On the other hand, in the second cutting step, the SiC crystal structure is cut in a direction intersecting the nearest-neighbor atom direction, so that the stress on the SiC crystal structure becomes discontinuous. However, in the second cutting step, stress is applied to the SiC crystal structure along the nearest-neighbor atom direction, and the SiC crystal structure is cut along the nearest-neighbor atom direction.

[0019] This makes it possible to suppress the occurrence of protrusions in the second cut portion, thereby improving the flatness of the first cut portion and the second cut portion, and thus provides a crystal cutting method that can appropriately cut a SiC crystal structure made of hexagonal crystals from two different directions.

[0020] One embodiment of the present invention provides a method for manufacturing a SiC semiconductor device, the method including the steps of: preparing a SiC crystal structure made of a hexagonal crystal; setting a rectangular device region in the SiC crystal structure, the rectangular device region having a [1-100] oriented side along the [1-100] direction of the hexagonal crystal and a [11-20] oriented side along the [11-20] direction of the hexagonal crystal, and forming a functional device in the device region; a first cutting step of cutting the SiC crystal structure along the [1-100] oriented side of the device region to form a first cut portion in the SiC crystal structure; and a second cutting step of cutting the SiC crystal structure along the [11-20] oriented side of the device region to form a second cut portion in the SiC crystal structure that crosses the first cut portion.

[0021] According to this method for manufacturing a SiC semiconductor device, the SiC crystal structure is cut in a first cutting step along the [1-100] direction that intersects with the nearest neighbor atomic direction, and in a second cutting step, the SiC crystal structure is cut in the [11-20] direction that is the nearest neighbor atomic direction.

[0022] In the first cutting step, the uncut SiC crystal structure is cut, so that the stress on the SiC crystal structure does not become discontinuous. This makes it possible to suppress the occurrence of protuberances in the first cut portion. On the other hand, in the second cutting step, the SiC crystal structure is cut in a direction intersecting the nearest-neighbor atom direction, so that the stress on the SiC crystal structure becomes discontinuous. However, in the second cutting step, stress is applied to the SiC crystal structure along the nearest-neighbor atom direction, and the SiC crystal structure is cut along the nearest-neighbor atom direction.

[0023] This makes it possible to suppress the occurrence of protrusions in the second cut portion, thereby improving the flatness of the first cut portion and the second cut portion, and thus provides a method for manufacturing a SiC semiconductor device that can appropriately cut a SiC crystal structure made of hexagonal crystals from two different directions.

[0024] One embodiment of the present invention provides a SiC semiconductor device including a SiC semiconductor layer made of a hexagonal crystal, including a first main surface on one side, a second main surface on the other side, a first side surface connecting the first main surface and the second main surface and extending along a [11-20] direction of the hexagonal crystal, and a second side surface connecting the first main surface and the second main surface, extending along the [1-100] direction of the hexagonal crystal, and having an in-plane variation of 20 μm or less along the [11-20] direction of the hexagonal crystal.

[0025] The above and other objects, features and advantages of the present invention will become apparent from the following detailed description of the embodiments with reference to the accompanying drawings. [Brief description of the drawings]

[0026] [Figure 1] FIG. 1 is a diagram showing a unit cell of a 4H—SiC single crystal applied to an embodiment of the present invention. [Diagram 2] FIG. 2 is a plan view showing the silicon surface of the unit cell of the 4H—SiC single crystal shown in FIG. [Diagram 3] FIG. 3 is a perspective view showing a 4H—SiC crystal structure including a 4H—SiC single crystal. [Figure 4] FIG. 4 is a plan view showing a state in which the 4H—SiC crystal structure is fractured. [Figure 5A] FIG. 5A is a cross-sectional perspective view of a partial region of the 4H—SiC crystal structure shown in FIG. 3, for illustrating the SiC processing method in accordance with the first embodiment of the present invention. [Figure 5B] FIG. 5B is a cross-sectional perspective view showing a step subsequent to that of FIG. 5A. [Figure 5C] FIG. 5C is a cross-sectional perspective view showing a step subsequent to FIG. 5B. [Figure 5D] FIG. 5D is a cross-sectional perspective view showing a step subsequent to FIG. 5C. [Figure 6] FIG. 6 is a cross-sectional view showing a modified layer formed in the step of FIG. 5B. [Figure 7] FIG. 7 is a graph showing the components of the 4H—SiC crystal structure. [Figure 8A]FIG. 8A is a cross-sectional perspective view of a partial region of the 4H—SiC crystal structure shown in FIG. 3, for illustrating a SiC processing method in accordance with a second embodiment of the present invention. [Figure 8B] FIG. 8B is a cross-sectional perspective view showing a step subsequent to that of FIG. 8A. [Figure 8C] FIG. 8C is a cross-sectional perspective view showing a step subsequent to FIG. 8B. [Figure 8D] FIG. 8D is a cross-sectional perspective view showing a step subsequent to FIG. 8C. [Figure 9A] FIG. 9A is a cross-sectional perspective view of a partial region of the 4H—SiC crystal structure shown in FIG. 3, for illustrating a SiC processing method in accordance with a third embodiment of the present invention. [Figure 9B] FIG. 9B is a cross-sectional perspective view showing a step subsequent to that of FIG. 9A. [Figure 9C] FIG. 9C is a cross-sectional perspective view showing a step subsequent to FIG. 9B. [Figure 9D] FIG. 9D is a cross-sectional perspective view showing a step subsequent to FIG. 9C. [Figure 10A] FIG. 10A is a cross-sectional perspective view of a partial region of the 4H—SiC crystal structure shown in FIG. 3, for illustrating a SiC processing method in accordance with a fourth embodiment of the present invention. [Figure 10B] FIG. 10B is a cross-sectional perspective view showing a step subsequent to that of FIG. 10A. [Figure 10C] FIG. 10C is a cross-sectional perspective view showing a step subsequent to that of FIG. 10B. [Figure 10D] FIG. 10D is a cross-sectional perspective view showing a step subsequent to FIG. 10C. [Figure 11A] FIG. 11A is a cross-sectional perspective view of a partial region of the 4H—SiC crystal structure shown in FIG. 3, for illustrating a SiC processing method in accordance with a fifth embodiment of the present invention. [Figure 11B] FIG. 11B is a cross-sectional perspective view showing a step subsequent to that of FIG. 11A. [Figure 11C] FIG. 11C is a cross-sectional perspective view showing a step subsequent to that of FIG. 11B. [Figure 11D] FIG. 11D is a cross-sectional perspective view showing a step subsequent to FIG. 11C. [Figure 12A] FIG. 12A is a cross-sectional perspective view of a partial region of the 4H—SiC crystal structure shown in FIG. 3, for illustrating a SiC processing method in accordance with a sixth embodiment of the present invention. [Figure 12B] FIG. 12B is a cross-sectional perspective view showing a step subsequent to that of FIG. 12A. [Figure 12C] FIG. 12C is a cross-sectional perspective view showing a step subsequent to FIG. 12B. [Figure 12D] FIG. 12D is a cross-sectional perspective view showing a step subsequent to FIG. 12C. [Figure 13A] FIG. 13A is a cross-sectional perspective view of a partial region of the 4H—SiC crystal structure shown in FIG. 3, for illustrating a SiC processing method in accordance with a seventh embodiment of the present invention. [Figure 13B] FIG. 13B is a cross-sectional perspective view showing a step subsequent to that of FIG. 13A. [Figure 13C] FIG. 13C is a cross-sectional perspective view showing a step subsequent to FIG. 13B. [Figure 13D] FIG. 13D is a cross-sectional perspective view showing a step subsequent to FIG. 13C. [Figure 14A] FIG. 14A is a cross-sectional perspective view of a partial region of the 4H—SiC crystal structure shown in FIG. 3, for illustrating a SiC processing method in accordance with an eighth embodiment of the present invention. [Figure 14B] FIG. 14B is a cross-sectional perspective view showing a step subsequent to that of FIG. 14A. [Figure 14C] FIG. 14C is a cross-sectional perspective view showing a step subsequent to that of FIG. 14B. [Figure 14D] FIG. 14D is a cross-sectional perspective view showing a step subsequent to FIG. 14C. [Figure 15A] FIG. 15A is a cross-sectional perspective view of a partial region of the 4H—SiC crystal structure shown in FIG. 3, for illustrating a SiC processing method in accordance with a ninth embodiment of the present invention. [Figure 15B] FIG. 15B is a cross-sectional perspective view showing a step subsequent to that of FIG. 15A. [Figure 15C] FIG. 15C is a cross-sectional perspective view showing a step subsequent to that of FIG. 15B. [Figure 15D]FIG. 15D is a cross-sectional perspective view showing a step subsequent to FIG. 15C. [Figure 16A] FIG. 16A is a cross-sectional perspective view of a partial region of the 4H—SiC crystal structure shown in FIG. 3, for illustrating a SiC processing method in accordance with a tenth embodiment of the present invention. [Figure 16B] FIG. 16B is a cross-sectional perspective view showing a step subsequent to that of FIG. 16A. [Figure 16C] FIG. 16C is a cross-sectional perspective view showing a step subsequent to that of FIG. 16B. [Figure 16D] FIG. 16D is a cross-sectional perspective view showing a step subsequent to that of FIG. 16C. [Figure 17] FIG. 17 is a perspective view showing a schematic configuration of a SiC semiconductor device according to an eleventh embodiment of the present invention. [Figure 18] FIG. 18 is a plan view of the SiC semiconductor device shown in FIG. [Figure 19] FIG. 19 is a cross-sectional view taken along line XIX-XIX shown in FIG. [Figure 20] FIG. 20 is an enlarged view of the area XX shown in FIG. [Figure 21] FIG. 21 is an enlarged view of region XXI shown in FIG. [Figure 22] FIG. 22 is a graph showing the components of the SiC semiconductor layer shown in FIG. [Diagram 23] FIG. 23 is a perspective view showing a 4H—SiC crystal structure used in the manufacture of the SiC semiconductor device shown in FIG. [Figure 24A] 24A is a cross-sectional perspective view of a partial region of the 4H—SiC crystal structure shown in FIG. 23, for illustrating one example of a method for manufacturing the SiC semiconductor device shown in FIG. [Figure 24B] FIG. 24B is a cross-sectional perspective view showing a step subsequent to that of FIG. 24A. [Figure 24C] FIG. 24C is a cross-sectional perspective view showing a step subsequent to that of FIG. 24B. [Figure 24D] FIG. 24D is a cross-sectional perspective view showing a step subsequent to that of FIG. 24C. [Figure 24E] FIG. 24E is a cross-sectional perspective view showing a step subsequent to FIG. 24D. [Figure 24F] FIG. 24F is a cross-sectional perspective view showing a step subsequent to that of FIG. 24E. [Figure 24G] FIG. 24G is a cross-sectional perspective view showing a step subsequent to that of FIG. 24F. [Fig. 24H] FIG. 24H is a cross-sectional perspective view showing a step subsequent to that of FIG. 24G. [Figure 24I] FIG. 24I is a cross-sectional perspective view showing a step subsequent to that of FIG. 24H. [Figure 24J] FIG. 24J is a cross-sectional perspective view showing a step subsequent to that of FIG. 24I. [Figure 24K] FIG. 24K is a cross-sectional perspective view showing a step subsequent to that of FIG. 24J. [Figure 24L] FIG. 24L is a cross-sectional perspective view showing a step subsequent to that of FIG. 24K. [Figure 25A] FIG. 25A is a perspective view showing the 4H—SiC crystal structure shown in FIG. 23, and is a perspective view for explaining an example of the cleavage step of FIG. 24K. [Figure 25B] FIG. 25B is a perspective view showing a step subsequent to that of FIG. 25A. [Figure 25C] FIG. 25C is a perspective view showing a step subsequent to that of FIG. 25B. [Figure 25D] FIG. 25D is a perspective view showing a step subsequent to that of FIG. 25C. [Figure 26] FIG. 26 is a plan view for explaining the planar shape of an SiC semiconductor device that has been singulated through the manufacturing method for an SiC semiconductor device according to a reference example. [Figure 27] FIG. 27 is a plan view for illustrating the planar shape of the SiC semiconductor device shown in FIG. 17 which has been divided into individual pieces through the manufacturing method of FIGS. 24A to 24L. [Figure 28] FIG. 28 is a cross-sectional view of a region corresponding to FIG. 19, showing a schematic configuration of a SiC semiconductor device according to a twelfth embodiment of the present invention. [Figure 29] FIG. 29 is a cross-sectional view of a region corresponding to FIG. 19, showing a schematic configuration of a SiC semiconductor device according to a thirteenth embodiment of the present invention. [Diagram 30]FIG. 30 is a cross-sectional view of a region corresponding to FIG. 19, showing a schematic configuration of a SiC semiconductor device according to a fourteenth embodiment of the present invention. [Diagram 31] FIG. 31 is a cross-sectional view of a region corresponding to FIG. 19, showing a schematic configuration of a SiC semiconductor device according to a fifteenth embodiment of the present invention. [Diagram 32] FIG. 32 is a cross-sectional view of a region corresponding to FIG. 19, showing a schematic configuration of a SiC semiconductor device according to a sixteenth embodiment of the present invention. [Diagram 33] FIG. 33 is a cross-sectional view of a region corresponding to FIG. 19, showing a schematic configuration of a SiC semiconductor device according to a seventeenth embodiment of the present invention. [Diagram 34] FIG. 34 is a cross-sectional view of a region corresponding to FIG. 19, showing a schematic configuration of a SiC semiconductor device according to an eighteenth embodiment of the present invention. [Diagram 35] FIG. 35 is a cross-sectional view of a region corresponding to FIG. 19, showing a schematic configuration of a SiC semiconductor device according to a nineteenth embodiment of the present invention. [Diagram 36] FIG. 36 is a top view showing a SiC semiconductor device according to the twentieth embodiment of the present invention. [Figure 37] FIG. 37 is a top view showing the SiC semiconductor device shown in FIG. 36 with the resin layer removed. [Figure 38] FIG. 38 is an enlarged view of a region XXXVIII shown in FIG. 37, and is a view for explaining the structure of the first main surface of the SiC semiconductor layer. [Figure 39] FIG. 39 is a cross-sectional view taken along line XXXIX-XXXIX shown in FIG. [Diagram 40] FIG. 40 is a cross-sectional view taken along the line XL-XL shown in FIG. [Diagram 41] FIG. 41 is an enlarged view of region XLI shown in FIG. [Diagram 42] FIG. 42 is a cross-sectional view taken along the line XLII-XLII shown in FIG. [Diagram 43] FIG. 43 is an enlarged view of region XLIII shown in FIG. [Diagram 44] FIG. 44 is an enlarged view of region XLIV shown in FIG. [Diagram 45] FIG. 45 is an enlarged view of a region corresponding to FIG. 44, showing a SiC semiconductor device according to the twenty-first embodiment of the present invention. [Figure 46] FIG. 46 is an enlarged view of a region corresponding to FIG. 44, showing a SiC semiconductor device according to the twenty-second embodiment of the present invention. [Figure 47] FIG. 47 is an enlarged view of a region corresponding to FIG. 44, showing a SiC semiconductor device according to the twenty-third embodiment of the present invention. [Figure 48] FIG. 48 is an enlarged view of a region corresponding to FIG. 44, showing a SiC semiconductor device according to the twenty-fourth embodiment of the present invention. [Figure 49] FIG. 49 is an enlarged view of a region corresponding to FIG. 44, showing a SiC semiconductor device according to the twenty-fifth embodiment of the present invention. [Figure 50] FIG. 50 is an enlarged view of a region corresponding to FIG. 44, showing a SiC semiconductor device according to the twenty-sixth embodiment of the present invention. [Figure 51] FIG. 51 is an enlarged view of a region corresponding to FIG. 44, showing a SiC semiconductor device according to the twenty-seventh embodiment of the present invention. [Figure 52] FIG. 52 is a cross-sectional view of a region corresponding to FIG. 44, showing a SiC semiconductor device according to the twenty-eighth embodiment of the present invention. [Figure 53] FIG. 53 is a cross-sectional view of a region corresponding to FIG. 44, showing a SiC semiconductor device according to the twenty-ninth embodiment of the present invention. [Figure 54] FIG. 54 is a cross-sectional view of a region corresponding to FIG. 44, showing a SiC semiconductor device according to the 30th embodiment of the present invention. [Figure 55] FIG. 55 is a cross-sectional view of a region corresponding to FIG. 42, showing the SiC semiconductor device according to the thirty-first embodiment of the present invention. [Figure 56]FIG. 56 is a cross-sectional view of a region corresponding to FIG. 42, showing a SiC semiconductor device according to the thirty-second embodiment of the present invention. [Figure 57] FIG. 57 is a cross-sectional view of a region corresponding to FIG. 42, showing a SiC semiconductor device according to the thirty-third embodiment of the present invention. [Figure 58] FIG. 58 is an enlarged view of a region corresponding to FIG. 38, showing a SiC semiconductor device according to the thirty-fourth embodiment of the present invention. [Figure 59] FIG. 59 is a cross-sectional view taken along the line LIX-LIX shown in FIG. [Figure 60] FIG. 60 is an enlarged view of a region corresponding to FIG. 38, showing a SiC semiconductor device according to the thirty-fifth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] In an embodiment of the present invention, a crystal structure made of hexagonal crystals is applied. The crystal structure made of hexagonal crystals may include a material species having a thermal conductivity of 0.35 W / cmK or more and 25 W / cmK or less. The crystal structure made of hexagonal crystals may include a material species having a thermal conductivity of more than 2.5 W / cmK.

[0028] As the crystal structure made of hexagonal crystals, various materials that form hexagonal crystals, such as sapphire (Al2O3), gallium nitride (GaN), silicon carbide (SiC), diamond (C), etc., are applied.

[0029] The thermal conductivity of the materials increases in the order of sapphire (Al2O3), gallium nitride (GaN), silicon carbide (SiC), and diamond (C). The thermal conductivity of sapphire (Al2O3) is between 0.35W / cmK and 0.45W / cmK (more specifically, about 0.4W / cmK). The thermal conductivity of gallium nitride (GaN) is between 1.5W / cmK and 2.5W / cmK (more specifically, about 2.0W / cmK).

[0030] The thermal conductivity of silicon carbide (SiC) is between 4.5W / cmK and 5.5W / cmK (more specifically, about 4.9W / cmK). The thermal conductivity of diamond (C) is between 10W / cmK and 25W / cmK (more specifically, about 22W / cmK).

[0031] In the embodiment of the present invention, an example in which a SiC crystal structure made of hexagonal crystal is applied will be described as an example of a crystal structure made of hexagonal crystal. A SiC single crystal made of hexagonal crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, and 6H-SiC single crystal according to the period of the atomic arrangement. In the embodiment of the present invention, an example in which a 4H-SiC single crystal is applied will be described, but other polytypes and other material species constituting a hexagonal crystal are not excluded from the present invention.

[0032] The crystal structure of the 4H-SiC single crystal will be described below with reference to Figures 1 and 2. Figure 1 is a diagram showing a unit cell of a 4H-SiC single crystal (hereinafter simply referred to as a "unit cell") applied to an embodiment of the present invention. Figure 2 is a plan view showing the silicon surface of the unit cell shown in Figure 1.

[0033] 1 and 2, the unit cell includes a tetrahedral structure in which one Si atom and four C atoms are bonded in a tetrahedral arrangement (regular tetrahedral arrangement). The unit cell has an atomic arrangement in which the tetrahedral structures are stacked in a four-layer period. The unit cell has a hexagonal prism structure having regular hexagonal silicon faces, regular hexagonal carbon faces, and six side faces connecting the silicon faces and the carbon faces.

[0034] A silicon surface is a surface terminated by silicon atoms, with one silicon atom located at each of the six vertices of a regular hexagon and one silicon atom located at the center of the regular hexagon.

[0035] A carbon face is a terminal face terminated by C atoms, with one C atom located at each of the six vertices of a regular hexagon and one C atom located at the center of the regular hexagon.

[0036] The crystal plane of the unit cell is defined by four coordinate axes (a1, a2, a3, c) including the a1 axis, a2 axis, a3 axis, and c axis. The value of a3 among the four coordinate axes is -(a1+a2). Below, the crystal plane of a 4H-SiC single crystal is explained based on the silicon plane as an example of a hexagonal crystal termination plane.

[0037] The a1, a2 and a3 axes are set along the arrangement direction of the nearest Si atoms (hereinafter simply referred to as the "nearest atom direction") with respect to the Si atom located at the center in a plan view of the silicon surface seen from the c-axis. The a1, a2 and a3 axes are set at angles shifted by 120° each, following the arrangement of the Si atoms.

[0038] The c-axis is set in the normal direction of the silicon surface based on the Si atom located at the center. The silicon surface is the (0001) surface. The carbon surface is the (000-1) surface. The side surface of the hexagonal prism includes six crystal planes aligned along the nearest atom direction in a plan view of the silicon surface from the c-axis. More specifically, the side surface of the hexagonal prism includes six crystal planes formed by the nearest Si atoms.

[0039] The side surface of the hexagonal prism includes, in a plan view of the silicon surface seen from the c-axis, the (1-100), (0-110), (-1010), (-1100), (01-10), and (10-10) planes clockwise from the tip of the a1 axis.

[0040] In a hexagonal prism, a diagonal that does not pass through the center includes six crystal planes along a cross direction that crosses the nearest-neighbor atom direction in a plan view of the silicon surface from the c-axis (hereinafter, simply referred to as the "cross direction of the nearest-neighbor atom direction"). When viewed from the Si atom located at the center, the cross direction of the nearest-neighbor atom direction is an orthogonal direction that is perpendicular to the nearest-neighbor atom direction. More specifically, a diagonal that does not pass through the center in a hexagonal prism includes six crystal planes formed by Si atoms that are not nearest neighbors.

[0041] In a hexagonal prism, diagonals that do not pass through the center include the (11-20), (1-210), (-2110), (-1-120), (-12-10), and (2-1-10) planes in a plan view of the silicon surface from the c-axis.

[0042] The crystal directions of the unit cell are defined by the normal directions of the crystal planes. The normal direction of the (1-100) plane is the [1-100] direction. The normal direction of the (0-110) plane is the [0-110] direction. The normal direction of the (-1010) plane is the [-1010] direction. The normal direction of the (-1100) plane is the [-1100] direction. The normal direction of the (01-10) plane is the [01-10] direction. The normal direction of the (10-10) plane is the [10-10] direction.

[0043] The normal direction of the (11-20) plane is the [11-20] direction. The normal direction of the (1-210) plane is the [1-210] direction. The normal direction of the (-2110) plane is the [-2110] direction. The normal direction of the (-1-120) plane is the [-1-120] direction. The normal direction of the (-12-10) plane is the [-12-10] direction. The normal direction of the (2-1-10) plane is the [2-1-10] direction.

[0044] Hexagonal crystals have six-fold symmetry, and there are equivalent crystal planes and equivalent crystal directions every 60°. For example, the (1-100), (0-110), (-1010), (-1100), (01-10), and (10-10) planes form equivalent crystal planes. In addition, the (11-20), (1-210), (-2110), (-1-120), (-12-10), and (2-1-10) planes form equivalent crystal planes.

[0045] Additionally, the [1-100], [0-110], [-1010], [-1100], [01-10], and [10-10] directions form equivalent crystal directions, while the [11-20], [1-210], [-2110], [-1-120], [-12-10], and [2-1-10] directions form equivalent crystal directions.

[0046] The c-axis is in the

[0001] direction ([000-1] direction). The a1-axis is in the [2-1-10] direction ([-2110] direction). The a2-axis is in the [-12-10] direction ([1-210] direction). The a3-axis is in the [-1-120] direction ([11-20] direction).

[0047] The

[0001] and [000-1] directions are sometimes simply referred to as c-axes. The (0001) and (000-1) planes are sometimes simply referred to as c-planes. The [11-20] and [-1-120] directions are sometimes simply referred to as a-axes. The (11-20) and (-1-120) planes are sometimes simply referred to as a-planes. The [1-100] and [-1100] directions are sometimes simply referred to as m-axes. The (1-100) and (-1100) planes are sometimes simply referred to as m-planes.

[0048] FIG. 3 is a perspective view showing a 4H—SiC crystal structure 1 including a 4H—SiC single crystal.

[0049] In this embodiment, the 4H—SiC crystal structure 1 is formed in a plate or disk shape. The 4H—SiC crystal structure 1 may be formed in a circular (disk) shape.

[0050] The thickness of the 4H—SiC crystal structure 1 may be 1 μm or more and 1000 μm or less. The thickness of the 4H—SiC crystal structure 1 may be 1 μm or more and 50 μm or less, 50 μm or more and 150 μm or less, 150 μm or more and 250 μm or less, 250 μm or more and 400 μm or less, 400 μm or more and 600 μm or less, 600 μm or more and 800 μm or less, or 800 μm or more and 1000 μm or less.

[0051] The 4H-SiC crystal structure 1 has a first main surface 2 on one side, a second main surface 3 on the other side, and a side surface 4 connecting the first main surface 2 and the second main surface 3. The first main surface 2 and the second main surface 3 of the 4H-SiC crystal structure 1 may have an off angle θ inclined at an angle of 10° or less in the [11-20] direction with respect to the (0001) plane. The off angle θ is also the angle between the normal direction N to the first main surface 2 and the second main surface 3 and the c-axis of the 4H-SiC crystal structure 1.

[0052] The off angle θ may be 0° or more and 4° or less. When the off angle θ is 0°, the normal direction N and the c-axis are aligned. The off angle θ may be more than 0° and less than 4°. The off angle θ is typically set to 2° or 4°, more specifically, in the range of 2°±10% or 4°±10%.

[0053] An orientation flat 5, which is an example of a mark indicating a crystal orientation, is formed on a side surface 4 of the 4H-SiC crystal structure 1. The orientation flat 5 is a notch formed on the side surface 4 of the 4H-SiC crystal structure 1. In this embodiment, the orientation flat 5 extends linearly along the [11-20] direction.

[0054] A plurality of (for example, two) orientation flats indicating crystal orientation may be formed on the side surface 4 of the 4H-SiC crystal structure 1. In this case, a first orientation flat and a second orientation flat may be formed on the side surface 4 of the 4H-SiC crystal structure 1. The first orientation flat may be a notch extending linearly along the [11-20] direction. The second orientation flat may be a notch extending linearly along the [1-100] direction.

[0055] Instead of the orientation flat 5, the side surface 4 of the 4H-SiC crystal structure 1 may have an orientation notch formed as a recess recessed toward the center of the 4H-SiC crystal structure 1.

[0056] The 4H—SiC crystal structure 1 includes a first corner 6 connecting the first main surface 2 and the side surface 4, and a second corner 7 connecting the second main surface 3 and the side surface 4. The first corner 6 has a first chamfered portion 8 sloping downward from the first main surface 2 toward the side surface 4. The second corner 7 has a second chamfered portion 9 sloping downward from the second main surface 3 toward the side surface 4.

[0057] The first chamfered portion 8 may be formed in a convex curved shape. The second chamfered portion 9 may be formed in a convex curved shape. The first chamfered portion 8 and the second chamfered portion 9 suppress cracks in the 4H—SiC crystal structure 1.

[0058] FIG. 4 is a plan view showing a state in which the 4H—SiC crystal structure 1 is fractured.

[0059] The 4H-SiC crystal structure 1 has different physical properties depending on the crystal plane and the crystal direction. For example, the 4H-SiC crystal structure 1 has the physical property that it is easily broken along the nearest atom direction and is not easily broken along the intersecting direction of the nearest atom direction. More specifically, the intersecting direction of the nearest atom direction is an orthogonal direction perpendicular to the nearest atom direction.

[0060] Referring to FIG. 4, for example, when an external force is applied to the center of 4H—SiC crystal structure 1 to break 4H—SiC crystal structure 1, 4H—SiC crystal structure 1 is broken along six directions with the center of first main surface 2 as the reference.

[0061] More specifically, the 4H—SiC crystal structure 1 is broken along the [11-20] direction, the [−12-10] direction and the [−2110] direction, all of which are nearest-neighbor atomic directions.

[0062] The 4H-SiC crystal structure 1 is difficult to break along the direction perpendicular to the [11-20] direction, the direction perpendicular to the [-12-10] direction, and the direction perpendicular to the [-2110] direction. That is, the 4H-SiC crystal structure 1 is difficult to break along the [-1100] direction, the [10-10] direction, and the [01-10] direction. The [-1100] direction, the [10-10] direction, and the [01-10] direction are all intersecting directions of the nearest atomic directions.

[0063] The following describes a processing method performed on the 4H—SiC crystal structure 1. The following processing method can also be applied to a manufacturing method for a SiC semiconductor device.

[0064] 5A to 5D are cross-sectional perspective views of a partial region of the 4H—SiC crystal structure 1 shown in FIG. 3, illustrating the SiC processing method in accordance with the first embodiment of the present invention.

[0065] First, referring to FIG. 5A, a 4H—SiC crystal structure 1 is prepared as an example of a SiC processing target.

[0066] 5B, a processed region 10 selectively set on the first main surface 2 of the 4H—SiC crystal structure 1 is heated to form a modified layer 11 in which the SiC is modified to have other properties. In this process, the modified layer 11 is formed in a strip shape extending along an arbitrary direction.

[0067] The heating of the processing area 10 may be performed by an ablation processing method using laser irradiation. In the ablation processing method, an ultraviolet laser may be used. The laser energy, the laser pulse duty ratio, and the laser irradiation speed are each set to any value depending on the size, shape, thickness, etc. of the modified layer 11 to be formed.

[0068] In the ablation processing method, a depression 12 is formed in a surface layer portion of the first main surface 2, depression 12 being depressed from the first main surface 2 toward the second main surface 3. The depression 12 includes a bottom portion and a side portion. The depression 12 may be formed in a tapered shape in which the opening width narrows from the first main surface 2 toward the bottom portion. The bottom portion of the depression 12 may be formed in a curved shape toward the second main surface 3.

[0069] The recess 12 includes an opening side corner and a bottom side corner. The opening side corner of the recess 12 connects the first main surface 2 and a side of the recess 12. The bottom side corner of the recess 12 connects the bottom and a side of the recess 12.

[0070] The width W of the depression 12 may be more than 0 μm and not more than 10 μm. The width W of the depression 12 is the width in a direction perpendicular to the direction in which the depression 12 extends. The width W of the depression 12 may be more than 0 μm and not more than 2.5 μm, 2.5 μm or more and not more than 5 μm, 5 μm or more and not more than 7.5 μm, or 7.5 μm or more and not more than 10 μm. When the thickness of the 4H—SiC crystal structure 1 is 150 μm or less, the width W of the depression 12 is preferably more than 0 μm and not more than 5 μm.

[0071] The depth D of the depression 12 may be more than 0 μm and not more than 30 μm. The depth D of the depression 12 is the distance from the first main surface 2 to the bottom of the depression 12 in the normal direction N. The depth D of the depression 12 may be more than 0 μm and not more than 5 μm, 5 μm or more to 10 μm or less, 10 μm or more to 15 μm or less, 15 μm or more to 20 μm or less, 20 μm or more to 25 μm or less, or 25 μm or more to 30 μm or less. When the thickness of the 4H—SiC crystal structure 1 is 150 μm or less, the depth D of the depression 12 is preferably more than 0 μm and not more than 15 μm.

[0072] The modified layer 11 is formed in the form of a film along the inner wall of the depression 12. The thickness of the portion of the modified layer 11 covering the bottom wall of the depression 12 may be greater than the thickness of the portion of the modified layer 11 covering the side wall of the depression 12. The modified layer 11 may be formed along the inner wall of the depression 12 with a uniform thickness.

[0073] The modified layer 11 defines a recess 13 within the depression 12. More specifically, the recess 13 is defined by the outer surface of the modified layer 11. The recess 13 includes a bottom and a side. The recess 13 may be formed in a tapered shape in which the opening width narrows from the first main surface 2 toward the bottom. The bottom of the recess 13 may be formed in a curved shape toward the second main surface 3.

[0074] Recess 13 includes an opening side corner and a bottom side corner. The opening side corner of recess 13 connects first main surface 2 of 4H—SiC crystal structure 1 and a side of recess 13. The bottom side corner of recess 13 connects the bottom and side of recess 13.

[0075] The width WR of the recess 13 is less than the width W of the indentation 12. The width WR of the recess 13 may be more than 0 μm and less than 10 μm. The width WR of the recess 13 may be more than 0 μm and less than 2.5 μm, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, or 7.5 μm or more and less than 10 μm. When the thickness of the 4H—SiC crystal structure 1 is 150 μm or less, the width WR of the recess 13 is preferably more than 0 μm and less than 5 μm.

[0076] The depth DR of the recess 13 is less than the depth D of the dent 12. The depth DR of the recess 13 may be more than 0 μm and less than 30 μm. The depth DR of the recess 13 may be more than 0 μm and less than 5 μm, 5 μm or more and less than 10 μm, 10 μm or more and less than 15 μm, 15 μm or more and less than 20 μm, 20 μm or more and less than 25 μm, or 25 μm or more and less than 30 μm. When the thickness of the 4H—SiC crystal structure 1 is 150 μm or less, the depth DR of the recess 13 is preferably more than 0 μm and less than 15 μm.

[0077] Next, referring to FIG. 5C, the corners of the modified layer 11 are rounded. More specifically, the outer surface of the modified layer 11 is planarized by removing unevenness from the outer surface of the modified layer 11. A part of the modified layer 11 may be removed by an etching method. The etching method may be a dry etching method or a wet etching method. Here, a part of the modified layer 11 is removed by a plasma etching method as an example of a dry etching method.

[0078] The modified layer 11 has a component different from that of the 4H-SiC crystal structure 1. The etching rate (etching selectivity) for the modified layer 11 is different from the etching rate (etching selectivity) for SiC. Therefore, a part of the modified layer 11 can be appropriately removed while leaving the 4H-SiC crystal structure 1. As a result, the opening side corners of the recess 13 are rounded inwardly of the recess 13. Also, the bottom side corners of the recess 13 are rounded inwardly of the recess 13.

[0079] The recess 13 with rounded opening corners can reduce stress concentration on the modified layer 11 at the opening corners. Also, the recess 13 with rounded bottom corners can reduce stress concentration on the modified layer 11 at the bottom corners. This can suppress undesirable cracks caused by stress on the modified layer 11.

[0080] 5D, the 4H—SiC crystal structure 1 may be cleaved starting from the processed region 10. More specifically, the 4H—SiC crystal structure 1 may be cleaved starting from the depression 12. The 4H—SiC crystal structure 1 may be cleaved by applying stress to the depression 12. In this step, a step of applying thermal stress to the depression 12 by heating and cooling is performed.

[0081] The heating process of the depression 12 may be performed by a laser irradiation method. The laser irradiation method may be performed by an infrared laser (for example, a CO2 laser). The heating process of the depression 12 thermally induces a compressive stress starting from the depression 12. The laser energy, the laser pulse duty ratio, and the laser irradiation speed are each set to any value according to the magnitude of the stress to be applied to the depression 12.

[0082] The step of cooling the recess 12 may include a step of supplying a cooling fluid to the recess 12. The cooling fluid may include water or air, or a mixture of water and air (aerosol). The step of cooling the recess 12 thermally induces a tensile stress originating from the recess 12.

[0083] The step of supplying the cooling fluid may include a step of injecting (spraying) the cooling fluid by a coolant jet method or a cooling gas supply method. The step of cooling the depression 12 may be performed after the step of heating the depression 12, or may be performed simultaneously with the step of heating the depression 12. The compressive stress generated in the step of heating the depression 12 and the tensile stress generated in the step of cooling the depression 12 cause the 4H—SiC crystal structure 1 to be cleaved along the depression 12.

[0084] After cleavage, 4H—SiC crystal structure 1 has cleavage surface 14. Cleavage surface 14 is continuous with inclined portion 15 consisting of a remaining portion of depression 12. A part of modified layer 11 is exposed at a corner connecting first main surface 2 of 4H—SiC crystal structure 1 and cleavage surface 14. Modified layer 11 is formed along inclined portion 15.

[0085] Fig. 6 is a cross-sectional view showing modified layer 11 formed in the step of Fig. 5B. Fig. 7 is a graph showing the configuration of modified layer 11. Fig. 7 shows the results of examining the components of 4H—SiC crystal structure 1 by Raman spectroscopy.

[0086] FIG. 6 shows a first region A, a second region B and a third region C. The first region A shows a surface portion of the modified layer 11. The surface portion of the modified layer 11 is a region located on the first main surface 2 side of the 4H—SiC crystal structure 1. The second region B shows a bottom portion of the modified layer 11. The bottom portion of the modified layer 11 is a region located on the second main surface 3 side of the 4H—SiC crystal structure 1 with respect to the surface portion of the modified layer 11. The third region C shows a region of the 4H—SiC crystal structure 1 outside the modified layer 11.

[0087] Fig. 7 shows a first curve LA, a second curve LB, and a third curve LC. The first curve LA shows the component of the first region A shown in Fig. 6. The second curve LB shows the component of the second region B shown in Fig. 6. The third curve LC shows the component of the third region C shown in Fig. 6.

[0088] The first curve LA has a peak value derived from Si (silicon) in the wavelength range of 500 nm to 550 nm, and the second curve LB has a peak value derived from Si (silicon) in the wavelength range of 500 nm to 550 nm, and a peak value derived from C (carbon) in the wavelength range of 1300 nm to 1700 nm.

[0089] The third curve LC has a peak value derived from SiC (silicon carbide) in the wavelength range of 750 nm or more and 800 nm or less. Therefore, in the third region C, the modified layer 11 is not formed, and only the 4H-SiC single crystal exists.

[0090] With reference to the first curve LA, the silicon density of the surface portion (first region A) of the modified layer 11 is higher than the carbon density of the surface portion of the modified layer 11. That is, the surface portion of the modified layer 11 includes a Si modified layer in which the SiC of the 4H—SiC crystal structure 1 is modified to Si. The Si modified layer may include Si polycrystals. The Si modified layer may include amorphous Si. The Si modified layer may include Si polycrystals and amorphous Si. The Si modified layer may include a Si amorphous layer as a main component.

[0091] With reference to the second curve LB, the silicon density at the bottom (second region B) of the modified layer 11 is higher than the carbon density at the bottom of the modified layer 11. The bottom of the modified layer 11 includes a Si modified layer in which the SiC of the 4H—SiC crystal structure 1 is modified to Si. The Si modified layer may include Si polycrystals. The Si modified layer may include amorphous Si. The Si modified layer may include Si polycrystals and amorphous Si. The Si modified layer may include a Si amorphous layer as a main component.

[0092] With reference to the first curve LA and the second curve LB, the modified layer 11 has different components in the surface portion (first region A) and the bottom portion (second region B). More specifically, the modified layer 11 has different silicon densities along the thickness direction. The silicon density of the bottom portion of the modified layer 11 is lower than the silicon density of the surface portion of the modified layer 11. In addition, the modified layer 11 has different carbon densities along the thickness direction. The carbon density of the bottom portion of the modified layer 11 is higher than the carbon density of the surface portion of the modified layer 11.

[0093] From the results of the first curve LA to the third curve LC, it can be seen that the process of forming the modified layer 11 includes a process of heating the processed region 10 to a temperature at which C atoms are desorbed or sublimated from SiC. As a result, the modified layer 11 is formed on the first main surface 2 of the 4H—SiC crystal structure 1.

[0094] As described above, according to this SiC processing method, the outer surface of the 4H—SiC crystal structure 1 can be processed by the step of forming the modified layer 11 and the step of removing the modified layer 11. In addition, the 4H—SiC crystal structure 1 can be cleaved by utilizing the depressions 12 in the modified layer 11.

[0095] In particular, the recess 13 having rounded opening side corners can alleviate stress concentration on the modified layer 11 at the opening side corners. Also, the recess 13 having rounded bottom side corners can alleviate stress concentration on the modified layer 11 at the bottom side corners. This can suppress undesirable cracks caused by stress on the modified layer 11.

[0096] 8A to 8D are cross-sectional perspective views illustrating a partial region of the 4H—SiC crystal structure 1 shown in Fig. 3, for explaining a SiC processing method according to a second embodiment of the present invention. In the following, explanations of structures and manufacturing steps corresponding to those explained in Fig. 5A to 5D will be omitted.

[0097] First, with reference to FIG. 8A, a 4H—SiC crystal structure 1 is prepared as an example of a SiC processing target.

[0098] Next, referring to Fig. 8B, a modified layer 11, a depression 12, and a recess 13 are formed in a processing region 10 selectively set on the first main surface 2. The modified layer 11, the depression 12, and the recess 13 are formed through a process similar to that shown in Fig. 5B described above.

[0099] Next, referring to Fig. 8C, the modified layer 11 is entirely removed while leaving the 4H-SiC crystal structure 1. The modified layer 11 is removed through a process similar to that shown in Fig. 5C described above. As a result, a depression 12 defined by the 4H-SiC crystal structure 1 remains in the first main surface 2.

[0100] In this process, the opening side corners of the depression 12 are rounded in a curved shape toward the inside of the depression 12. In addition, the bottom side corners of the depression 12 are rounded in a curved shape toward the outside of the depression 12. The depression 12 with rounded opening side corners can alleviate stress concentration on the depression 12 at the opening side corners. In addition, the depression 12 with rounded bottom side corners can alleviate stress concentration on the depression 12 at the bottom side corners. This can suppress undesirable cracks caused by stress on the depression 12.

[0101] Next, referring to Fig. 8D, the 4H-SiC crystal structure 1 may be cleaved starting from the depression 12. The 4H-SiC crystal structure 1 may be cleaved through a process similar to that of Fig. 5D described above. The 4H-SiC crystal structure 1 after cleavage has a cleavage surface 14. The cleavage surface 14 is continuous with an inclined portion 15 consisting of a remaining portion of the depression 12.

[0102] As described above, according to this SiC processing method, the outer surface of the 4H-SiC crystal structure 1 can be processed by the step of forming the modified layer 11 and the step of removing the modified layer 11. In addition, the 4H-SiC crystal structure 1 can be cleaved by utilizing the depression 12 formed in the outer surface of the 4H-SiC crystal structure 1 through the step of removing the modified layer 11.

[0103] In particular, recess 12 having rounded opening side corners can alleviate stress concentration on recess 12 at the opening side corners. Also, recess 12 having rounded bottom side corners can alleviate stress concentration on recess 12 at the bottom side corners. This can suppress undesirable cracks caused by stress on recess 12.

[0104] 9A to 9D are cross-sectional perspective views illustrating a partial region of the 4H—SiC crystal structure 1 shown in Fig. 3, for explaining a SiC processing method according to a third embodiment of the present invention. In the following, explanations of structures and manufacturing steps corresponding to those described in Fig. 5A to 5D will be omitted.

[0105] 9A, a 4H-SiC crystal structure 1 is prepared as an example of a SiC processing target. In this embodiment, the 4H-SiC crystal structure 1 has a layered structure including a SiC semiconductor wafer 16 and a SiC epitaxial layer 17. The SiC epitaxial layer 17 may have an impurity concentration (e.g., n-type impurity concentration) less than the impurity concentration (e.g., n-type impurity concentration) of the SiC semiconductor wafer 16.

[0106] A first main surface 2 of the 4H—SiC crystal structure 1 is formed by a SiC epitaxial layer 17. A second main surface 3 of the 4H—SiC crystal structure 1 is formed by a SiC semiconductor wafer 16. A side surface 4 of the 4H—SiC crystal structure 1 is formed by the SiC semiconductor wafer 16 and the SiC epitaxial layer 17.

[0107] The SiC epitaxial layer 17 is formed by epitaxially growing SiC from the SiC semiconductor wafer 16. The thickness of the SiC epitaxial layer 17 is less than the thickness of the SiC semiconductor wafer 16.

[0108] The thickness of the SiC semiconductor wafer 16 may be 1 μm or more and less than 1000 μm. The thickness of the SiC semiconductor wafer 16 may be 1 μm or more and 50 μm or less, 50 μm or more and 150 μm or less, 150 μm or more and 250 μm or less, 250 μm or more and 400 μm or less, 400 μm or more and 600 μm or less, 600 μm or more and 800 μm or less, or 800 μm or more and 1000 μm or less.

[0109] The thickness of SiC epitaxial layer 17 may be 1 μm or more and 100 μm or less. The thickness of SiC epitaxial layer 17 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, 40 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, or 75 μm or more and 100 μm or less.

[0110] Next, referring to Fig. 9B, a modified layer 11, a depression 12, and a recess 13 are formed in a processing region 10 selectively set on the first main surface 2 of the 4H-SiC crystal structure 1. The modified layer 11, the depression 12, and the recess 13 are formed in the SiC epitaxial layer 17. The modified layer 11, the depression 12, and the recess 13 are formed through the same process as that shown in Fig. 5B described above.

[0111] Next, referring to Fig. 9C, the modified layer 11 is partially removed while leaving the 4H-SiC crystal structure 1, and the outer surface of the modified layer 11 is flattened. The modified layer 11 is removed through a process similar to that of Fig. 5C described above. As a result, the opening side corners of the recess 13 are rounded inwardly of the recess 13. In addition, the bottom side corners of the recess 13 are rounded inwardly of the recess 13.

[0112] The recess 13 with rounded opening corners can reduce stress concentration on the modified layer 11 at the opening corners. Also, the recess 13 with rounded bottom corners can reduce stress concentration on the modified layer 11 at the bottom corners. This can suppress undesirable cracks caused by stress on the modified layer 11.

[0113] Next, referring to Fig. 9D, the 4H-SiC crystal structure 1 may be cleaved starting from the depression 12. The 4H-SiC crystal structure 1 may be cleaved through a process similar to that of Fig. 5D described above. When the impurity concentration of the SiC semiconductor wafer 16 is higher than that of the SiC epitaxial layer 17, the attenuation rate of the laser light for the SiC semiconductor wafer 16 is higher than that for the SiC epitaxial layer 17.

[0114] Therefore, by irradiating the laser light so as to reach the SiC semiconductor wafer 16, the SiC semiconductor wafer 16 can be efficiently heated. This makes it possible to increase the compressive stress generated in the heating process of the recess 12 and the tensile stress generated in the cooling process of the recess 12. As a result, the cleavage force applied to the 4H—SiC crystal structure 1 can be increased.

[0115] After cleavage, 4H—SiC crystal structure 1 has cleavage surface 14. Cleavage surface 14 is continuous with inclined portion 15 consisting of a remaining portion of depression 12. A part of modified layer 11 is exposed at a corner connecting first main surface 2 of 4H—SiC crystal structure 1 and cleavage surface 14. Modified layer 11 is formed along inclined portion 15.

[0116] As described above, according to this SiC processing method, the outer surface of the SiC epitaxial layer 17 can be processed by the step of forming the modified layer 11 and the step of removing the modified layer 11. In addition, the 4H—SiC crystal structure 1 can also be cleaved by utilizing the recess 12.

[0117] In particular, the recess 13 having rounded opening side corners can alleviate stress concentration on the modified layer 11 at the opening side corners. Also, the recess 13 having rounded bottom side corners can alleviate stress concentration on the modified layer 11 at the bottom side corners. This can suppress undesirable cracks caused by stress on the modified layer 11.

[0118] 10A to 10D are cross-sectional perspective views illustrating a partial region of the 4H—SiC crystal structure 1 shown in FIG. 3, for explaining a SiC processing method according to a fourth embodiment of the present invention. In the following, explanations of structures and manufacturing steps corresponding to those explained in FIG. 5A to 5D will be omitted.

[0119] 10A, a 4H-SiC crystal structure 1 is prepared as an example of a SiC processing target. In this embodiment, the 4H-SiC crystal structure 1 has a layered structure including a SiC semiconductor wafer 16 and a SiC epitaxial layer 17. The SiC epitaxial layer 17 may have an impurity concentration (e.g., n-type impurity concentration) less than the impurity concentration (e.g., n-type impurity concentration) of the SiC semiconductor wafer 16.

[0120] A first main surface 2 of the 4H—SiC crystal structure 1 is formed by a SiC epitaxial layer 17. A second main surface 3 of the 4H—SiC crystal structure 1 is formed by a SiC semiconductor wafer 16. A side surface 4 of the 4H—SiC crystal structure 1 is formed by the SiC semiconductor wafer 16 and the SiC epitaxial layer 17.

[0121] The SiC epitaxial layer 17 is formed by epitaxially growing SiC from the SiC semiconductor wafer 16. The thickness of the SiC epitaxial layer 17 is less than the thickness of the SiC semiconductor wafer 16.

[0122] The thickness of the SiC semiconductor wafer 16 may be 1 μm or more and less than 1000 μm. The thickness of the SiC semiconductor wafer 16 may be 1 μm or more and 50 μm or less, 50 μm or more and 150 μm or less, 150 μm or more and 250 μm or less, 250 μm or more and 400 μm or less, 400 μm or more and 600 μm or less, 600 μm or more and 800 μm or less, or 800 μm or more and 1000 μm or less.

[0123] The thickness of SiC epitaxial layer 17 may be 1 μm or more and 100 μm or less. The thickness of SiC epitaxial layer 17 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, 40 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, or 75 μm or more and 100 μm or less.

[0124] 10B, modified layer 11, depression 12, and recess 13 are formed in processed region 10 selectively set on first main surface 2 of 4H—SiC crystal structure 1. Modified layer 11, depression 12, and recess 13 are formed in SiC epitaxial layer 17. Modified layer 11, depression 12, and recess 13 are formed through the same process as that shown in FIG. 5B described above.

[0125] Next, referring to Fig. 10C, the modified layer 11 is entirely removed while leaving the 4H-SiC crystal structure 1. The modified layer 11 is removed through a process similar to that of Fig. 5C described above. As a result, a depression 12 defined by the 4H-SiC crystal structure 1 remains on the first main surface 2. In this process, the opening side corners of the depression 12 are rounded inwardly of the depression 12. In addition, the bottom side corners of the depression 12 are rounded inwardly of the depression 12.

[0126] The recess 12 having rounded opening side corners can alleviate stress concentration on the opening side corners of the recess 12. Also, the recess 12 having rounded bottom side corners can alleviate stress concentration on the bottom side corners of the recess 12. This can suppress undesirable cracks caused by stress on the recess 12.

[0127] 10D, the 4H—SiC crystal structure 1 may be cleaved starting from the depression 12. The 4H—SiC crystal structure 1 may be cleaved through a process similar to that of FIG. 5D described above. When the impurity concentration of the SiC semiconductor wafer 16 is higher than that of the SiC epitaxial layer 17, the attenuation rate of the laser light for the SiC semiconductor wafer 16 is higher than that for the SiC epitaxial layer 17.

[0128] Therefore, by irradiating the laser light so as to reach the SiC semiconductor wafer 16, it is possible to efficiently heat the SiC semiconductor wafer 16. This makes it possible to increase the compressive stress generated in the heating step of the recess 12 and the tensile stress generated in the cooling step of the recess 12.

[0129] This makes it possible to increase the cleavage force applied to the 4H—SiC crystal structure 1. After cleavage, the 4H—SiC crystal structure 1 has a cleavage surface 14. The cleavage surface 14 is continuous with an inclined portion 15 consisting of the remaining portion of the depression 12.

[0130] As described above, according to this SiC processing method, the outer surface of the SiC epitaxial layer 17 can be processed by the step of forming the modified layer 11 and the step of removing the modified layer 11. In addition, the 4H—SiC crystal structure 1 can also be cleaved by utilizing the recess 12.

[0131] In particular, recess 12 having rounded opening side corners can alleviate stress concentration on recess 12 at the opening side corners. Also, recess 12 having rounded bottom side corners can alleviate stress concentration on recess 12 at the bottom side corners. This can suppress undesirable cracks caused by stress on recess 12.

[0132] 11A to 11D are cross-sectional perspective views illustrating a partial region of the 4H—SiC crystal structure 1 shown in Fig. 3, for explaining a SiC processing method according to a fifth embodiment of the present invention. In the following, explanations of structures and manufacturing steps corresponding to those described in Fig. 5A to 5D will be omitted.

[0133] 11A, a 4H-SiC crystal structure 1 is prepared as an example of a SiC processing target. In this embodiment, the 4H-SiC crystal structure 1 has a layered structure including a SiC semiconductor wafer 16 and a SiC epitaxial layer 17. The SiC epitaxial layer 17 may have an impurity concentration (e.g., n-type impurity concentration) less than the impurity concentration (e.g., n-type impurity concentration) of the SiC semiconductor wafer 16.

[0134] A first main surface 2 of the 4H—SiC crystal structure 1 is formed by a SiC epitaxial layer 17. A second main surface 3 of the 4H—SiC crystal structure 1 is formed by a SiC semiconductor wafer 16. A side surface 4 of the 4H—SiC crystal structure 1 is formed by the SiC semiconductor wafer 16 and the SiC epitaxial layer 17.

[0135] The SiC epitaxial layer 17 is formed by epitaxially growing SiC from the SiC semiconductor wafer 16. The thickness of the SiC epitaxial layer 17 is less than the thickness of the SiC semiconductor wafer 16.

[0136] The thickness of the SiC semiconductor wafer 16 may be 1 μm or more and less than 1000 μm. The thickness of the SiC semiconductor wafer 16 may be 1 μm or more and 50 μm or less, 50 μm or more and 150 μm or less, 150 μm or more and 250 μm or less, 250 μm or more and 400 μm or less, 400 μm or more and 600 μm or less, 600 μm or more and 800 μm or less, or 800 μm or more and 1000 μm or less.

[0137] The thickness of SiC epitaxial layer 17 may be 1 μm or more and 100 μm or less. The thickness of SiC epitaxial layer 17 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, 40 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, or 75 μm or more and 100 μm or less.

[0138] 11B, a modified layer 11, a dent 12, and a recess 13 are formed in a processed region 10 selectively set on the first main surface 2 of the 4H—SiC crystal structure 1. The modified layer 11, the dent 12, and the recess 13 are formed through the same steps as those shown in FIG. 5B described above.

[0139] The modified layer 11, the depression 12 and the recess 13 are formed in the SiC epitaxial layer 17. More specifically, the modified layer 11, the depression 12 and the recess 13 are also formed in the SiC semiconductor wafer 16, from the SiC epitaxial layer 17 across the boundary between the SiC semiconductor wafer 16 and the SiC epitaxial layer 17.

[0140] Next, referring to Fig. 11C, the modified layer 11 is partially removed while leaving the 4H-SiC crystal structure 1, and the outer surface of the modified layer 11 is flattened. The modified layer 11 is removed through a process similar to that of Fig. 5C described above. As a result, the opening side corners of the recess 13 are rounded inwardly of the recess 13. In addition, the bottom side corners of the recess 13 are rounded inwardly of the recess 13.

[0141] The recess 13 with rounded opening corners can reduce stress concentration on the modified layer 11 at the opening corners. Also, the recess 13 with rounded bottom corners can reduce stress concentration on the modified layer 11 at the bottom corners. This can suppress undesirable cracks caused by stress on the modified layer 11.

[0142] 11D, the 4H—SiC crystal structure 1 may be cleaved starting from the depression 12. The 4H—SiC crystal structure 1 may be cleaved through a process similar to that of FIG. 5D described above. When the impurity concentration of the SiC semiconductor wafer 16 is higher than that of the SiC epitaxial layer 17, the attenuation rate of the laser light for the SiC semiconductor wafer 16 is higher than that for the SiC epitaxial layer 17.

[0143] Therefore, by irradiating the laser light so as to reach the SiC semiconductor wafer 16, the SiC semiconductor wafer 16 can be efficiently heated. In particular, in this process, the SiC semiconductor wafer 16 can be heated via the modified layer 11 formed in the SiC semiconductor wafer 16.

[0144] This makes it possible to efficiently increase the compressive stress generated in the heating step of the recess 12 and the tensile stress generated in the cooling step of the recess 12. As a result, the cleavage force applied to the 4H—SiC crystal structure 1 can be efficiently increased.

[0145] After cleavage, 4H—SiC crystal structure 1 has cleavage surface 14. Cleavage surface 14 is continuous with inclined portion 15 consisting of a remaining portion of depression 12. A part of modified layer 11 is exposed at a corner connecting first main surface 2 of 4H—SiC crystal structure 1 and cleavage surface 14. Modified layer 11 is formed along inclined portion 15.

[0146] As described above, according to this SiC processing method, the outer surface of the SiC epitaxial layer 17 can be processed by the step of forming the modified layer 11 and the step of removing the modified layer 11. In addition, the 4H—SiC crystal structure 1 can also be cleaved by utilizing the recess 12.

[0147] In particular, the recess 13 having rounded opening side corners can alleviate stress concentration on the modified layer 11 at the opening side corners. Also, the recess 13 having rounded bottom side corners can alleviate stress concentration on the modified layer 11 at the bottom side corners. This can suppress undesirable cracks caused by stress on the modified layer 11.

[0148] 12A to 12D are cross-sectional perspective views illustrating a partial region of the 4H—SiC crystal structure 1 shown in Fig. 3, for explaining a SiC processing method according to a sixth embodiment of the present invention. In the following, explanations of structures and manufacturing steps corresponding to those explained in Fig. 5A to 5D will be omitted.

[0149] 12A, a 4H-SiC crystal structure 1 is prepared as an example of a SiC processing target. In this embodiment, the 4H-SiC crystal structure 1 has a layered structure including a SiC semiconductor wafer 16 and a SiC epitaxial layer 17. The SiC epitaxial layer 17 may have an impurity concentration (e.g., n-type impurity concentration) less than the impurity concentration (e.g., n-type impurity concentration) of the SiC semiconductor wafer 16.

[0150] A first main surface 2 of the 4H—SiC crystal structure 1 is formed by a SiC epitaxial layer 17. A second main surface 3 of the 4H—SiC crystal structure 1 is formed by a SiC semiconductor wafer 16. A side surface 4 of the 4H—SiC crystal structure 1 is formed by the SiC semiconductor wafer 16 and the SiC epitaxial layer 17.

[0151] The SiC epitaxial layer 17 is formed by epitaxially growing SiC from the SiC semiconductor wafer 16. The thickness of the SiC epitaxial layer 17 is less than the thickness of the SiC semiconductor wafer 16.

[0152] The thickness of the SiC semiconductor wafer 16 may be 1 μm or more and less than 1000 μm. The thickness of the SiC semiconductor wafer 16 may be 1 μm or more and 50 μm or less, 50 μm or more and 150 μm or less, 150 μm or more and 250 μm or less, 250 μm or more and 400 μm or less, 400 μm or more and 600 μm or less, 600 μm or more and 800 μm or less, or 800 μm or more and 1000 μm or less.

[0153] The thickness of SiC epitaxial layer 17 may be 1 μm or more and 100 μm or less. The thickness of SiC epitaxial layer 17 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, 40 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, or 75 μm or more and 100 μm or less.

[0154] 12B, a modified layer 11, a depression 12 and a recess 13 are formed in a processed region 10 selectively set on the first main surface 2 of the 4H—SiC crystal structure 1. The modified layer 11 is formed through a process similar to that shown in FIG.

[0155] The modified layer 11, the depression 12 and the recess 13 are formed in the SiC epitaxial layer 17. More specifically, the modified layer 11, the depression 12 and the recess 13 are also formed in the SiC semiconductor wafer 16, from the SiC epitaxial layer 17 across the boundary between the SiC semiconductor wafer 16 and the SiC epitaxial layer 17.

[0156] Next, referring to Fig. 12C, the modified layer 11 is entirely removed while leaving the 4H-SiC crystal structure 1. The modified layer 11 is removed through a process similar to that shown in Fig. 5C described above. As a result, a recess 12 defined by the SiC semiconductor wafer 16 and the SiC epitaxial layer 17 remains on the first main surface 2.

[0157] In this process, the opening side corners of the depression 12 are rounded in a curved shape toward the inside of the depression 12. In addition, the bottom side corners of the depression 12 are rounded in a curved shape toward the outside of the depression 12. The depression 12 with rounded opening side corners can alleviate stress concentration on the depression 12 at the opening side corners. In addition, the depression 12 with rounded bottom side corners can alleviate stress concentration on the depression 12 at the bottom side corners. This can suppress undesirable cracks caused by stress on the depression 12.

[0158] 12D, the 4H—SiC crystal structure 1 may be cleaved starting from the depression 12. The 4H—SiC crystal structure 1 may be cleaved through a process similar to that of FIG. 5D described above. When the impurity concentration of the SiC semiconductor wafer 16 is higher than that of the SiC epitaxial layer 17, the attenuation rate of the laser light for the SiC semiconductor wafer 16 is higher than that of the SiC epitaxial layer 17.

[0159] Therefore, by irradiating the laser light so as to reach the SiC semiconductor wafer 16, it is possible to efficiently heat the SiC semiconductor wafer 16. Particularly, in this step, the SiC semiconductor wafer 16 exposed from the bottom of the recess 12 can be directly heated by the laser light.

[0160] This makes it possible to efficiently increase the compressive stress generated in the heating step of the depression 12 and the tensile stress generated in the cooling step of the depression 12. Thus, it is possible to efficiently increase the cleavage force applied to the 4H—SiC crystal structure 1. The 4H—SiC crystal structure 1 after cleavage has a cleavage plane 14. The cleavage plane 14 is continuous with an inclined portion 15 consisting of the remaining portion of the depression 12.

[0161] As described above, according to this SiC processing method, the outer surface of the SiC epitaxial layer 17 can be processed by the step of forming the modified layer 11 and the step of removing the modified layer 11. In addition, the 4H—SiC crystal structure 1 can be cleaved by utilizing the depression 12 formed in the SiC epitaxial layer 17 through the step of removing the modified layer 11.

[0162] In particular, recess 12 having rounded opening side corners can alleviate stress concentration on recess 12 at the opening side corners. Also, recess 12 having rounded bottom side corners can alleviate stress concentration on recess 12 at the bottom side corners. This can suppress undesirable cracks caused by stress on recess 12.

[0163] Figures 13A to 13D are cross-sectional perspective views illustrating a partial region of the 4H-SiC crystal structure 1 shown in Figure 3, for explaining the SiC processing method according to the seventh embodiment of the present invention. In the following, explanations of structures and manufacturing steps corresponding to those explained in Figures 5A to 5D will be omitted.

[0164] 13A, a 4H-SiC crystal structure 1 is prepared as an example of a SiC processing target. In this embodiment, the 4H-SiC crystal structure 1 has a layered structure including a SiC semiconductor wafer 16 and a SiC epitaxial layer 17. The SiC epitaxial layer 17 may have an impurity concentration (e.g., n-type impurity concentration) less than the impurity concentration (e.g., n-type impurity concentration) of the SiC semiconductor wafer 16.

[0165] A first main surface 2 of the 4H—SiC crystal structure 1 is formed by a SiC epitaxial layer 17. A second main surface 3 of the 4H—SiC crystal structure 1 is formed by a SiC semiconductor wafer 16. A side surface 4 of the 4H—SiC crystal structure 1 is formed by the SiC semiconductor wafer 16 and the SiC epitaxial layer 17.

[0166] The thickness of the SiC semiconductor wafer 16 may be 1 μm or more and less than 1000 μm. The thickness of the SiC semiconductor wafer 16 may be 1 μm or more and 50 μm or less, 50 μm or more and 150 μm or less, 150 μm or more and 250 μm or less, 250 μm or more and 400 μm or less, 400 μm or more and 600 μm or less, 600 μm or more and 800 μm or less, or 800 μm or more and 1000 μm or less.

[0167] The thickness of SiC epitaxial layer 17 may be 1 μm or more and 100 μm or less. The thickness of SiC epitaxial layer 17 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, 40 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, or 75 μm or more and 100 μm or less.

[0168] Next, referring to Fig. 13B, modified layer 11, depression 12 and recess 13 are formed in processed region 10 selectively set on second main surface 3 of 4H-SiC crystal structure 1 instead of first main surface 2 of 4H-SiC crystal structure 1. That is, modified layer 11, depression 12 and recess 13 are formed in SiC semiconductor wafer 16. Modified layer 11, depression 12 and recess 13 are formed on second main surface 3 through the same process as that shown in Fig. 5B described above.

[0169] The recess 12 includes a bottom and a side. The recess 12 may be formed in a tapered shape in which the opening width narrows from the second main surface 3 toward the bottom. The bottom of the recess 12 may be formed in a curved shape toward the first main surface 2. The recess 12 includes an opening side corner and a bottom side corner. The opening side corner of the recess 12 connects the second main surface 3 and the side of the recess 12. The bottom side corner of the recess 12 connects the bottom and the side of the recess 12.

[0170] The width W of the depression 12 may be more than 0 μm and not more than 10 μm. The width W of the depression 12 is the width in a direction perpendicular to the direction in which the depression 12 extends. The width W of the depression 12 may be more than 0 μm and not more than 2.5 μm, 2.5 μm or more and not more than 5 μm, 5 μm or more and not more than 7.5 μm, or 7.5 μm or more and not more than 10 μm. When the thickness of the 4H—SiC crystal structure 1 is 150 μm or less, the width W of the depression 12 is preferably more than 0 μm and not more than 5 μm.

[0171] The depth D of the depression 12 may be more than 0 μm and not more than 30 μm. The depth D of the depression 12 is the distance from the second main surface 3 to the bottom of the depression 12 in the normal direction N. The depth D of the depression 12 may be more than 0 μm and not more than 5 μm, 5 μm or more to 10 μm or less, 10 μm or more to 15 μm or less, 15 μm or more to 20 μm or less, 20 μm or more to 25 μm or less, or 25 μm or more to 30 μm or less. When the thickness of the 4H—SiC crystal structure 1 is 150 μm or less, the depth D of the depression 12 is preferably more than 0 μm and not more than 15 μm.

[0172] The modified layer 11 is formed in the form of a film along the inner wall of the depression 12. The thickness of the portion of the modified layer 11 covering the bottom wall of the depression 12 may be greater than the thickness of the portion of the modified layer 11 covering the side wall of the depression 12. The modified layer 11 may be formed along the inner wall of the depression 12 with a uniform thickness.

[0173] The modified layer 11 defines a recess 13 within the depression 12. More specifically, the recess 13 is defined by the outer surface of the modified layer 11. The recess 13 includes a bottom and a side. The recess 13 may be formed in a tapered shape in which the opening width narrows from the second main surface 3 toward the first main surface 2. The bottom of the recess 13 may be formed in a curved shape toward the first main surface 2.

[0174] The recess 13 includes an open side corner and a bottom side corner. The open side corner of the recess 13 connects the second main surface 3 and a side of the recess 13. The bottom side corner of the recess 13 connects the bottom and a side of the recess 13.

[0175] The width WR of the recess 13 is less than the width W of the indentation 12. The width WR of the recess 13 may be more than 0 μm and less than 10 μm. The width WR of the recess 13 may be more than 0 μm and less than 2.5 μm, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, or 7.5 μm or more and less than 10 μm. When the thickness of the 4H—SiC crystal structure 1 is 150 μm or less, the width WR of the recess 13 is preferably more than 0 μm and less than 5 μm.

[0176] The depth DR of the recess 13 is less than the depth D of the dent 12. The depth DR of the recess 13 may be more than 0 μm and less than 30 μm. The depth DR of the recess 13 may be more than 0 μm and less than 5 μm, 5 μm or more and less than 10 μm, 10 μm or more and less than 15 μm, 15 μm or more and less than 20 μm, 20 μm or more and less than 25 μm, or 25 μm or more and less than 30 μm. When the thickness of the 4H—SiC crystal structure 1 is 150 μm or less, the depth DR of the recess 13 is preferably more than 0 μm and less than 15 μm.

[0177] Next, referring to Fig. 13C, the modified layer 11 is partially removed while leaving the 4H-SiC crystal structure 1, and the outer surface of the modified layer 11 is flattened. The modified layer 11 is removed through a process similar to that of Fig. 5C described above. As a result, the opening side corners of the recess 13 are rounded inwardly of the recess 13. In addition, the bottom side corners of the recess 13 are rounded inwardly of the recess 13.

[0178] The recess 13 with rounded opening corners can reduce stress concentration on the modified layer 11 at the opening corners. Also, the recess 13 with rounded bottom corners can reduce stress concentration on the modified layer 11 at the bottom corners. This can suppress undesirable cracks caused by stress on the modified layer 11.

[0179] Next, referring to Fig. 13D, the 4H-SiC crystal structure 1 may be cleaved starting from the depression 12. The 4H-SiC crystal structure 1 may be cleaved through a process similar to that of Fig. 5D described above. When the impurity concentration of the SiC semiconductor wafer 16 is higher than that of the SiC epitaxial layer 17, the attenuation rate of the laser light for the SiC semiconductor wafer 16 is higher than that for the SiC epitaxial layer 17.

[0180] Therefore, by irradiating the laser light so as to reach the SiC semiconductor wafer 16, the SiC semiconductor wafer 16 can be efficiently heated. Particularly, in this step, the SiC semiconductor wafer 16 can be heated by the laser light through the modified layer 11. This makes it possible to efficiently increase the compressive stress generated in the heating step of the recess 12 and the tensile stress generated in the cooling step of the recess 12. Therefore, the cleavage force applied to the 4H—SiC crystal structure 1 can be efficiently increased.

[0181] After cleavage, the 4H—SiC crystal structure 1 has a cleavage plane 14. The cleavage plane 14 is continuous with an inclined portion 15 consisting of a remaining portion of the recess 12. A part of the modified layer 11 is exposed at a corner connecting the second main surface 3 of the 4H—SiC crystal structure 1 and the cleavage plane 14. The modified layer 11 is formed along the inclined portion 15.

[0182] As described above, according to this SiC processing method, the outer surface of the SiC semiconductor wafer 16 can be processed by the step of forming the modified layer 11 and the step of removing the modified layer 11. In addition, the 4H—SiC crystal structure 1 can also be cleaved by utilizing the recess 12.

[0183] In particular, the recess 13 having rounded opening side corners can alleviate stress concentration on the modified layer 11 at the opening side corners. Also, the recess 13 having rounded bottom side corners can alleviate stress concentration on the modified layer 11 at the bottom side corners. This can suppress undesirable cracks caused by stress on the modified layer 11.

[0184] Figures 14A to 14D are cross-sectional perspective views illustrating a partial region of the 4H-SiC crystal structure 1 shown in Figure 3, for explaining a SiC processing method according to an eighth embodiment of the present invention. In the following, explanations of structures and manufacturing steps corresponding to those explained in Figures 5A to 5D will be omitted.

[0185] 14A, a 4H-SiC crystal structure 1 is prepared as an example of a SiC processing target. In this embodiment, the 4H-SiC crystal structure 1 has a layered structure including a SiC semiconductor wafer 16 and a SiC epitaxial layer 17. The SiC epitaxial layer 17 may have an impurity concentration (e.g., n-type impurity concentration) less than the impurity concentration (e.g., n-type impurity concentration) of the SiC semiconductor wafer 16.

[0186] A first main surface 2 of the 4H—SiC crystal structure 1 is formed by a SiC epitaxial layer 17. A second main surface 3 of the 4H—SiC crystal structure 1 is formed by a SiC semiconductor wafer 16. A side surface 4 of the 4H—SiC crystal structure 1 is formed by the SiC semiconductor wafer 16 and the SiC epitaxial layer 17.

[0187] The SiC epitaxial layer 17 is formed by epitaxially growing SiC from the SiC semiconductor wafer 16. The thickness of the SiC epitaxial layer 17 is less than the thickness of the SiC semiconductor wafer 16.

[0188] The thickness of the SiC semiconductor wafer 16 may be 1 μm or more and less than 1000 μm. The thickness of the SiC semiconductor wafer 16 may be 1 μm or more and 50 μm or less, 50 μm or more and 150 μm or less, 150 μm or more and 250 μm or less, 250 μm or more and 400 μm or less, 400 μm or more and 600 μm or less, 600 μm or more and 800 μm or less, or 800 μm or more and 1000 μm or less.

[0189] The thickness of SiC epitaxial layer 17 may be 1 μm or more and 100 μm or less. The thickness of SiC epitaxial layer 17 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, 40 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, or 75 μm or more and 100 μm or less.

[0190] Next, referring to Fig. 14B, a modified layer 11, a depression 12 and a recess 13 are formed in a processing region 10 selectively set on the second main surface 3 of the 4H-SiC crystal structure 1, instead of the first main surface 2 of the 4H-SiC crystal structure 1. The modified layer 11, the depression 12 and the recess 13 are formed in a SiC semiconductor wafer 16. The modified layer 11, the depression 12 and the recess 13 are formed on the second main surface 3 through the same process as that shown in Fig. 5B described above.

[0191] The recess 12 includes a bottom and a side. The recess 12 may be formed in a tapered shape in which the opening width narrows from the second main surface 3 toward the bottom. The bottom of the recess 12 may be formed in a curved shape toward the first main surface 2. The recess 12 includes an opening side corner and a bottom side corner. The opening side corner of the recess 12 connects the second main surface 3 and the side of the recess 12. The bottom side corner of the recess 12 connects the bottom and the side of the recess 12.

[0192] The width W of the depression 12 may be more than 0 μm and not more than 10 μm. The width W of the depression 12 is the width in a direction perpendicular to the direction in which the depression 12 extends. The width W of the depression 12 may be more than 0 μm and not more than 2.5 μm, 2.5 μm or more and not more than 5 μm, 5 μm or more and not more than 7.5 μm, or 7.5 μm or more and not more than 10 μm. When the thickness of the 4H—SiC crystal structure 1 is 150 μm or less, the width W of the depression 12 is preferably more than 0 μm and not more than 5 μm.

[0193] The depth D of the depression 12 may be more than 0 μm and not more than 30 μm. The depth D of the depression 12 is the distance from the second main surface 3 to the bottom of the depression 12 in the normal direction N. The depth D of the depression 12 may be more than 0 μm and not more than 5 μm, 5 μm or more to 10 μm or less, 10 μm or more to 15 μm or less, 15 μm or more to 20 μm or less, 20 μm or more to 25 μm or less, or 25 μm or more to 30 μm or less. When the thickness of the 4H—SiC crystal structure 1 is 150 μm or less, the depth D of the depression 12 is preferably more than 0 μm and not more than 15 μm.

[0194] The modified layer 11 is formed in the form of a film along the inner wall of the depression 12. The thickness of the portion of the modified layer 11 covering the bottom wall of the depression 12 may be greater than the thickness of the portion of the modified layer 11 covering the side wall of the depression 12. The modified layer 11 may be formed along the inner wall of the depression 12 with a uniform thickness.

[0195] The modified layer 11 defines a recess 13 within the depression 12. More specifically, the recess 13 is defined by the outer surface of the modified layer 11. The recess 13 includes a bottom and a side. The recess 13 may be formed in a tapered shape in which the opening width narrows from the second main surface 3 toward the first main surface 2. The bottom of the recess 13 may be formed in a curved shape toward the first main surface 2.

[0196] The recess 13 includes an open side corner and a bottom side corner. The open side corner of the recess 13 connects the second main surface 3 and a side of the recess 13. The bottom side corner of the recess 13 connects the bottom and a side of the recess 13.

[0197] The width WR of the recess 13 is less than the width W of the indentation 12. The width WR of the recess 13 may be more than 0 μm and less than 10 μm. The width WR of the recess 13 may be more than 0 μm and less than 2.5 μm, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, or 7.5 μm or more and less than 10 μm. When the thickness of the 4H—SiC crystal structure 1 is 150 μm or less, the width WR of the recess 13 is preferably more than 0 μm and less than 5 μm.

[0198] The depth DR of the recess 13 is less than the depth D of the dent 12. The depth DR of the recess 13 may be more than 0 μm and less than 30 μm. The depth DR of the recess 13 may be more than 0 μm and less than 5 μm, 5 μm or more and less than 10 μm, 10 μm or more and less than 15 μm, 15 μm or more and less than 20 μm, 20 μm or more and less than 25 μm, or 25 μm or more and less than 30 μm. When the thickness of the 4H—SiC crystal structure 1 is 150 μm or less, the depth DR of the recess 13 is preferably more than 0 μm and less than 15 μm.

[0199] Next, referring to FIG. 14C, the modified layer 11 is entirely removed while leaving the 4H—SiC crystal structure 1. The modified layer 11 is removed through a process similar to that of FIG. 5C described above. As a result, the depression 12 defined by the SiC semiconductor wafer 16 remains on the second main surface 3. In this process, the opening side corners of the depression 12 are rounded inwardly of the depression 12. In addition, the bottom side corners of the depression 12 are rounded inwardly of the depression 12.

[0200] The recess 12 having rounded opening side corners can alleviate stress concentration on the opening side corners of the recess 12. Also, the recess 12 having rounded bottom side corners can alleviate stress concentration on the bottom side corners of the recess 12. This can suppress undesirable cracks caused by stress on the recess 12.

[0201] 14D, the 4H—SiC crystal structure 1 may be cleaved starting from the depression 12. The 4H—SiC crystal structure 1 may be cleaved through a process similar to that of FIG. 5D described above. When the impurity concentration of the SiC semiconductor wafer 16 is higher than that of the SiC epitaxial layer 17, the attenuation rate of the laser light for the SiC semiconductor wafer 16 is higher than that for the SiC epitaxial layer 17.

[0202] Therefore, by irradiating the laser light so as to reach the SiC semiconductor wafer 16, it is possible to efficiently heat the SiC semiconductor wafer 16. In particular, in this step, the portion of the SiC semiconductor wafer 16 exposed from the bottom of the recess 12 can be directly heated by the laser light.

[0203] This makes it possible to efficiently increase the compressive stress generated in the heating step of the depression 12 and the tensile stress generated in the cooling step of the depression 12. Thus, it is possible to efficiently increase the cleavage force applied to the 4H—SiC crystal structure 1. The 4H—SiC crystal structure 1 after cleavage has a cleavage plane 14. The cleavage plane 14 is continuous with an inclined portion 15 consisting of the remaining portion of the depression 12.

[0204] As described above, according to this SiC processing method, the outer surface of the SiC semiconductor wafer 16 can be processed by the step of forming the modified layer 11 and the step of removing the modified layer 11. In addition, the 4H—SiC crystal structure 1 can also be cleaved by utilizing the recess 12.

[0205] In particular, recess 12 having rounded opening side corners can alleviate stress concentration on recess 12 at the opening side corners. Also, recess 12 having rounded bottom side corners can alleviate stress concentration on recess 12 at the bottom side corners. This can suppress undesirable cracks caused by stress on recess 12.

[0206] 15A to 15D are cross-sectional perspective views illustrating a partial region of the 4H—SiC crystal structure 1 shown in Fig. 3, for explaining a SiC processing method according to a ninth embodiment of the present invention. In the following, explanations of structures and manufacturing steps corresponding to those described in Fig. 5A to 5D will be omitted.

[0207] First, referring to Fig. 15A, a 4H-SiC crystal structure 1 is prepared as an example of a SiC processing target. In this embodiment, a coating layer 18 is formed on a first main surface 2 of the 4H-SiC crystal structure 1 to cover the first main surface 2. The coating layer 18 may have a single-layer structure made of a metal layer or an insulating layer. The coating layer 18 may have a multilayer structure including a metal layer and an insulating layer.

[0208] Examples of the insulating material of the coating layer 18 include silicon oxide and silicon nitride. Examples of the metal material of the coating layer 18 include aluminum, copper, gold, titanium, titanium nitride, etc. The coating layer 18 may be formed by at least one of an oxidation treatment method, a CVD method, a sputtering method, a vapor deposition method, and a plating method.

[0209] Next, referring to Fig. 15B, a modified layer 11, a dent 12 and a recess 13 are formed in a processed region 10 selectively set on the first main surface 2 of the 4H—SiC crystal structure 1. The modified layer 11, the dent 12 and the recess 13 are formed on the first main surface 2 through a process similar to that shown in Fig. 5B described above.

[0210] In this step, the first main surface 2 is irradiated with laser light through the coating layer 18. The coating layer 18 is melted or sublimated by the irradiation of the laser light. As a result, the first main surface 2 is exposed from the coating layer 18. In addition, the laser light is continuously irradiated to the portion of the first main surface 2 that is exposed from the coating layer 18.

[0211] As a result, a modified layer 11, a depression 12, and a recess 13 are formed on the first main surface 2. The depression 12 may be connected to the removed portion of the coating layer 18. The modified layer 11 may cover the coating layer 18. The modified layer 11 may cover the removed portion of the coating layer 18.

[0212] Here, an example has been described in which the step of irradiating 4H—SiC crystal structure 1 with laser light is carried out simultaneously with the step of irradiating coating layer 18 with laser light. However, the step of irradiating 4H—SiC crystal structure 1 with laser light may be carried out after the step of irradiating coating layer 18 with laser light by changing the irradiation conditions, etc.

[0213] The attenuation rate of the laser light with respect to coating layer 18 is preferably equal to or greater than the attenuation rate of the laser light with respect to 4H—SiC crystal structure 1. This allows coating layer 18 to be efficiently melted or sublimated by the laser energy with respect to 4H—SiC crystal structure 1.

[0214] Next, referring to Fig. 15C, the modified layer 11 is partially removed while leaving the 4H-SiC crystal structure 1 and the covering layer 18, and the outer surface of the modified layer 11 is flattened. The modified layer 11 is removed through a process similar to that shown in Fig. 5C described above.

[0215] The modified layer 11 has a different component from the coating layer 18. The etching rate (etching selectivity) for the modified layer 11 is different from the etching rate (etching selectivity) for the coating layer 18. Therefore, a part of the modified layer 11 can be removed while leaving the 4H—SiC crystal structure 1 and the coating layer 18. As a result, the opening side corners of the recess 13 are rounded inwardly and curved. Also, the bottom side corners of the recess 13 are rounded inwardly and curved.

[0216] The recess 13 with rounded opening corners can reduce stress concentration on the modified layer 11 at the opening corners. Also, the recess 13 with rounded bottom corners can reduce stress concentration on the modified layer 11 at the bottom corners. This can suppress undesirable cracks caused by stress on the modified layer 11.

[0217] Next, referring to Fig. 15D, 4H-SiC crystal structure 1 may be cleaved starting from depression 12. 4H-SiC crystal structure 1 may be cleaved through a process similar to that of Fig. 5D described above. After cleavage, 4H-SiC crystal structure 1 has cleavage surface 14. Cleavage surface 14 is continuous with inclined portion 15 consisting of the remaining portion of depression 12. In addition, inclined portion 15 is exposed from coating layer 18.

[0218] As described above, according to this SiC processing method, the outer surface of the 4H-SiC crystal structure 1 can be processed by the step of forming the modified layer 11 and the step of removing the modified layer 11. In addition, the 4H-SiC crystal structure 1 can be cleaved by utilizing the depression 12 formed in the outer surface of the 4H-SiC crystal structure 1 through the step of removing the modified layer 11.

[0219] In particular, the recess 13 having rounded opening side corners can alleviate stress concentration on the modified layer 11 at the opening side corners. Also, the recess 13 having rounded bottom side corners can alleviate stress concentration on the modified layer 11 at the bottom side corners. This can suppress undesirable cracks caused by stress on the modified layer 11.

[0220] In this embodiment, an example has been described in which a portion of modified layer 11 is removed from first main surface 2 of 4H—SiC crystal structure 1 in the step of Fig. 15C. However, the entire modified layer 11 may be removed in the step of Fig. 15C. The manufacturing method in which coating layer 18 is formed is also applicable to the first to eighth embodiments described above.

[0221] 16A to 16D are cross-sectional perspective views illustrating a partial region of the 4H—SiC crystal structure 1 shown in Fig. 3, for explaining the SiC processing method according to the tenth embodiment of the present invention. In the following, explanations of structures and manufacturing steps corresponding to those explained in Fig. 5A to 5D will be omitted.

[0222] 16A, a 4H-SiC crystal structure 1 is prepared as an example of a SiC processing target. In this embodiment, the 4H-SiC crystal structure 1 has a layered structure including a SiC semiconductor wafer 16 and a SiC epitaxial layer 17. The SiC epitaxial layer 17 may have an impurity concentration (e.g., n-type impurity concentration) less than the impurity concentration (e.g., n-type impurity concentration) of the SiC semiconductor wafer 16.

[0223] A first main surface 2 of the 4H—SiC crystal structure 1 is formed by a SiC epitaxial layer 17. A second main surface 3 of the 4H—SiC crystal structure 1 is formed by a SiC semiconductor wafer 16. A side surface 4 of the 4H—SiC crystal structure 1 is formed by the SiC semiconductor wafer 16 and the SiC epitaxial layer 17.

[0224] The SiC epitaxial layer 17 is formed by epitaxially growing SiC from the SiC semiconductor wafer 16. The thickness of the SiC epitaxial layer 17 is less than the thickness of the SiC semiconductor wafer 16.

[0225] The thickness of the SiC semiconductor wafer 16 may be 1 μm or more and less than 1000 μm. The thickness of the SiC semiconductor wafer 16 may be 1 μm or more and 50 μm or less, 50 μm or more and 150 μm or less, 150 μm or more and 250 μm or less, 250 μm or more and 400 μm or less, 400 μm or more and 600 μm or less, 600 μm or more and 800 μm or less, or 800 μm or more and 1000 μm or less.

[0226] The thickness of SiC epitaxial layer 17 may be 1 μm or more and 100 μm or less. The thickness of SiC epitaxial layer 17 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, 40 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, or 75 μm or more and 100 μm or less.

[0227] In this embodiment, a coating layer 18 is formed on the second main surface 3 of the 4H—SiC crystal structure 1 to cover the second main surface 3. The coating layer 18 may have a single-layer structure made of a metal layer or an insulating layer. The coating layer 18 may have a multilayer structure including a metal layer and an insulating layer.

[0228] Examples of the insulating material of the coating layer 18 include silicon oxide and silicon nitride. Examples of the metal material of the coating layer 18 include aluminum, copper, gold, titanium, titanium nitride, etc. The coating layer 18 may be formed by at least one of an oxidation treatment method, a CVD method, a sputtering method, a vapor deposition method, and a plating method.

[0229] 16B, modified layer 11, depression 12 and recess 13 are formed in processed region 10 selectively set on second main surface 3 of 4H—SiC crystal structure 1 instead of first main surface 2 of 4H—SiC crystal structure 1. Modified layer 11, depression 12 and recess 13 are formed on second main surface 3 through steps similar to those shown in FIG. 5B above.

[0230] In this step, the second main surface 3 is irradiated with laser light through the coating layer 18. The coating layer 18 is melted or sublimated by the irradiation of the laser light. As a result, the second main surface 3 is exposed from the coating layer 18. In addition, the laser light is continuously irradiated to the portion of the second main surface 3 exposed from the coating layer 18. As a result, the modified layer 11, the depression 12, and the recess 13 are formed on the second main surface 3.

[0231] Here, an example has been described in which the step of irradiating 4H—SiC crystal structure 1 with laser light is carried out simultaneously with the step of irradiating coating layer 18 with laser light. However, the step of irradiating 4H—SiC crystal structure 1 with laser light may be carried out after the step of irradiating coating layer 18 with laser light by changing the irradiation conditions, etc.

[0232] The attenuation rate of the laser light with respect to coating layer 18 is preferably equal to or greater than the attenuation rate of the laser light with respect to 4H—SiC crystal structure 1. This allows coating layer 18 to be efficiently melted or sublimated by the laser energy with respect to 4H—SiC crystal structure 1.

[0233] The depression 12 includes a bottom and a side. The depression 12 may be formed in a tapered shape in which the opening width narrows from the second main surface 3 toward the bottom. The bottom of the depression 12 may be formed in a curved shape toward the first main surface 2. The depression 12 includes an opening side corner and a bottom side corner. The opening side corner of the depression 12 connects the second main surface 3 and the side of the depression 12. The bottom side corner of the depression 12 connects the bottom and the side of the depression 12. The depression 12 may be connected to the portion of the coating layer 18 from which it has been removed.

[0234] The width W of the depression 12 may be more than 0 μm and not more than 10 μm. The width W of the depression 12 is the width in a direction perpendicular to the direction in which the depression 12 extends. The width W of the depression 12 may be more than 0 μm and not more than 2.5 μm, 2.5 μm or more and not more than 5 μm, 5 μm or more and not more than 7.5 μm, or 7.5 μm or more and not more than 10 μm. When the thickness of the 4H—SiC crystal structure 1 is 150 μm or less, the width W of the depression 12 is preferably more than 0 μm and not more than 5 μm.

[0235] The depth D of the depression 12 may be more than 0 μm and not more than 30 μm. The depth D of the depression 12 is the distance from the second main surface 3 to the bottom of the depression 12 in the normal direction N. The depth D of the depression 12 may be more than 0 μm and not more than 5 μm, 5 μm or more to 10 μm or less, 10 μm or more to 15 μm or less, 15 μm or more to 20 μm or less, 20 μm or more to 25 μm or less, or 25 μm or more to 30 μm or less. When the thickness of the 4H—SiC crystal structure 1 is 150 μm or less, the depth D of the depression 12 is preferably more than 0 μm and not more than 15 μm.

[0236] The modified layer 11 is formed in the form of a film along the inner wall of the depression 12. The thickness of the portion of the modified layer 11 covering the bottom surface of the depression 12 may be greater than the thickness of the portion of the modified layer 11 covering the side wall of the depression 12. The modified layer 11 may be formed with a uniform thickness along the inner wall of the depression 12. The modified layer 11 may cover the covering layer 18. The modified layer 11 may cover the removed portion of the covering layer 18.

[0237] The modified layer 11 defines a recess 13 within the depression 12. More specifically, the recess 13 is defined by the outer surface of the modified layer 11. The recess 13 includes a bottom and a side. The recess 13 may be formed in a tapered shape in which the opening width narrows from the second main surface 3 toward the first main surface 2. The bottom of the recess 13 may be formed in a curved shape toward the first main surface 2.

[0238] The recess 13 includes an open side corner and a bottom side corner. The open side corner of the recess 13 connects the second main surface 3 and a side of the recess 13. The bottom side corner of the recess 13 connects the bottom and a side of the recess 13.

[0239] The width WR of the recess 13 is less than the width W of the indentation 12. The width WR of the recess 13 may be more than 0 μm and less than 10 μm. The width WR of the recess 13 may be more than 0 μm and less than 2.5 μm, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, or 7.5 μm or more and less than 10 μm. When the thickness of the 4H—SiC crystal structure 1 is 150 μm or less, the width WR of the recess 13 is preferably more than 0 μm and less than 5 μm.

[0240] The depth DR of the recess 13 is less than the depth D of the dent 12. The depth DR of the recess 13 may be more than 0 μm and less than 30 μm. The depth DR of the recess 13 may be more than 0 μm and less than 5 μm, 5 μm or more and less than 10 μm, 10 μm or more and less than 15 μm, 15 μm or more and less than 20 μm, 20 μm or more and less than 25 μm, or 25 μm or more and less than 30 μm. When the thickness of the 4H—SiC crystal structure 1 is 150 μm or less, the depth DR of the recess 13 is preferably more than 0 μm and less than 15 μm.

[0241] Next, referring to Fig. 16C, the modified layer 11 is partially removed while leaving the 4H-SiC crystal structure 1 and the covering layer 18, and the outer surface of the modified layer 11 is flattened. The modified layer 11 is removed through a process similar to that shown in Fig. 5C described above.

[0242] The modified layer 11 has a different component from the coating layer 18. The etching rate (etching selectivity) for the modified layer 11 is different from the etching rate (etching selectivity) for the coating layer 18. Therefore, a part of the modified layer 11 can be removed while leaving the 4H—SiC crystal structure 1 and the coating layer 18. As a result, the opening side corners of the recess 13 are rounded inwardly and curved. Also, the bottom side corners of the recess 13 are rounded inwardly and curved.

[0243] The recess 13 with rounded opening corners can reduce stress concentration on the modified layer 11 at the opening corners. Also, the recess 13 with rounded bottom corners can reduce stress concentration on the modified layer 11 at the bottom corners. This can suppress undesirable cracks caused by stress on the modified layer 11.

[0244] Next, referring to Fig. 16D, the 4H-SiC crystal structure 1 may be cleaved starting from the depression 12. The 4H-SiC crystal structure 1 may be cleaved through a process similar to that of Fig. 5D described above. The 4H-SiC crystal structure 1 after cleavage has a cleavage surface 14. The cleavage surface 14 is continuous with an inclined portion 15 consisting of a remaining portion of the depression 12. In addition, the inclined portion 15 is exposed from the coating layer 18.

[0245] As described above, according to this SiC processing method, the outer surface of the 4H-SiC crystal structure 1 can be processed by the step of forming the modified layer 11 and the step of removing the modified layer 11. In addition, the 4H-SiC crystal structure 1 can be cleaved by utilizing the depression 12 formed in the outer surface of the 4H-SiC crystal structure 1 through the step of removing the modified layer 11.

[0246] In particular, the recess 13 having rounded opening side corners can alleviate stress concentration on the modified layer 11 at the opening side corners. Also, the recess 13 having rounded bottom side corners can alleviate stress concentration on the modified layer 11 at the bottom side corners. This can suppress undesirable cracks caused by stress on the modified layer 11.

[0247] In this embodiment, an example in which a part of the modified layer 11 is removed in the step of Fig. 16C has been described. However, the entire modified layer 11 may be removed in the step of Fig. 16C. The manufacturing method in which the coating layer 18 is formed is also applicable to the first to eighth embodiments described above.

[0248] Fig. 17 is a perspective view showing a schematic configuration of a SiC semiconductor device 21 according to an eleventh embodiment of the present invention. Fig. 18 is a plan view of the SiC semiconductor device 21 shown in Fig. 17. Fig. 19 is a cross-sectional view taken along line XIX-XIX shown in Fig. 18. Fig. 20 is an enlarged view of a region XX shown in Fig. 19. The SiC semiconductor device 21 is a device manufactured using the 4H-SiC crystal structure 1 described above.

[0249] 17 to 20, SiC semiconductor device 21 includes SiC semiconductor layer 22. The thickness of SiC semiconductor layer 22 may be 1 μm or more and less than 1000 μm. The thickness of SiC semiconductor layer 22 may be 1 μm or more and 50 μm or less, 50 μm or more and 150 μm or less, 150 μm or more and 250 μm or less, 250 μm or more and 400 μm or less, 400 μm or more and 600 μm or less, 600 μm or more and 800 μm or less, or 800 μm or more and 1000 μm or less.

[0250] The SiC semiconductor layer 22 has a first main surface 23 on one side, a second main surface 24 on the other side, and side surfaces 25A, 25B, 25C, and 25D connecting the first main surface 23 and the second main surface 24. In this embodiment, the side surfaces 25A to 25D are all cut surfaces. More specifically, the side surfaces 25A to 25D are cleavage surfaces.

[0251] The first main surface 23 and the second main surface 24 are formed in a quadrangular shape (in this embodiment, a rectangular shape) in a plan view (hereinafter simply referred to as "plan view") seen from their normal direction N. Side surface 25A faces side surface 25C. Side surface 25B faces side surface 25D.

[0252] The SiC semiconductor layer 22 includes a 4H-SiC single crystal. The first main surface 23 and the second main surface 24 face the c-plane of the 4H-SiC single crystal. The first main surface 23 faces the (0001) plane, and the second main surface 24 faces the (000-1) plane.

[0253] The first main surface 23 and the second main surface 24 have an off angle θ inclined at an angle of 10° or less in the [11-20] direction with respect to the (0001) plane. The off angle θ may be 0° or more and 2° or less, 2° or more and 4° or less, 4° or more and 6° or less, 6° or more and 8° or less, or 8° or more and 10° or less. The off angle θ is preferably 0° or more and 4° or less.

[0254] The off angle θ of 0° means that the normal direction N and the c-axis are aligned. The off angle θ may be greater than 0° and less than 4°. The off angle θ is typically set to 2° or 4°, more specifically, in the range of 2°±10% or 4°±10%.

[0255] The side surfaces 25A to 25D each extend planarly along the normal direction N. The length of the side surfaces 25A to 25D may be 1 mm or more and 10 mm or less. The length of the side surfaces 25A to 25D may be 1 mm or more and 2.5 mm or less, 2.5 mm or more and 5 mm or less, 5 mm or more and 7.5 mm or less, or 7.5 mm or more and 10 mm or less. The length of the side surfaces 25A to 25D is preferably 2 mm or more and 5 mm or less.

[0256] The side surfaces 25A to 25D extend along the nearest atom direction and the intersecting direction of the nearest atom direction. More specifically, the intersecting direction of the nearest atom direction is an orthogonal direction perpendicular to the nearest atom direction. In this embodiment, the side surfaces 25A to 25D extend along the [11-20] direction and the [1-100] direction.

[0257] The side surface 25A and the side surface 25C are formed along the [11-20] direction. The side surface 25B and the side surface 25D are formed along the [1-100] direction. The side surface 25A and the side surface 25C may be formed along the [1-100] direction, and the side surface 25B and the side surface 25D may be formed along the [11-20] direction.

[0258] The in-plane variation of the side surfaces 25A to 25D is 20 μm or less. The in-plane variation of the side surfaces 25B and 25D extending along the [1-100] direction is 20 μm or less along the [11-20] direction. More specifically, the in-plane variation of the side surfaces 25B and 25D is 10 μm or less.

[0259] The in-plane variation of the side surfaces 25A and 25C extending in the [11-20] direction is 20 μm or less in the [1-100] direction. More specifically, the in-plane variation of the side surfaces 25A and 25C is 10 μm or less.

[0260] The in-plane variation is defined by the maximum value of the distance between a reference virtual line and a measurement virtual line set on one of the side surfaces 25A-25D selected from the side surfaces 25A-25D. The reference virtual line is a straight line connecting two corners of the SiC semiconductor layer 22 in a plan view, and is set on the selected one of the side surfaces 25A-25D. The measurement virtual line is a straight line extending parallel to the reference virtual line in a plan view, and is set so as to be in contact with the top or base of a protuberance (meander) present on the selected one of the side surfaces 25A-25D.

[0261] For example, the distance between the reference virtual line and the measurement virtual line touching the top of the ridge (meander), and the distance between the reference virtual line and the measurement virtual line touching the base of the ridge (meander) are measured. The maximum value of the measured distances between the reference virtual line and the measurement virtual line defines the in-plane variation of the selected one of the side surfaces 25A to 25D.

[0262] In this embodiment, the SiC semiconductor layer 22 is + The SiC semiconductor layer 22 has a layered structure including an n-type SiC semiconductor substrate 31 and an n-type SiC epitaxial layer 32. The second main surface 24 of the SiC semiconductor layer 22 is formed by the SiC semiconductor substrate 31. The first main surface 23 of the SiC semiconductor layer 22 is formed by the SiC epitaxial layer 32. The SiC semiconductor substrate 31 and the SiC epitaxial layer 32 form side surfaces 25A to 25D of the SiC semiconductor layer 22.

[0263] The thickness of the SiC semiconductor substrate 31 may be 1 μm or more and less than 1000 μm. The thickness of the SiC semiconductor substrate 31 may be 1 μm or more and 50 μm or less, 50 μm or more and 150 μm or less, 150 μm or more and 250 μm or less, 250 μm or more and 400 μm or less, 400 μm or more and 600 μm or less, 600 μm or more and 800 μm or less, or 800 μm or more and 1000 μm or less. The thickness of the SiC semiconductor substrate 31 is preferably 50 μm or more and 150 μm or less. By reducing the thickness of the SiC semiconductor substrate 31, the resistance value can be reduced by shortening the current path.

[0264] The SiC epitaxial layer 32 has a thickness less than that of the SiC semiconductor substrate 31. The thickness of the SiC epitaxial layer 32 may be 1 μm or more and 100 μm or less. The thickness of the SiC epitaxial layer 32 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, 40 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, or 75 μm or more and 100 μm or less. The thickness of the SiC epitaxial layer 32 is preferably 5 μm or more and 20 μm or less.

[0265] The n-type impurity concentration of the SiC epitaxial layer 32 is equal to or lower than the n-type impurity concentration of the SiC semiconductor substrate 31. The n-type impurity concentration of the SiC semiconductor substrate 31 is 1.0×10 18 cm -3 Above 1.0×10 21 cm -3 The n-type impurity concentration of the SiC epitaxial layer 32 may be 1.0×10 15 cm -3 Above 1.0×10 18 cm -3 It may be the following.

[0266] The SiC semiconductor layer 22 includes an active region 33 and an outer region 34. The active region 33 includes an impurity region 33A having n-type impurities and / or p-type impurities. The active region 33 is a region in which a semiconductor functional device is formed by the impurity region 33A. The semiconductor functional device may include a diode. The semiconductor functional device may include a transistor. The semiconductor functional device may include a field effect transistor.

[0267] In plan view, active region 33 may be set in the center of SiC semiconductor layer 22 with a gap inward from side surfaces 25A-25D. Active region 33 may be set in a quadrangle shape having four sides parallel to side surfaces 25A-25D in plan view.

[0268] The outer region 34 is a region outside the active region 33. The outer region 34 may be set in a region between the side surfaces 25A-25D and the periphery of the active region 33. The outer region 34 may be set in an annular shape (for example, endless) surrounding the active region 33 in a plan view.

[0269] The SiC semiconductor device 21 includes an insulating layer 35 formed on the first main surface 23. The insulating layer 35 selectively covers the first main surface 23. The insulating layer 35 may include silicon oxide or silicon nitride. The peripheral edge of the insulating layer 35 is continuous with the side surfaces 25A to 25D. The insulating layer 35 has an opening 39 formed therein to selectively expose the active region 33.

[0270] The SiC semiconductor device 21 includes a first electrode layer 36 formed on the first main surface 23. More specifically, the first electrode layer 36 is formed on an insulating layer 35. The first electrode layer 36 may include conductive polysilicon or metal. The first electrode layer 36 extends from above the insulating layer 35 into an opening 39. The first electrode layer 36 is electrically connected to the active region 33 within the opening 39.

[0271] The SiC semiconductor device 21 includes a resin layer 37 formed on the first main surface 23. More specifically, the resin layer 37 is formed on the insulating layer 35. The resin layer 37 selectively covers the first electrode layer 36. The peripheral portion 46 of the resin layer 37 described above is formed at a distance from the side surfaces 25A to 25D in an inner region. As a result, the resin layer 37 exposes the peripheral portion of the SiC semiconductor layer 22 in a plan view.

[0272] The resin layer 37 may contain a negative type or a positive type photosensitive resin. In this embodiment, the resin layer 37 contains polybenzoxazole as an example of a positive type photosensitive resin. The resin layer 37 may contain polyimide as an example of a negative type photosensitive resin. An opening 40 that exposes the first electrode layer 36 is formed in the resin layer 37.

[0273] The SiC semiconductor device 21 includes a second electrode layer 38 formed on the second main surface 24. The second electrode layer 38 covers the second main surface 24. The second electrode layer 38 is electrically connected to the second main surface 24. The second electrode layer 38 may include conductive polysilicon or a metal.

[0274] At corners connecting first main surface 23 and side surfaces 25A-25D of SiC semiconductor layer 22, inclined portions 41 are formed that slope downward from first main surface 23 toward side surfaces 25A-25D. The corners of SiC semiconductor layer 22 include corners that connect first main surface 23 and side surfaces 25A, 25C and extend along the [11-20] direction. The corners of SiC semiconductor layer 22 include corners that connect first main surface 23 and side surfaces 25B, 25D and extend along the [1-100] direction.

[0275] More specifically, the inclined portion 41 is formed in the SiC epitaxial layer 32. The inclined portion 41 is formed in a region on the first main surface 23 side with respect to a boundary region between the SiC semiconductor substrate 31 and the SiC epitaxial layer 32. Therefore, the SiC epitaxial layer 32 is exposed from the inclined portion 41.

[0276] The inclined portion 41 is formed by the inner wall of a recess recessed from the first main surface 23 toward the second main surface 24. The inclined portion 41 has an upper end 41a and a lower end 41b. The upper end 41a of the inclined portion 41 is located on the first main surface 23 side. The lower end 41b of the inclined portion 41 is located on the second main surface 24 side.

[0277] Upper end 41a of inclined portion 41 extends from SiC epitaxial layer 32 toward insulating layer 35 and is continuous with insulating layer 35. That is, SiC epitaxial layer 32 and insulating layer 35 are exposed from inclined portion 41. Also, a peripheral portion of insulating layer 35 is formed in an inner region of SiC semiconductor layer 22 with respect to side surfaces 25A-25D.

[0278] An upper end 41a of the inclined portion 41 is connected to the upper surface of the insulating layer 35. In the inclined portion 41, an upper connection portion 41c connecting the upper end 41a of the inclined portion 41 and the upper surface of the insulating layer 35 may be formed in a curved shape toward the outside of the SiC semiconductor layer 22. A lower end 41b of the inclined portion 41 is connected to the side surfaces 25A to 25D. The lower end 41b of the inclined portion 41 may be formed in a curved shape toward the second main surface 24.

[0279] The width WI of the inclined portion 41 may be equal to or smaller than the in-plane variation of the side surfaces 25A to 25D. The width WI of the inclined portion 41 may be less than the in-plane variation of the side surfaces 25A to 25D. The width WI of the inclined portion 41 is the width in a direction perpendicular to the direction in which the inclined portion 41 extends in a plan view.

[0280] The width WI of the inclined portion 41 may be more than 0 μm and not more than 10 μm. The width WI may be more than 0 μm and not more than 2 μm, 2 μm or more and not more than 4 μm, 4 μm or more and not more than 6 μm, 6 μm or more and not more than 8 μm, or 8 μm or more and not more than 10 μm. When the thickness of the SiC semiconductor layer 22 is 150 μm or less, the width WI of the inclined portion 41 is preferably more than 0 μm and not more than 5 μm. It is further preferable that the width WI of the inclined portion 41 is more than 0 μm and not more than 2.5 μm.

[0281] The depth D of the inclined portion 41 may be more than 0 μm and not more than 30 μm. The depth D of the inclined portion 41 is the distance from the first main surface 23 to the lower end of the inclined portion 41 in the normal direction N. The depth D of the inclined portion 41 may be more than 0 μm and not more than 5 μm, 5 μm or more and not more than 10 μm, 10 μm or more and not more than 15 μm, 15 μm or more and not more than 20 μm, 20 μm or more and not more than 25 μm, or 25 μm or more and not more than 30 μm. When the thickness of the SiC semiconductor layer 22 is 150 μm or less, the depth D of the inclined portion 41 is preferably more than 0 μm and not more than 15 μm.

[0282] The SiC semiconductor device 21 includes a modified layer 42 formed in an area on the first main surface 23 side of the side surfaces 25A-25D, in which SiC is modified to have another property. In this embodiment, the modified layer 42 is formed in the SiC epitaxial layer 32. More specifically, the modified layer 42 is formed in an area on the first main surface 23 side with respect to the boundary region between the SiC semiconductor substrate 31 and the SiC epitaxial layer 32.

[0283] The modified layer 42 is formed along the corners connecting the first main surface 23 and the side surfaces 25A-25D. More specifically, the modified layer 42 is formed at the corners connecting the first main surface 23 and the side surfaces 25A, 25C and extending along the [11-20] direction. The modified layer 42 is also formed at the corners connecting the first main surface 23 and the side surfaces 25B, 25D and extending along the [1-100] direction.

[0284] The modified layer 42 extends in a strip shape on the side surfaces 25A to 25D in a direction parallel to the first main surface 23. That is, the modified layer 42 extends in a strip shape along the [1-100] direction and the [11-20] direction. The modified layer 42 is formed in a ring shape (e.g., endless shape) surrounding the active region 33 on the side surfaces 25A to 25D.

[0285] The modified layer 42 is formed in the form of a film along the inclined portion 41 of the SiC semiconductor layer 22. The thickness of the portion of the modified layer 42 covering the bottom wall of the inclined portion 41 may be greater than the thickness of the portion of the modified layer 42 covering the side wall of the inclined portion 41. The modified layer 42 may be formed with a uniform thickness along the inner wall of the inclined portion 41.

[0286] The modified layer 42 includes an upper covering portion 42a and a lower covering portion 42b. The upper covering portion 42a of the modified layer 42 covers the upper end portion 41a of the inclined portion 41. The upper covering portion 42a of the modified layer 42 covers the SiC epitaxial layer 32. The upper covering portion 42a of the modified layer 42 extends from the SiC epitaxial layer 32 toward the insulating layer 35 and covers the insulating layer 35. The upper covering portion 42a of the modified layer 42 may be formed in a curved shape extending outward from the SiC semiconductor layer 22.

[0287] The lower covering portion 42b of the modified layer 42 covers the lower end portion 41b of the inclined portion 41. The lower covering portion 42b of the modified layer 42 covers the SiC epitaxial layer 32. The lower covering portion 42b of the modified layer 42 includes a connecting portion 42c connected to the side surfaces 25A to 25D. The connecting portion 42c of the modified layer 42 may be a cleaved portion of the modified layer 42. The connecting portion 42c of the modified layer 42 may be formed flush with the side surfaces 25A to 25D.

[0288] The modified layer 42 is exposed from a peripheral portion 46 of the resin layer 37. The peripheral portion 46 of the resin layer 37 is a portion where a dicing street was formed when the SiC semiconductor device 21 was cut out from the 4H-SiC crystal structure 1. By exposing the modified layer 42 from the resin layer 37, it is no longer necessary to physically cut the resin layer 37. Therefore, the SiC semiconductor device 21 can be smoothly cut out from the 4H-SiC crystal structure 1 while the active region 33 is appropriately protected by the resin layer 37.

[0289] The width WM of the modified layer 42 may be equal to or smaller than the in-plane variation of the side surfaces 25A to 25D. The width WM of the modified layer 42 may be smaller than the in-plane variation of the side surfaces 25A to 25D. The width WM of the modified layer 42 is the width in a direction perpendicular to the direction in which the modified layer 42 extends in a plan view.

[0290] The width WM of the modified layer 42 may be more than 0 μm and not more than 10 μm. The width WM of the modified layer 42 may be more than 0 μm and not more than 2 μm, 2 μm or more and not more than 4 μm, 4 μm or more and not more than 6 μm, 6 μm or more and not more than 8 μm, or 8 μm or more and not more than 10 μm. When the thickness of the SiC semiconductor layer 22 is 150 μm or less, the width WM of the modified layer 42 is preferably more than 0 μm and not more than 5 μm. The width WM of the modified layer 42 is more preferably more than 0 μm and not more than 2.5 μm.

[0291] The thickness T of the modified layer 42 may be more than 0 μm and not more than 30 μm. The thickness T of the modified layer 42 is the thickness along the normal direction N of the modified layer 42. The thickness T of the modified layer 42 may be more than 0 μm and not more than 5 μm, 5 μm or more and not more than 10 μm, 10 μm or more and not more than 15 μm, 15 μm or more and not more than 20 μm, 20 μm or more and not more than 25 μm, or 25 μm or more and not more than 30 μm. When the thickness of the SiC semiconductor layer 22 is not more than 150 μm, the thickness T of the modified layer 42 is preferably more than 0 μm and not more than 15 μm.

[0292] Fig. 21 is an enlarged view of region XXI shown in Fig. 17. Fig. 22 is a graph showing the configuration of the modified layer 42. Fig. 22 shows the results of examining the components of the SiC semiconductor layer 22 by Raman spectroscopy.

[0293] 21 shows a first region A, a second region B, and a third region C. The first region A shows a surface portion of the modified layer 42. The surface portion of the modified layer 42 is a region of the modified layer 42 located on the first main surface 23 side of the SiC semiconductor layer 22 (here, the upper covering portion 42a).

[0294] The second region B indicates the bottom of the modified layer 42. The bottom of the modified layer 42 is a region (here, the lower covering portion 42b) of the modified layer 42 that is located on the second main surface 24 side with respect to the surface portion of the modified layer 42. The third region C indicates a region of the SiC semiconductor layer 22 outside the modified layer 42 (here, the SiC epitaxial layer 32).

[0295] Fig. 22 shows a first curve LA, a second curve LB, and a third curve LC. The first curve LA shows the component of the first region A shown in Fig. 21. The second curve LB shows the component of the second region B shown in Fig. 21. The third curve LC shows the component of the third region C shown in Fig. 21.

[0296] The first curve LA has a peak value derived from Si (silicon) in the wavelength range of 500 nm to 550 nm, and the second curve LB has a peak value derived from Si (silicon) in the wavelength range of 500 nm to 550 nm, and a peak value derived from C (carbon) in the wavelength range of 1300 nm to 1700 nm.

[0297] The third curve LC has a peak value derived from SiC (silicon carbide) in the wavelength range of 750 nm or more and 800 nm or less. Therefore, in the third region C, the modified layer 42 is not formed, and only 4H-SiC single crystals are present.

[0298] With reference to the first curve LA, the silicon density of the surface portion (first region A) of the modified layer 42 is higher than the carbon density of the surface portion of the modified layer 42. That is, the surface portion of the modified layer 42 includes a Si modified layer in which SiC of the 4H—SiC crystal structure 1 is modified to Si. The Si modified layer may include Si polycrystals. The Si modified layer may include amorphous Si. The Si modified layer may include Si polycrystals and amorphous Si. The Si modified layer may include a Si amorphous layer as a main component.

[0299] With reference to the second curve LB, the silicon density at the bottom (second region B) of the modified layer 42 is higher than the carbon density at the bottom of the modified layer 42. The bottom of the modified layer 42 includes a Si modified layer in which SiC of the 4H—SiC crystal structure 1 is modified to Si. The Si modified layer may include Si polycrystals. The Si modified layer may include amorphous Si. The Si modified layer may include Si polycrystals and amorphous Si. The Si modified layer may include a Si amorphous layer as a main component.

[0300] With reference to the first curve LA and the second curve LB, the modified layer 42 has different components in the surface portion (first region A) and the bottom portion (second region B). More specifically, the modified layer 42 has different silicon densities along the thickness direction. The silicon density of the bottom portion of the modified layer 42 is lower than the silicon density of the surface portion of the modified layer 42. In addition, the modified layer 42 has different carbon densities along the thickness direction. The carbon density of the bottom portion of the modified layer 42 is higher than the carbon density of the surface portion of the modified layer 42.

[0301] FIG. 23 is a perspective view showing a 4H—SiC crystal structure 1 used in the manufacture of the SiC semiconductor device 21 shown in FIG.

[0302] 23, a manufacturing method for SiC semiconductor device 21 uses 4H—SiC crystal structure 1 having a stacked structure including SiC semiconductor wafer 51 and SiC epitaxial layer 52. SiC semiconductor wafer 51 serves as a base for SiC semiconductor substrate 31. SiC epitaxial layer 52 serves as a base for SiC epitaxial layer 32. SiC epitaxial layer 52 is formed by epitaxially growing SiC from SiC semiconductor wafer 51.

[0303] A first main surface 2 of the 4H—SiC crystal structure 1 is formed by a SiC epitaxial layer 52. A second main surface 3 of the 4H—SiC crystal structure 1 is formed by a SiC semiconductor wafer 51. A side surface 4 of the 4H—SiC crystal structure 1 is formed by the SiC semiconductor wafer 51 and the SiC epitaxial layer 52.

[0304] In the method for manufacturing the SiC semiconductor device 21, a plurality of device regions 53 corresponding to the SiC semiconductor device 21 are set on the first main surface 2 of the 4H—SiC crystal structure 1. The plurality of device regions 53 are set in a matrix array at intervals in the [1-100] direction and the [11-20] direction. Each of the plurality of device regions 53 has a side along the [1-100] direction and a side along the [11-20] direction.

[0305] The device regions 53 are partitioned by lattice-shaped cutting lines 54 extending along the [1-100] direction and the [11-20] direction. More specifically, the cutting lines 54 include a plurality of first cutting lines 55 and a plurality of second cutting lines 56. The first cutting lines 55 each extend along the [1-100] direction. The second cutting lines 56 each extend along the [11-20] direction.

[0306] After a predetermined structure has been formed in the 4H—SiC crystal structure 1, the 4H—SiC crystal structure 1 is cut along the lines to be cut 54, thereby cutting out a plurality of SiC semiconductor devices 21.

[0307] 24A to 24L are cross-sectional perspective views of a partial region of the 4H—SiC crystal structure 1 shown in FIG. 23, illustrating one example of a method for manufacturing the SiC semiconductor device 21 shown in FIG.

[0308] 24A to 24L show four device regions 53 as partial regions of 4H—SiC crystal structure 1. Also, Fig. 24I to Fig. 24K show enlarged end views of partial regions of device region 53 as viewed from the [1-100] direction. Fig. 24A to Fig. 24L incorporate the technical ideas described above in Fig. 9A to Fig. 9D.

[0309] First, with reference to FIG. 24A, the 4H—SiC crystal structure 1 shown in FIG. 23 is prepared.

[0310] 24B, a plurality of active regions 33 are formed in the plurality of device regions 53, respectively. The plurality of active regions 33 are formed by introducing p-type impurities and / or n-type impurities into the plurality of device regions 53, respectively.

[0311] Next, referring to Fig. 24C, an insulating layer 35 is formed on the first main surface 2 of the 4H-SiC crystal structure 1. The insulating layer 35 includes silicon oxide. The insulating layer 35 may be formed by a CVD method or a thermal oxidation treatment method. In this embodiment, the insulating layer 35 is formed by a thermal oxidation treatment on the first main surface 2.

[0312] 24D, unnecessary portions of the insulating layer 35 are removed. This forms a plurality of openings 39 in the insulating layer 35. Each opening 39 exposes an active area 33 of each device region 53. The unnecessary portions of the insulating layer 35 may be removed by an etching method through a mask (not shown).

[0313] Next, referring to FIG. 24E, the first electrode layer 36 is formed on the insulating layer 35. In the process of forming the first electrode layer 36, first, a conductive material is deposited on the insulating layer 35 by a sputtering method or a CVD method. Next, unnecessary portions of the conductive material are removed by an etching method using a mask (not shown). In this way, each first electrode layer 36 is formed in each device region 53.

[0314] Next, referring to FIG. 24F, a resin is applied onto the insulating layer 35 to form a resin layer 37 covering the first electrode layer 36.

[0315] 24G, the resin layer 37 is selectively exposed to light and then developed. As a result, the resin layer 37 having openings 40 exposing each of the first electrode layers 36 and a peripheral portion 46 exposing the cutting lines 54 is formed on the insulating layer 35. The peripheral portion 46 of the resin layer 37 defines the dicing street.

[0316] 24H, a second electrode layer 38 is formed on the second main surface 3 of the 4H—SiC crystal structure 1. The second electrode layer 38 is formed by depositing a conductive material on the second main surface 3 by a sputtering method or a CVD method.

[0317] 24I, the line to cut 54 is heated to form a modified layer 42 (first modified layer) in which SiC is modified to another property. Here, an example is shown in which the first line to cut 55 along the [1-100] direction is heated first.

[0318] More specifically, the step of forming the modified layer 42 includes a step of heating the line to be cut 54 to a temperature at which C atoms are desorbed or sublimated from SiC. As a result, the modified layer 42 is formed on the first main surface 2 of the 4H—SiC crystal structure 1.

[0319] The heating of the cutting line 54 may be performed by an ablation process using laser irradiation. In the ablation process, an ultraviolet laser may be used. The laser energy, the laser pulse duty ratio, and the laser irradiation speed are each set to any value depending on the size, shape, thickness, etc. of the modified layer 42 to be formed.

[0320] In the ablation processing method, the first main surface 2 is irradiated with laser light through the insulating layer 35. The insulating layer 35 is melted or sublimated by the irradiation of the laser light. As a result, the first main surface 2 is exposed from the insulating layer 35. In addition, the laser light is continuously irradiated to the portion of the first main surface 2 exposed from the insulating layer 35. As a result, a modified layer 42 is formed on the first main surface 2.

[0321] In this step, a recess 57 is formed which penetrates the insulating layer 35 and recesses from the first main surface 2 toward the second main surface 3. The recess 57 includes a bottom and a side. The recess 57 may be formed in a tapered shape in which the opening width narrows from the first main surface 2 toward the bottom. The bottom of the recess 57 may be formed in a curved shape toward the second main surface 3.

[0322] The width W of the recess 57 may be more than 0 μm and not more than 10 μm. The width W of the recess 57 is the width in a direction perpendicular to the direction in which the recess 57 extends. The width W of the recess 57 may be more than 0 μm and not more than 2.5 μm, 2.5 μm or more and not more than 5 μm, 5 μm or more and not more than 7.5 μm, or 7.5 μm or more and not more than 10 μm. When the thickness of the 4H—SiC crystal structure 1 is 150 μm or less, the width W of the recess 57 is preferably more than 0 μm and not more than 5 μm.

[0323] The modified layer 42 is formed in the form of a film along the inner wall of the recess 57. The thickness of the portion of the modified layer 42 covering the bottom wall of the recess 57 may be greater than the thickness of the portion of the modified layer 42 covering the side wall of the recess 57. The modified layer 42 may be formed along the inner wall of the recess 57 with a uniform thickness.

[0324] The modified layer 42 is also formed on the insulating layer 35 in the depression 57. That is, the modified layer 42 is formed so as to cover the insulating layer 35 in the depression 57. The modified layer 42 defines a recess 58 in the depression 57. More specifically, the recess 58 is defined by the outer surface of the modified layer 42.

[0325] The recess 58 includes a bottom and a side. The recess 58 may be formed in a tapered shape in which the opening width narrows from the first main surface 2 toward the bottom. The bottom of the recess 58 may be formed in a curved shape toward the second main surface 3. The recess 58 includes an opening side corner and a bottom side corner. The opening side corner of the recess 58 connects the upper surface of the insulating layer 35 and the side of the recess 58. The bottom side corner of the recess 58 connects the bottom of the recess 58 and the side of the recess 58.

[0326] The width WR of the recess 58 is less than the width W of the indentation 57. The width WR of the recess 58 may be more than 0 μm and less than 10 μm. The width WR of the recess 58 may be more than 0 μm and less than 2.5 μm, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, or 7.5 μm or more and less than 10 μm. When the thickness of the 4H—SiC crystal structure 1 is 150 μm or less, the width WR of the recess 58 is preferably more than 0 μm and less than 5 μm.

[0327] The depth DR of the recess 58 is less than the depth D of the dent 57. The depth DR of the recess 58 may be more than 0 μm and less than 30 μm. The depth DR of the recess 58 may be more than 0 μm and less than 5 μm, 5 μm or more and less than 10 μm, 10 μm or more and less than 15 μm, 15 μm or more and less than 20 μm, 20 μm or more and less than 25 μm, or 25 μm or more and less than 30 μm. When the thickness of the 4H—SiC crystal structure 1 is 150 μm or less, the depth DR of the recess 58 is preferably more than 0 μm and less than 15 μm.

[0328] Next, referring to Fig. 24J, the second line to cut 56 along the [11-20] direction is heated in the same manner as in Fig. 24I. As a result, the modified layer 42 (second modified layer), the depression 57, and the recess 58 are formed in the second line to cut 56.

[0329] The modified layer 42, the depression 57, and the recess 58 along the first line to cut 55 form a first cleavage line 61 for cleaving the 4H—SiC crystal structure 1 along the [1-100] direction. The modified layer 42, the depression 57, and the recess 58 along the second line to cut 56 form a second cleavage line 62 for cleaving the 4H—SiC crystal structure 1 along the [11-20] direction.

[0330] In this process, the process of forming the second cleavage lines 62 after forming the first cleavage lines 61 has been described. However, the order of forming the first cleavage lines 61 and the second cleavage lines 62 is arbitrary and is not limited to the above order. For example, the first cleavage lines 61 may be formed after the second cleavage lines 62 are formed. In addition, any first cleavage lines 55 and any second cleavage lines 56 may be selected, and the first cleavage lines 61 and the second cleavage lines 62 may be formed alternately.

[0331] Next, referring to FIG. 24K, after the step of forming the modified layer 42, the corners of the modified layer 42 may be rounded. More specifically, the outer surface of the modified layer 42 may be flattened by removing irregularities from the outer surface of the modified layer 42. The modified layer 42 may be removed by an etching method. The etching method may be a dry etching method or a wet etching method. The modified layer 42 may be removed by a plasma etching method, which is an example of a dry etching method.

[0332] The modified layer 42 has a different component from the 4H—SiC crystal structure 1. The etching rate (etching selectivity) for the modified layer 42 is different from the etching rate (etching selectivity) for SiC. In addition, the modified layer 42 has a different component from the insulating layer 35. The etching rate (etching selectivity) for the modified layer 42 is different from the etching rate (etching selectivity) for the insulating layer 35.

[0333] Therefore, a part of the modified layer 42 can be removed while leaving the 4H—SiC crystal structure 1 and the insulating layer 35. As a result, the corners on the opening side of the recess 58 are rounded inwardly of the recess 58. Also, the corners on the bottom side of the recess 58 are rounded inwardly of the recess 58.

[0334] The recess 58 with rounded opening corners can alleviate stress concentration on the modified layer 42 at the opening corners. Also, the recess 58 with rounded bottom corners can alleviate stress concentration on the modified layer 42 at the bottom corners. This can suppress undesirable cracks caused by stress on the modified layer 42. In the step of FIG. 24K, the technical ideas of FIGS. 8A to 8D may be incorporated to remove the entire modified layer 42.

[0335] Next, with reference to Fig. 24L, the 4H-SiC crystal structure 1 is cleaved along the first cleavage line 61 ([1-100] direction) and the second cleavage line 62 ([11-20] direction). Hereinafter, with reference to Figs. 25A to 25D, the cleavage step of the 4H-SiC crystal structure 1 will be specifically described.

[0336] 25A to 25D are perspective views showing the 4H—SiC crystal structure 1 shown in FIG. 23, and are perspective views for explaining an example of the cleavage step of FIG. 24L.

[0337] 25A, in this step, first, the 4H-SiC crystal structure 1 is cleaved along a direction intersecting the nearest-neighbor atomic directions. That is, the 4H-SiC crystal structure 1 is cleaved along a first cleavage line 61 ([1-100] direction). More specifically, the 4H-SiC crystal structure 1 is cleaved in sequence along any first cleavage line 61 selected from a plurality of first cleavage lines 61.

[0338] The 4H—SiC crystal structure 1 may be cleaved by applying stress to the first cleavage line 61. In this step, a step of applying thermal stress to the first cleavage line 61 by heating and cooling is performed.

[0339] The heating process of the first cleavage line 61 may be performed by a laser irradiation method. The laser irradiation method may be performed by an infrared laser (for example, a CO2 laser). The heating process of the first cleavage line 61 thermally induces a compressive stress starting from the first cleavage line 61. The laser energy, the laser pulse duty ratio, and the laser irradiation speed are each set to any value according to the magnitude of the stress to be applied to the first cleavage line 61.

[0340] The step of cooling the first cleavage line 61 may include a step of supplying a cooling fluid to the first cleavage line 61. The cooling fluid may include water or air, or a mixture of water and air (aerosol). The step of cooling the first cleavage line 61 thermally induces a tensile stress originating from the first cleavage line 61.

[0341] The step of supplying the cooling fluid may include a step of injecting (spraying) the cooling fluid by a coolant jet method or a cooling gas supply method. The step of cooling the first cleavage line 61 may be performed after the step of heating the first cleavage line 61. The step of cooling the first cleavage line 61 may be performed simultaneously with the step of heating the first cleavage line 61.

[0342] The compressive stress generated in the heating process of the first cleavage line 61 and the tensile stress generated in the cooling process of the first cleavage line 61 cause the 4H—SiC crystal structure 1 to be cleaved along the first cleavage line 61 ([1-100] direction).

[0343] 25B, the 4H—SiC crystal structure 1 is divided into a plurality of rectangular portions extending along the [1-100] direction. Each of the rectangular portions includes a plurality of device regions 53 arranged in a line along the [1-100] direction.

[0344] 25C, the 4H-SiC crystal structure 1 is cleaved along the nearest-neighbor atomic direction. That is, the 4H-SiC crystal structure 1 is cleaved along the second cleavage lines 62 ([11-20] direction). More specifically, the 4H-SiC crystal structure 1 is cleaved in sequence along any second cleavage line 62 selected from the plurality of second cleavage lines 62.

[0345] The 4H—SiC crystal structure 1 may be cleaved by applying stress to the second cleavage line 62. In this step, a step of applying thermal stress to the second cleavage line 62 by heating and cooling is performed.

[0346] The heating process of the second cleavage line 62 may be performed by a laser irradiation method. The laser irradiation method may be performed by an infrared laser (for example, a CO2 laser). The heating process of the second cleavage line 62 thermally induces a compressive stress starting from the second cleavage line 62. The laser energy, the laser pulse duty ratio, and the laser irradiation speed are each set to any value according to the magnitude of the stress to be applied to the second cleavage line 62.

[0347] The step of cooling the second cleavage line 62 may include the step of supplying a cooling fluid to the second cleavage line 62. The cooling fluid may include water or air, or a mixture of water and air (aerosol). The step of cooling the second cleavage line 62 thermally induces a tensile stress originating from the second cleavage line 62.

[0348] The supply of the cooling fluid may be performed by injecting (spraying) the cooling fluid using a coolant jet method or a cooling gas supply method. The cooling step of the second cleavage line 62 may be performed after the heating step of the second cleavage line 62. The cooling step of the second cleavage line 62 may be performed simultaneously with the heating step of the second cleavage line 62.

[0349] The compressive stress generated in the heating step of the second cleavage line 62 and the tensile stress generated in the cooling step of the second cleavage line 62 cause the 4H—SiC crystal structure 1 to be cleaved along the second cleavage line 62 ([11-20] direction).

[0350] 25D, a plurality of SiC semiconductor devices 21 are cut out from a plurality of rectangular portions extending along the [1-100] direction. Through the steps including those described above, the SiC semiconductor device 21 is manufactured.

[0351] Fig. 26 is a plan view for explaining the planar shape of SiC semiconductor device 71 individualized through the manufacturing method of SiC semiconductor device 71 according to the reference example. Fig. 27 is a plan view for explaining the planar shape of SiC semiconductor device 21 shown in Fig. 17 individualized through the manufacturing method of Figs. 25A to 25D.

[0352] In the method for manufacturing a SiC semiconductor device 71 according to the reference example, the 4H-SiC crystal structure 1 is cleaved (thermally cleaved) along the second cleavage line 62 ([11-20] direction), and then the 4H-SiC crystal structure 1 is cleaved (thermally cleaved) along the first cleavage line 61 ([1-100] direction). That is, in the method for manufacturing a SiC semiconductor device 71 according to the reference example, after a cleavage step in the nearest neighbor atomic direction, a cleavage step in a direction intersecting the nearest neighbor atomic direction is carried out.

[0353] 26, in the SiC semiconductor device 71 according to the reference example, the side surfaces 25A, 25C along the [11-20] direction are formed relatively flat. In the cleavage process in the [11-20] direction, the 4H-SiC crystal structure 1 is cleaved along the nearest-neighbor atomic direction, and at the same time, the stress (thermal stress) generated in the 4H-SiC crystal structure 1 continues continuously. Therefore, the generation of a protuberance in the cleavage portion is suppressed.

[0354] On the other hand, the side surfaces 25B and 25D along the [1-100] direction have meanders 72 that protrude relatively greatly along the [11-20] direction. Of the side surfaces 25A to 25D, the in-plane variation of the side surfaces 25B and 25D along the [1-100] direction exceeds 20 μm.

[0355] In the cleavage process in the [1-100] direction, the 4H-SiC crystal structure 1 is cleaved along a direction intersecting the nearest-neighbor atomic direction. Moreover, since the 4H-SiC crystal structure 1 has already been cleaved along the [11-20] direction, the stress (thermal stress) applied to the 4H-SiC crystal structure 1 cannot be continuously applied.

[0356] As a result, a force (force along the [11-20] direction) that maintains the Si atomic arrangement acts from the side surfaces 25A and 25C, forming a relatively large protruding meander 72 on the side surfaces 25B and 25D. Such meander 72 tends to originate particularly from a connection portion 73 between the side surfaces 25A and 25C formed by the first cleavage step and the side surfaces 25B and 25D formed by the second cleavage step. In the SiC semiconductor device 71 according to the reference example, the meander 72 worsens the in-plane variation of the side surfaces 25B and 25D.

[0357] The in-plane variation is defined by the maximum value of the distance between a reference virtual line 74 and a measurement virtual line 75 that are set on one of the side surfaces 25A-25D selected from the side surfaces 25A-25D. The reference virtual line 74 is a straight line that connects two corners of the SiC semiconductor layer 22 in a plan view, and is set on the selected one of the side surfaces 25A-25D. The measurement virtual line 75 is a straight line that extends parallel to the reference virtual line 74 in a plan view, and is set so as to be in contact with the top or base of a protuberance (meander 72) present on the selected one of the side surfaces 25A-25D.

[0358] For example, the distance between the reference virtual line 74 and the measurement virtual line 75 that touches the top of the ridge (meander 72), and the distance between the reference virtual line 74 and the measurement virtual line 75 that touches the base of the ridge (meander 72) are measured. The maximum value of the measured distances between the reference virtual line 74 and the measurement virtual line 75 defines the in-plane variation of the selected one of the side surfaces 25A-25D.

[0359] The distance between adjacent device regions 53 in the [11-20] and [1-100] directions is set in consideration of the meandering 72 (in-plane variation). Therefore, when a relatively large meandering 72 (in-plane variation) is formed, it is necessary to increase the distance between the device regions 53 in order to suppress contact between adjacent SiC semiconductor devices 71. Therefore, the number of SiC semiconductor devices 71 that can be obtained from one 4H—SiC crystal structure 1 is limited by the meandering 72 (in-plane variation).

[0360] 27, in the method for manufacturing SiC semiconductor device 21, 4H-SiC crystal structure 1 is cleaved (thermally cleaved) along first cleavage line 61 ([1-100] direction), and then cleaved (thermally cleaved) along second cleavage line 62 ([11-20] direction). That is, in the method for manufacturing SiC semiconductor device 21, a cleavage step in the nearest neighbor atomic direction is carried out after a cleavage step in the direction intersecting the nearest neighbor atomic direction.

[0361] In the cleavage process in the [1-100] direction, the 4H-SiC crystal structure 1 is cleaved in a direction intersecting the nearest-neighbor atomic direction, but since the stress (thermal stress) applied to the 4H-SiC crystal structure 1 is continuous, the occurrence of protrusions at the cleavage portion is suppressed.

[0362] On the other hand, in the cleavage process in the [11-20] direction, since the 4H-SiC crystal structure 1 has already been cleaved along the [1-100] direction, the stress (thermal stress) applied to the 4H-SiC crystal structure 1 becomes discontinuous. However, in this process, stress (thermal stress) is applied to the 4H-SiC crystal structure 1 along the nearest atom direction ([11-20] direction), and the 4H-SiC crystal structure 1 is cleaved along the nearest atom direction ([11-20] direction). This suppresses the occurrence of protrusions at the cleavage portion.

[0363] In particular, this process sequence suppresses the occurrence of meandering 72 originating from connection portion 73 connecting side surfaces 25A, 25C and side surfaces 25B, 25D. As a result, an in-plane variation of 20 μm or less, more specifically, 10 μm or less can be achieved in side surfaces 25A to 25D. Furthermore, this process sequence also enables an in-plane variation of 20 μm or less, more specifically, 10 μm or less to be achieved in side surfaces 25B and 25D along the [1-100] direction. Therefore, the flatness of all side surfaces 25A to 25D can be improved.

[0364] In addition, since the meandering 72 can be suppressed, the distance between adjacent device regions 53 in the [11-20] direction and the [1-100] direction can be narrowed, thereby increasing the number of SiC semiconductor devices 21 that can be obtained from one 4H—SiC crystal structure 1.

[0365] 26 and 27, it can be seen that the linearity of cleavage is stable regardless of the crystal direction when the stress (thermal stress) applied to the 4H-SiC crystal structure 1 is continuous. On the other hand, it can be seen that the linearity of cleavage becomes unstable in the direction intersecting the nearest atomic direction when the stress (thermal stress) applied to the 4H-SiC crystal structure 1 is discontinuous.

[0366] This phenomenon is particularly evident in semiconductor materials with relatively high thermal conductivity among the various semiconductor materials used in semiconductor devices. In particular, SiC has a relatively high thermal conductivity compared to that of single crystal silicon (Si), sapphire (Al2O3), and gallium nitride (GaN).

[0367] The thermal conductivity of SiC is between 4.5W / cmK and 5.5W / cmK (more specifically, about 4.9W / cmK). The thermal conductivity of Si is about 1.5W / cmK. The thermal conductivity of sapphire (Al2O3) is about 0.4W / cmK. The thermal conductivity of gallium nitride (GaN) is about 2.0W / cmK.

[0368] That is, compared to silicon single crystal (Si), sapphire (Al2O3), gallium nitride (GaN), etc., SiC has a property that the stress (thermal stress) caused by heat dissipation is easily discontinuous. Therefore, in SiC, the risk of in-plane variation increases in the cleavage process in the direction intersecting the nearest neighbor atomic direction when the stress (thermal stress) is discontinuous. Therefore, the order of performing the cleavage process in the nearest neighbor atomic direction after the cleavage process in the direction intersecting the nearest neighbor atomic direction is particularly effective for SiC, which has a relatively high thermal conductivity.

[0369] 26 and 27, a case will be considered in which SiC semiconductor layer 22 has side surfaces 25A and 25C that form short sides of a rectangle and side surfaces 25B and 25D that form long sides of a rectangle in a plan view. In this case, side surfaces 25B and 25D have areas that exceed the areas of side surfaces 25A and 25C.

[0370] Therefore, when there are side surfaces having a relatively large area, it is preferable to determine in advance the orientation of the multiple device regions 53 relative to the crystal direction so that the stress (thermal stress) is continuously transmitted in the second cutting step. That is, it is preferable that the side surfaces 25A and 25C forming the short sides of the rectangle are formed along the [1-100] direction, and the side surfaces 25B and 25D forming the long sides of the rectangle are formed along the [11-20] direction.

[0371] In this case, first, the 4H-SiC crystal structure 1 is cut along the [1-100] direction to form the side surfaces 25A and 25C that form the short sides of the rectangle, and then, the 4H-SiC crystal structure 1 is cut along the [11-20] direction to form the side surfaces 25B and 25D that form the long sides of the rectangle.

[0372] According to this process order, the continuity of the stress (thermal stress) can be increased in the second cutting process, and therefore the flatness can be increased on the side surfaces 25B and 25D, which have relatively large areas. Therefore, when cutting the rectangular device region 53, it is preferable to set the short side of the device region 53 in the [1-100] direction and the long side of the device region 53 in the [11-20] direction.

[0373] As described above, according to this embodiment, a crystal cutting method can be provided that can appropriately cut a hexagonal 4H—SiC crystal structure 1 from two different directions. Also, according to this embodiment, a manufacturing method for a SiC semiconductor device using the crystal cutting method can be provided. Moreover, by such a manufacturing method for a SiC semiconductor device, a SiC semiconductor device 21 can be manufactured and provided.

[0374] Fig. 28 is a cross-sectional view of a region corresponding to Fig. 19, showing a schematic configuration of a SiC semiconductor device 91 according to a twelfth embodiment of the present invention. In the following, structures corresponding to those described with respect to the SiC semiconductor device 21 are given the same reference numerals, and descriptions thereof will be omitted.

[0375] 28, SiC semiconductor device 91 is manufactured by a manufacturing method in which the technical idea described with reference to Figs. 10A to 10D is incorporated into the steps of Figs. 24A to 24L. More specifically, SiC semiconductor device 91 does not have modified layer 42. In SiC semiconductor device 91, only inclined portion 41 is formed at the corner portion of SiC semiconductor layer 22.

[0376] As described above, even when manufacturing the SiC semiconductor device 91, the same effects as those described in the eleventh embodiment can be achieved.

[0377] Fig. 29 is a cross-sectional view of a region corresponding to Fig. 19, showing a schematic configuration of a SiC semiconductor device 92 according to a thirteenth embodiment of the present invention. In the following, structures corresponding to those described with respect to the SiC semiconductor device 21 are given the same reference numerals and will not be described.

[0378] 29, SiC semiconductor device 92 is manufactured by a manufacturing method in which the technical idea described with reference to Figures 11A to 11D is incorporated into the steps of Figures 24A to 24L. In the steps of Figures 24A to 24L, the step of Figure 24K does not necessarily have to be performed.

[0379] More specifically, the SiC semiconductor device 92 includes an inclined portion 41 and a modified layer 42 that reach the SiC semiconductor substrate 31. The inclined portion 41 reaches the SiC semiconductor substrate 31 across the boundary region between the SiC semiconductor substrate 31 and the SiC epitaxial layer 32. The SiC semiconductor substrate 31, the SiC epitaxial layer 32, and the insulating layer 35 are exposed from the inclined portion 41. A lower end 41b of the inclined portion 41 is located within the SiC semiconductor substrate 31. The lower end 41b of the inclined portion 41 may be formed in a curved shape toward the second main surface 24.

[0380] The modified layer 42 is formed in a film shape along the inclined portion 41 of the SiC semiconductor layer 22. The modified layer 42 crosses the boundary region between the SiC semiconductor substrate 31 and the SiC epitaxial layer 32 and reaches the SiC semiconductor substrate 31. The modified layer 42 is in contact with the SiC semiconductor substrate 31, the SiC epitaxial layer 32, and the insulating layer 35.

[0381] The lower covering portion 42b of the modified layer 42 covers the SiC semiconductor substrate 31. The lower covering portion 42b of the modified layer 42 includes a connecting portion 42c connected to the side surfaces 25A to 25D. The connecting portion 42c of the modified layer 42 may be a cleaved portion of the modified layer 42. The connecting portion 42c of the modified layer 42 may be formed flush with the side surfaces 25A to 25D.

[0382] As described above, even when manufacturing the SiC semiconductor device 92, the same effects as those described in the eleventh embodiment can be achieved.

[0383] Fig. 30 is a cross-sectional view of a region corresponding to Fig. 19, showing a schematic configuration of a SiC semiconductor device 93 according to a fourteenth embodiment of the present invention. In the following, structures corresponding to those described with respect to the SiC semiconductor device 21 are given the same reference numerals, and descriptions thereof will be omitted.

[0384] 30, SiC semiconductor device 93 is manufactured by a manufacturing method in which the technical idea described with reference to the above-mentioned FIGS. 12A to 12D is incorporated into the steps of the above-mentioned FIGS. 24A to 24L.

[0385] More specifically, the SiC semiconductor device 93 does not have a modified layer 42. In the SiC semiconductor device 93, only an inclined portion 41 is formed at a corner portion of the SiC semiconductor layer 22. The inclined portion 41 crosses the boundary region between the SiC semiconductor substrate 31 and the SiC epitaxial layer 32 and reaches the SiC semiconductor substrate 31.

[0386] A lower end 41b of the inclined portion 41 is located within the SiC semiconductor substrate 31. The lower end 41b of the inclined portion 41 may be formed in a curved shape toward the second main surface 24. From the inclined portion 41, the SiC semiconductor substrate 31, the SiC epitaxial layer 32, and the insulating layer 35 are exposed.

[0387] As described above, even when manufacturing the SiC semiconductor device 93, the same effects as those described in the eleventh embodiment can be achieved.

[0388] Fig. 31 is a cross-sectional view of a region corresponding to Fig. 19, showing a schematic configuration of a SiC semiconductor device 94 according to a fifteenth embodiment of the present invention. In the following, structures corresponding to those described with respect to the SiC semiconductor device 21 are given the same reference numerals and will not be described.

[0389] 31, SiC semiconductor device 94 does not have inclined portions 41 at the corners of SiC semiconductor layer 22. SiC semiconductor device 94 includes modified layers 42 formed in the middle of SiC semiconductor layer 22 in the thickness direction on side surfaces 25A-25D.

[0390] More specifically, the modified layer 42 is formed in the middle of the SiC epitaxial layer 32 in the thickness direction on the side surfaces 25A to 25D. The modified layer 42 is formed in the SiC epitaxial layer 32 with a gap therebetween from the first main surface 23 toward the second main surface 24. The modified layer 42 is formed in the SiC epitaxial layer 32 with a gap therebetween from the boundary region between the SiC semiconductor substrate 31 and the SiC epitaxial layer 32 toward the first main surface 23.

[0391] Such modified layer 42 is formed by adjusting the focal point of the laser light in the steps of Figures 24J and 24I described above. In this case, modified layer 42 is heated and cooled from the second main surface 3 side of 4H-SiC crystal structure 1, and 4H-SiC crystal structure 1 is cleaved. The step of Figure 24K does not necessarily have to be performed.

[0392] As described above, even when manufacturing the SiC semiconductor device 94, the same effects as those described in the eleventh embodiment can be achieved.

[0393] Fig. 32 is a cross-sectional view of a region corresponding to Fig. 19, showing a schematic configuration of a SiC semiconductor device 95 according to a sixteenth embodiment of the present invention. In the following, structures corresponding to those described with respect to the SiC semiconductor device 21 are given the same reference numerals and will not be described.

[0394] 32, SiC semiconductor device 95 does not have inclined portions 41 at the corners of SiC semiconductor layer 22. SiC semiconductor device 95 includes modified layers 42 formed in the middle of SiC semiconductor layer 22 in the thickness direction on side surfaces 25A-25D.

[0395] The modified layer 42 has an upper end on the first main surface 23 side and a lower end on the second main surface 24 side. The upper end of the modified layer 42 is formed on the SiC epitaxial layer 32 with a gap between it and the first main surface 23 toward the second main surface 24. The lower end of the modified layer 42 is formed on the SiC semiconductor substrate 31, crossing the boundary region between the SiC semiconductor substrate 31 and the SiC epitaxial layer 32.

[0396] Such modified layer 42 is formed by adjusting the focal point of the laser light in the steps of Figures 24J and 24I described above. In this case, modified layer 42 is heated and cooled from the second main surface 3 side of 4H-SiC crystal structure 1, and 4H-SiC crystal structure 1 is cleaved. The step of Figure 24K does not necessarily have to be performed.

[0397] As described above, even when manufacturing the SiC semiconductor device 95, the same effects as those described in the eleventh embodiment can be achieved.

[0398] Fig. 33 is a cross-sectional view of a region corresponding to Fig. 19, showing a schematic configuration of a SiC semiconductor device 96 according to a seventeenth embodiment of the present invention. In the following, structures corresponding to those described with respect to the SiC semiconductor device 21 are given the same reference numerals, and descriptions thereof will be omitted.

[0399] 33, SiC semiconductor device 96 is manufactured by a manufacturing method in which the technical idea described with reference to Figures 13A to 13D is incorporated into the steps of Figures 24A to 24L. In the steps of Figures 24A to 24L, the step of Figure 24K does not necessarily have to be performed.

[0400] More specifically, the SiC semiconductor device 96 includes an inclined portion 41 and a modified layer 42 formed in a region on the second main surface 24 side of the SiC semiconductor layer 22 on the side surfaces 25A to 25D.

[0401] The inclined portions 41 are formed at corners connecting the second main surface 24 and the side surfaces 25A to 25D. The corners of the SiC semiconductor layer 22 include corners that connect the second main surface 24 and the side surfaces 25A, 25C and extend along the [11-20] direction. The corners of the SiC semiconductor layer 22 include corners that connect the second main surface 24 and the side surfaces 25B, 25D and extend along the [1-100] direction. The inclined portions 41 are inclined downward from the second main surface 24 toward the side surfaces 25A to 25D.

[0402] The inclined portion 41 is formed by an inner wall of a recess that is recessed from the second main surface 24 toward the first main surface 23 at a corner of the SiC semiconductor layer 22. The inclined portion 41 is formed in the SiC semiconductor substrate 31. More specifically, the inclined portion 41 is formed in a region on the second main surface 24 side with respect to a boundary region between the SiC semiconductor substrate 31 and the SiC epitaxial layer 32.

[0403] The inclined portion 41 has an upper end 41d and a lower end 41e. The upper end 41d of the inclined portion 41 is located on the first main surface 23 side of the SiC semiconductor layer 22. The upper end 41d of the inclined portion 41 is continuous with the side surfaces 25A to 25D. The upper end 41d of the inclined portion 41 may be formed in a curved shape toward the first main surface 23. The lower end 41e of the inclined portion 41 is located on the second main surface 24 side of the SiC semiconductor layer 22. The lower end 41e of the inclined portion 41 is connected to the second main surface 24 of the SiC semiconductor layer 22.

[0404] The width WI of the inclined portion 41 may be equal to or smaller than the in-plane variation of the side surfaces 25A to 25D. The width WI of the inclined portion 41 may be less than the in-plane variation of the side surfaces 25A to 25D. The width WI of the inclined portion 41 is the width in a direction perpendicular to the direction in which the inclined portion 41 extends in a plan view.

[0405] The width WI of the inclined portion 41 may be more than 0 μm and not more than 10 μm. The width WI of the inclined portion 41 may be more than 0 μm and not more than 2.5 μm, 2.5 μm or more and not more than 5 μm, 5 μm or more and not more than 7.5 μm, or 7.5 μm or more and not more than 10 μm. When the thickness of the SiC semiconductor layer 22 is 150 μm or less, the width WI of the inclined portion 41 is preferably more than 0 μm and not more than 5 μm. The width WI of the inclined portion 41 is more preferably more than 0 μm and not more than 2.5 μm.

[0406] The depth D of the inclined portion 41 may be more than 0 μm and not more than 30 μm. The depth D of the inclined portion 41 is the distance from the second main surface 24 to the upper end of the inclined portion 41 in the normal direction N. The depth D of the inclined portion 41 may be more than 0 μm and not more than 5 μm, 5 μm or more and not more than 10 μm, 10 μm or more and not more than 15 μm, 15 μm or more and not more than 20 μm, 20 μm or more and not more than 25 μm, or 25 μm or more and not more than 30 μm. When the thickness of the SiC semiconductor layer 22 is 150 μm or less, the depth D of the inclined portion 41 is preferably more than 0 μm and not more than 15 μm.

[0407] The modified layer 42 is formed on the SiC semiconductor substrate 31. More specifically, the modified layer 42 is formed in a region on the second main surface 24 side of the SiC semiconductor layer 22 with respect to the boundary region between the SiC semiconductor substrate 31 and the SiC epitaxial layer 32. The modified layer 42 is formed along a corner portion connecting the second main surface 24 and the side surfaces 25A to 25D. The modified layer 42 is formed in a corner portion connecting the second main surface 24 and the side surfaces 25A, 25C and extending along the [11-20] direction. The modified layer 42 is formed in a corner portion connecting the second main surface 24 and the side surfaces 25B, 25D and extending along the [1-100] direction.

[0408] In this embodiment, the modified layer 42 extends in a strip shape on the side surfaces 25A to 25D in a direction parallel to the second main surface 24. That is, the modified layer 42 extends in a strip shape along the [1-100] direction and the [11-20] direction. The modified layer 42 is formed in an annular (endless) shape surrounding the active region 33 on the side surfaces 25A to 25D.

[0409] The modified layer 42 is formed in the form of a film along the inclined portion 41 of the SiC semiconductor layer 22. The thickness of the portion of the modified layer 42 covering the bottom wall of the inclined portion 41 may be greater than the thickness of the portion of the modified layer 42 covering the side wall of the inclined portion 41. The modified layer 42 may be formed with a uniform thickness along the inner wall of the inclined portion 41.

[0410] The modified layer 42 includes an upper covered portion 42d and a lower covered portion 42e. The upper covered portion 42d of the modified layer 42 covers the upper end portion 41d of the inclined portion 41. The lower covered portion 42e of the modified layer 42 covers the lower end portion 41e of the inclined portion 41.

[0411] The upper covering portion 42d of the modified layer 42 includes a connecting portion 42f connected to the side surfaces 25A to 25D. The connecting portion 42f of the modified layer 42 may be a cleaved portion of the modified layer 42. The connecting portion 42f of the modified layer 42 may be formed flush with the side surfaces 25A to 25D.

[0412] The width WM of the modified layer 42 may be equal to or smaller than the in-plane variation of the side surfaces 25A to 25D. The width WM of the modified layer 42 may be smaller than the in-plane variation of the side surfaces 25A to 25D. The width WM of the modified layer 42 is the width in a direction perpendicular to the direction in which the modified layer 42 extends in a plan view.

[0413] The width WM of the modified layer 42 may be more than 0 μm and not more than 10 μm. The width WM of the modified layer 42 may be more than 0 μm and not more than 2 μm, 2 μm or more and not more than 4 μm, 4 μm or more and not more than 6 μm, 6 μm or more and not more than 8 μm, or 8 μm or more and not more than 10 μm. When the thickness of the SiC semiconductor layer 22 is 150 μm or less, the width WM of the modified layer 42 is preferably more than 0 μm and not more than 5 μm. The width WM of the modified layer 42 is more preferably more than 0 μm and not more than 2.5 μm.

[0414] The thickness T of the modified layer 42 may be more than 0 μm and not more than 30 μm. The thickness T of the modified layer 42 is the thickness along the normal direction N of the modified layer 42. The thickness T of the modified layer 42 may be more than 0 μm and not more than 5 μm, 5 μm or more and not more than 10 μm, 10 μm or more and not more than 15 μm, 15 μm or more and not more than 20 μm, 20 μm or more and not more than 25 μm, or 25 μm or more and not more than 30 μm. When the thickness of the SiC semiconductor layer 22 is not more than 150 μm, the thickness T of the modified layer 42 is preferably more than 0 μm and not more than 15 μm.

[0415] The second electrode layer 38 exposes the modified layer 42 at the second main surface 24 of the SiC semiconductor layer 22. That is, the peripheral portion of the second electrode layer 38 is formed in an inner region of the SiC semiconductor layer 22 with respect to the side surfaces 25A-25D. The modified layer 42 extends from the inclined portion 41 toward the second electrode layer 38 and may have a covering portion that covers the second electrode layer 38.

[0416] As described above, even when manufacturing the SiC semiconductor device 96, the same effects as those described in the eleventh embodiment can be achieved.

[0417] Fig. 34 is a cross-sectional view of a region corresponding to Fig. 19, showing a schematic configuration of a SiC semiconductor device 97 according to an 18th embodiment of the present invention. In the following, structures corresponding to those described with respect to the SiC semiconductor device 21 are given the same reference numerals and will not be described.

[0418] 34, SiC semiconductor device 97 is manufactured by a manufacturing method in which the technical idea described with reference to the above-mentioned FIGS. 14A to 14D is incorporated into the steps of the above-mentioned FIGS. 24A to 24L.

[0419] More specifically, the SiC semiconductor device 97 does not have a modified layer 42. The SiC semiconductor device 97 includes an inclined portion 41 formed in a region on the second main surface 24 side of the SiC semiconductor layer 22 in the side surfaces 25A to 25D.

[0420] Inclined portions 41 are formed at corners connecting second main surface 24 and side surfaces 25A-25D. The corners of SiC semiconductor layer 22 include corners that connect second main surface 24 and side surfaces 25A, 25C and extend along the [11-20] direction. The corners of SiC semiconductor layer 22 include corners that connect second main surface 24 and side surfaces 25B, 25D and extend along the [1-100] direction.

[0421] Inclined portion 41 slopes downward from second main surface 24 toward side surfaces 25A-25D. Inclined portion 41 is formed at a corner portion of SiC semiconductor layer 22 by an inner wall of a recess that is recessed from second main surface 24 toward first main surface 23.

[0422] The inclined portion 41 is formed in the SiC semiconductor substrate 31. More specifically, the inclined portion 41 is formed in a region on the second main surface 24 side with respect to a boundary region between the SiC semiconductor substrate 31 and the SiC epitaxial layer 32.

[0423] The inclined portion 41 has an upper end 41d and a lower end 41e. The upper end 41d of the inclined portion 41 is located on the first main surface 23 side. The lower end 41e of the inclined portion 41 is located on the second main surface 24 side. The upper end 41d of the inclined portion 41 is continuous with the side surfaces 25A to 25D. The upper end 41d of the inclined portion 41 may be formed in a curved shape toward the first main surface 23. The lower end 41e of the inclined portion 41 is connected to the second main surface 24.

[0424] The width WI of the inclined portion 41 may be equal to or smaller than the in-plane variation of the side surfaces 25A to 25D. The width WI of the inclined portion 41 may be less than the in-plane variation of the side surfaces 25A to 25D. The width WI of the inclined portion 41 is the width in a direction perpendicular to the direction in which the inclined portion 41 extends in a plan view.

[0425] The width WI of the inclined portion 41 may be more than 0 μm and not more than 10 μm. The width WI of the inclined portion 41 may be more than 0 μm and not more than 2.5 μm, 2.5 μm or more and not more than 5 μm, 5 μm or more and not more than 7.5 μm, or 7.5 μm or more and not more than 10 μm. When the thickness of the SiC semiconductor layer 22 is 150 μm or less, the width WI of the inclined portion 41 is preferably more than 0 μm and not more than 5 μm. The width WI of the inclined portion 41 is more preferably more than 0 μm and not more than 2.5 μm.

[0426] The depth D of the inclined portion 41 may be more than 0 μm and not more than 30 μm. The depth D of the inclined portion 41 is the distance from the first main surface 23 to the lower end of the inclined portion 41 in the normal direction N. The depth D of the inclined portion 41 may be more than 0 μm and not more than 5 μm, 5 μm or more and not more than 10 μm, 10 μm or more and not more than 15 μm, 15 μm or more and not more than 20 μm, 20 μm or more and not more than 25 μm, or 25 μm or more and not more than 30 μm. When the thickness of the SiC semiconductor layer 22 is 150 μm or less, the depth D of the inclined portion 41 is preferably more than 0 μm and not more than 15 μm.

[0427] The second electrode layer 38 has an inclined portion 41 exposed at the second main surface 24. That is, the peripheral portion of the second electrode layer 38 is formed in an inner region of the SiC semiconductor layer 22 with respect to the side surfaces 25A to 25D.

[0428] As described above, even when manufacturing the SiC semiconductor device 97, the same effects as those described in the eleventh embodiment can be achieved.

[0429] Fig. 35 is a cross-sectional view of a region corresponding to Fig. 19, showing a schematic configuration of a SiC semiconductor device 98 according to a nineteenth embodiment of the present invention. In the following, structures corresponding to those described with respect to the SiC semiconductor device 21 are given the same reference numerals and will not be described.

[0430] 35, SiC semiconductor device 98 does not have inclined portions 41 at corners on the side of first main surface 23 and at corners on the side of second main surface 24. SiC semiconductor device 98 includes modified layers 42 formed in the middle of SiC semiconductor layer 22 in the thickness direction on side surfaces 25A-25D.

[0431] More specifically, the modified layer 42 is formed in the middle in the thickness direction of the SiC semiconductor substrate 31. The modified layer 42 is formed on the second main surface 24 side with a gap therebetween with respect to the boundary region between the SiC semiconductor substrate 31 and the SiC epitaxial layer 32. The modified layer 42 is also formed on the SiC epitaxial layer 32 side with a gap therebetween with respect to the second main surface 24.

[0432] Such modified layer 42 is formed by adjusting the focal point of the laser light when the laser light is irradiated onto second main surface 24. In this case, modified layer 42 is heated and cooled from the second main surface 3 side of 4H—SiC crystal structure 1, and 4H—SiC crystal structure 1 is cleaved. The step of FIG. 24K does not necessarily have to be performed.

[0433] As described above, even when manufacturing a SiC semiconductor device 98, the same effects as those described in the eleventh embodiment can be achieved.

[0434] Fig. 36 is a top view showing a SiC semiconductor device 101 according to the twentieth embodiment of the present invention. Fig. 37 is a top view showing the SiC semiconductor device 101 shown in Fig. 36, with the resin layer 116 removed. The SiC semiconductor device 101 is a device manufactured using the above-mentioned 4H-SiC crystal structure 1. The SiC semiconductor device 101 is also an example showing a specific structure of the above-mentioned SiC semiconductor device 21.

[0435] 36 and 37, a SiC semiconductor device 101 includes a SiC semiconductor layer 102. The thickness of the SiC semiconductor layer 102 may be 1 μm or more and less than 1000 μm. The thickness of the SiC semiconductor layer 102 may be 1 μm or more and 50 μm or less, 50 μm or more and 150 μm or less, 150 μm or more and 250 μm or less, 250 μm or more and 400 μm or less, 400 μm or more and 600 μm or less, 600 μm or more and 800 μm or less, or 800 μm or more and 1000 μm or less.

[0436] The SiC semiconductor layer 102 has a first main surface 103 on one side, a second main surface 104 on the other side, and side surfaces 105A, 105B, 105C, and 105D connecting the first main surface 103 and the second main surface 104. In this embodiment, the side surfaces 105A to 105D are all cut surfaces. More specifically, the side surfaces 105A to 105D are cleavage surfaces.

[0437] The first main surface 103 and the second main surface 104 are formed in a quadrangular shape (rectangular shape in this embodiment) in a plan view (hereinafter simply referred to as "plan view") seen from their normal direction N. Side surface 105A faces side surface 105C. Side surface 105B faces side surface 105D.

[0438] The SiC semiconductor layer 102 includes a 4H-SiC single crystal. The first main surface 103 and the second main surface 104 face the c-plane of the 4H-SiC single crystal. The first main surface 103 faces the (0001) plane, and the second main surface 104 faces the (000-1) plane.

[0439] The first main surface 103 and the second main surface 104 have an off angle θ inclined at an angle of 10° or less in the [11-20] direction with respect to the (0001) plane. The off angle θ may be 0° or more and 2° or less, 2° or more and 4° or less, 4° or more and 6° or less, 6° or more and 8° or less, or 8° or more and 10° or less. The off angle θ is preferably 0° or more and 4° or less.

[0440] The off angle θ of 0° means that the normal direction N and the c-axis are aligned. The off angle θ may be greater than 0° and less than 4°. The off angle θ is typically set to 2° or 4°, more specifically, in the range of 2°±10% or 4°±10%.

[0441] The side surfaces 105A to 105D each extend planarly along the normal direction N. The length of the side surfaces 105A to 105D may be 1 mm or more and 10 mm or less. The length of the side surfaces 105A to 105D may be 1 mm or more and 2.5 mm or less, 2.5 mm or more and 5 mm or less, 5 mm or more and 7.5 mm or less, or 7.5 mm or more and 10 mm or less. The length of the side surfaces 105A to 105D is preferably 2 mm or more and 5 mm or less.

[0442] The side surfaces 105A to 105D extend along the nearest atom direction and the intersecting direction of the nearest atom direction. More specifically, the intersecting direction of the nearest atom direction is an orthogonal direction perpendicular to the nearest atom direction. In this embodiment, the side surfaces 105A to 105D extend along the [11-20] direction and the [1-100] direction.

[0443] Side 105A and side 105C forming the short sides of the rectangle are formed along the direction intersecting the nearest atom direction (i.e., the [1-100] direction). Side 105B and side 105D forming the long sides of the rectangle are formed along the nearest atom direction (i.e., the [11-20] direction). Side 105A and side 105C may be formed along the [11-20] direction, and side 105B and side 105D may be formed along the [1-100] direction.

[0444] The in-plane variation of the side surfaces 105A to 105D is 20 μm or less. The in-plane variation of the side surfaces 105A and 105C extending along the [1-100] direction in the [11-20] direction is 20 μm or less. More specifically, the in-plane variation of the side surfaces 105A and 105C is 10 μm or less.

[0445] The in-plane variation of the side surfaces 105B and 105D extending in the [11-20] direction is 20 μm or less along the [1-100] direction. More specifically, the in-plane variation of the side surfaces 105B and 105D is 10 μm or less.

[0446] The in-plane variation is defined by the maximum value of the distance between a reference virtual line and a measurement virtual line set on one of the side surfaces 105A-105D selected from the side surfaces 105A-105D. The reference virtual line is a straight line connecting two corners of the SiC semiconductor layer 102 in a plan view, and is set on the selected one of the side surfaces 105A-105D. The measurement virtual line is a straight line extending parallel to the reference virtual line in a plan view, and is set so as to be in contact with the top or base of a protuberance (meander) present on the selected one of the side surfaces 105A-105D.

[0447] For example, the distance between the reference virtual line and the measurement virtual line touching the top of the ridge (meander), and the distance between the reference virtual line and the measurement virtual line touching the base of the ridge (meander) are measured. The maximum value of the measured distances between the reference virtual line and the measurement virtual line defines the in-plane variation of the selected one of the side surfaces 105A-105D.

[0448] The SiC semiconductor layer 102 includes an active region 106 and an outer region 107. The active region 106 is a region in which a vertical MISFET (Metal Insulator Semiconductor Field Effect Transistor) as an example of a field effect transistor is formed. The outer region 107 is a region outside the active region 106.

[0449] The active region 106 may be set in the center of the SiC semiconductor layer 102 with a gap inward from the side surfaces 105A-105D in a plan view. The active region 106 may be set in a quadrangular shape (rectangular shape in this embodiment) having four sides parallel to the side surfaces 105A-105D in a plan view.

[0450] The outer region 107 is set in a region between the side surfaces 105A to 105D and the active region 106. The outer region 107 may be set in a ring shape (for example, endless shape) surrounding the active region 106 in a plan view.

[0451] The SiC semiconductor device 101 includes a gate terminal electrode layer 108 and a source terminal electrode layer 109 formed on a first main surface 103. The gate terminal electrode layer 108, in this embodiment, includes a gate pad 110 and gate fingers 111. The gate pad 110 and the gate fingers 111 are disposed in the active region 106.

[0452] The gate pad 110 is formed in a region along the side surface 105A in a plan view. The gate pad 110 is formed in a region along the center of the side surface 105A in a plan view. The gate pad 110 may be formed in a region along a corner connecting any two of the side surfaces 105A to 105D in a plan view. The gate pad 110 is formed in a quadrangular shape in a plan view.

[0453] The gate fingers 111 include outer gate fingers 111A and inner gate fingers 111B. The outer gate fingers 111A are drawn out from the gate pad 110 and extend in a strip shape along the periphery of the active area 106. In this embodiment, the outer gate fingers 111A are formed along three side surfaces 105A, 105B, and 105D, and define the inner area of ​​the active area 106 from three directions.

[0454] The outer gate finger 111A has a pair of open ends 112A, 112B. The pair of open ends 112A, 112B of the outer gate finger 111A are formed in a region facing the gate pad 110 with an inner region of the active region 106 in between. In this embodiment, the pair of open ends 112A, 112B of the outer gate finger 111A are formed in a region along the side surface 105C.

[0455] The inner gate finger 111B is drawn out from the gate pad 110 to an inner region of the active region 106. The inner gate finger 111B extends in a strip shape in the inner region of the active region 106. The inner gate finger 111B extends from the side surface 105A toward the side surface 105C.

[0456] In this embodiment, the source terminal electrode layer 109 includes a source pad 113, a source lead-out wiring 114, and a source connection portion 115. The source pad 113 is formed in the active region 106 at a distance from the gate pad 110 and the gate fingers 111. The source pad 113 covers a C-shaped region (inverted C-shape in FIGS. 36 and 37) defined by the gate pad 110 and the gate fingers 111. The source pad 113 is formed in a C-shape (inverted C-shape in FIGS. 36 and 37) in a plan view.

[0457] The source lead-out wiring 114 is formed in the outer region 107. The source lead-out wiring 114 extends in a strip shape along the active region 106. In this embodiment, the source lead-out wiring 114 is formed in a ring shape (for example, endless shape) surrounding the active region 106 in a plan view. The source lead-out wiring 114 is electrically connected to the SiC semiconductor layer 102 in the outer region 107.

[0458] The source connection part 115 connects the source pad 113 and the source lead-out wiring 114. The source connection part 115 is formed in a region between a pair of open ends 112A, 112B of the outer gate finger 111A. The source connection part 115 crosses the boundary region between the active region 106 and the outer region 107 from the source pad 113 and is connected to the source lead-out wiring 114.

[0459] The MISFET formed in the active region 106 structurally includes an npn-type parasitic bipolar transistor. When an avalanche current generated in the outer region 107 flows into the active region 106, the parasitic bipolar transistor turns on. In this case, there is a possibility that control of the MISFET becomes unstable due to, for example, latch-up.

[0460] Therefore, in the SiC semiconductor device 101, the structure of the source terminal electrode layer 109 is utilized to form an avalanche current absorption structure that absorbs the avalanche current generated in the region outside the active region .

[0461] More specifically, the avalanche current generated in the outer region 107 is absorbed by the source lead-out wiring 114. The avalanche current reaches the source pad 113 via the source connection part 115. When a conductor for external connection (e.g., a bonding wire) is connected to the source pad 113, the avalanche current is taken out by this conductor.

[0462] This makes it possible to prevent the parasitic bipolar transistor from being turned on due to an undesired current generated in the outer region 107. This makes it possible to prevent latch-up, thereby improving the stability of the MISFET.

[0463] A gate voltage is applied to the gate pad 110 and the gate finger 111. The gate voltage may be 10 V or more and 50 V or less (for example, about 30 V). A source voltage is applied to the source pad 113. The source voltage may be a reference voltage (for example, a GND voltage).

[0464] The SiC semiconductor device 101 includes a resin layer 116 formed on the first main surface 103 (more specifically, on an interlayer insulating layer 191 described later). For clarity, the resin layer 116 is shown by hatching in Fig. 36. The resin layer 116 covers the gate pad 110, the gate fingers 111, and the source pad 113.

[0465] The resin layer 116 may include a negative type or a positive type photosensitive resin. In this embodiment, the resin layer 116 includes polybenzoxazole as an example of a positive type photosensitive resin. The resin layer 116 may include polyimide as an example of a negative type photosensitive resin.

[0466] The resin layer 116 includes a gate pad opening 117 and a source pad opening 118. The gate pad opening 117 exposes the gate pad 110. The source pad opening 118 exposes the source pad 113.

[0467] Peripheral portion 119 of resin layer 116 is formed at a distance inward from side surfaces 105A to 105D. As a result, resin layer 116 exposes the peripheral portion of SiC semiconductor layer 102 (more specifically, interlayer insulating layer 191, which will be described later).

[0468] Peripheral edge 119 of resin layer 116 is a portion that forms a dicing street when SiC semiconductor device 101 is cut out from 4H-SiC crystal structure 1. By exposing the peripheral edge of SiC semiconductor layer 102 from resin layer 116, it becomes unnecessary to physically cut resin layer 116. Therefore, SiC semiconductor device 101 can be smoothly cut out from 4H-SiC crystal structure 1.

[0469] FIG. 38 is an enlarged view of region XXXVIII shown in FIG. 37, and is a view for explaining the structure of first main surface 103 of SiC semiconductor layer 102. FIG. 39 is a cross-sectional view taken along line XXXIX-XXXIX shown in FIG. 38. FIG. 40 is a cross-sectional view taken along line XL-XL shown in FIG. 38. FIG. 41 is an enlarged view of region XLI shown in FIG. 39. FIG. 42 is a cross-sectional view taken along line XLII-XLII shown in FIG. 37. FIG. 43 is an enlarged view of region XLIII shown in FIG. 42. FIG. 44 is an enlarged view of region XLIV shown in FIG. 42.

[0470] 38 to 44, in this embodiment, the SiC semiconductor layer 102 is +The semiconductor device has a layered structure including an n-type SiC semiconductor substrate 121 and an n-type SiC epitaxial layer 122.

[0471] The second main surface 104 of the SiC semiconductor layer 102 is formed by the SiC semiconductor substrate 121. The first main surface 103 of the SiC semiconductor layer 102 is formed by the SiC epitaxial layer 122. Side surfaces 105A to 105D of the SiC semiconductor layer 102 are formed by the SiC semiconductor substrate 121 and the SiC epitaxial layer 122. The second main surface 104 may be a ground surface having grinding marks.

[0472] The thickness of the SiC epitaxial layer 122 is less than the thickness of the SiC semiconductor substrate 121. The thickness of the SiC semiconductor substrate 121 may be 1 μm or more and less than 1000 μm. The thickness of the SiC semiconductor substrate 121 may be 1 μm or more and 50 μm or less, 50 μm or more and 150 μm or less, 150 μm or more and 250 μm or less, 250 μm or more and 400 μm or less, 400 μm or more and 600 μm or less, 600 μm or more and 800 μm or less, or 800 μm or more and 1000 μm or less.

[0473] The thickness of the SiC semiconductor substrate 121 is preferably 150 μm or less. By reducing the thickness of the SiC semiconductor substrate 121, the resistance value can be reduced by shortening the current path.

[0474] The thickness of the SiC epitaxial layer 122 may be 1 μm or more and 100 μm or less. The thickness of the SiC epitaxial layer 122 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, 40 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, or 75 μm or more and 100 μm or less. The thickness of the SiC epitaxial layer 122 is preferably 5 μm or more and 20 μm or less.

[0475] The n-type impurity concentration of the SiC epitaxial layer 122 is equal to or lower than the n-type impurity concentration of the SiC semiconductor substrate 121. The n-type impurity concentration of the SiC semiconductor substrate 121 is 1.0×1018 cm -3 Above 1.0×10 21 cm -3 The n-type impurity concentration of the SiC epitaxial layer 122 may be 1.0×10 15 cm -3 Above 1.0×10 18 cm -3 It may be the following.

[0476] In this embodiment, the SiC epitaxial layer 122 has a plurality of regions having different n-type impurity concentrations along the normal direction N. More specifically, the SiC epitaxial layer 122 includes a high-concentration region 122a having a relatively high n-type impurity concentration and a low-concentration region 122b having a lower n-type impurity concentration than the high-concentration region 122a.

[0477] The high concentration region 122a is formed in a region on the first major surface 103 side. The low concentration region 122b is formed in a region on the second major surface 104 side with respect to the high concentration region 122a. The n-type impurity concentration of the high concentration region 122a is 1×10 16 cm -3 More than 1×10 18 cm -3 The n-type impurity concentration of the low concentration region 122b may be 1×10 15 cm -3 More than 1×10 16 cm -3 It may be the following.

[0478] The thickness of the high concentration region 122a is equal to or smaller than the thickness of the low concentration region 122b. More specifically, the thickness of the high concentration region 122a is less than the thickness of the low concentration region 122b. In other words, the thickness of the high concentration region 122a is less than half of the total thickness of the SiC epitaxial layer 122.

[0479] The SiC epitaxial layer 122 is formed, for example, in the process of preparing the 4H-SiC crystal structure 1 (see Figures 23 and 24A), by changing the amount of n-type impurity introduced (added amount) along the growth direction of SiC when epitaxially growing SiC from a SiC semiconductor wafer 51.

[0480] The SiC semiconductor device 101 includes a drain pad 123 connected to the second main surface 104 of the SiC semiconductor layer 102. That is, the SiC semiconductor substrate 121 is formed as a drain region 124 of the MISFET. The SiC epitaxial layer 122 is formed as a drift region 125 of the MISFET. The maximum voltage that can be applied between the source pad 113 and the drain pad 123 in the off state may be 1000V or more and 10000V or less.

[0481] The drain pad 123 may include at least one of an Al layer, a Ti layer, a Ni layer, an Au layer, and an Ag layer. The drain pad 123 may have a laminated structure in which at least two of an Al layer, a Ti layer, a Ni layer, an Au layer, and an Ag layer are laminated in any manner. The drain pad 123 may have a single-layer structure made of an Al layer, a Ti layer, a Ni layer, an Au layer, or an Ag layer. The drain pad 123 may have a four-layer structure including a Ti layer, a Ni layer, an Au layer, and an Ag layer laminated in this order from the second main surface 104.

[0482] The SiC semiconductor device 101 includes a p-type body region 126 formed in a surface layer portion of the first main surface 103 of the SiC semiconductor layer 102 in the active region 106. The p-type impurity concentration of the body region 126 is 1×10 17 cm -3 More than 1×10 20 cm -3 The body region 126 defines the active area 106.

[0483] The SiC semiconductor device 101 includes a plurality of gate trenches 131 in a surface layer portion of the first main surface 103 in the active region 106. The plurality of gate trenches 131 are formed at intervals in an arbitrary first direction X. The plurality of gate trenches 131 are formed in a strip shape extending along a second direction Y intersecting the first direction X. The second direction Y is a direction perpendicular to the first direction X. As a result, the plurality of gate trenches 131 are formed in a stripe shape extending along the second direction Y as a whole in a plan view.

[0484] It is preferable that the first direction X is set to the [11-20] direction, and the second direction Y is set to the [1-100] direction. In other words, it is preferable that the multiple gate trenches 131 are formed at intervals in the [11-20] direction and are formed in a band shape extending along the [1-100] direction.

[0485] The first direction X may be set to the [1-100] direction, and the second direction Y may be set to the [11-20] direction. In other words, the multiple gate trenches 131 may be formed at intervals in the [1-100] direction and in strip shapes extending along the [11-20] direction.

[0486] Each gate trench 131 extends in a strip shape from the periphery on one side (side surface 105B side) to the periphery on the other side (side surface 105D side) of the active region 106. Each gate trench 131 crosses an intermediate portion between the periphery on one side and the periphery on the other side of the active region 106. One end of each gate trench 131 is located at the periphery on one side of the active region 106. The other end of each gate trench 131 is located at the periphery on the other side of the active region 106.

[0487] Each gate trench 131 has a length on the order of millimeters (length of 1 mm or more). The length of each gate trench 131 may be 1 mm or more and 10 mm or less. The length of each gate trench 131 may be 1 mm or more and 2 mm or less, 2 mm or more and 4 mm or less, 4 mm or more and 6 mm or less, 6 mm or more and 8 mm or less, or 8 mm or more and 10 mm or less. The length of each gate trench 131 is preferably 2 mm or more and 5 mm or less. In addition, the total extension of one or more gate trenches 131 per unit area is preferably 0.5 μm / μm. 2 More than 0.75μm / μm 2 It is preferable that:

[0488] Each gate trench 131 includes an active trench portion 131a and a contact trench portion 131b. The active trench portion 131a is a portion that is along the channel region of the MISFET in the active region 106. The contact trench portion 131b is a portion of the gate trench 131 that is primarily intended for contact with the gate finger 111.

[0489] The contact trench portion 131b is drawn out from the active trench portion 131a to the peripheral portion of the active region 106. The contact trench portion 131b is formed in a region directly below the gate finger 111. The drawn-out amount of the contact trench portion 131b is arbitrary.

[0490] Each gate trench 131 penetrates the body region 126 and reaches the SiC epitaxial layer 122. The bottom wall of each gate trench 131 is located in the SiC epitaxial layer 122.

[0491] More specifically, the bottom wall of each gate trench 131 is located in the high concentration region 122a of the SiC epitaxial layer 122. The bottom wall of the gate trench 131 may be formed parallel to the first main surface 103. The bottom wall of the gate trench 131 may be formed in a curved shape toward the second main surface 104.

[0492] The sidewall of the gate trench 131 may extend along the normal direction N. The sidewall of the gate trench 131 may be formed substantially perpendicular to the first main surface 103 of the SiC semiconductor layer 102. The gate trench 131 may be formed in a tapered shape with a bottom area less than an opening area.

[0493] The depth of the gate trench 131 along the normal direction N may be 0.5 μm or more and 3 μm or less. The depth of the gate trench 131 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less. The depth of the gate trench 131 is preferably 0.5 μm or more and 1.0 μm or less.

[0494] The width of the gate trench 131 along the first direction X may be 0.1 μm or more and 2 μm or less. The width of the gate trench 131 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, or 1.5 μm or more and 2 μm or less. The width of the gate trench 131 is preferably 0.1 μm or more and 0.5 μm or less.

[0495] 41, opening edge portion 132 of each gate trench 131 includes an inclined portion 133 that slopes downward from the first main surface 103 toward the gate trench 131. The opening edge portion 132 of the gate trench 131 is a corner portion that connects the first main surface 103 and a sidewall of the gate trench 131.

[0496] In this embodiment, the inclined portion 133 is formed in a curved shape recessed toward the SiC semiconductor layer 102. The inclined portion 133 may be formed in a curved shape protruding toward the inside of the gate trench 131. The electric field with respect to the opening edge portion 132 is alleviated by the inclined portion 133.

[0497] The SiC semiconductor device 101 includes a gate insulating layer 134 and a gate electrode layer 135 formed in each gate trench 131. In Fig. 38, the gate insulating layer 134 and the gate electrode layer 135 are indicated by hatching.

[0498] The gate insulating layer 134 includes silicon oxide. The gate insulating layer 134 may include other insulating films such as silicon nitride. The gate insulating layer 134 is formed in the form of a film along the inner wall surface of the gate trench 131. The gate insulating layer 134 defines a recess space in the gate trench 131.

[0499] The gate insulating layer 134 includes a first region 134a, a second region 134b, and a third region 134c. The first region 134a is formed along the sidewall of the gate trench 131. The second region 134b is formed along the bottom wall of the gate trench 131. The third region 134c is extended from the first region 134a onto the first main surface 103 and is formed on the first main surface 103.

[0500] The thickness T1 of the first region 134a is less than the thickness T2 of the second region 134b and the thickness T3 of the third region 134c. The ratio T2 / T1 of the thickness T2 of the second region 134b to the thickness T1 of the first region 134a may be greater than or equal to 2 and less than or equal to 5. The ratio T3 / T1 of the thickness T3 of the third region 134c to the thickness T1 of the first region 134a may be greater than or equal to 2 and less than or equal to 5.

[0501] The thickness T1 of the first region 134a may be 0.01 μm or more and 0.2 μm or less. The thickness T2 of the second region 134b may be 0.05 μm or more and 0.5 μm or less. The thickness T3 of the third region 134c may be 0.05 μm or more and 0.5 μm or less.

[0502] By thinning the first region 134a, it is possible to suppress an increase in carriers induced in the body region 126 in the region near the sidewall of the gate trench 131. This makes it possible to suppress an increase in channel resistance. By thickening the second region 134b, it is possible to alleviate electric field concentration on the bottom wall of the gate trench 131.

[0503] The thickening of the third region 134c can improve the breakdown voltage of the gate insulating layer 134 in the vicinity of the opening edge portion 132. The thickening of the third region 134c can also prevent the third region 134c from being lost by an etching method. This allows the third region 134c to protect the first region 134a.

[0504] For example, it is possible to prevent the first region 134a from being removed by an etching method due to the disappearance of the third region 134c. This allows the gate electrode layer 135 to be appropriately opposed to the SiC semiconductor layer 102 (the body region 126) with the gate insulating layer 134 interposed therebetween.

[0505] The gate insulating layer 134 further includes a bulging portion 134d that bulges into the gate trench 131 at the opening edge portion 132. The bulging portion 134d is formed in a portion that connects the first region 134a and the third region 134c of the gate insulating layer 134. The bulging portion 134d protrudes in a curved shape toward the inside of the gate trench 131. The bulging portion 134d narrows the opening of the gate trench 131 at the opening edge portion 132.

[0506] The bulging portion 134d improves the dielectric strength of the gate insulating layer 134 at the opening edge portion 132. The gate insulating layer 134 may be formed without the bulging portion 134d. The gate insulating layer 134 may be formed to have a uniform thickness.

[0507] The gate electrode layer 135 is embedded in the gate trench 131 with the gate insulating layer 134 sandwiched therebetween. More specifically, the gate electrode layer 135 is embedded in a recess space defined by the gate insulating layer 134. The gate electrode layer 135 is controlled by a gate voltage.

[0508] The gate electrode layer 135 is formed in a wall shape extending along the normal direction N in a cross-sectional view. The gate electrode layer 135 has an upper end portion located on the opening side of the gate trench 131. The upper end portion of the gate electrode layer 135 is formed in a curved shape recessed toward the bottom wall of the gate trench 131. The upper end portion of the gate electrode layer 135 has a narrowed portion that is narrowed along the bulging portion 134d of the gate insulating layer 134.

[0509] The cross-sectional area of ​​the gate electrode layer 135 in the direction perpendicular to the direction in which the gate trench 131 extends (first direction X) is 0.05 μm 2 More than 0.5μm 2 The cross-sectional area of ​​the gate electrode layer 135 is defined as the product of the thickness of the gate electrode layer 135 along the normal direction N and the width of the gate electrode layer 135 along the first direction X.

[0510] The thickness of the gate electrode layer 135 is the distance from the upper end to the lower end of the gate electrode layer 135. The width of the gate electrode layer 135 is the width of the gate electrode layer 135 at the midpoint between the upper end and the lower end of the gate electrode layer 135. When the upper end is a curved surface (in this embodiment, a curved shape recessed downward), the position of the upper end of the gate electrode layer 135 is the midpoint of the upper end of the gate electrode layer 135.

[0511] The cross-sectional area of ​​the gate electrode layer 135 is 0.05 μm 2 More than 0.1μm 2 Below, 0.1μm 2 More than 0.2μm 2 Below, 0.2μm 2 More than 0.3μm 2 Below, 0.3μm 2 More than 0.4μm 2 Less than or equal to 0.4μm 2 More than 0.5μm 2 It may be the following.

[0512] The gate electrode layer 135 may include at least one of conductive polysilicon, tungsten, aluminum, copper, an aluminum alloy, and a copper alloy. In this embodiment, the gate electrode layer 135 includes p-type polysilicon doped with p-type impurities. The p-type impurities of the gate electrode layer 135 may include at least one of boron (B), aluminum (Al), indium (In), and gallium (Ga).

[0513] The p-type impurity concentration of the gate electrode layer 135 is equal to or higher than the p-type impurity concentration of the body region 126. More specifically, the p-type impurity concentration of the gate electrode layer 135 exceeds the p-type impurity concentration of the body region 126. The p-type impurity concentration of the gate electrode layer 135 is equal to or higher than 1×10 18 cm -3 More than 1×10 22 cm -3 The sheet resistance of the gate electrode layer 135 may be 10 Ω / □ or more and 500 Ω / □ or less (approximately 200 Ω / □ in this embodiment).

[0514] 38 and 40, the SiC semiconductor device 101 further includes a gate wiring layer 136 formed in the active region 106. In Fig. 40, the gate wiring layer 136 is indicated by hatching. The gate wiring layer 136 electrically connects the gate pad 110 (gate finger 111) and the gate electrode layer 135.

[0515] In this embodiment, the gate wiring layer 136 is formed on the first main surface 103. More specifically, the gate wiring layer 136 is formed on the third region 134c of the gate insulating layer 134.

[0516] In this embodiment, the gate wiring layer 136 is formed along the gate finger 111. More specifically, the gate wiring layer 136 is formed along three side surfaces 105A, 105B, and 105D of the SiC semiconductor layer 102, and defines an inner region of the active region 106 from three directions.

[0517] The gate wiring layer 136 is connected to the gate electrode layer 135 exposed from the contact trench portion 131b of each gate trench 131. In this embodiment, the gate wiring layer 136 is formed by an extended portion of the gate electrode layer 135 extended from each gate trench 131 onto the first main surface 103. An upper end of the gate wiring layer 136 is connected to an upper end of the gate electrode layer 135.

[0518] 38, 39 and 41, SiC semiconductor device 101 includes a plurality of source trenches 141 formed in first main surface 103 in active region 106. Each source trench 141 is formed in a region between two gate trenches 131 adjacent to each other.

[0519] Each source trench 141 is formed in a band shape extending along the second direction Y. The multiple source trenches 141 are formed in a stripe shape extending along the second direction Y as a whole in a plan view. As a result, the multiple gate trenches 131 and the multiple source trenches 141 are formed alternately along the first direction X and are formed in a stripe shape extending along the second direction Y.

[0520] The pitch between the central portions of two adjacent source trenches 141 in the first direction X may be 1.5 μm or more and 3 μm or less. The pitch of the source trenches 141 may be 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less.

[0521] Each source trench 141 penetrates the body region 126 and reaches the SiC epitaxial layer 122. The bottom wall of each source trench 141 is located in the SiC epitaxial layer 122. More specifically, the bottom wall of each source trench 141 is located in the high concentration region 122a.

[0522] In this embodiment, the depth of the source trench 141 in relation to the normal direction N is equal to or greater than the depth of the gate trench 131. More specifically, the depth of the source trench 141 exceeds the depth of the gate trench 131. The bottom wall of the source trench 141 is located on the second main surface 104 side relative to the bottom wall of the gate trench 131.

[0523] The bottom wall of the source trench 141 is located in a region between the bottom wall of the gate trench 131 and the low concentration region 122b in the normal direction N. The bottom wall of the source trench 141 may be formed parallel to the first main surface 103. The bottom wall of the source trench 141 may be formed in a curved shape toward the second main surface 104.

[0524] The sidewalls of the source trench 141 may extend along the normal direction N. The sidewalls of the source trench 141 may be formed substantially perpendicular to the first main surface 103. The source trench 141 may be formed in a tapered shape with a bottom area less than an opening area.

[0525] The ratio of the depth of the source trench 141 to the depth of the gate trench 131 may be 1.5 or more. The ratio of the depth of the source trench 141 to the depth of the gate trench 131 is preferably 2 or more.

[0526] The depth of source trench 141 may be 0.5 μm or more and 10 μm or less. The depth of source trench 141 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. The depth of source trench 141 is preferably 1 μm or more and 6 μm or less.

[0527] The width of the source trench 141 may be 0.1 μm or more and 2 μm or less. The width of the source trench 141 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, or 1.5 μm or more and 2 μm or less. The width of the source trench 141 is preferably 0.1 μm or more and 0.5 μm or less. The width of the source trench 141 in the first direction X may be approximately equal to the width of the gate trench 131 in the first direction X. The width of the source trench 141 may be equal to or more than the width of the gate trench 131.

[0528] The SiC semiconductor device 101 includes a source insulating layer 142 and a source electrode layer 143 formed in each source trench 141. In Fig. 38, the source insulating layer 142 and the source electrode layer 143 are indicated by hatching.

[0529] The source insulating layer 142 may contain silicon oxide. The source insulating layer 142 may contain other insulating films such as silicon nitride. The source insulating layer 142 is formed in a film shape along the inner wall surface of the source trench 141 and defines a recess space in the source trench 141.

[0530] The source insulating layer 142 includes a first region 142a and a second region 142b. The first region 142a is formed along a side wall of the source trench 141. The second region 142b is formed along a bottom wall of the source trench 141. A thickness T11 of the first region 142a is less than a thickness T12 of the second region 142b.

[0531] A ratio T12 / T11 of a thickness T12 of the second region 142b to a thickness T11 of the first region 142a may be equal to or greater than 2 and equal to or less than 5. The thickness T11 of the first region 142a may be equal to or greater than 0.01 μm and equal to or less than 0.2 μm. The thickness T12 of the second region 142b may be equal to or greater than 0.05 μm and equal to or less than 0.5 μm.

[0532] A thickness T11 of the first region 142a may be approximately equal to a thickness T1 of the first region 134a of the gate insulating layer 134. A thickness T12 of the second region 142b may be approximately equal to a thickness T2 of the second region 134b of the gate insulating layer 134. The source insulating layer 142 may be formed to have a uniform thickness.

[0533] The source electrode layer 143 is embedded in the source trench 141 with the source insulating layer 142 sandwiched therebetween. More specifically, the source electrode layer 143 is embedded in a recess space defined by the source insulating layer 142. The source electrode layer 143 is controlled by a source voltage.

[0534] The source electrode layer 143 has an upper end located on the opening side of the source trench 141. The upper end of the source electrode layer 143 is formed on the bottom wall side of the source trench 141 with respect to the first main surface 103. The upper end of the source electrode layer 143 is formed in a curved shape recessed toward the bottom wall of the source trench 141. The upper end of the source electrode layer 143 may be formed parallel to the first main surface 103.

[0535] An upper end of the source electrode layer 143 may be located above the first main surface 103. An upper end of the source electrode layer 143 may protrude above an upper end of the source insulating layer 142. An upper end of the source electrode layer 143 may be located below an upper end of the source insulating layer 142.

[0536] The thickness of the source electrode layer 143 along the normal direction N may be 0.5 μm or more and 10 μm or less (for example, about 1 μm). The thickness of the source electrode layer 143 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. The thickness of the source electrode layer 143 is preferably 1 μm or more and 6 μm or less.

[0537] The source electrode layer 143 preferably contains polysilicon having properties similar to those of SiC. This can reduce stress caused by the source electrode layer 143 in the SiC semiconductor layer 102. The source electrode layer 143 may contain the same conductive material type as the gate electrode layer 135.

[0538] The source electrode layer 143 may include conductive polysilicon. The source electrode layer 143 may include n-type polysilicon or p-type polysilicon as an example of conductive polysilicon. The source electrode layer 143 may include at least one of tungsten, aluminum, copper, an aluminum alloy, and a copper alloy instead of conductive polysilicon.

[0539] When the gate electrode layer 135 includes p-type polysilicon doped with p-type impurities, the source electrode layer 143 preferably includes p-type polysilicon doped with p-type impurities. This allows the source electrode layer 143 to be formed simultaneously with the gate electrode layer 135.

[0540] In this case, the p-type impurity of the source electrode layer 143 may include at least one of boron (B), aluminum (Al), indium (In), and gallium (Ga). The p-type impurity concentration of the source electrode layer 143 is equal to or higher than the p-type impurity concentration of the body region 126. More specifically, the p-type impurity concentration of the source electrode layer 143 exceeds the p-type impurity concentration of the body region 126.

[0541] The p-type impurity concentration of the source electrode layer 143 is 1×10 18 cm -3 More than 1×10 22 cm -3 The sheet resistance of the source electrode layer 143 may be 10 Ω / □ or more and 500 Ω / □ or less (approximately 200 Ω / □ in this embodiment).

[0542] The p-type impurity concentration of the source electrode layer 143 may be approximately equal to the p-type impurity concentration of the gate electrode layer 135. The sheet resistance of the source electrode layer 143 may be approximately equal to the sheet resistance of the gate electrode layer 135.

[0543] Thus, the SiC semiconductor device 101 has a trench gate structure 151 and a trench source structure 152. The trench gate structure 151 includes a gate trench 131, a gate insulating layer 134, and a gate electrode layer 135. The trench source structure 152 includes a source trench 141, a source insulating layer 142, and a source electrode layer 143.

[0544] The SiC semiconductor device 101 has an n-type junction region formed in a surface portion of the body region 126 along the side wall of the gate trench 131. + The source region 153 includes an n-type source region 153. The n-type impurity concentration of the source region 153 is 1.0×10 18 cm -3 Above 1.0×10 21 cm -3 The source regions 153 are formed along one sidewall and the other sidewall of the gate trench 131 in the first direction X.

[0545] The multiple source regions 153 are each formed in a band shape extending along the second direction Y. The multiple source regions 153 are formed in a stripe shape as a whole in a plan view. Each source region 153 is exposed from a side wall of the gate trench 131 and a side wall of the source trench 141.

[0546] The SiC semiconductor device 101 has a p + The contact regions 154 include a p-type impurity concentration that exceeds the p-type impurity concentration of the body region 126. The p-type impurity concentration of the contact regions 154 is 1.0×10 18 cm -3 Above 1.0×10 21 cm -3 It may be the following.

[0547] The multiple contact regions 154 are formed along the side walls of the multiple source trenches 141, respectively. In this embodiment, multiple contact regions 154 are formed for one source trench 141. For one source trench 141, the multiple contact regions 154 are formed at intervals in the second direction Y along the source trench 141.

[0548] The contact regions 154 are formed at intervals from the gate trench 131 in the first direction X. As a result, each contact region 154 faces the gate trench 131 with the source region 153 interposed therebetween in a plan view.

[0549] Each contact region 154 covers the sidewall and bottom wall of the source trench 141. The bottom of each contact region 154 may be formed parallel to the bottom wall of the source trench 141. More specifically, each contact region 154 integrally includes a first surface region 154a, a second surface region 154b, and an inner wall region 154c.

[0550] The first surface region 154a is formed along one sidewall of the source trench 141 in the surface portion of the first main surface 103. The first surface region 154a extends from one sidewall of the source trench 141 toward the adjacent gate trench 131. The first surface region 154a may extend to an intermediate region between the source trench 141 and the gate trench 131.

[0551] The second surface region 154b is formed along the other sidewall of the source trench 141 in the surface portion of the first main surface 103. The second surface region 154b extends from the other side surface of the source trench 141 toward the adjacent gate trench 131. The second surface region 154b may extend to an intermediate region between the source trench 141 and the gate trench 131.

[0552] The inner wall region 154c is formed in a region along the inner wall of the source trench 141 in the SiC semiconductor layer 102. The inner wall region 154c is formed along the side wall of the source trench 141. The inner wall region 154c covers a corner portion connecting the side wall and the bottom wall of the source trench 141. The inner wall region 154c covers the bottom wall of the source trench 141 from the side wall of the source trench 141 through the corner portion. The bottom of each contact region 154 is formed by the inner wall region 154c.

[0553] The SiC semiconductor device 101 includes a plurality of p-type deep well regions 155 formed in a surface layer portion of the first main surface 103. The deep well regions 155 are also referred to as breakdown voltage adjusting regions (breakdown voltage holding regions) that adjust the breakdown voltage of the SiC semiconductor layer 102 in the active region 106.

[0554] The multiple deep well regions 155 are formed in a one-to-one correspondence with the multiple source trenches 141. Each deep well region 155 covers the inner wall of the corresponding source trench 141 with the contact region 154 in between. The deep well region 155 is formed in a strip shape extending along the source trench 141 in a plan view. The deep well region 155 is formed along the side wall of the source trench 141.

[0555] The deep well region 155 covers a corner portion connecting the side wall and the bottom wall of the source trench 141. The deep well region 155 covers the side wall of the source trench 141 through the corner portion and the bottom wall of the source trench 141. The deep well region 155 is continuous with the body region 126 on the side wall of the source trench 141.

[0556] The deep well region 155 is formed in the high concentration region 122a of the SiC epitaxial layer 122. The deep well region 155 has a bottom portion located on the second main surface 104 side with respect to the bottom wall of the gate trench 131. The bottom portion of the deep well region 155 may be formed parallel to the bottom wall of the source trench 141.

[0557] The p-type impurity concentration of the deep well region 155 may be approximately equal to the p-type impurity concentration of the body region 126. The p-type impurity concentration of the deep well region 155 may be greater than the p-type impurity concentration of the body region 126. The p-type impurity concentration of the deep well region 155 may be less than the p-type impurity concentration of the body region 126.

[0558] The p-type impurity concentration of the deep well region 155 may be equal to or lower than the p-type impurity concentration of the contact region 154. The p-type impurity concentration of the deep well region 155 may be lower than the p-type impurity concentration of the contact region 154. The p-type impurity concentration of the deep well region 155 may be 1.0×10 17 cm -3 Above 1.0×10 19 cm -3 It may be the following.

[0559] The deep well region 155 forms a pn junction with the SiC semiconductor layer 102 (high concentration region 122a of the SiC epitaxial layer 122). A depletion layer spreads from this pn junction toward the multiple gate trenches 131. The depletion layer spreading from the deep well region 155 extends toward a region on the second main surface 104 side with respect to the bottom wall of the gate trench 131.

[0560] The depletion layer extending from the deep well region 155 may overlap the bottom wall of the gate trench 131. The depletion layer extending from the bottom of the deep well region 155 may overlap the bottom wall of the gate trench 131.

[0561] In a SiC semiconductor device including only a pn junction diode, since the structure does not include a trench, there is little problem of electric field concentration in the SiC semiconductor layer 102. The deep well region 155 brings the trench gate type MISFET closer to the structure of a pn junction diode.

[0562] This allows the electric field in the SiC semiconductor layer 102 to be alleviated in the trench-gate MISFET. Narrowing the pitch between adjacent deep well regions 155 is effective in alleviating electric field concentration. With the deep well region 155 having a bottom portion on the second main surface 104 side with respect to the bottom wall of the gate trench 131, the depletion layer allows the electric field concentration on the gate trench 131 to be appropriately alleviated.

[0563] The bottoms of the multiple deep well regions 155 are preferably formed at approximately constant intervals from the second main surface 104. This can suppress variation in the distance between the bottoms of the deep well regions 155 and the second main surface 104. In this case, the withstand voltage (e.g., electrostatic breakdown resistance) of the SiC semiconductor layer 102 can be suppressed from being limited by the deep well regions 155, and therefore the withstand voltage can be appropriately improved.

[0564] In this embodiment, the high concentration region 122a of the SiC epitaxial layer 122 is interposed in the region between the plurality of adjacent deep well regions 155. This makes it possible to reduce the JFET (Junction Field Effect Transistor) resistance in the region between the plurality of deep well regions 155.

[0565] Furthermore, in this embodiment, the bottom of the deep well region 155 is located within the high concentration region 122a of the SiC epitaxial layer 122. This allows the current path to be expanded in the lateral direction parallel to the first main surface 103 by utilizing the high concentration region 122a located directly below the deep well region 155. As a result, the current spreading resistance can be reduced. In this structure, the low concentration region 122b of the SiC epitaxial layer 122 increases the breakdown voltage of the SiC semiconductor layer 102.

[0566] Further, the deep well region 155 is formed by utilizing the source trench 141. That is, the deep well region 155 is formed conformally to the inner wall of the source trench 141. This makes it possible to appropriately suppress the occurrence of variations in the depth of each deep well region 155. Furthermore, by utilizing the source trench 141, the deep well region 155 can be appropriately formed in a relatively deep region of the SiC semiconductor layer 102.

[0567] The SiC semiconductor device 101 includes a plurality of source sub-trenches 156 formed in a region along an upper end portion of the source electrode layer 143 on the first main surface 103. The plurality of source sub-trenches 156 communicate with the corresponding source trenches 141 and form part of the sidewalls of the source trenches 141.

[0568] In this embodiment, the source sub-trench 156 is formed in a ring shape (for example, endless shape) surrounding the upper end portion of the source electrode layer 143 in a plan view. In other words, the source sub-trench 156 borders the upper end portion of the source electrode layer 143.

[0569] The source sub-trench 156 is formed by digging down a part of the source insulating layer 142. More specifically, the source sub-trench 156 is formed by digging down from the first main surface 103 to the upper end of the source insulating layer 142 and the upper end of the source electrode layer 143.

[0570] An upper end of the source electrode layer 143 has a narrowed shape relative to a lower end of the source electrode layer 143. The lower end of the source electrode layer 143 is a portion of the source electrode layer 143 located on the bottom wall side of the source trench 141. The width of the upper end of the source electrode layer 143 along the first direction X may be smaller than the width of the lower end of the source electrode layer 143 along the first direction X.

[0571] The source sub-trench 156 is formed in a tapered shape such that the bottom area is less than the opening area in a cross-sectional view. The bottom wall of the source sub-trench 156 may be formed in a curved shape toward the second main surface 104.

[0572] The source region 153, the contact region 154, the source insulating layer 142, and the source electrode layer 143 are exposed from the inner wall of the source sub-trench 156. At least the first region 142a of the source insulating layer 142 is exposed from the bottom wall of the source sub-trench 156. The upper end of the first region 142a of the source insulating layer 142 is located below the first main surface 103.

[0573] An opening edge 157 of each source trench 141 includes an inclined portion 158 that slopes downward from the first main surface 103 toward the inside of the source trench 141. The opening edge 157 of the source trench 141 is a corner that connects the first main surface 103 and the sidewall of the source trench 141. The inclined portion 158 of the source trench 141 is formed by a source sub-trench 156.

[0574] In this embodiment, the inclined portion 158 is formed in a curved shape recessed toward the SiC semiconductor layer 102. The inclined portion 158 may be formed in a curved shape protruding toward the source sub-trench 156. The electric field with respect to the opening edge portion 157 is relaxed by the inclined portion 158.

[0575] The SiC semiconductor device 101 includes a low resistance electrode layer 159 formed on the gate electrode layer 135. The low resistance electrode layer 159 covers an upper end of the gate electrode layer 135 in the gate trench 131. That is, the trench gate structure 151 includes the low resistance electrode layer 159.

[0576] The low resistance electrode layer 159 includes a conductive material having a sheet resistance less than the sheet resistance of the gate electrode layer 135. The sheet resistance of the low resistance electrode layer 159 may be 0.01 Ω / □ or more and 10 Ω / □ or less. The sheet resistance of the low resistance electrode layer 159 may be 0.01 Ω / □ or more and 0.1 Ω / □ or less, 0.1 Ω / □ or more and 1 Ω / □ or less, 1 Ω / □ or more and 2 Ω / □ or less, 2 Ω / □ or more and 4 Ω / □ or less, 4 Ω / □ or more and 6 Ω / □ or less, 6 Ω / □ or more and 8 Ω / □ or less, or 8 Ω / □ or more and 10 Ω / □ or less.

[0577] The current supplied into the gate trench 131 flows through the low resistance electrode layer 159 having a relatively low sheet resistance, and is transmitted to the entire gate electrode layer 135. This allows the entire gate electrode layer 135 to be quickly transitioned from an OFF state to an ON state, thereby suppressing delays in switching response.

[0578] In particular, in the case of the gate trench 131 having a length on the order of millimeters, it takes time to transmit a current, but the delay in the switching response can be appropriately suppressed by using the low-resistance electrode layer 159. In other words, the low-resistance electrode layer 159 is formed as a current diffusion electrode layer that diffuses a current in the gate trench 131.

[0579] The low resistance electrode layer 159 is formed in a film shape. The low resistance electrode layer 159 has a connection portion 159a that contacts the upper end portion of the gate electrode layer 135 and a non-connection portion 159b on the opposite side thereof. The connection portion 159a and the non-connection portion 159b of the low resistance electrode layer 159 may be formed in a curved shape following the upper end portion of the gate electrode layer 135. The connection portion 159a and the non-connection portion 159b of the low resistance electrode layer 159 may take various forms.

[0580] The entirety of the connection portion 159a of the low resistance electrode layer 159 may be located above the first main surface 103. The entirety of the connection portion 159a of the low resistance electrode layer 159 may be located below the first main surface 103.

[0581] The connection portion 159a of the low-resistance electrode layer 159 may include a portion located above the first main surface 103. The connection portion 159a of the low-resistance electrode layer 159 may include a portion located below the first main surface 103. For example, the center portion of the connection portion 159a of the low-resistance electrode layer 159 may be located below the first main surface 103, and the peripheral portion of the connection portion 159a of the low-resistance electrode layer 159 may be located above the first main surface 103.

[0582] The entire non-connected portion 159b of the low resistance electrode layer 159 may be located above the first main surface 103. The entire non-connected portion 159b of the low resistance electrode layer 159 may be located below the first main surface 103.

[0583] The non-connected portion 159b of the low-resistance electrode layer 159 may include a portion located above the first main surface 103. The non-connected portion 159b of the low-resistance electrode layer 159 may include a portion located below the first main surface 103. For example, the center portion of the non-connected portion 159b of the low-resistance electrode layer 159 may be located below the first main surface 103, and the peripheral portion of the non-connected portion 159b of the low-resistance electrode layer 159 may be located above the first main surface 103.

[0584] The low resistance electrode layer 159 has an edge 159c in contact with the gate insulating layer 134. The edge 159c of the low resistance electrode layer 159 is in contact with a corner (in this embodiment, the bulge 134d) in the gate insulating layer 134 that connects the first region 134a and the second region 134b.

[0585] An edge portion 159c of the low-resistance electrode layer 159 is formed in a region on the first main surface 103 side with respect to the bottom of the source region 153. In other words, the edge portion 159c of the low-resistance electrode layer 159 is formed in a region on the first main surface 103 side with respect to the boundary region between the body region 126 and the source region 153.

[0586] Therefore, the edge 159c of the low-resistance electrode layer 159 faces the source region 153 across the gate insulating layer 134. The edge 159c of the low-resistance electrode layer 159 does not face the body region 126 across the gate insulating layer 134. This makes it possible to suppress the formation of a leakage current path in the region of the gate insulating layer 134 between the low-resistance electrode layer 159 and the body region 126.

[0587] The leakage current path may be formed by undesired diffusion of the electrode material of the low resistance electrode layer 159 into the gate insulating layer 134. By connecting the edge portion 159c of the low resistance electrode layer 159 to the relatively thick third region 134c (the bulging portion 134d) in the gate insulating layer 134, the formation of the leakage current path can be appropriately suppressed.

[0588] With respect to the normal direction N, the thickness TR of the low-resistance electrode layer 159 is equal to or smaller than the thickness TG of the gate electrode layer 135 (TR≦TG). More specifically, the thickness TR of the low-resistance electrode layer 159 is equal to or smaller than half the thickness TG of the gate electrode layer 135 (TR≦TG / 2).

[0589] A ratio TR / TG of a thickness TR of the low resistance electrode layer 159 to a thickness TG of the gate electrode layer 135 may be 0.01 or more and 1 or less. The ratio TR / TG may be 0.01 or more and 0.1 or less, 0.1 or more and 0.2 or less, 0.2 or more and 0.4 or less, 0.4 or more and 0.6 or less, 0.6 or more and 0.8 or less, or 0.8 or more and 1 or less.

[0590] The thickness TG of the gate electrode layer 135 may be 0.5 μm or more and 3 μm or less. The thickness TG of the gate electrode layer 135 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less.

[0591] The thickness TR of the low resistance electrode layer 159 may be 0.01 μm or more and 3 μm or less. The thickness TR of the low resistance electrode layer 159 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less.

[0592] In this embodiment, the low-resistance electrode layer 159 also covers the upper end of the gate wiring layer 136. A portion of the low-resistance electrode layer 159 covering the upper end of the gate wiring layer 136 is integrally formed with a portion of the low-resistance electrode layer 159 covering the upper end of the gate electrode layer 135. As a result, the low-resistance electrode layer 159 covers the entire area of ​​the gate electrode layer 135 and the entire area of ​​the gate wiring layer 136.

[0593] Therefore, the current supplied from the gate pad 110 (gate finger 111) flows through the low resistance electrode layer 159 having a relatively low sheet resistance, and is transmitted to the entire gate electrode layer 135 and the gate wiring layer 136. This allows the entire gate electrode layer 135 to be quickly transitioned from the OFF state to the ON state via the gate wiring layer 136, thereby suppressing delays in switching response.

[0594] In particular, in the case of the gate trench 131 having a length on the order of millimeters, the low resistance electrode layer 159 covering the upper end of the gate wiring layer 136 can appropriately suppress delays in switching response.

[0595] The low resistance electrode layer 159 includes a polycide layer. More specifically, the low resistance electrode layer 159 is made of a p-type polycide layer containing p-type impurities added to the gate electrode layer 135 (p-type polysilicon). The polycide layer is formed by silicidizing a surface layer of the gate electrode layer 135 containing p-type polysilicon with a metal material. The silicidation of the p-type polysilicon is performed by heat treatment. The heat treatment may be a rapid thermal annealing (RTA) method.

[0596] In this embodiment, the low resistance electrode layer 159 has a resistivity of 10 μΩ·cm or more and 110 μΩ·cm or less. The resistivity of the low resistance electrode layer 159 may be 10 μΩ·cm or more and 20 μΩ·cm or less, 20 μΩ·cm or more and 40 μΩ·cm or less, 40 μΩ·cm or more and 60 μΩ·cm or less, 60 μΩ·cm or more and 80 μΩ·cm or less, or 80 μΩ·cm or more and 110 μΩ·cm or less.

[0597] More specifically, the low resistance electrode layer 159 contains at least one of TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, and WSi2 as a polycide. Of these, NiSi, CoSi2, and TiSi2 have relatively small resistivity and temperature dependency, and are therefore suitable as a polycide layer forming the low resistance electrode layer 159.

[0598] The sheet resistance in the gate trench 131 in which the gate electrode layer 135 (p-type polysilicon) and the low resistance electrode layer 159 (p-type polycide) are embedded is equal to or lower than the sheet resistance of the gate electrode layer 135 (p-type polysilicon) alone. The sheet resistance in the gate trench 131 is preferably equal to or lower than the sheet resistance of n-type polysilicon doped with n-type impurities.

[0599] The sheet resistance in the gate trench 131 is approximated to the sheet resistance of the low resistance electrode layer 159. That is, the sheet resistance in the gate trench 131 may be 0.01 Ω / □ or more and 10 Ω / □ or less. The sheet resistance in the gate trench 131 may be 0.01 Ω / □ or more and 0.1 Ω / □ or less, 0.1 Ω / □ or more and 1 Ω / □ or less, 1 Ω / □ or more and 2 Ω / □ or less, 2 Ω / □ or more and 4 Ω / □ or less, 4 Ω / □ or more and 6 Ω / □ or less, 6 Ω / □ or more and 8 Ω / □ or less, or 8 Ω / □ or more and 10 Ω / □ or less. The sheet resistance in the gate trench 131 is preferably less than 10 Ω / □.

[0600] 42 and 43, the active region 106 has an active main surface 161 forming a part of the first main surface 103. The outer region 107 has an outer main surface 162 forming a part of the first main surface 103. The outer main surface 162 is connected to the side surfaces 105A to 105D.

[0601] The outer principal surface 162 is located on the second principal surface 104 side with respect to the active principal surface 161. In this embodiment, the outer region 107 is formed by digging the first principal surface 103 toward the second principal surface 104 side. Therefore, the outer region 107 is formed in a region recessed toward the second principal surface 104 side with respect to the active principal surface 161.

[0602] The outer main surface 162 may be located on the second main surface 104 side with respect to the bottom wall of the gate trench 131. The outer main surface 162 may be formed at a depth position substantially equal to the bottom wall of the source trench 141. In other words, the outer main surface 162 may be located on substantially the same plane as the bottom wall of the source trench 141. The distance between the outer main surface 162 and the second main surface 104 may be substantially equal to the distance between the bottom wall of the source trench 141 and the second main surface 104.

[0603] The outer main surface 162 may be located on the second main surface 104 side with respect to the bottom wall of the source trench 141. The outer main surface 162 may be located on the second main surface 104 side with respect to the bottom wall of the source trench 141 within a range of more than 0 μm and not more than 1 μm.

[0604] The SiC epitaxial layer 122 is exposed from the outer main surface 162. More specifically, a high concentration region 122a of the SiC epitaxial layer 122 is exposed from the outer main surface 162. The outer main surface 162 faces a low concentration region 122b of the SiC epitaxial layer 122, with the high concentration region 122a of the SiC epitaxial layer 122 sandwiched therebetween.

[0605] In this embodiment, the active area 106 is partitioned into a plateau shape by the outer area 107. That is, the active area 106 is formed as an active plateau 163 that protrudes upward from the outer area 107.

[0606] The active plateau 163 includes an active sidewall 164 connecting the active main surface 161 and the outer main surface 162. The first main surface 103 of the SiC semiconductor layer 102 is formed by the active main surface 161, the outer main surface 162 and the active sidewall 164.

[0607] In this embodiment, the active sidewall 164 extends along a direction substantially perpendicular to the active principal surface 161 (the outer principal surface 162). The active sidewall 164 may be inclined downward from the active principal surface 161 toward the outer principal surface 162. The active sidewall 164 defines a boundary region between the active region 106 and the outer region 107.

[0608] The SiC epitaxial layer 122 is exposed from the active sidewall 164. More specifically, the high concentration region 122a of the SiC epitaxial layer 122 is exposed from the active sidewall 164. This allows the main structure of the MISFET to be appropriately formed in the high concentration region 122a defined by the active plateau 163.

[0609] At least the body region 126 is exposed from the region of the active sidewall 164 on the active main surface 161 side.

[0610] The SiC semiconductor device 101 has a p-type ferroelectric material formed in a surface layer of the outer main surface 162 (first main surface 103) in the outer region 107. + The semiconductor device includes a p-type diode region 171, a p-type outer deep well region 172, and a p-type field limit structure 173.

[0611] The diode region 171 is formed in a region between the active sidewall 164 and the side surfaces 105A-105D in the outer region 107. The diode region 171 is formed at a distance from the active sidewall 164 and the side surfaces 105A-105D.

[0612] The diode region 171 extends in a strip shape along the active region 106 in a plan view. In this embodiment, the diode region 171 is formed in a ring shape (for example, endless shape) surrounding the active region 106 in a plan view.

[0613] The diode region 171 overlaps with the source lead-out wiring 114 in a plan view. The diode region 171 is electrically connected to the source lead-out wiring 114. The diode region 171 forms a part of the avalanche current absorption structure.

[0614] The diode region 171 forms a pn junction with the SiC semiconductor layer 102. More specifically, the diode region 171 is located in the SiC epitaxial layer 122. Therefore, the diode region 171 forms a pn junction with the SiC epitaxial layer 122.

[0615] More specifically, the diode region 171 is located in the high concentration region 122a of the SiC epitaxial layer 122. Therefore, the diode region 171 forms a pn junction with the high concentration region 122a of the SiC epitaxial layer 122. This forms a pn junction diode 174 with the diode region 171 as the anode and the SiC semiconductor layer 102 as the cathode.

[0616] The entire diode region 171 is located on the second main surface 104 side with respect to the bottom wall of the gate trench 131. The bottom of the diode region 171 is located on the second main surface 104 side with respect to the bottom wall of the source trench 141. The bottom of the diode region 171 may be formed at a depth position substantially equal to the bottom of the contact region 154. In other words, the bottom of the diode region 171 may be located on substantially the same plane as the bottom of the contact region 154.

[0617] The distance between the bottom of diode region 171 and second main surface 104 may be approximately equal to the distance between the bottom of contact region 154 and second main surface 104. The bottom of diode region 171 may be located on the second main surface 104 side with respect to the bottom of contact region 154. The bottom of diode region 171 may be located on the second main surface 104 side with respect to the bottom of contact region 154 within a range of more than 0 μm and not more than 1 μm.

[0618] The p-type impurity concentration of the diode region 171 is approximately equal to the p-type impurity concentration of the contact region 154. The p-type impurity concentration of the diode region 171 exceeds the p-type impurity concentration of the body region 126. The p-type impurity concentration of the diode region 171 is approximately equal to the p-type impurity concentration of the contact region 154. 18 cm -3 Above 1.0×10 21 cm -3 It may be the following.

[0619] The outer deep well region 172 is formed in a region between the active sidewall 164 and the diode region 171 in a plan view. In this embodiment, the outer deep well region 172 is formed at an interval from the active sidewall 164 toward the diode region 171. The outer deep well region 172 is also referred to as a breakdown voltage adjusting region (breakdown voltage holding region) that adjusts the breakdown voltage of the SiC semiconductor layer 102 in the outer region 107.

[0620] The outer deep well region 172 extends in a strip shape along the active region 106 in a plan view. In this embodiment, the outer deep well region 172 is formed in an annular (for example, endless) shape surrounding the active region 106 in a plan view.

[0621] The bottom of the outer deep well region 172 is located on the second main surface 104 side with respect to the bottom of the diode region 171. In this embodiment, the outer deep well region 172 covers the diode region 171 from the second main surface 104 side. The outer deep well region 172 may overlap with the source lead-out wiring 114 in a plan view.

[0622] The outer deep well region 172 is electrically connected to the source lead-out wiring 114 via the diode region 171. The outer deep well region 172 may form part of a pn junction diode 174. The outer deep well region 172 may form part of an avalanche current absorption structure.

[0623] The entire outer deep well region 172 is located on the second main surface 104 side with respect to the bottom wall of the gate trench 131. The bottom of the outer deep well region 172 is located on the second main surface 104 side with respect to the bottom wall of the source trench 141.

[0624] The bottom of the outer deep well region 172 may be formed at a depth position approximately equal to the bottom of the deep well region 155. In other words, the bottom of the outer deep well region 172 may be located on approximately the same plane as the bottom of the deep well region 155. The distance between the bottom of the outer deep well region 172 and the outer main surface 162 may be approximately equal to the distance between the bottom of the deep well region 155 and the bottom wall of the source trench 141.

[0625] The distance between the bottom of the outer deep well region 172 and the second main surface 104 may be approximately equal to the distance between the bottom of the deep well region 155 and the second main surface 104. This makes it possible to suppress variation between the distance between the bottom of the outer deep well region 172 and the second main surface 104 of the deep well region 155 and the distance between the bottom of the deep well region 155 and the second main surface 104.

[0626] In this case, the withstand voltage (eg, electrostatic breakdown resistance) of the SiC semiconductor layer 102 can be prevented from being limited by the outer deep well region 172 and the deep well region 155, so that the withstand voltage can be appropriately improved.

[0627] The bottom of the outer deep well region 172 may be located on the second main surface 104 side with respect to the bottom of the deep well region 155. The bottom of the outer deep well region 172 may be located on the second main surface 104 side with respect to the bottom of the deep well region 155 within a range of more than 0 μm and not more than 1 μm.

[0628] The p-type impurity concentration of the outer deep well region 172 may be equal to or lower than the p-type impurity concentration of the diode region 171. The p-type impurity concentration of the outer deep well region 172 may be lower than the p-type impurity concentration of the diode region 171.

[0629] The p-type impurity concentration of the outer deep well region 172 may be approximately equal to the p-type impurity concentration of the deep well region 155. The p-type impurity concentration of the outer deep well region 172 may be approximately equal to the p-type impurity concentration of the body region 126.

[0630] The p-type impurity concentration of the outer deep well region 172 may be greater than the p-type impurity concentration of the body region 126. The p-type impurity concentration of the outer deep well region 172 may be less than the p-type impurity concentration of the body region 126.

[0631] The p-type impurity concentration of the outer deep well region 172 may be equal to or less than the p-type impurity concentration of the contact region 154. The p-type impurity concentration of the outer deep well region 172 may be less than the p-type impurity concentration of the contact region 154. The p-type impurity concentration of the outer deep well region 172 may be greater than or equal to 1.0×10 17 cm -3 Above 1.0×10 19 cm -3 It may be the following.

[0632] The field limit structure 173 is formed in a region between the diode region 171 and the side surfaces 105A to 105D in a plan view. In this embodiment, the field limit structure 173 is formed at an interval from the diode region 171 toward the side surfaces 105A to 105D.

[0633] The field limit structure 173 includes one or more (for example, 2 to 20) field limit regions. In this embodiment, the field limit structure 173 includes a field limit region group having a plurality (five) of field limit regions 175A, 175B, 175C, 175D, and 175E.

[0634] The field limit regions 175A to 175E are formed in this order at intervals in a direction away from the diode region 171. The field limit regions 175A to 175E are each formed in a strip shape extending along the periphery of the active region 106 in a plan view.

[0635] More specifically, the field limit regions 175A to 175E are each formed in a ring shape (for example, endless shape) in a plan view surrounding the active region 106. The field limit regions 175A to 175E are also referred to as FLR (Field Limiting Ring) regions.

[0636] In this embodiment, the bottoms of the field limit regions 175A to 175E are located on the second main surface 104 side with respect to the bottom of the diode region 171. In this embodiment, the innermost field limit region 175A of the field limit regions 175A to 175E covers the diode region 171 from the second main surface 104 side.

[0637] The field limit region 175A may overlap with the above-mentioned source lead-out wiring 114 in a plan view. The field limit region 175A may be electrically connected to the source lead-out wiring 114 via the diode region 171. The field limit region 175A may form a part of the pn junction diode 174. The field limit region 175A may form a part of the avalanche current absorption structure.

[0638] The entire field limit regions 175A to 175E are located on the second main surface 104 side with respect to the bottom wall of the gate trench 131. The bottoms of the field limit regions 175A to 175E are located on the second main surface 104 side with respect to the bottom wall of the source trench 141.

[0639] The field limit regions 175A-175E may be formed at a depth position substantially equal to that of the deep well region 155 (outer deep well region 172). In other words, the bottoms of the field limit regions 175A-175E may be located on substantially the same plane as the bottom of the deep well region 155 (outer deep well region 172).

[0640] The bottoms of the field limit regions 175A-175E may be located on the outer main surface 162 side with respect to the bottom of the deep well region 155 (outer deep well region 172). The bottoms of the field limit regions 175A-175E may be located on the second main surface 104 side with respect to the bottom of the deep well region 155 (outer deep well region 172).

[0641] The width between adjacent field limit regions 175A-175E may be different from each other. The distance between adjacent field limit regions 175A-175E may be increased in a direction away from the active region 106. The distance between adjacent field limit regions 175A-175E may be decreased in a direction away from the active region 106.

[0642] The depths of the field limit regions 175A to 175E may be different from one another. The depths of the field limit regions 175A to 175E may decrease in a direction away from the active region 106. The depths of the field limit regions 175A to 175E may increase in a direction away from the active region 106.

[0643] The p-type impurity concentration of the field limit regions 175A to 175E may be equal to or lower than the p-type impurity concentration of the diode region 171. The p-type impurity concentration of the field limit regions 175A to 175E may be lower than the p-type impurity concentration of the diode region 171.

[0644] The p-type impurity concentration of the field limit regions 175A-175E may be equal to or lower than the p-type impurity concentration of the outer deep well region 172. The p-type impurity concentration of the field limit regions 175A-175E may be lower than the p-type impurity concentration of the outer deep well region 172.

[0645] The p-type impurity concentration of the field limit regions 175A-175E may be equal to or higher than the p-type impurity concentration of the outer deep well region 172. The p-type impurity concentration of the field limit regions 175A-175E may be higher than the p-type impurity concentration of the outer deep well region 172.

[0646] The p-type impurity concentration of the field limit regions 175A to 175E is 1.0×10 15 cm -3 Above 1.0×10 18 cm -3 It is preferable that the p-type impurity concentration of the field limit regions 175A to 175E<the p-type impurity concentration of the outer deep well region 172<the p-type impurity concentration of the diode region 171.

[0647] The field limit structure 173 relieves electric field concentration in the outer region 107. The number, width, depth, p-type impurity concentration, etc. of the field limit regions can take various values ​​depending on the electric field to be relieved.

[0648] The SiC semiconductor device 101 includes an outer insulating layer 181 formed on the outer main surface 162 (first main surface 103) in the outer region 107. The outer insulating layer 181 selectively covers the diode region 171, the outer deep well region 172, and the field limit structure 173 in the outer region 107.

[0649] The outer insulating layer 181 is formed in a film shape along the active sidewall 164 and the outer main surface 162. The outer insulating layer 181 is continuous with the gate insulating layer 134 on the active main surface 161. More specifically, the outer insulating layer 181 is continuous with the third region 134c of the gate insulating layer 134.

[0650] The outer insulating layer 181 may include silicon oxide. The outer insulating layer 181 may include other insulating films such as silicon nitride. In this embodiment, the outer insulating layer 181 is formed of the same insulating material type as the gate insulating layer 134.

[0651] The outer insulating layer 181 includes a first region 181a and a second region 181b. The first region 181a of the outer insulating layer 181 covers the active sidewall 164. The second region 181b of the outer insulating layer 181 covers the outer main surface 162.

[0652] The thickness of the second region 181b of the outer insulating layer 181 may be equal to or less than the thickness of the first region 181a of the outer insulating layer 181. The thickness of the second region 181b of the outer insulating layer 181 may be less than the thickness of the first region 181a of the outer insulating layer 181.

[0653] The thickness of the first region 181a of the outer insulating layer 181 may be approximately equal to the thickness of the first region 134a of the gate insulating layer 134. The thickness of the second region 181b of the outer insulating layer 181 may be approximately equal to the thickness of the third region 134c of the gate insulating layer 134. The outer insulating layer 181 may be formed to have a uniform thickness.

[0654] 42 and 43, SiC semiconductor device 101 includes a sidewall 182 that covers active sidewall 164. Sidewall 182 protects and reinforces active plateau 163 from the outer region 107 side.

[0655] The sidewalls 182 form a step reducing structure that reduces a step 183 formed between the active principal surface 161 and the outer principal surface 162. When an upper layer structure is formed that covers the boundary region between the active region 106 and the outer region 107, the upper layer structure covers the sidewalls 182. The sidewalls 182 increase the planarity of the upper layer structure.

[0656] The sidewall 182 may have an inclined portion 184 that slopes downward from the active principal surface 161 toward the outer principal surface 162. The inclined portion 184 can appropriately reduce the step 183. The inclined portion 184 may be formed in a curved shape that is recessed toward the SiC semiconductor layer 102 side. The inclined portion 184 may be formed in a curved shape that protrudes outward from the SiC semiconductor layer 102.

[0657] The sidewall 182 is formed in a self-aligned manner with respect to the active main surface 161. More specifically, the sidewall 182 is formed along the active sidewall 164. In this embodiment, the sidewall 182 is formed in a ring shape (for example, endless shape) surrounding the active region 106 in a plan view.

[0658] The sidewalls 182 may include an insulating material. In this case, the sidewalls 182 can improve the insulation of the active region 106 from the outer region 107. The sidewalls 182 may include a conductive material.

[0659] The sidewalls 182 may include the same conductive material type as the gate electrode layer 135. The sidewalls 182 may include the same conductive material type as the source electrode layer 143. This allows the sidewalls 182 to be formed simultaneously with the gate electrode layer 135 and / or the source electrode layer 143.

[0660] In this embodiment, the sidewall 182 includes polysilicon. The sidewall 182 may include n-type polysilicon or p-type polysilicon. When the gate electrode layer 135 includes p-type polysilicon doped with p-type impurities, the sidewall 182 preferably includes p-type polysilicon doped with p-type impurities. The p-type impurities of the sidewall 182 may include at least one of boron (B), aluminum (Al), indium (In), and gallium (Ga).

[0661] The p-type impurity concentration of the sidewall 182 is equal to or greater than the p-type impurity concentration of the body region 126. More specifically, the p-type impurity concentration of the sidewall 182 exceeds the p-type impurity concentration of the body region 126. The p-type impurity concentration of the sidewall 182 may be approximately equal to the p-type impurity concentration of the gate electrode layer 135. The sheet resistance of the source electrode layer 143 may be approximately equal to the sheet resistance of the gate electrode layer 135.

[0662] The p-type impurity concentration of the sidewall 182 is 1×10 18 cm -3 More than 1×10 22 cm -3 The sheet resistance of the sidewall 182 may be 10 Ω / □ or more and 500 Ω / □ or less (about 200 Ω / □ in this embodiment).

[0663] 39 to 43, SiC semiconductor device 101 includes an interlayer insulating layer 191 formed on first main surface 103. Interlayer insulating layer 191 selectively covers active region 106 and outer region 107. Interlayer insulating layer 191 is formed in the form of a film along active main surface 161 and outer main surface 162.

[0664] The interlayer insulating layer 191 selectively covers the trench gate structure 151, the gate wiring layer 136, and the trench source structure 152 in the active region 106. The interlayer insulating layer 191 selectively covers the diode region 171, the outer deep well region 172, and the field limit structure 173 in the outer region 107.

[0665] The interlayer insulating layer 191 is formed along the outer surface (inclined portion 184) of the sidewall 182 in the boundary region between the active region 106 and the outer region 107. The peripheral edge of the interlayer insulating layer 191 may be formed flush with the side surfaces 105A to 105D.

[0666] The interlayer insulating layer 191 may include silicon oxide or silicon nitride. The interlayer insulating layer 191 may include phosphorus silicate glass (PSG) and / or boron phosphorus silicate glass (BPSG), which are examples of silicon oxide.

[0667] The interlayer insulating layer 191 may have a single layer structure made of a PSG layer or a BPSG layer. The interlayer insulating layer 191 may have a multilayer structure including a PSG layer or a BPSG layer stacked in this order from the first main surface 103 side. The interlayer insulating layer 191 may have a multilayer structure including a BPSG layer or a PSG layer stacked in this order from the first main surface 103 side.

[0668] A gate contact hole 192, a source contact hole 193, a diode contact hole 194, and an anchor hole 195 are formed in the interlayer insulating layer 191. The gate contact hole 192 exposes the gate wiring layer 136 in the active region 106. The gate contact hole 192 may be formed in a strip shape along the gate wiring layer 136.

[0669] An opening edge portion of the gate contact hole 192 is formed in a curved shape toward the inside of the gate contact hole 192. The opening edge portion of the gate contact hole 192 may be formed in a curved shape recessed toward the interlayer insulating layer 191.

[0670] The source contact hole 193 exposes the source region 153, the contact region 154, and the trench source structure 152 in the active region 106. The source contact hole 193 may be formed in a strip shape along the trench source structure 152, etc.

[0671] An opening edge portion of the source contact hole 193 is formed in a curved shape toward the inside of the source contact hole 193. The opening edge portion of the source contact hole 193 may be formed in a curved shape recessed toward the inside of the interlayer insulating layer 191.

[0672] The diode contact hole 194 exposes the diode region 171 in the outer region 107. The diode contact hole 194 may be formed in a strip shape (more specifically, an endless shape (annular shape)) extending along the diode region 171.

[0673] The diode contact hole 194 may expose the outer deep well region 172 and / or the field limit structure 173. An opening edge portion of the diode contact hole 194 is formed in a curved shape toward the inside of the diode contact hole 194. An opening edge portion of the diode contact hole 194 may be formed in a curved shape recessed toward the inside of the interlayer insulating layer 191.

[0674] The anchor holes 195 are formed by digging down the interlayer insulating layer 191 in the outer region 107. The anchor holes 195 expose the first main surface 103 (the outer main surface 162). The anchor holes 195 are formed in the regions between the field limit structure 173 and the side surfaces 105A to 105D in a plan view.

[0675] 37, the anchor hole 195 extends in a band shape along the active region 106 in a plan view. In this embodiment, the anchor hole 195 is formed in a ring shape (for example, endless shape) surrounding the active region 106 in a plan view.

[0676] An opening edge portion of the anchor hole 195 is formed in a curved shape toward the inside of the anchor hole 195. An opening edge portion of the anchor hole 195 may be formed in a curved shape recessed toward the inside of the interlayer insulating layer 191.

[0677] 42 and 44, an inclined portion 196 and a modified layer 197 are formed in the outer region 107. The modified layer 197 is formed by modifying SiC to have other properties. The inclined portion 196 and the modified layer 197 correspond to the inclined portion 41 and the modified layer 42 of the SiC semiconductor device 21, respectively. The description of the components of the modified layer 197 applies mutatis mutandis to the description of the components of the modified layer 42 (see also FIGS. 21 and 22).

[0678] Inclined portions 196 are formed at corners connecting outer principal surface 162 (first principal surface 103) and side surfaces 105A-105D. The corners of SiC semiconductor layer 102 include corners that connect outer principal surface 162 and side surfaces 105A, 105C and extend along the [1-100] direction. The corners of SiC semiconductor layer 102 include corners that connect outer principal surface 162 and side surfaces 105B, 105D and extend along the [11-20] direction.

[0679] Inclined portion 196 slopes downward from outer principal surface 162 toward side surfaces 105A-105D. Inclined portion 196 is formed by the inner wall of a recess that is recessed from outer principal surface 162 toward second principal surface 104 at a corner of SiC semiconductor layer 102.

[0680] In this embodiment, the inclined portion 196 is formed in the SiC epitaxial layer 122. The inclined portion 196 is formed in a region on the outer main surface 162 side with respect to the boundary region between the SiC semiconductor substrate 121 and the SiC epitaxial layer 122. Therefore, the SiC epitaxial layer 122 is exposed from the inclined portion 196.

[0681] More specifically, the inclined portion 196 is formed in a region on the outer main surface 162 side of the boundary region between the high concentration region 122a and the low concentration region 122b in the SiC epitaxial layer 122. In other words, the high concentration region 122a is exposed from the inclined portion 196.

[0682] The inclined portion 196 has an upper end 196a and a lower end 196b. The upper end 196a of the inclined portion 196 is located on the outer main surface 162 side. The lower end 196b of the inclined portion 196 is located on the second main surface 104 side.

[0683] In this embodiment, an upper end 196a of the inclined portion 196 extends from the SiC epitaxial layer 122 toward an insulating laminated structure 198 including the outer insulating layer 181 and the interlayer insulating layer 191, and is continuous with the insulating laminated structure 198. That is, the SiC epitaxial layer 122 and the insulating laminated structure 198 are exposed from the inclined portion 196. The peripheral portion of the insulating laminated structure 198 is formed in an inner region of the SiC semiconductor layer 102 with respect to the side surfaces 105A to 105D. The insulating laminated structure 198 corresponds to the insulating layer 35 of the SiC semiconductor device 21 described above.

[0684] An upper end 196a of the inclined portion 196 is connected to the upper surface of the interlayer insulating layer 191. In the inclined portion 196, an upper connection portion 196c that connects the upper end 196a of the inclined portion 196 and the upper surface of the insulating stacked structure 198 may be formed in a curved shape extending outward from the SiC semiconductor layer 102.

[0685] The lower end 196b of the inclined portion 196 exposes the SiC epitaxial layer 122. More specifically, the lower end 196b of the inclined portion 196 exposes the high concentration region 122a of the SiC epitaxial layer 122. The lower end 196b of the inclined portion 196 is connected to the side surfaces 105A to 105D. The lower end 196b of the inclined portion 196 may be formed in a curved shape toward the second main surface 104.

[0686] 44, the width WI of the inclined portion 196 may be equal to or smaller than the in-plane variation of the side surfaces 105A to 105D. The width WI of the inclined portion 196 may be smaller than the in-plane variation of the side surfaces 105A to 105D. The width WI of the inclined portion 196 is the width in a direction perpendicular to the direction in which the inclined portion 196 extends in a plan view.

[0687] The width WI of the inclined portion 196 may be more than 0 μm and not more than 10 μm. The width WI of the inclined portion 196 may be more than 0 μm and not more than 2 μm, 2 μm or more and not more than 4 μm, 4 μm or more and not more than 6 μm, 6 μm or more and not more than 8 μm, or 8 μm or more and not more than 10 μm. When the thickness of the SiC semiconductor layer 102 is 150 μm or less, the width WI of the inclined portion 196 is preferably more than 0 μm and not more than 5 μm. The width WI of the inclined portion 196 is more preferably more than 0 μm and not more than 2.5 μm.

[0688] The depth D of the inclined portion 196 may be more than 0 μm and not more than 30 μm. The depth D of the inclined portion 196 is the distance from the outer main surface 162 (first main surface 103) to the lower end 196b of the inclined portion 196 in relation to the normal direction N. The depth D of the inclined portion 196 may be more than 0 μm and not more than 5 μm, 5 μm or more and not more than 10 μm, 10 μm or more and not more than 15 μm, 15 μm or more and not more than 20 μm, 20 μm or more and not more than 25 μm, or 25 μm or more and not more than 30 μm. When the thickness of the SiC semiconductor layer 102 is 150 μm or less, the depth D of the inclined portion 196 is preferably more than 0 μm and not more than 15 μm.

[0689] The modified layer 197 is formed in the region of the side surfaces 105A to 105D on the first principal surface 103 side. More specifically, the modified layer 197 is formed along the corners connecting the outer principal surface 162 and the side surfaces 105A to 105D. More specifically, the modified layer 197 is formed in the corners connecting the outer principal surface 162 and the side surfaces 105A and 105C and extending along the [1-100] direction. The modified layer 197 is formed in the corners connecting the outer principal surface 162 and the side surfaces 105B and 105D and extending along the [11-20] direction.

[0690] In this embodiment, the modified layer 197 is formed in the SiC epitaxial layer 122. More specifically, the modified layer 197 is formed in a region on the outer main surface 162 side with respect to the boundary region between the SiC semiconductor substrate 121 and the SiC epitaxial layer 122. More specifically, the modified layer 197 is formed in the high concentration region 122a of the SiC epitaxial layer 122. In this embodiment, the modified layer 197 is formed in a region on the outer main surface 162 side with respect to the boundary region between the high concentration region 122a and the low concentration region 122b.

[0691] In this embodiment, the modified layer 197 extends in a strip shape on the side surfaces 105A to 105D in a direction parallel to the outer main surface 162. That is, the modified layer 197 extends in a strip shape along the [1-100] direction and the [11-20] direction. The modified layer 197 is formed in a ring shape (e.g., endless shape) surrounding the outer region 107 on the side surfaces 105A to 105D.

[0692] 44, the width WM of the modified layer 197 may be equal to or smaller than the in-plane variation of the side surfaces 105A to 105D. The width WM of the modified layer 197 may be smaller than the in-plane variation of the side surfaces 105A to 105D. The width WM of the modified layer 197 is the width in a direction perpendicular to the direction in which the modified layer 197 extends in a plan view.

[0693] The width WM of the modified layer 197 may be more than 0 μm and not more than 10 μm. The width WM of the modified layer 197 may be more than 0 μm and not more than 2 μm, 2 μm or more and not more than 4 μm, 4 μm or more and not more than 6 μm, 6 μm or more and not more than 8 μm, or 8 μm or more and not more than 10 μm. When the thickness of the SiC semiconductor layer 102 is 150 μm or less, the width WM of the modified layer 197 is preferably more than 0 μm and not more than 5 μm. The width WM of the modified layer 197 is more preferably more than 0 μm and not more than 2.5 μm.

[0694] The thickness T of the modified layer 197 may be more than 0 μm and not more than 30 μm. The thickness T of the modified layer 197 is the thickness along the normal direction N of the modified layer 197. The thickness T of the modified layer 197 may be more than 0 μm and not more than 5 μm, 5 μm or more and not more than 10 μm, 10 μm or more and not more than 15 μm, 15 μm or more and not more than 20 μm, 20 μm or more and not more than 25 μm, or 25 μm or more and not more than 30 μm. When the thickness of the SiC semiconductor layer 102 is not more than 150 μm, the thickness T of the modified layer 197 is preferably more than 0 μm and not more than 15 μm.

[0695] The modified layer 197 is formed in the form of a film along the inclined portion 196 of the SiC semiconductor layer 102. The thickness of the portion of the modified layer 197 covering the bottom wall of the inclined portion 196 may be greater than the thickness of the portion of the modified layer 197 covering the side wall of the inclined portion 196. The modified layer 197 may be formed with a uniform thickness along the inner wall of the inclined portion 196.

[0696] The modified layer 197 includes an upper covering portion 197a and a lower covering portion 197b. The upper covering portion 197a of the modified layer 197 covers an upper end portion 196a of the inclined portion 196. The lower covering portion 197b of the modified layer 197 covers a lower end portion 196b of the inclined portion 196.

[0697] The upper covering portion 197a of the modified layer 197 covers the SiC epitaxial layer 122. More specifically, the upper covering portion 197a of the modified layer 197 covers the high concentration region 122a. The modified layer 197 extends from the SiC epitaxial layer 122 toward the insulating stacked structure 198 and covers the insulating stacked structure 198. The upper covering portion 197a of the modified layer 197 may be formed in a curved shape extending outward from the SiC semiconductor layer 102.

[0698] The lower covering portion 197b of the modified layer 197 covers the SiC epitaxial layer 122. More specifically, the lower covering portion 197b of the modified layer 197 covers the high concentration region 122a. The lower covering portion 197b of the modified layer 197 includes a connecting portion 197c connected to the side surfaces 105A to 105D. The connecting portion 197c of the modified layer 197 may be a cleaved portion of the modified layer 197. The connecting portion 197c of the modified layer 197 may be formed flush with the side surfaces 105A to 105D.

[0699] The aforementioned gate terminal electrode layer 108 and source terminal electrode layer 109 are formed on an interlayer insulating layer 191. The gate terminal electrode layer 108 and the source terminal electrode layer 109 each have a laminated structure including a barrier electrode layer 201 and a main electrode layer 202 laminated in this order from the first main surface 103 side.

[0700] The barrier electrode layer 201 may have a single-layer structure made of a titanium layer or a titanium nitride layer, or may have a laminated structure including a titanium layer and a titanium nitride layer laminated in this order from the first main surface 103 side.

[0701] The thickness of the main electrode layer 202 exceeds the thickness of the barrier electrode layer 201. The main electrode layer 202 comprises a conductive material having a resistance value lower than the resistance value of the barrier electrode layer 201. The main electrode layer 202 may comprise at least one of aluminum, copper, an aluminum alloy, and a copper alloy. The main electrode layer 202 may comprise at least one of an aluminum-silicon alloy, an aluminum-silicon-copper alloy, and an aluminum-copper alloy. In this embodiment, the main electrode layer 202 comprises an aluminum-silicon-copper alloy.

[0702] The gate finger 111 of the gate terminal electrode layer 108 enters the gate contact hole 192 from above the interlayer insulating layer 191. The gate finger 111 is electrically connected to the gate wiring layer 136 in the gate contact hole 192. This allows an electrical signal from the gate pad 110 to be transmitted to the gate electrode layer 135 via the gate finger 111.

[0703] The source pad 113 of the source terminal electrode layer 109 extends into the source contact hole 193 and the source sub-trench 156 from above the interlayer insulating layer 191. The source pad 113 is electrically connected to the source region 153, the contact region 154, and the source electrode layer 143 in the source contact hole 193 and the source sub-trench 156.

[0704] The above-mentioned source electrode layer 143 may be formed by utilizing a partial region of the source pad 113. In other words, the source electrode layer 143 may be formed by a portion of the source pad 113 that extends into the source trench 141.

[0705] The source lead-out wiring 114 of the source terminal electrode layer 109 enters the diode contact hole 194 from above the interlayer insulating layer 191. The source lead-out wiring 114 is electrically connected to the diode region 171 in the diode contact hole 194.

[0706] A source connection portion 115 of the source terminal electrode layer 109 is led out from the active region 106 across the sidewall 182 to the outer region 107. The source connection portion 115 forms a part of an upper layer structure covering the sidewall 182.

[0707] The SiC semiconductor device 101 includes a passivation layer 203 formed on the interlayer insulating layer 191. The passivation layer 203 may include silicon oxide and / or silicon nitride. In this embodiment, the passivation layer 203 has a single-layer structure made of a silicon nitride layer.

[0708] The passivation layer 203 is formed in a film shape along the interlayer insulating layer 191. The passivation layer 203 selectively covers the active region 106 and the outer region 107 via the interlayer insulating layer 191.

[0709] The passivation layer 203 extends from the active region 106 across the sidewalls 182 to the outer region 107. The passivation layer 203 forms part of an upper structure covering the sidewalls 182.

[0710] A gate subpad opening 204 and a source subpad opening 205 (see also FIG. 37) are formed in the passivation layer 203. The gate subpad opening 204 exposes the gate pad 110. The source subpad opening 205 exposes the source pad 113.

[0711] 42, passivation layer 203 extends from above interlayer insulating layer 191 into anchor hole 195 in outer region 107. Passivation layer 203 is connected to outer main surface 162 (first main surface 103) within anchor hole 195. A recess is formed in the outer surface of passivation layer 203 in a region located above anchor hole 195, following the shape of anchor hole 195.

[0712] The peripheral portion of the passivation layer 203 may be formed flush with the side surfaces 105A to 105D. The peripheral portion of the passivation layer 203 may be formed spaced apart from the side surfaces 105A to 105D inward. In other words, the peripheral portion of the passivation layer 203 may expose the interlayer insulating layer 191.

[0713] The peripheral portion of passivation layer 203 may be a portion that formed part of a dicing street when cutting out SiC semiconductor device 101 from 4H-SiC crystal structure 1. By exposing outer main surface 162 (first main surface 103) from the peripheral portion of passivation layer 203, it becomes unnecessary to physically cut passivation layer 203. Therefore, SiC semiconductor device 101 can be smoothly cut out from 4H-SiC crystal structure 1.

[0714] The aforementioned resin layer 116 is formed on the passivation layer 203. The resin layer 116 is formed in a film shape along the passivation layer 203. The resin layer 116 selectively covers the active region 106 and the outer region 107 with the passivation layer 203 and the interlayer insulating layer 191 sandwiched therebetween.

[0715] The resin layer 116 is extended from the active region 106 across the sidewall 182 to the outer region 107. The resin layer 116 forms part of an upper layer structure that covers the sidewall 182.

[0716] The gate pad opening 117 of the resin layer 116 communicates with the gate subpad opening 204 of the passivation layer 203. The inner wall of the gate pad opening 117 is located outside the inner wall of th...

Claims

1. Providing a crystal structure; forming a first portion to be cut on a surface of the crystal structure, the first portion having a first depression extending in a thickness direction of the crystal structure and a first modified layer along a wall surface of the first depression; forming a second portion to be cut on a surface of the crystal structure, the second portion having a second depression extending in a thickness direction of the crystal structure and a second modified layer along a wall surface of the second depression and intersecting with the first portion to be cut; a cutting step of cleaving or cutting the crystal structure along the first portion to be cut and the second portion to be cut, a thickness of a portion of the first modified layer covering a bottom wall of the first recess is greater than a thickness of a portion of the first modified layer covering a side wall of the first recess; A method for manufacturing a semiconductor device, wherein a thickness of a portion of the second modified layer covering a bottom wall of the second recess is greater than a thickness of a portion of the second modified layer covering a side wall of the second recess.

2. The crystal structure is a hexagonal crystal, The first intended cutting portion extends in an m-axis direction of the hexagonal crystal, The method for manufacturing a semiconductor device according to claim 1 , wherein the second intended cutting portion extends in an a-axis direction of the hexagonal crystal.

3. the step of forming the first portion to be cut includes a step of forming the first depression by heating the crystal structure, 3 . The method for manufacturing a semiconductor device according to claim 1 , wherein the step of forming the second portion to be cut includes the step of forming the second recess by heating the crystal structure.

4. The step of forming the first recess also serves as a step of forming the first modified layer, The method for manufacturing a semiconductor device according to claim 3 , wherein the step of forming the second recess also serves as a step of forming the second modified layer.

5. The first cut portion has the first recess having a tapered shape, 5. The method for manufacturing a semiconductor device according to claim 1, wherein the second portion to be cut has the second recess having a tapered shape.

6. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein the cutting process includes a process of cleaving the crystal structure starting from the first intended cutting portion, and a process of cleaving the crystal structure starting from the second intended cutting portion.

7. the cleaving step of the first portion to be cut includes a step of heating and cooling the first portion to be cut, 7. The method for manufacturing a semiconductor device according to claim 1, wherein the step of cleaving the second portion to be cut includes the step of heating and cooling the second portion to be cut.

8. The method for manufacturing a semiconductor device according to any one of claims 1 to 7, further comprising, prior to the step of forming the first planned cutting portion and the step of forming the second planned cutting portion, a step of setting a device region on a surface of the crystal structure and forming a functional device in the device region.

9. The crystal structure is a hexagonal crystal, the device region has a first side extending in an m-axis direction of the hexagonal crystal and a second side extending in an a-axis direction of the hexagonal crystal; the first cutting portion extends along the first side of the device region, The method for manufacturing a semiconductor device according to claim 8 , wherein the second cutting portion extends along the second side of the device region.

10. 10. The method of claim 8, wherein the step of forming the functional device comprises the steps of: setting a plurality of the device regions on a surface of the crystal structure; and forming a plurality of the functional devices in the plurality of the device regions, respectively.

11. The crystal structure includes a layered structure including a crystal substrate and an epitaxial layer, the first intended cutting portion is formed in the epitaxial layer, 11. The method for manufacturing a semiconductor device according to claim 1, wherein the second cutting portion is formed in the epitaxial layer.

12. the crystal substrate has a first impurity concentration; The method for manufacturing a semiconductor device according to claim 11 , wherein the epitaxial layer has a second impurity concentration that is less than the first impurity concentration.

13. the first modified layer of the first portion to be cut has a portion located on the crystal substrate and a portion located on the epitaxial layer, 13 . The method for manufacturing a semiconductor device according to claim 11 , wherein the second modified layer in the second portion to be cut has a portion located in the crystal substrate and a portion located in the epitaxial layer.

14. The method for manufacturing a semiconductor device according to any one of claims 1 to 13, wherein the crystal structure includes a SiC single crystal.

15. a semiconductor layer having a first major surface on one side, a second major surface on the other side, a first side surface extending in a first direction, and a second side surface extending in a second direction intersecting the first direction; one or more inclined portions formed on either or both of a connection portion between the first main surface and the first side surface and a connection portion between the second main surface and the second side surface; one or more modified layers formed on either or both of the first side and the second side, an in-plane variation of the first side surface along the second direction is 20 μm or less; A semiconductor device, wherein an in-plane variation of the second side surface along the first direction is 20 μm or less.

16. The semiconductor layer is made of a hexagonal crystal, the first direction is the a-axis direction of the hexagonal crystal; The semiconductor device according to claim 15 , wherein the second direction is an m-axis direction of the hexagonal crystal.

17. the semiconductor layer has a layered structure including a crystal substrate and an epitaxial layer, the first main surface being on the epitaxial layer side, and the second main surface being on the crystal substrate side; The semiconductor device according to claim 15 or 16, wherein the one or more inclined portions are formed in the epitaxial layer.

18. The semiconductor device of claim 17 , wherein the one or more sloped portions have a portion located in the crystal substrate and a portion located in the epitaxial layer.

19. The semiconductor device according to claim 15, wherein one or more of the modified layers are exposed from either one or both of the first side surface and the second side surface.

20. The semiconductor device according to claim 15, wherein the one or more modified layers are formed along the one or more inclined portions.

21. 21. The semiconductor device according to claim 15, further comprising a functional device formed in the semiconductor layer.

22. The semiconductor device according to claim 21 , wherein the functional device includes an insulated gate transistor.

23. The semiconductor device according to claim 21 , wherein the functional device comprises a diode.

24. The semiconductor device according to any one of claims 15 to 23, wherein the semiconductor layer includes a SiC single crystal.

25. Providing a crystal structure; forming a first portion to be cut on a surface of the crystal structure, the first portion having a first depression extending in a thickness direction of the crystal structure and a first modified layer along a wall surface of the first depression; forming a second portion to be cut on a surface of the crystal structure, the second portion having a second recess extending in a thickness direction of the crystal structure and a second modified layer along a wall surface of the second recess and crossing the first portion to be cut; a cutting step of cleaving or cutting the crystal structure along the first portion to be cut and the second portion to be cut, a thickness of a portion of the first modified layer covering a bottom wall of the first recess is greater than a thickness of a portion of the first modified layer covering a side wall of the first recess; a thickness of a portion of the second modified layer covering a bottom wall of the second depression is greater than a thickness of a portion of the second modified layer covering a side wall of the second depression.

26. The crystal structure is a hexagonal crystal, The first intended cutting portion extends in an m-axis direction of the hexagonal crystal, The crystal cutting method according to claim 25 , wherein the second portion to be cut extends in an a-axis direction of the hexagonal crystal.

27. the step of forming the first portion to be cut includes a step of forming the first depression by heating the crystal structure, 27. The crystal cutting method according to claim 25, wherein the step of forming the second portion to be cut includes a step of forming the second recess by heating the crystal structure.

28. The step of forming the first recess also serves as a step of forming the first modified layer, 28. The crystal cutting method according to claim 27, wherein the step of forming the second recess also serves as a step of forming the second modified layer.

29. The first cut portion has the first recess having a tapered shape, The crystal cutting method according to any one of claims 25 to 28, wherein the second portion to be cut has the second depression having a tapered shape.

30. The crystal cutting method according to any one of claims 25 to 29, wherein the cutting step includes a step of cleaving the crystal structure starting from the first planned cutting portion, and a step of cleaving the crystal structure starting from the second planned cutting portion.

31. the cleaving step of the first portion to be cut includes a step of heating and cooling the first portion to be cut, The crystal cutting method according to any one of claims 25 to 30, wherein the step of cleaving the second portion to be cut includes a step of heating and cooling the second portion to be cut.

32. The crystal cutting method according to any one of claims 25 to 31, wherein the crystal structure includes a SiC single crystal.

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