Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device which has high surge current resistance while maintaining low Vf characteristics by forming an ohmic electrode of low resistance, and a method of manufacturing the silicon carbide semiconductor device.SOLUTION: A silicon carbide semiconductor device comprises an active region 10, a first-conductivity type region 12, and a termination region 20. The silicon carbide semiconductor device has a first second-conductivity type region 13, a silicide film 33, and a first electrode 14 in the active region 10, and a second second-conductivity type region 21 in the termination region 20. The active region 10 consists of an ohmic region 81 where the first electrode 14 is in contact with the silicide film 33, an ineffective region 80 where the first electrode 14 is in contact with the first second-conductivity type region 13, and a Schottky region 82 where the first electrode 14 is in contact with the first-conductivity type region 12. The ohmic region 81, ineffective region 80 and Schottky region 82 are provided in stripes. In the termination region 20, the second second-conductivity type region 21 connects with the ohmic region 81 and ineffective region 80.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device. [Background technology]

[0002] In recent years, silicon carbide (SiC) semiconductors have been attracting attention as a semiconductor material that can be used to fabricate (manufacture) semiconductor devices (hereinafter referred to as silicon carbide semiconductor devices) that exceed the limits of semiconductor devices using silicon (Si) semiconductors. In particular, silicon carbide semiconductors are expected to be applied to high-voltage (e.g., 1700 V or higher) semiconductor devices by taking advantage of their characteristics of higher dielectric breakdown field strength and higher thermal conductivity compared to silicon semiconductors.

[0003] When the silicon carbide semiconductor device is a diode (hereinafter referred to as a silicon carbide diode), n - n-type drift region - Since the design specifications of the type epitaxial layer can be set to a thin thickness and a high impurity concentration, silicon carbide diodes up to a breakdown voltage of about 3300V generally have a Schottky barrier diode (SBD) structure.

[0004] The structure of a conventional silicon carbide diode with an SBD structure will be described. Fig. 25 is a plan view showing a conventional silicon carbide semiconductor device as viewed from the front surface side of a semiconductor substrate. A conventional silicon carbide semiconductor device 140 shown in Fig. 25 is a vertical silicon carbide diode with an SBD structure in which a Schottky junction is formed along the entire front surface of a semiconductor substrate 130 made of silicon carbide in an active region 110.

[0005] The Schottky junction of the conventional silicon carbide semiconductor device 140 is an n-type junction exposed on the front surface of the semiconductor substrate 130. -The semiconductor substrate 130 is formed of a front surface electrode (not shown) made of a metal layer provided on the front surface of the semiconductor substrate 130. Reference numerals 120 and 121 denote an edge termination region and a field limiting ring (FLR), respectively.

[0006] Normally, in an SBD structure, there is a problem that the electric field strength at the junction surface between the semiconductor substrate 130 and the front electrode is high, and that this increases the reverse leakage current due to electrons tunneling through the Schottky barrier when a reverse voltage is applied, or that this increases the reverse leakage current due to surface defects inherent to silicon carbide. For this reason, a silicon carbide diode has been proposed that employs a Junction Barrier Schottky (JBS) structure in which a Schottky junction and a pn junction are mixed on the front side of the semiconductor substrate 130.

[0007] The structure of a conventional silicon carbide diode with a JBS structure will be described. Fig. 26 is a plan view showing another example of a conventional silicon carbide semiconductor device as viewed from the front surface side of a semiconductor substrate. Fig. 26 does not show the breakdown voltage structure of the edge termination region, and the front surface electrode 114 and field oxide film 115 arranged on the front surface of the semiconductor substrate 130. Fig. 27 is a cross-sectional view showing the cross-sectional structure taken along line AA-AA' in Fig. 26. Reference numeral 119 denotes a back surface electrode.

[0008] Conventional silicon carbide semiconductor device 140′ shown in FIGS. 26 and 27 differs from conventional silicon carbide semiconductor device 140 shown in FIG. 25 in that in active region 110, n - The SBD structure is formed by a Schottky junction between the p-type drift region 112 and the titanium film 131 that constitutes the front electrode 114, and the p-type region 113 and the n-type - The point is that a JBS structure formed by a pn junction with the type drift region 112 is mixed.

[0009] The p-type regions 113 are selectively provided in the surface region of the front surface of the semiconductor substrate 130 in the active region 110. - The p-type drift region 112 is exposed. - A pn junction is formed on the front surface of the semiconductor substrate 130 between the adjacent p-type drift regions 112. - The type drift region 112 forms a Schottky junction with a titanium film 131 that is the bottom layer of a front surface electrode 114 provided on the front surface of a semiconductor substrate 130 .

[0010] By adopting a JBS structure in which a Schottky junction and a pn junction are mixed at the junction surface between the semiconductor substrate 130 and the front surface electrode 114 in this manner, it is possible to reduce the electric field strength at the junction surface between the semiconductor substrate 130 and the front surface electrode 114, and therefore it is possible to suppress the reverse leakage current to the same level as an FWD (Free Wheeling Diode) using a silicon semiconductor. In Figure 26, the striped p-type regions 113 extending in a direction parallel to the front surface of the semiconductor substrate 130 are indicated by hatching.

[0011] 25, when a surge voltage is applied, the surge current that is generated in the semiconductor substrate 130 and flows in the forward direction is drawn only in a small amount (hereinafter, referred to as the drawn amount) from the semiconductor substrate 130 to the front surface electrode 114. This is because the SBD-structure diode is a unipolar device that does not use minority carriers for electrical conduction, and therefore in the high current region where a high forward current flows through the diode, the contact (electrical contact) between the semiconductor substrate 130 and the front surface electrode 114 has high resistance.

[0012] When the contact between the semiconductor substrate 130 and the front electrode 114 has high resistance, when a high surge current flows in the forward direction in the semiconductor substrate, the surge current is locally concentrated due to heat generation at the interface between the semiconductor substrate 130 and the front electrode 114. This surge current concentration causes the Schottky junction surface and the n-type junction immediately below the Schottky junction surface to be heated. -Type epitaxial layer (n - Since breakdown occurs in the type drift region 112, the amount of surge current drawn from within the semiconductor substrate 130 to the front electrode 114 is reduced.

[0013] It has been confirmed that the amount of surge current drawn is large in a diode with a JBS structure using a silicon semiconductor. For this reason, in the conventional silicon carbide semiconductor device 140′ shown in FIG. 26, similarly to a diode with a JBS structure using a silicon semiconductor, the p-type region 113 and the n-type region 114 are separated. - It was assumed that the amount of surge current drawn would increase due to the rise in surge current caused by the bipolar action of the pn junction formed on the front surface of semiconductor substrate 130 between type drift region 112 and semiconductor substrate 130, but this effect was not noticeable.

[0014] 26 has a small surge current draw amount, because a sufficiently low-resistance ohmic contact cannot be obtained between p-type region 113 constituting the p-n junction of the JBS structure and front surface electrode 114. Therefore, it is considered that a metal electrode (hereinafter referred to as ohmic electrode) that makes an ohmic junction with p-type region 113 is formed between p-type region 113 and front surface electrode 114, and a surge current is caused to flow locally to the p-n junction of the JBS structure, thereby improving the surge current withstand capability.

[0015] Figure 28 is a cross-sectional view showing another example of a conventional silicon carbide semiconductor device. Figure 28 is Figure 3 of Patent Document 2 listed below. Conventional silicon carbide semiconductor device 150 shown in Figure 28 differs from conventional silicon carbide semiconductor device 140' shown in Figures 26 and 27 in that an ohmic electrode 133' is provided on p-type region 113 as the bottom layer of front surface electrode 114, and an n-type - 1. The point is that a Schottky junction between the p-type drift region 112 and the Schottky electrode 131' and an ohmic junction between the p-type region 113 and the ohmic electrode 133' are mixed together.

[0016] Conventional methods for manufacturing silicon carbide diodes with JBS structure include- Only on the portion of the n-type drift region exposed on the front surface of the semiconductor substrate, - A method has been proposed in which a metal electrode (hereinafter referred to as Schottky electrode) that forms a Schottky junction with the type drift region is formed, and then an ohmic electrode that forms an ohmic junction with the p-type region that constitutes the pn junction of the JBS structure is formed on the front surface of the semiconductor substrate so as to cover the Schottky electrode (see, for example, Patent Document 1 below).

[0017] The following Patent Document 1 discloses that aluminum (Al) or nickel (Ni) is used as the material for the ohmic electrode, and molybdenum (Mo) is used as the material for the Schottky electrode. The following Patent Document 1 also discloses that a p-type region constituting the pn junction of the JBS structure is provided with a p-type region having a higher impurity concentration than the p-type region. + This document discloses a silicon carbide diode in which a p-type contact region is selectively formed to improve the ohmic properties between the p-type region and an ohmic electrode.

[0018] Another method for manufacturing a silicon carbide diode having a conventional JBS structure is to form an ohmic electrode only on the p-type region constituting the pn junction of the JBS structure, and then form an n-type ohmic electrode on the front surface of the semiconductor substrate so as to cover the ohmic electrode. - A method for forming a Schottky electrode that forms a Schottky junction with a type drift region has been proposed (see, for example, Patent Document 2 below). Patent Document 2 below discloses that aluminum is used as the material for the ohmic electrode and molybdenum (Mo) is used as the material for the Schottky electrode.

[0019] In addition, as another method for manufacturing a silicon carbide diode with a conventional JBS structure, a method for producing n-type ... - A method for forming a silicide (NiSi2) film that serves as an anode electrode that forms a Schottky junction with a p-type drift region and an ohmic junction with a p-type region that constitutes a pn junction of a JBS structure has been disclosed (for example, see Patent Document 3 below).

[0020] As a method for forming an ohmic electrode on a p-type region, a method has been proposed in which an aluminum film and a nickel film are sequentially stacked on a semiconductor substrate made of silicon carbide so as to cover the p-type region, and then annealed (heat treated) at 1000°C to cause a silicide reaction between silicon atoms in the semiconductor substrate and nickel atoms in the nickel film, thereby forming a nickel silicide (NiSi) film that serves as an ohmic electrode that makes an ohmic contact with the p-type region (for example, see Non-Patent Document 1 below).

[0021] As another method for forming an ohmic electrode on a p-type region, a method has been proposed in which a nickel film and an aluminum film are sequentially laminated on a semiconductor substrate made of silicon carbide so as to cover the p-type region, and then these metal films and the semiconductor substrate are reacted by heat treatment at a temperature of 850°C to 1050°C to form a p-type ohmic electrode made of an alloy of nickel, aluminum, silicon and carbon (C) (see, for example, Patent Document 4 below).

[0022] As another method for forming an ohmic electrode on a p-type region, a method has been proposed in which an aluminum film and a silicon film having an elemental composition ratio of 89:11 (=Al:Si) are sequentially stacked on a semiconductor substrate made of silicon carbide so as to cover the p-type region, and then a heat treatment is performed at a temperature of 400°C to 500°C to form an alloy film of the aluminum film and the silicon film and form an ohmic junction between the alloy film and the p-type region (see, for example, Patent Document 5 below).

[0023] As another method for forming an ohmic electrode, it has been proposed to form a nickel film on a high-concentration impurity region formed by ion-implanting silicon atoms into a semiconductor substrate made of silicon carbide, form a thermal reaction layer precursor layer only at the interface between the high-concentration impurity region and the nickel film by heat treatment at a temperature of 400°C to 600°C, and then convert the thermal reaction layer precursor layer into a low-resistance thermal reaction layer by heat treatment at 950°C (see, for example, Patent Document 6 below).

[0024] As another method for forming an ohmic electrode, it has been proposed to form a thermal reaction layer precursor layer by heat treatment between a semiconductor substrate made of silicon carbide and a metal material film in a contact hole of an interlayer insulating film, and to convert the thermal reaction layer precursor layer into a thermal reaction layer by a heat treatment at a higher temperature than the first heat treatment (see, for example, Patent Document 7 below). Patent Document 7 below discloses that the material of the metal material film is titanium aluminum or nickel, and that the first heat treatment is performed at a low temperature that does not cause harmful solid-phase reactions between the metal material film and the interlayer insulating film.

[0025] Furthermore, Patent Document 7 listed below discloses a method for a salicide process in which a metal material film is formed so as to be in contact with the entire surface of a semiconductor substrate within a contact hole in an interlayer insulating film, the contact points between the metal material film and the semiconductor substrate are silicided by heat treatment, and a thermal reaction layer is formed in a self-aligned manner over the entire surface of the contact points, by removing the non-silicided parts of the metal material film (parts excluding the thermal reaction layer) by etching, thereby leaving only the parts of the metal material film that have become the thermal reaction layer.

[0026] Fig. 29 is a cross-sectional view showing an example of an ohmic electrode formed in a self-aligned manner by a conventional method for manufacturing a silicon carbide semiconductor device. Fig. 29 is Fig. 1 of Patent Document 7 below. A conventional silicon carbide semiconductor device 160 shown in Fig. 29 includes, in a contact hole 163a of an interlayer insulating film 163, a thermal reaction layer serving as an ohmic electrode 164 that contacts and electrically connects a high concentration impurity region 162 in a surface region of a semiconductor substrate 161 made of silicon carbide and a wiring layer 165 embedded in the contact hole 163a of the interlayer insulating film 163.

[0027] The ohmic electrode 164 is formed in a self-aligned manner on the entire surface of the semiconductor substrate 161 within the contact hole 163a of the interlayer insulating film 163, using the interlayer insulating film 163 as a mask, by the salicide process described in Patent Document 7 below. The ohmic electrode 164 is provided in a surface region of the high-concentration impurity region 162 exposed on the surface of the semiconductor substrate 161 within the contact hole 163a of the interlayer insulating film 163, and protrudes from the front surface of the semiconductor substrate 161 in a direction away from the front surface of the semiconductor substrate 161.

[0028] As another method for forming an ohmic electrode, it has been proposed to form an electrode film that covers the surface on which a resist pattern is formed, and then lift off the resist pattern to form a p-type ohmic electrode having a gap between the electrode film formed inside the hole and the oxide film (see, for example, Patent Document 8 below). [Prior art documents] [Patent documents]

[0029] [Patent Document 1] Patent No. 5546759 [Patent Document 2] JP 2008-282972 A [Patent Document 3] JP 2003-158259 A [Patent Document 4] Patent No. 4291875 [Patent Document 5] Japanese Patent Application Publication No. 1999-020616 [Patent Document 6] JP 2017-175115 A [Patent Document 7] JP 2005-276978 A [Patent Document 8] JP 2013-120776 A [Non-patent literature]

[0030] [Non-Patent Document 1] N. Kiritani and 7 others, Single Material Ohmic Contacts Simultaneously Formed on the Source / P-well / Gate of 4H-SiC Vertical MOSFETs, Materials Science Forum, Switzerland, Trans Tech Publications, 2003, Vol. 433-436, pp. 669-672 Summary of the Invention [Problem to be solved by the invention]

[0031] However, even if an ohmic electrode that contacts only p-type region 113 is provided between semiconductor substrate 130 and Schottky electrode (titanium film 131) in order to improve the surge current withstand capability of conventional silicon carbide semiconductor device 140' (silicon carbide diode with JBS structure: see Figures 26 and 27) described above, if the ohmic electrode is a nickel silicide film, the contact resistance between p-type region 113 and the ohmic electrode cannot be sufficiently reduced, and therefore the specified designed value of the surge current withstand capability (IFSM) cannot be obtained.

[0032] In order to increase the contact resistance between the p-type region 113 and the ohmic electrode, if the contact area between the p-type region 113 and the ohmic electrode is increased, while maintaining the active region 110 at the same surface area, the n - The junction area between the n-type drift region 112 and the Schottky electrode is reduced. -The amount of electron current flowing from the type drift region 112 to the Schottky electrode is reduced, making it difficult to achieve a low forward voltage (Vf). Thus, when an ohmic electrode is formed at the expense of the Schottky electrode area, the IFSM characteristics improve but the Vf characteristics deteriorate, and there is a trade-off between the Vf characteristics and the IFSM characteristics.

[0033] For example, there is an example in which an ohmic electrode having a larger area than a Schottky electrode is formed on p-type region 113, thereby improving the IFSM characteristics at the expense of lowering the Vf characteristics. Fig. 30 is a plan view showing a conventional silicon carbide semiconductor device in which the area of ​​the ohmic electrode is increased, as viewed from the front surface side of the semiconductor substrate. In Fig. 30, in addition to forming an ohmic electrode on stripe-shaped p-type region 113, an ohmic electrode is also formed on dot-shaped (rectangular) p-type region 113' connecting p-type region 113. This forms an ohmic electrode having a larger area than a Schottky electrode.

[0034] In order to solve the above-mentioned problems associated with the conventional techniques, an object of the present invention is to provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device that have high surge current resistance while maintaining low Vf characteristics by forming a low resistance ohmic electrode. [Means for solving the problem]

[0035] In order to solve the above-mentioned problems and achieve the object of the present invention, a silicon carbide semiconductor device according to the present invention has the following features. An active region is provided in a semiconductor substrate made of silicon carbide. A termination region is provided in the semiconductor substrate, surrounding the periphery of the active region. A first conductivity type region exposed to a first main surface of the semiconductor substrate is provided within the semiconductor substrate. A first second conductivity type region is selectively provided in the active region between the first main surface of the semiconductor substrate and the first conductivity type region, in contact with the first conductivity type region. A silicide film is provided in ohmic junction with the first second conductivity type region. A first electrode is provided in contact with the silicide film, the first second conductivity type region, and the first conductivity type region. A second electrode is provided on a second main surface of the semiconductor substrate. A second second conductivity type region is provided in the termination region, surrounding the active region. The active region is composed of an ohmic region where the first electrode is in contact with the silicide film, an ineffective region where the first electrode is in contact with the first second conductivity type region, and a Schottky region where the first electrode is in contact with the first conductivity type region. The ohmic region, the ineffective region, and the Schottky region are provided in a stripe shape. In the termination region, the silicide film also makes an ohmic junction with the second second conductivity type region, and the second second conductivity type region is connected to the ohmic region and the ineffective region. In order to solve the above-mentioned problems and achieve the object of the present invention, the silicon carbide semiconductor device according to the present invention has the following features. An active region is provided in a semiconductor substrate made of silicon carbide. A termination region is provided in the semiconductor substrate to surround the periphery of the active region. A first conductivity type region exposed to a first main surface of the semiconductor substrate is provided inside the semiconductor substrate. A first second conductivity type region is selectively provided in the active region between a first main surface of the semiconductor substrate and the first conductivity type region and in contact with the first conductivity type region. A silicide film is provided to form an ohmic junction with the first second conductivity type region. A first electrode is provided to contact the silicide film, the first second conductivity type region, and the first conductivity type region. A second electrode is provided on a second main surface of the semiconductor substrate. A second second conductivity type region is provided in the termination region surrounding the active region.The active region is composed of an ohmic region where the first electrode contacts the silicide film, an ineffective region where the first electrode contacts the first second conductivity type region, and a Schottky region where the first electrode contacts the first conductivity type region. The ohmic region, the ineffective region, and the Schottky region are arranged in a stripe shape. In the termination region, the second second conductivity type region connects to the ohmic region and the ineffective region. The contact resistance between the silicide film and the first electrode in the ohmic region is 5.0×10. -3 Ωcm 2 Below The second second conductive type region is provided in two layers. In order to solve the above-mentioned problems and achieve the object of the present invention, a silicon carbide semiconductor device according to the present invention has the following features. An active region is provided in a semiconductor substrate made of silicon carbide. A termination region is provided in the semiconductor substrate, surrounding the periphery of the active region. A first conductivity type region exposed to a first main surface of the semiconductor substrate is provided inside the semiconductor substrate. A first second conductivity type region is selectively provided in the active region between the first main surface of the semiconductor substrate and the first conductivity type region, in contact with the first conductivity type region. A silicide film is provided in ohmic junction with the first second conductivity type region. A first electrode is provided in contact with the silicide film, the first second conductivity type region, and the first conductivity type region. A second electrode is provided on a second main surface of the semiconductor substrate. A second second conductivity type region is provided in the termination region, surrounding the active region. The active region is composed of an ohmic region where the first electrode contacts the silicide film, an ineffective region where the first electrode contacts the first second conductivity type region, and a Schottky region where the first electrode contacts the first conductivity type region. The ohmic region, the ineffective region, and the Schottky region are arranged in a stripe shape. In the termination region, the second second conductivity type region connects with the ohmic region and the ineffective region. The silicide film contains nickel, silicon, and aluminum.

[0036] In addition, the present invention provides a silicon carbide semiconductor device, comprising: The silicon carbide semiconductor device according to the present invention further comprises a field oxide film, and the silicide film in the termination region is in contact with the field oxide film on a sidewall of the field oxide film. The silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, is characterized in that the first electrode is provided so as to extend over the field oxide film towards the chip end side. The silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, is characterized in that the first electrode is a laminated film of an aluminum alloy film and a titanium film, and the titanium film terminates at a position facing the second second conductivity type region in the depth direction. The silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, is characterized in that the second second conductivity type region is provided in duplicate. The silicon carbide semiconductor device according to the present invention, in the above-mentioned invention,The ohmic regions are provided in a plurality of stripes, and the ohmic regions are not connected to each other in the active region.

[0038] In the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, a contact resistance between the silicide film and the first electrode in the ohmic region is 5.0×10 -4 Ωcm 2 The present invention is characterized in that:

[0040] In the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the ohmic region and the Schottky region are in contact with the ineffective region.

[0041] In addition, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the ohmic region has a width of 2 μm or less.

[0042] In order to solve the above-mentioned problems and achieve the object of the present invention, the method for manufacturing a silicon carbide semiconductor device according to the present invention has the following features. The method for manufacturing a silicon carbide semiconductor device includes a semiconductor substrate made of silicon carbide, an active region, and a termination region surrounding the periphery of the active region. First, a first step of forming a first conductivity type region forming a first main surface of the semiconductor substrate is performed inside the semiconductor substrate. Next, a second step of selectively forming a first second conductivity type region in contact with the first conductivity type region between the first main surface of the semiconductor substrate and the first conductivity type region in the active region is performed. Next, a third step of forming a second second conductivity type region surrounding the active region is performed in the termination region. Next, a fourth step of forming an oxide film covering the first conductivity type region and the first second conductivity type region is performed on the first main surface of the semiconductor substrate. Next, a fifth step of selectively removing the oxide film to form a first opening in the oxide film exposing the first second conductivity type region is performed. Next, a sixth step is performed in which a first nickel film, an aluminum film, and a metal film having a melting point higher than aluminum are sequentially stacked in contact with the first main surface of the semiconductor substrate in the first opening of the oxide film to form a metal material film. Next, a seventh step is performed in which the metal material film is reacted with the semiconductor substrate by a first heat treatment to form a compound layer in a self-aligned manner on the first main surface of the semiconductor substrate in the first opening of the oxide film using the oxide film as a mask. Next, after the seventh step, an eighth step is performed in which an excess portion of the metal material film excluding the compound layer is removed. Next, after the eighth step, a ninth step is performed in which nickel silicide is formed inside the compound layer by a second heat treatment at a temperature higher than that of the first heat treatment to form a silicide film that forms an ohmic junction with the semiconductor substrate. Next, after the ninth step, a tenth step is performed in which the oxide film sandwiched between the silicide films is removed to form a contact hole that connects all of the first openings. Next, an eleventh step is performed in which a first electrode is formed on the first main surface of the semiconductor substrate inside the contact hole by sequentially stacking a titanium film that is in contact with the first conductivity type region and forms a Schottky junction with the first conductivity type region and a metal electrode film that contains aluminum. Next, a twelfth step is performed in which a second electrode is formed on the second main surface of the semiconductor substrate.

[0043] In the fifth step, the width of the first opening is formed narrower than the width of the first second-conductivity type region, so that the active region is formed to include an ohmic region where the first electrode contacts the silicide film, an ineffective region where the first electrode contacts the first second-conductivity type region, and a Schottky region where the first electrode contacts the first conductivity type region. Furthermore, in the fifth step, the ohmic region, the ineffective region, and the Schottky region are formed in a stripe shape, and the second second-conductivity type region is connected to the ohmic region and the ineffective region in the termination region.

[0044] According to the above-mentioned invention, the stripe-shaped Schottky regions and the stripe-shaped low-resistance ohmic regions are alternately provided, and the high-resistance ineffective regions are provided between them. This allows the low-resistance ohmic regions to be formed without narrowing the area of ​​the Schottky regions, thereby improving the IFSM characteristics while maintaining the Vf characteristics. Effect of the Invention

[0045] ADVANTAGEOUS EFFECTS OF THE PRESENT DISCLOSURE According to the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device of the present invention, by forming a low resistance ohmic electrode, it is possible to achieve an effect of increasing the surge current withstand capability while maintaining low Vf characteristics. [Brief description of the drawings]

[0046] [Figure 1] 1 is a plan view showing a layout of a silicon carbide semiconductor device according to an embodiment as viewed from the front surface side of a semiconductor substrate. [Diagram 2] 1 is a plan view showing a layout of a silicon carbide semiconductor device according to an embodiment as viewed from the front surface side of a semiconductor substrate. [Diagram 3] 3 is a cross-sectional view showing a cross-sectional structure taken along line AA' in FIG. 2. [Figure 4] FIG. 4 is a cross-sectional view showing a detailed structure of a region surrounded by a dashed line in FIGS. 1 to 3. [Diagram 5]1 is a graph showing IFSM versus contact resistance. [Figure 6] 1 is a graph showing IFSM characteristics and Vf characteristics versus Schottky electrode area ratio. [Figure 7] 1 is a flowchart outlining a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 8] 1A to 1C are cross-sectional views showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment. [Figure 9] 1A to 1C are cross-sectional views showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment. [Figure 10] 1A to 1C are cross-sectional views showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment. [Figure 11] 1A to 1C are cross-sectional views showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment. [Figure 12] 1A to 1C are cross-sectional views showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment. [Figure 13] 1A to 1C are cross-sectional views showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment. [Figure 14] 1A to 1C are cross-sectional views showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment. [Figure 15] 1A to 1C are cross-sectional views showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment. [Figure 16] 1A to 1C are cross-sectional views showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment. [Figure 17] 1A to 1C are cross-sectional views showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment. [Figure 18] 1A to 1C are cross-sectional views showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment. [Figure 19] 4 is a cross-sectional view showing details of an opening formed in an oxide film of the silicon carbide semiconductor device according to the embodiment; FIG. [Figure 20] 5A to 5C are cross-sectional views each showing a schematic state during the manufacture of a front surface electrode of the silicon carbide semiconductor device according to the embodiment. [Figure 21] 5A to 5C are cross-sectional views each showing a schematic state during the manufacture of a front surface electrode of the silicon carbide semiconductor device according to the embodiment. [Figure 22] 5A to 5C are cross-sectional views each showing a schematic state during the manufacture of a front surface electrode of the silicon carbide semiconductor device according to the embodiment. [Diagram 23] 1 is another plan view showing a layout of the silicon carbide semiconductor device according to the embodiment as viewed from the front surface side of the semiconductor substrate. FIG. [Figure 24] 1 is another plan view showing a layout of the silicon carbide semiconductor device according to the embodiment as viewed from the front surface side of the semiconductor substrate. FIG. [Diagram 25] 1 is a plan view showing a conventional silicon carbide semiconductor device as viewed from the front surface side of a semiconductor substrate. [Figure 26] FIG. 11 is a plan view showing another example of a conventional silicon carbide semiconductor device as viewed from the front surface side of a semiconductor substrate. [Figure 27] 27 is a cross-sectional view showing a cross-sectional structure taken along line AA-AA' in FIG. 26. [Figure 28] FIG. 11 is a cross-sectional view showing another example of a conventional silicon carbide semiconductor device. [Figure 29] 1 is a cross-sectional view showing an example of an ohmic electrode formed in a self-aligned manner by a conventional method for manufacturing a silicon carbide semiconductor device. [Diagram 30] 1 is a plan view showing a conventional silicon carbide semiconductor device in which the area of ​​an ohmic electrode is increased, as viewed from the front surface side of a semiconductor substrate. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0047] Preferred embodiments of the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, in a layer or region prefixed with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - attached to n or p respectively mean that the impurity concentration is higher and lower than that of a layer or region not prefixed with n or p. Note that in the following description of the embodiments and the accompanying drawings, the same reference numerals are attached to similar configurations, and duplicated explanations are omitted. Note that in the notation of Miller indices, "-" means a bar attached to the index immediately following it, and adding "-" before an index represents a negative index.

[0048] (Embodiment) The structure of a silicon carbide semiconductor device according to an embodiment will be described. Figures 1 and 2 are plan views showing a layout of a silicon carbide semiconductor device according to an embodiment as viewed from the front surface side of a semiconductor substrate. Figure 1 shows an example of a layout of a p-type region (first second conductivity type region) 13 constituting a JBS structure. Figure 2 illustrates an example of a layout of bonding pads 41 among the various parts on the front surface of a semiconductor substrate (semiconductor chip) 30 made of silicon carbide (SiC).

[0049] Silicon carbide semiconductor device 40 according to the embodiment shown in FIGS. 1 and 2 includes a front electrode (first electrode) 14 (see FIG. 3) and an n-type semiconductor substrate 30 on the front surface side of active region 10. - The SBD structure is formed by a Schottky junction with a p-type drift region (first conductivity type region) 12, and a p-type region 13 and an n - The present invention is a silicon carbide diode having a mixed structure, in which a JBS structure is formed by a pn junction with a type drift region 12 and a silicon carbide diode having a mixed structure.

[0050] n - The n-type drift regions 12 and the p-type regions 13 are arranged approximately evenly in a substantially uniform pattern within the surface of the active region 10. -The n-type drift regions 12 and the p-type regions 13 are arranged, for example, in stripes extending in the same direction parallel to the front surface of the semiconductor substrate 30, and are arranged alternately and repeatedly in contact with each other in the short direction perpendicular to the long direction of the stripes. - The p-type drift regions 12 are exposed on the front surface of the semiconductor substrate 30 between adjacent p-type regions 13.

[0051] The active region 10 is a region through which current flows when the silicon carbide diode is in an on-state. The active region 10 has, for example, a substantially rectangular planar shape and is disposed substantially in the center of the semiconductor substrate 30. The edge termination region 20 is a region between the active region 10 and the edge of the semiconductor substrate 30, and surrounds the periphery of the active region 10. The edge termination region 20 is an n - This region maintains a breakdown voltage by relaxing the electric field on the front surface side of the semiconductor substrate 30 in the type drift region 12. The breakdown voltage is the limit voltage at which the element does not malfunction or break down.

[0052] A breakdown voltage structure such as a junction termination extension (JTE) structure is disposed in edge termination region 20 (see FIG. 3). The JTE structure is a breakdown voltage structure having a substantially rectangular planar shape that surrounds active region 10 and has multiple p-type regions (reference numerals 22 and 23 in FIG. 3) with different impurity concentrations, such that p-type regions with lower impurity concentrations are disposed from the inside (the center side of semiconductor substrate 30) to the outside (the edge side of semiconductor substrate 30).

[0053] A field limiting ring (FLR: Field Limiting Ring (second second conductivity type region)) 21 is disposed in a connection region 20a (see FIG. 3) of the edge termination region 20. The FLR 21 is a p + The edge termination region 20 is a mold region that extends outward from the connection region 20a of the edge termination region 20 and is a p - The FLRs 21 are in contact with the p-type regions 13 (see FIG. 3). The FLRs 21 may be in contact with the p-type regions 13 in the longitudinal direction in which the p-type regions 13 extend in a stripe shape.

[0054] The connecting region 20a of the edge termination region 20 is a region between the active region 10 and a field oxide film 15 described below, surrounds the periphery of the active region 10, and connects the active region 10 to a breakdown voltage structure portion of the edge termination region 20. The breakdown voltage structure portion of the edge termination region 20 is a portion of the edge termination region 20 from the inner edge of the field oxide film 15 described below to the edge of the semiconductor substrate (chip edge), and is used in the JTE structure or n + A predetermined breakdown voltage structure such as a mold channel stopper region 24 (see FIG. 3) is disposed.

[0055] The front surface electrode 14 (see FIG. 3) is provided on the front surface of the semiconductor substrate 30 in the active region 10. The front surface electrode 14 has an n - In contact with the n-type drift region 12 and the p-type region 13, - The semiconductor substrate 30 is electrically connected to the p-type drift region 12 and the p-type region 13. A passivation film 18 (see FIG. 3) is provided on the front surface of the semiconductor substrate 30. The passivation film 18 functions as a protective film that protects the element structure and front surface electrode 14 on the front surface side of the semiconductor substrate 30.

[0056] The passivation film 18 has an opening 18a that exposes a part of the front surface electrode 14. The part of the front surface electrode 14 exposed in the opening 18a of the passivation film 18 functions as a bonding pad 41. The bonding pad 41 is disposed, for example, in the center of the semiconductor substrate 30. An aluminum (Al) wire (not shown), which is the most common wiring connection when supplying current to the bonding pad 41, is bonded (joined) to the bonding pad 41.

[0057] 2 shows a junction 42 between bonding pad 41 and an aluminum wire (not shown) in a circular planar shape. For example, when an aluminum wire with a diameter of 500 μm is bonded to bonding pad 41, junction 42 between bonding pad 41 and the aluminum wire needs to assume a surface area of ​​about 1 mm square. The reason for this is that the way in which a surge current flows in the forward direction within the surface of semiconductor substrate 30 when a surge voltage is applied differs depending on the withstand voltage class of the silicon carbide diode.

[0058] The bonding pad 41 is preferably disposed in the center of the semiconductor substrate 30, but as described above, - Since the p-type drift region 12 and the p-type region 13 are arranged approximately evenly in a substantially uniform pattern within the surface of the active region 10, the electrical characteristics are not adversely affected even if the bonding pad 41 is not arranged in the center of the semiconductor substrate 30. This allows for a high degree of freedom in wire bonding.

[0059] Next, a cross-sectional structure of silicon carbide semiconductor device 40 according to an embodiment will be described. Fig. 3 is a cross-sectional view showing the cross-sectional structure along line A-A' in Fig. 2. As described above, silicon carbide semiconductor device 40 according to the embodiment has an SBD structure and a JBS structure of a silicon carbide diode in active region 10 of semiconductor substrate 30 made of silicon carbide, and a JTE structure as a breakdown voltage structure in edge termination region 20.

[0060] The semiconductor substrate 30 is made of silicon carbide. + On the front surface of the starting mold substrate 11, - n-type drift region 12 - It is an epitaxial substrate in which a type epitaxial layer is stacked. + The starting substrate 11 is n + The semiconductor substrate 30 is an n-type cathode region. - The main surface (n - n-type drift region 12 - The surface of the n-type epitaxial layer) is the front surface, + The main surface (n +The back surface of the mold starting substrate 11 is referred to as the back surface.

[0061] In the active region 10, one or more p-type regions 13 constituting a JBS structure are selectively provided in the surface region on the front surface side of the semiconductor substrate 30. The p-type regions 13 are connected to the front surface of the semiconductor substrate 30 and - The p-type region 13 is exposed on the front surface of the semiconductor substrate 30 and is disposed between the n-type drift region 12 and the p-type region 13. - It contacts the mold drift region 12 .

[0062] In edge termination region 20, the surface region on the front surface side of semiconductor substrate 30 includes FLR 21, one or more p-type regions (here, two: p - Type 22 and p -- Type region 23) and n + The FLR 21 is provided in the entire area of ​​the connecting region 20a of the edge termination region 20 and extends outward from the connecting region 20a to form a p - It contacts the mold region 22. The active region 10 is located inside the FLR 21.

[0063] p - The mold region 22 is provided outside the FLR 21, away from the transition region 20a of the edge termination region 20, and adjacent to the FLR 21. -- The type region 23 is p - Provided outside the mold region 22, p - adjacent to the mold region 22. + The type channel stopper region 24 is p -- Outside the mold region 23, p -- It is provided away from the mold area 23. + The mold channel stopper region 24 is exposed at the edge (chip edge) of the semiconductor substrate 30.

[0064] FLR21, p - type region 22, p -- Type regions 23 and n + The n-type channel stopper region 24 is disposed on the front surface of the semiconductor substrate 30. -The FLR21, p - type region 22, p -- Type regions 23 and n + The n-type channel stopper region 24 is exposed on the front surface of the semiconductor substrate 30 and has an n-type - The FLR21, p - type region 22, p -- Type regions 23 and n + The depth of the n-type channel stopper region 24 may be the same as the depth of the p-type region 13, for example.

[0065] The front surface of the semiconductor substrate 30 is covered with a field oxide film 15. The field oxide film 15 may be a laminated film in which, for example, a thermal oxide film 16 and a deposited oxide film 17 are laminated in this order. The thermal oxide film 16 can improve the adhesion between the semiconductor substrate 30 and the field oxide film 15. When the field oxide film 15 includes the deposited oxide film 17, the field oxide film 15 can be formed in a shorter time than when the entire field oxide film 15 is made of the thermal oxide film 16.

[0066] The field oxide film 15 has a contact hole 15a that exposes almost the entire front surface of the semiconductor substrate 30 in the active region 10. The sidewall of the contact hole 15a in the field oxide film 15 (the inner side surface of the field oxide film 15) is, for example, approximately perpendicular to the front surface of the semiconductor substrate 30. The contact hole 15a in the field oxide film 15 is provided in the entire area from the active region 10 to the connecting region 20a of the edge termination region 20.

[0067] The contact hole 15a of the field oxide film 15 is provided with n - In this embodiment, p-type drift region 12 and p-type region 13, as well as an inner portion of FLR 21 in edge termination region 20, are exposed. Inside contact hole 15a of field oxide film 15, on the front surface of semiconductor substrate 30, front surface electrode 14 functioning as an anode electrode is provided along the front surface of semiconductor substrate 30.

[0068] The front electrode 14 has a layered structure in which a titanium film 31 and an aluminum alloy film (metal electrode film containing aluminum) 32 are layered in this order. In addition, the front electrode 14 has a lowermost nickel silicide (NiSi) film 33 (33a, 33b) selectively provided between the front surface of the semiconductor substrate 30 and the titanium film 31. The nickel silicide film 33 contains aluminum. The nickel silicide film 33 may contain carbon (C). The front electrode 14 may extend outward on the field oxide film 15.

[0069] The titanium film 31 is provided on the entire front surface of the semiconductor substrate 30 inside the contact hole 15a. - The n-type drift region 12 is in contact with the titanium film 31. - The junction with the n-type drift region 12 is - This is a Schottky electrode that forms a Schottky junction with the type drift region 12. The titanium film 31 extends outward on the field oxide film 15 and may be terminated, for example, at a position facing the FLR 21 in the depth direction.

[0070] The aluminum alloy film 32 covers the entire surface of the titanium film 31, is electrically connected to the titanium film 31, and is electrically connected to the nickel silicide film 33 via the titanium film 31. The aluminum alloy film 32 extends on the field oxide film 15 to the outside of the titanium film 31, and has a p - It may terminate at a position facing the mold region 22. The aluminum alloy film 32 is, for example, an aluminum silicon (AlSi) film. Instead of the aluminum alloy film 32, an aluminum film may be provided.

[0071] The nickel silicide film 33 has a first nickel silicide film 33a provided between the p-type region 13 and the titanium film 31, and a second nickel silicide film 33b provided between the FLR 21 and the titanium film 31. The first nickel silicide film 33a is an ohmic electrode that forms an ohmic junction with the p-type region 13. The first nickel silicide film 33a has a function of increasing the amount of current (pulling amount) that is drawn from within the semiconductor substrate 30 to the front surface electrode 14 when a surge voltage is applied, which is a surge current that occurs within the semiconductor substrate 30 and flows in the forward direction, thereby improving the surge current withstand capability.

[0072] As described later, the first nickel silicide film 33a is formed by reacting the surface region of the semiconductor substrate 30 with the metal material film 52 (see FIG. 20) by heat treatment at a contact point between the p-type region 13 and the metal material film 52 deposited on the front surface of the semiconductor substrate 30. Therefore, the first nickel silicide film 33a is provided in the surface region of the front surface of the semiconductor substrate 30, contacts the p-type region 13 in the depth direction, and protrudes from the front surface of the semiconductor substrate 30 in a direction away from the front surface of the semiconductor substrate 30.

[0073] Fig. 4 is a cross-sectional view showing a detailed structure of a region S surrounded by a dashed line in Figs. 1 to 3. As shown in Fig. 4, a width w2a of the first nickel silicide film 33a is narrower than a width w1 of the p-type region 13. By making the width w2a of the first nickel silicide film 33a narrower than the width w1 of the p-type region 13, the p-type region 13 is exposed on the front surface of the semiconductor substrate 30. As a result, a high-resistance Schottky junction is formed between the p-type region 13 and the titanium film 31.

[0074] The active region 10 includes a stripe-shaped ineffective region 80 where the titanium film 31 is in contact with the p-type region 13 constituting the JBS structure, a stripe-shaped ohmic region 81 where the titanium film 31 is in contact with the first nickel silicide film 33a, and a stripe-shaped ineffective region 82 where the titanium film 31 is in contact with the n-type region 13. -The active region 10 is composed of an ohmic region 81, two ineffective regions 80 surrounding the ohmic region 81, and a stripe-shaped Schottky region 82 in contact with the type drift region 12. Thus, one period consisting of four regions, namely, an ohmic region 81, two ineffective regions 80 surrounding the ohmic region 81, and a Schottky region 82, is repeated. The stripe shape is a long and narrow rectangle whose horizontal direction is shorter than its vertical direction, as shown in Figures 1 and 2.

[0075] Such a periodic structure allows the ohmic regions 81 to be uniformly and densely arranged throughout the active region 10. Therefore, when a high surge current flows in the forward direction within the semiconductor substrate, the surge current can be dispersed, improving the IFSM characteristics.

[0076] 5 is a graph showing the IFSM characteristics versus contact resistance. In FIG. 5, the horizontal axis shows the contact resistance, with the unit being Ωcm. 2 The vertical axis represents the IFSM characteristics. As shown in FIG. 5, when the contact resistance is 5.0×10 -3 cm 2 When the IFSM characteristic is less than 5.0×10 -4 cm 2 It can be seen that the IFSM characteristics are further improved when the contact resistance is less than 100%, which is believed to be because the lower the contact resistance is, the less heat is generated due to the resistance, and the more the IFSM characteristics are improved.

[0077] In order to improve the IFSM characteristics, the ohmic region 81 is a low resistance region, and the contact resistance is 5.0×10 -3 cm 2 Less than or equal to 5.0×10 -4 cm 2 On the other hand, the ineffective region 80 is a high resistance region, and the contact resistance is preferably 1.0×10 -3 cm 2 It is preferable that the width w4 of the ineffective region 80 is, for example, not less than 0.1 μm and not more than 2 μm. The IFSM can be increased by making the ohmic region 81 have such a low resistance.

[0078] 1 and 2, p-type region 13 is connected to a guard ring (FLR 21 in FIGS. 1 and 2) provided in edge termination region 20. That is, in edge termination region 20, ohmic region 81 and invalid region 80 are connected to edge termination region 20. Furthermore, if second nickel silicide film 33b is also provided in the guard ring, first nickel silicide film 33a of ohmic region 81 is connected to second nickel silicide film 33b.

[0079] In a conventional embodiment in which dot-shaped ohmic electrodes are arranged (see FIG. 30), there are areas near the periphery that are far from the ohmic electrodes and areas near the periphery. In this embodiment, however, the ohmic electrodes are arranged evenly even near the periphery. This allows the surge current to be dispersed more evenly when it flows, and prevents localized current concentration, improving the IFSM characteristics. In addition, an ineffective region 80 is always sandwiched between the ohmic region 81 and the Schottky region 82. This allows the ineffective region 80 to direct carriers to the ohmic region 81, reducing leakage current.

[0080] Moreover, an ineffective region 80 is provided around the ohmic region 81, and the ohmic regions 81 are not connected to each other in the active region 10. That is, the ineffective region 80 and the Schottky region 82 are present between adjacent first nickel silicide films 33a. Thus, in the embodiment, there is no wide ohmic region that spans multiple stripes of the ohmic region 81. For example, there is no wide ohmic region like the ohmic electrode on the conventional p-type region 113' (see FIG. 30). As a result, the area of ​​the ohmic region 81 does not increase, and the Vf characteristics can be maintained.

[0081] Such a structure can be formed, for example, as described later, by using nickel silicide generated by reacting a metal material film 52 in which nickel, aluminum, and nickel are deposited in this order with the surface region of the semiconductor substrate 30 by heat treatment. The low-resistance first nickel silicide film 33a is formed by self-alignment, which removes the non-silicided portion of the metal material film 52 (except for the heat reaction layer) by etching. A low-resistance p-type ohmic electrode is formed by using the metal material film 52 in which nickel, aluminum, and nickel are deposited in this order. In addition, by forming it by self-alignment, an ohmic electrode is formed inside the JBS structure with a width of several μm, and the Vf characteristics can be maintained. In this way, the low-resistance ohmic region 81 can be formed without narrowing the area of ​​the Schottky region 82, so that the IFSM characteristics can be improved while maintaining the Vf characteristics.

[0082] Moreover, by making the width w2a of the first nickel silicide film 33a narrower than the width w1 of the p-type region 13, a design margin can be provided to improve the alignment accuracy of a mask (a remaining portion of the field oxide film 15 described below: see FIG. 10) used when forming the first nickel silicide film 33a. This allows the first nickel silicide film 33a to be positioned with good positional accuracy at a position facing the p-type region 13 in the depth direction.

[0083] FIG. 6 is a graph showing IFSM and Vf with respect to the Schottky electrode area ratio. In FIG. 6, the horizontal axis shows the area ratio of the Schottky electrode in %, and the unit is %. The area ratio of the Schottky electrode is the ratio of the area of ​​the Schottky region to the area of ​​the entire active region 10. Since the active region 10 is composed of an ineffective region 80, an ohmic region 81, and a Schottky region 82, the area ratio of the Schottky electrode is the area of ​​the Schottky region 82 / (area of ​​the Schottky region 82+area of ​​the ohmic region 81+area of ​​the ineffective region 80). This area ratio is the result of changing the area of ​​the Schottky region 82 while keeping the area of ​​the ohmic region 81 constant. The left vertical axis shows IFSM, and the right vertical axis shows Vf. In FIG. 6, ■ and □ show Vf, and ◆ and ◇ show IFSM. Moreover, ■ and ◆ represent the case of a silicon carbide semiconductor device in which an ohmic electrode is formed also on the conventional dot-shaped p-type region 113', and □ and ◇ represent the case of the silicon carbide semiconductor device of the embodiment. Note that in Fig. 6, these symbols are displayed overlapping each other. For example, in the case of the silicon carbide semiconductor device of the embodiment, three □ are overlapping each other.

[0084] 6, in a conventional silicon carbide semiconductor device, when the area ratio of the Schottky electrode is reduced, the IFSM value increases and is improved, but the Vf value increases and is deteriorated. On the other hand, in the embodiment, it is shown that the IFSM characteristic can be improved while maintaining the Vf characteristic by adjusting the width w5 of Schottky region 82 and the width w2a of ohmic region 81 to make the areas of Schottky region 82 and ohmic region 81 approximately the same (more precisely, the area ratio of the Schottky electrode is approximately 55%).

[0085] The area ratio of the ineffective region 80 in the active region 10 is preferably 15% or more and 35% or less. The area ratio of the ohmic region 81 in the active region 10 is preferably 10% or more and 35% or less. The area ratio of the Schottky region 82 in the active region 10 is preferably 35% or more and 65% or less. In this case, the sum of the ineffective region 80 and the ohmic region 81 is 35% or more and 65% or less with respect to the active region. The respective area ratios are selected from values ​​that make the sum of the area ratio of the ineffective region 80, the area ratio of the ohmic region 81, and the area ratio of the Schottky region 82 100%. By setting the area ratios in these ranges, it is possible to achieve both an improvement in surge current resistance and low Vf characteristics.

[0086] Here, the area ratio of the ineffective region 80 in the active region 10 is the area of ​​the ineffective region 80 / (area of ​​the Schottky region 82+area of ​​the ohmic region 81+area of ​​the ineffective region 80), and is calculated by 2×w4 / (2×w4+w2a+w5) when the Schottky region 82 and the ohmic region 81 are alternately provided one by one as in Fig. 4. Similarly, the area ratio of the ohmic region 81 in the active region 10 is the area of ​​the ohmic region 81 / (area of ​​the Schottky region 82+area of ​​the ohmic region 81+area of ​​the ineffective region 80), and is calculated by w2a / (2×w4+w2a+w5) when the Schottky region 82 and the ohmic region 81 are alternately provided one by one as in Fig. 4. In addition, the area ratio of the Schottky region 82 in the active region 10 is the same as the area ratio of the Schottky electrode, and when the Schottky regions 82 and the ohmic regions 81 are provided alternately one by one as shown in FIG. 4, it can be calculated by w5 / (2×w4+w2a+w5).

[0087] The second nickel silicide film 33b is an ohmic electrode that is in ohmic junction with the FLR 21. The second nickel silicide film 33b may be provided on almost the entire surface of the FLR 21 in the connecting region 20a of the edge termination region 20. The second nickel silicide film 33b contacts the field oxide film 15 on the sidewall of the field oxide film 15. Like the first nickel silicide film 33a, the second nickel silicide film 33b has the function of increasing the amount of surge current extracted and improving the surge current withstand capability.

[0088] By providing the second nickel silicide film 33b, an ohmic electrode having the same function as the first nickel silicide film 33a can be disposed in the connecting region 20a of the edge termination region 20. As a result, even if the chip size (planar dimension parallel to the front surface of the semiconductor substrate 30) is reduced, the total junction area between the first and second nickel silicide films 33a, 33b and the semiconductor substrate 30 can ensure a sufficient ohmic junction area between the front surface electrode 14 and the semiconductor substrate 30, which is necessary to obtain a predetermined surge current withstand capacity.

[0089] Also, the ohmic contact area between the FLR 21 and the second nickel silicide film 33b can be maximized by having the second nickel silicide film 33b extend outward to a position where the second nickel silicide film 33b contacts the field oxide film 15. This makes the width w2b of the second nickel silicide film 33b approximately the same as the width w3 of the connecting region 20a of the edge termination region 20, and as described above, the second nickel silicide film 33b can be provided on approximately the entire surface of the FLR 21 in the connecting region 20a of the edge termination region 20.

[0090] Furthermore, by making the width w2b of the second nickel silicide film 33b approximately the same as the width w3 of the connecting region 20a of the edge termination region 20, it is possible to reduce the forward voltage of the silicon carbide diode in the same manner as when the width w2a of the first nickel silicide film 33a is approximately the same as the width w1 of the p-type region 13. The width w2b of the second nickel silicide film 33b may be narrower than the width w3 of the connecting region 20a of the edge termination region 20, for example. The reason for this is the same as the reason for the width w2a of the first nickel silicide film 33a being narrower than the width w1 of the p-type region 13.

[0091] As described later, the second nickel silicide film 33b is formed by reacting the semiconductor substrate 30 with the metal material film 52 by heat treatment at the contact points between the FLR 21 and the metal material film 52 deposited on the front surface of the semiconductor substrate 30. The second nickel silicide film 33b is provided in a surface region of the front surface of the semiconductor substrate 30, contacts the FLR 21 in the depth direction, and protrudes from the front surface of the semiconductor substrate 30 in a direction away from the front surface of the semiconductor substrate 30.

[0092] The front surface of the semiconductor substrate 30 is covered with a field oxide film 15 except for the portion in contact with the front surface electrode 14. A passivation film 18 made of polyimide is provided on the top surface of the front surface of the semiconductor substrate 30. Here, n + On the top of the channel stopper region 24, + A channel stopper electrode may be provided in contact with and electrically connected to the type channel stopper region 24. The channel stopper electrode may be, for example, an aluminum alloy film formed simultaneously with the aluminum alloy film 32.

[0093] The passivation film 18 is a protective film that protects the front electrode 14 and the field oxide film 15. The passivation film 18 has an opening 18a in the active region 10 that exposes a part of the aluminum alloy film 32. The part of the front electrode 14 exposed in the opening 18a of the passivation film 18 functions as a bonding pad 41. +A back electrode (second electrode) 19 is provided on the entire back surface of the starting mold substrate 11, + The mold is electrically connected to the starting substrate 11.

[0094] Next, a method for manufacturing a silicon carbide semiconductor device 40 according to an embodiment will be described. Fig. 7 is a flowchart showing an outline of the method for manufacturing a silicon carbide semiconductor device according to an embodiment. Figs. 8 to 18 are cross-sectional views showing states during the manufacturing of a silicon carbide semiconductor device according to an embodiment. Fig. 19 is a cross-sectional view showing details of an opening formed in an oxide film of a silicon carbide semiconductor device according to an embodiment. Figs. 20 to 22 are cross-sectional views typically showing states during the manufacturing of a front surface electrode of a silicon carbide semiconductor device according to an embodiment.

[0095] First, as shown in Figure 8, + The starting substrate (semiconductor wafer) 11 is, for example, 5×10 18 / cm 3 A four-layer hexagonal silicon carbide (4H-SiC) substrate doped with about 1000 nm of nitrogen (N) is prepared. + The front surface of the starting substrate 11 may have an off angle of, for example, about 4° with respect to the (0001) plane. + On the front surface of the starting mold substrate 11, - For example, 1.8×10 16 / cm 3 Nitrogen doped n - A type epitaxial layer is grown.

[0096] n + n-type cathode region + The thickness of the starting mold substrate 11 may be, for example, about 350 μm. - n-type drift region 12 - The thickness of the n-type epitaxial layer may be, for example, about 6 μm. + On the front surface of the starting substrate 11, - n-type drift region 12 -A semiconductor substrate (semiconductor wafer) 30 is fabricated by stacking n-type epitaxial layers. As described above, the semiconductor substrate 30 is - The main surface on the side of the n-type drift region 12 is the front surface, + The main surface on the starting mold substrate 11 side is referred to as the back surface.

[0097] Next, as shown in Fig. 9, one or more p-type regions 13 constituting a JBS structure and FLRs 21 are selectively formed in the surface region of the front surface of semiconductor substrate 30 in active region 10 (see Figs. 1 and 3) by photolithography and first ion implantation of p-type impurities such as aluminum (step S1 (part 1)). For simplification, Fig. 9 illustrates a smaller number of p-type regions 13 (three in this case) than in Fig. 1 (the same applies to Figs. 10 to 18). The multiple p-type regions 13 are equally spaced in a direction parallel to the front surface of semiconductor substrate 30, for example, at intervals of about 2 µm.

[0098] At this time, while the semiconductor substrate 30 is heated at a temperature of, for example, about 500° C., n - Type epitaxial layer (n - In the first ion implantation, the impurity concentration of the box profile from the front surface of the semiconductor substrate 30 to a depth of 500 nm is set to 2×10 19 / cm 3 In order to achieve a target concentration of about 1000 keV, p-type impurities are ion-implanted in a plurality of stages at different acceleration energies in the range of about 30 keV to 350 keV.

[0099] Next, as shown in FIG. 10, a set of steps including photolithography and a second ion implantation of impurities is repeatedly performed under different conditions to form a p-type region (p - Type 22 and p -- 23) and n +and a type channel stopper region 24 (see FIG. 3) are selectively formed (step S1 (part 2)). This second ion implantation is performed in multiple stages, for example, in the same manner as the first ion implantation, so that the impurity concentration distribution has a box profile.

[0100] 11, the entire front surface of the semiconductor substrate 30 is covered with, for example, a carbon (C) protective film 50 for protection, and the first and second ion-implanted impurities are activated by heat treatment (step S2). In the process of step S2, for example, the semiconductor substrate 30 is inserted into a processing furnace of a heat treatment device, and the atmosphere in the processing furnace is heated to 1×10 -2 After suction (evacuation) until the pressure reached about 1×10 Pa or less, argon (Ar) gas was introduced into the processing furnace. 5 Heat treatment is performed at a temperature of about 1700° C. in an atmosphere of about Pa for about 5 minutes.

[0101] 12, for example, an ashing device is used to remove the carbon protective film 50 by ashing. For example, a reactive ion etching (RIE) device is used as the ashing device. After the inside of the processing furnace of the RIE device is set to an oxygen (O2) gas atmosphere at a pressure of about 6 Pa, radio frequency (RF) power of about 500 W is applied to the oxygen gas atmosphere to generate plasma, and the carbon protective film 50 is removed by ashing for about 5 minutes in the oxygen gas atmosphere.

[0102] 13, an oxide film 51 is formed on the entire front surface of the semiconductor substrate 30 (step S3). Next, the oxide film 51 is selectively removed by photolithography and etching to form openings (first and second openings) 51a and 51b (step S4). In the process of step S4, a plurality of openings 51a exposing different p-type regions 13 and one opening 51b exposing the inner portion of the FLR 21 in a substantially rectangular shape surrounding the periphery of the active region 10 are formed in the oxide film 51.

[0103] By the process of step S4, the oxide film 51 in the active region 10 is - The portion 15' covering the n-type drift region 12 and the portion that will become the field oxide film 15 in the edge termination region 20 are left. After the process of step S4, the entire oxide film 51, including the portion that will become the field oxide film 15, serves as an oxide film mask used in the formation of the nickel silicide film 33 in the process described below. - The portion 15' covering the mold drift region 12 does not remain in the product.

[0104] That is, in the process of step S4, the field oxide film 15 and the oxide film mask used for forming the nickel silicide film 33 are simultaneously formed. Therefore, the oxide film 51 has the same layered structure as the field oxide film 15. Specifically, the oxide film 51 is a layered oxide film having a thickness of about 500 nm, in which a thermal oxide film 16 and a deposited oxide film 17 (see FIG. 3) are layered in order by a thermal oxidation method and a chemical vapor deposition (CVD) method, for example.

[0105] The process of step S4 is preferably performed by dry etching with high dimensional accuracy. This allows p-type region 13 and FLR 21 to be exposed with high dimensional accuracy. In addition, the outer sidewall of opening 51b of oxide film 51 becomes the sidewall of contact hole 15a in field oxide film 15. Therefore, by performing the process of step S4 by dry etching, contact hole 15a in field oxide film 15 can be formed with high dimensional accuracy.

[0106] When opening 51a is formed by dry etching, opening 51a is formed in the shape shown in Fig. 19. As shown in Fig. 19, opening 51a has a tapered shape in which the bottom surface is narrower than the surface, and the angle θ between the sidewall of opening 51a and the surface of p-type region 13 is an angle of 80° to 90°. Although opening 51a has been described here, the same applies to opening 51b.

[0107] Next, a metal material film 52 is formed on the surface of the oxide film 51 from the surface to the front surface (surface) of the semiconductor substrate 30 in the openings 51a, 51b of the oxide film 51 by, for example, a sputtering method (step S5). The metal material film 52 is a laminated metal film in which a first nickel film 58, an aluminum film (metal film containing aluminum) 53, and a second nickel film 54 are laminated in this order (FIG. 20). In FIG. 13, the first nickel film 58, the aluminum film 53, and the second nickel film 54 are collectively illustrated as one layer of the metal material film 52. In the following description, a three-layered metal material film 52 will be described, but the metal material film 52 may be a two-layered laminated metal film in which the aluminum film 53 and the second nickel film 54 are laminated in this order.

[0108] Here, in silicon carbide semiconductor devices, it is known that an aluminum film is formed as an ohmic electrode in order to reduce the contact resistance with the p-type region (p-type region 13 and field limiting ring 21 that constitute the JBS structure). However, aluminum alone causes a vigorous alloying reaction, and surface condensation occurs after heat treatment. Although it is possible to reduce the contact resistance with the p-type region by using nickel silicide in addition to aluminum, there is a limit to the reduction in sheet resistance.

[0109] Therefore, by using a laminated metal film in which an aluminum film and a nickel film are laminated in order, when silicon carbide and nickel are silicided, the excess carbon reacts with aluminum to form Al3C, which makes it possible to reduce the sheet resistance. Also, as with the silicided nickel, it is possible to form it in a self-aligned manner by performing two-stage sintering.

[0110] However, in the case of a laminated metal film in which an aluminum film and a nickel film are laminated in sequence, condensation of aluminum occurs on the surface of the semiconductor substrate, which places an upper limit on the temperature of the first sintering step, limiting the thickness of the silicide layer that can be formed, and also causing part of the silicide layer to disappear in the subsequent steps.

[0111] Therefore, in the method for manufacturing a silicon carbide semiconductor device according to the embodiment, a laminated metal film is used in which a first nickel film 58, an aluminum film 53, and a second nickel film 54 are laminated in this order. The first nickel film 58 is a film that suppresses condensation of aluminum on the surface of the semiconductor substrate 30 during the heat treatment in step S6 described below, and has a thickness t3 of, for example, about 80 nm. If the first nickel film 58 is not used, the aluminum film 53 will be in contact with the semiconductor substrate 30, and an Al-Ni-Si compound (compound layer) 55 described below cannot be formed uniformly over the entire front surface of the semiconductor substrate 30. The aluminum film 53 has a thickness t1 of, for example, about 80 nm.

[0112] The second nickel film 54 is a cap film that prevents the aluminum film 53 from melting during the heat treatment in step S6 described later, and has a thickness t2 of, for example, about 50 nm. The reason for using the cap film is as follows. If the cap film is not used, the aluminum film 53 melted during the heat treatment in step S6 becomes granular and is partially in contact with the semiconductor substrate 30. In this case, it is not possible to uniformly form an Al-Ni-Si compound (compound layer) 55 described later over the entire front surface of the semiconductor substrate 30.

[0113] Thereafter, the metal material film 52 is subjected to a first sintering (sintering) by heat treatment (step S6), thereby generating an aluminum-nickel-silicon (Al-Ni-Si) compound 55 in the openings 51a, 51b of the oxide film 51 (see FIG. 14). The mechanism by which the Al-Ni-Si compound 55 is generated by this heat treatment (first sintering) will be described in detail with reference to FIGS. 20 to 22.

[0114] Fig. 20 shows only the contact points between the metal material film 52 and the semiconductor substrate 30 in the openings 51a, 51b of the oxide film 51, and other parts are omitted (the same applies to Figs. 21 and 22). Fig. 20 shows the state in one opening (51a, 51b) of the oxide film 51, but all openings 51a, 51b of the oxide film 51 are in the same state as that shown in Fig. 20.

[0115] By the heat treatment in step S6, silicon atoms in the semiconductor substrate 30 are thermally diffused 61 into the aluminum film 53 at the contact points between the metal material film 52 and the semiconductor substrate 30 in the openings 51a, 51b of the oxide film 51. Aluminum atoms in the aluminum film 53 are thermally diffused 62 into the first nickel film 58 and the second nickel film 54. Nickel atoms in the first nickel film 58 are thermally diffused 63 into the semiconductor substrate 30, and nickel atoms in the second nickel film 54 are thermally diffused 64 into the aluminum film 53 (FIG. 21).

[0116] Due to the thermal diffusion 62 of aluminum atoms into the second nickel film 54 and the thermal diffusion 64 of nickel atoms into the aluminum film 53, an aluminum-nickel (AlNi) compound 56 is generated on the front surface of the semiconductor substrate 30 in the openings 51a, 51b of the oxide film 51 and on the surface of the oxide film 51. Furthermore, due to the thermal diffusion 62 of aluminum atoms into the first nickel film 58, the thermal diffusion 63 of nickel atoms into the semiconductor substrate 30, and the thermal diffusion 61 of silicon atoms into the first nickel film 58 and the aluminum film 53, an Al-Ni-Si compound 55 is generated at the contact points between the metal material film 52 and the semiconductor substrate 30 (FIG. 22).

[0117] Al-Ni-Si compound 55 is produced by a reaction between metal material film 52 and low impurity concentration portions of p-type region 13 and FLR 21, which are diffusion regions formed by ion implantation, located at a shallow depth position of about 20 nm to 30 nm from the front surface of semiconductor substrate 30. Therefore, a compound layer containing Al-Ni-Si compound 55 is formed in a self-aligned manner using oxide film 51 as a mask so as to penetrate into semiconductor substrate 30 in the depth direction within openings 51a, 51b of oxide film 51.

[0118] Furthermore, the Al-Ni-Si compound 55 contacts a portion of the p-type region 13 in which it is formed or the FLR 21 in which it is formed that is at a deeper position than the low impurity concentration portion from the front surface of the semiconductor substrate 30 and has a higher impurity concentration than the low impurity concentration portion. The Al-Ni-Si compound 55 forms a low resistance ohmic junction with the high impurity concentration in the p-type region 13 or the FLR 21.

[0119] Carbon (C) remaining in the semiconductor substrate 30 due to the silicide reaction between the Al-Ni-Si compound 55 and the semiconductor substrate 30 (hereinafter referred to as "excess carbon") may be precipitated in the Al-Ni-Si compound 55 to such an extent that it does not form a layer. The excess carbon is carbon atoms remaining in the semiconductor substrate 30 as a result of silicon atoms in the semiconductor substrate 30 being consumed by the above-mentioned silicide reaction. Specifically, the excess carbon may be precipitated and distributed in the Al-Ni-Si compound 55 in the form of particles.

[0120] The heat treatment time of step S6 is preferably, for example, 2 minutes or more in consideration of the uniformity of the chemical reaction, and is preferably, for example, about 1 hour or less in consideration of mass productivity of the product. The heat treatment temperature of step S6 is preferably, for example, about 500°C or more and 700°C or less. The heat treatment of step S6 is performed, for example, at 600°C for 10 minutes. The reason is as follows. If the heat treatment temperature of step S6 exceeds 700°C, the aluminum nickel compound 56 penetrates into the oxide film 51, which is a silicon oxide (SiO2) film, and reacts, and if the reaction proceeds further, nickel silicide is formed in the Schottky region. In the next step S7 for removing the excess metal (excess portion), the nickel silicide film 33 is not removed, so that the product remains inside the field oxide film 15 and on the Schottky region, and this product causes leakage defects when reverse bias is applied.

[0121] If the heat treatment temperature in step S6 is less than 400°C, the above reaction between the semiconductor substrate 30 and the metal material film 52 does not occur, and the metal material film 52 is completely removed in the subsequent processing in step S7 without using the metal material film 52. Also, if the heat treatment temperature in step S6 is less than 600°C, aluminum atoms in the aluminum film 53 are not thermally diffused into the semiconductor substrate 30. The heat treatment in step S6 is preferably performed in, for example, a heat treatment furnace in which the heat treatment temperature can be easily controlled uniformly. A uniform temperature means that the temperature is approximately the same within a range including an error allowable due to process variations. This concludes the detailed explanation of the first sintering.

[0122] 15, excess metal (excess portion) on oxide film 51 and in openings 51a, 51b of oxide film 51 is removed (step S7). The excess metal is unreacted metal material film 52 and metal other than Al-Ni-Si compound 55 generated from metal material film 52, specifically aluminum nickel compound 56 that did not contribute to the generation of Al-Ni-Si compound 55. In the process of step S7, the entire front surface of semiconductor substrate 30 is etched by wet etching using, for example, phosphoric acid, nitric acid, and acetic acid. As a result of the process of step S7, Al-Ni-Si compound 55 remains in each of openings 51a, 51b of oxide film 51.

[0123] 16, the Al-Ni-Si compound 55 is subjected to a second sintering by heat treatment (step S8). The heat treatment in step S8 generates nickel silicide in the Al-Ni-Si compound 55, and the Al-Ni-Si compound 55 becomes a nickel silicide film 33 that forms an ohmic junction with the semiconductor substrate 30. As a result, the nickel silicide film 33 that forms an ohmic junction with the semiconductor substrate 30 is formed in each of the openings 51a, 51b of the oxide film 51 in a self-aligned manner using the oxide film 51 as a mask.

[0124] The heat treatment temperature in step S8 may be higher than the heat treatment temperature in step S6, for example. The heat treatment temperature in step S8 is preferably about 900° C. or higher at which nickel silicide is generated in the Al-Ni-Si compound 55, and about 1100° C. or lower at which a vertical heat treatment furnace can be used to perform the heat treatment at low cost. The heat treatment in step S8 is performed at 975° C. for 10 minutes, for example. The heat treatment in step S8 is preferably performed using a heat treatment furnace that can uniformly control the heat treatment temperature.

[0125] 17, a resist film 57 is formed by photolithography, which has an opening corresponding to a region for forming the contact hole 15a in the field oxide film 15. Next, etching is performed using the resist film 57 as a mask to form the contact hole 15a penetrating the field oxide film 15 in the depth direction (step S9). In the process of step S9, only the portion of the oxide film 51 that will become the field oxide film 15 remains.

[0126] In the process of step S9, the oxide film 51 is etched in the active region 10. - The contact hole 15a already formed in the processing of step S4 appears by removing the entire portion 15' covering the mold drift region 12 and connecting all of the openings 51a, 51b of the oxide film 51. During the processing of step S9, the entire outer sidewall of the opening 51b of the oxide film 51 is completely covered with the resist film 57, so that the outer sidewall of the opening 51b of the oxide film 51 is not etched.

[0127] The entire surface of the active region 10 and the entire surface of the connection region 20a of the edge termination region 20 are exposed to the contact hole 15a of the field oxide film 15. As a result, all of the nickel silicide film 33 (33a, 33b) and the n - The portion of the type drift region 12 sandwiched between the adjacent nickel silicide films 33 is exposed.

[0128] When the widths w2a, w2b of the first and second nickel silicide films 33a, 33b are less than the width w1 of the p-type region 13 and less than the width w3 of the connecting region 20a of the edge termination region 20, respectively, the contact hole 15a of the field oxide film 15 further exposes portions of the surfaces of the p-type region 13 and the FLR 21 that are not joined to the nickel silicide film 33.

[0129] The process of step S9 is preferably performed by wet etching. This is because, if the process of step S9 is performed by dry etching, there is a risk that plasma damage due to dry etching may remain on the front surface of the semiconductor substrate 30. Even if the process of step S9 is performed by wet etching, the contact hole 15a can be formed in the field oxide film 15 with high dimensional accuracy. This is because, during the process of step S4, the outer sidewall of the opening 51b formed in the oxide film 51 with high dimensional accuracy by dry etching is composed of the sidewall of the contact hole 15a in the field oxide film 15.

[0130] In the process of step S4, n - The portion 15' that covers the n-type drift region 12 and the portion that becomes the field oxide film 15 are left (see FIG. 13). - A portion 15' covering the mold drift region 12 remains in the contact hole 15a of the field oxide film 15, and the outer sidewall of the opening 51b in the oxide film 51 is formed by the sidewall of the contact hole 15a in the field oxide film 15. The outer sidewall of the opening 51b in the oxide film 51 is completely covered in its entirety with the resist film 57 during the processing of step S9, and is not etched. Therefore, the position of the outer sidewall of the opening 51b in the oxide film 51 does not change after the processing of step S4.

[0131] In this way, the dimensional accuracy of the contact hole 15a in the field oxide film 15 is the same as the dimensional accuracy of the opening 51b in the oxide film 51 formed by dry etching, and does not depend on the dimensional accuracy of the wet etching in the process of step S9. Since the position of the outer sidewall of the opening 51b in the oxide film 51 does not change after the process of step S4, the second nickel silicide film 33b formed in a self-aligned manner using the oxide film 51 as a mask is maintained in contact with the outer sidewall of the opening 51b in the oxide film 51 even after the process of step S9. That is, the second nickel silicide film 33b is maintained in contact with the field oxide film 15 on the sidewall of the contact hole 15a even after the process of step S9.

[0132] 18, a titanium film 31 is formed on the entire surface from the surface of the field oxide film 15 to the front surface of the semiconductor substrate 30 in the contact hole 15a by physical vapor deposition (PVD) such as sputtering. Next, the titanium film 31 is left only in the contact hole 15a by photolithography and etching (Step S10). The thickness of the titanium film 31 may be, for example, about 100 nm. The titanium film 31 may extend from inside the contact hole 15a onto the field oxide film 15.

[0133] Next, the titanium film 31 is sintered by heat treatment at a temperature of, for example, about 500° C. for about 10 minutes. - A Schottky junction is formed with the type drift region 12. Next, an aluminum alloy film having a thickness of, for example, about 5 μm is formed over the entire surface from the surface of the titanium film 31 to the surface of the field oxide film 15 by physical vapor deposition such as sputtering. Next, the aluminum alloy film is selectively removed by photolithography and etching to leave the aluminum alloy film 32, which will become the front electrode 14, on the surface of the titanium film 31.

[0134] Next, the front surface of the semiconductor substrate 30 (semiconductor wafer) is covered with a protective film (not shown) for protection, and then the semiconductor substrate 30 is polished from the back side to thin the semiconductor substrate 30 to the product thickness. Next, the back surface (n + After nickel or titanium is formed on the entire back surface of mold starting substrate 11, laser annealing is performed to form back electrode 19 (step S11). Thereafter, the protective film on the front surface of semiconductor substrate 30 is removed, and then semiconductor substrate 30 is diced (cut) into individual chips, thereby completing silicon carbide semiconductor device 40 shown in FIGS. 1 to 3.

[0135] 23 and 24 are other plan views showing the layout of the silicon carbide semiconductor device according to the embodiment as viewed from the front surface side of the semiconductor substrate. As shown in Fig. 23 and Fig. 24, the field limiting ring may be doubled.

[0136] 23, an inner field limiting ring 21a may be provided inside the field limiting ring 21. In this embodiment, the inner field limiting ring 21a is provided in the active region 10, and an n-type region 13 is provided between the field limiting ring 21 and the inner field limiting ring 21a. - A mold drift region 12 is provided.

[0137] By providing the inner field limiting ring 21a, it is possible to disperse surge currents, disperse heat generation, and prevent heat from accumulating locally. In addition, the region of the inner field limiting ring 21a parallel to the p-type region 13 can have the same function as the p-type region 13.

[0138] 24, an outer field limiting ring 21b may be provided outside the field limiting ring 21. In this embodiment, the outer field limiting ring 21b is provided in the edge termination region 20, and a p-type region (p-type region constituting a JTE structure) is provided between the field limiting ring 21 and the outer field limiting ring 21b and the p-type region 13. - In this configuration, outer field limiting ring 21b is connected to front electrode 14 via a p-type region and inner field limiting ring 21a.

[0139] By providing the outer field limiting ring 21b, the electric field acting on this portion is alleviated, and a higher withstand voltage can be ensured.

[0140] As described above, according to the embodiment, the stripe-shaped Schottky regions and the stripe-shaped low-resistance ohmic regions are alternately provided, and the high-resistance ineffective regions are provided between them. This allows the low-resistance ohmic regions to be formed without narrowing the area of ​​the Schottky regions, thereby improving the IFSM characteristics while maintaining the Vf characteristics.

[0141] The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. The present invention is applicable to silicon carbide semiconductor devices including ohmic electrodes in ohmic contact with p-type regions arranged in a predetermined pattern.

[0142] Specifically, for example, the present invention relates to a p-type region (or a p-type semiconductor layer disposed between the p-type region and the main surface of the semiconductor substrate). + The present invention is useful for silicon carbide semiconductor devices having a configuration for reducing the contact resistance between a p-type contact region and an ohmic electrode, and for silicon carbide semiconductor devices having a structure in which an ohmic electrode in ohmic junction with a p-type region is in contact with an oxide film. [Industrial Applicability]

[0143] INDUSTRIAL APPLICABILITY As described above, the silicon carbide semiconductor device and the method for manufacturing a silicon carbide semiconductor device according to the present invention are useful for power semiconductor devices used in power conversion devices and power supply devices for various industrial machines and the like. [Explanation of symbols]

[0144] 10 Active area 11 n + Starting substrate 12n - Mold Drift Region 13,72,74 p-type region constituting the JBS structure 14 Front electrode 15 Field oxide 15' In the oxide film (oxide film mask), n is - Part covering the mold drift area 15a Field oxide contact hole 16 Thermal oxide film 17 Deposited oxide film 18 Passivation film 18a Opening in passivation film 19 Back electrode 20 Edge Termination Area 20a Edge termination area connection area 21 Field Limiting Ring (FLR) 21a Inner Field Limiting Ring 21b Outer field limiting ring 22 JTE Structure - type area 23 JTE Structure -- type area 24n + Mold channel stopper region 30 Semiconductor Substrate 31 Titanium membrane 32 Aluminum alloy film 33(33a, 33b) Nickel silicide film (first and second nickel silicide films) 40 Silicon carbide semiconductor device 41 Bonding Pad 42 Bonding pad and wire joint 50 Carbon protective film 51 Oxide film (Oxide film mask) 51a, 51b Openings in oxide film (oxide film mask) 52 Metal material film 53 Aluminum Film 54 Second Nickel Film 55 Aluminum-nickel-silicon (Al-Ni-Si) compounds 56 Aluminum Nickel Compounds 57 Resist film 58 First Nickel Film 61~64 Thermal diffusion 80 Invalid area 81 Ohmic region 82 Schottky Region w1 Width of the p-type region that constitutes the JBS structure w2a Width of the first nickel silicide film w2b Width of the second nickel silicide film w3 Width of the edge termination region w4 Width of the invalid area of ​​the JBS structure w5 Schottky region width

Claims

1. an active region provided in a semiconductor substrate made of silicon carbide; a termination region provided in the semiconductor substrate and surrounding the active region; a first conductivity type region provided within the semiconductor substrate and exposed to a first main surface of the semiconductor substrate; a first second-conductivity type region selectively provided in the active region between the first main surface of the semiconductor substrate and the first-conductivity type region and in contact with the first-conductivity type region; a silicide film in ohmic junction with the first second conductivity type region; a first electrode in contact with the silicide film, the first second conductivity type region, and the first conductivity type region; a second electrode provided on a second main surface of the semiconductor substrate; a second second conductivity type region provided in the termination region and surrounding the active region; Equipped with the active region is composed of an ohmic region where the first electrode is in contact with the silicide film, an ineffective region where the first electrode is in contact with the first second conductivity type region, and a Schottky region where the first electrode is in contact with the first conductivity type region; the ohmic region, the invalid region, and the Schottky region are provided in a stripe shape, a second second conductivity type region that is connected to the ohmic region and the ineffective region;

2. an active region provided in a semiconductor substrate made of silicon carbide; a termination region provided in the semiconductor substrate and surrounding the active region; a first conductivity type region provided within the semiconductor substrate and exposed to a first main surface of the semiconductor substrate; a first second-conductivity type region selectively provided in the active region between the first main surface of the semiconductor substrate and the first-conductivity type region and in contact with the first-conductivity type region; a silicide film in ohmic junction with the first second conductivity type region; a first electrode in contact with the silicide film, the first second conductivity type region, and the first conductivity type region; a second electrode provided on a second main surface of the semiconductor substrate; a second second conductivity type region provided in the termination region and surrounding the active region; Equipped with the active region is composed of an ohmic region where the first electrode is in contact with the silicide film, an ineffective region where the first electrode is in contact with the first second conductivity type region, and a Schottky region where the first electrode is in contact with the first conductivity type region; the ohmic region, the invalid region, and the Schottky region are provided in a stripe shape, In the termination region, the second second-conductivity type region is connected to the ohmic region and the invalid region; The contact resistance between the silicide film and the first electrode in the ohmic region is 5.0×10 -3 Ω cm 2 is as follows:

2. A silicon carbide semiconductor device comprising: a first region of a second conductivity type and a second region of a second conductivity type.

3. an active region provided in a semiconductor substrate made of silicon carbide; a termination region provided in the semiconductor substrate and surrounding the active region; a first conductivity type region provided within the semiconductor substrate and exposed to a first main surface of the semiconductor substrate; a first second-conductivity type region selectively provided in the active region between the first main surface of the semiconductor substrate and the first-conductivity type region and in contact with the first-conductivity type region; a silicide film in ohmic junction with the first second conductivity type region; a first electrode in contact with the silicide film, the first second conductivity type region, and the first conductivity type region; a second electrode provided on a second main surface of the semiconductor substrate; a second second conductivity type region provided in the termination region and surrounding the active region; Equipped with the active region is composed of an ohmic region where the first electrode is in contact with the silicide film, an ineffective region where the first electrode is in contact with the first second conductivity type region, and a Schottky region where the first electrode is in contact with the first conductivity type region; the ohmic region, the invalid region, and the Schottky region are provided in a stripe shape, In the termination region, the second second-conductivity type region is connected to the ohmic region and the invalid region; 4. A silicon carbide semiconductor device, wherein the silicide film contains nickel, silicon and aluminum.

4. 2. The silicon carbide semiconductor device according to claim 1, further comprising a field oxide film, said silicide film in said termination region being in contact with said field oxide film on a side wall of said field oxide film.

5. 5. The silicon carbide semiconductor device according to claim 4, wherein the first electrode is provided so as to extend on the field oxide film toward an end of a chip.

6. 6. The silicon carbide semiconductor device according to claim 5, wherein the first electrode is a laminated film of an aluminum alloy film and a titanium film, and the titanium film terminates at a position facing the second second conductivity type region in a depth direction.

7. 7. The silicon carbide semiconductor device according to claim 1, wherein the second second conductivity type region is provided in a double layer.

8. 8. The silicon carbide semiconductor device according to claim 1, wherein a plurality of the ohmic regions are provided in a stripe shape, and the ohmic regions are not connected to each other in the active region.

9. The contact resistance between the silicide film and the first electrode in the ohmic region is 5.0×10 -4 Ω cm 2 9. The silicon carbide semiconductor device according to claim 1, wherein:

10. 10. The silicon carbide semiconductor device according to claim 1, wherein the ohmic region and the Schottky region are in contact with the ineffective region.

11. 11. The silicon carbide semiconductor device according to claim 1, wherein the ohmic region has a width of 2 μm or less.

12. A method for manufacturing a silicon carbide semiconductor device including a semiconductor substrate made of silicon carbide, an active region, and a termination region surrounding the active region, the method comprising the steps of: a first step of forming a first conductivity type region within the semiconductor substrate, the first conductivity type region forming a first main surface of the semiconductor substrate; a second step of selectively forming, in the active region, a first second-conductivity type region between the first main surface of the semiconductor substrate and the first-conductivity type region and in contact with the first-conductivity type region; a third step of forming a second second conductivity type region in the termination region surrounding the active region; a fourth step of forming an oxide film on a first main surface of the semiconductor substrate so as to cover the first conductivity type region and the first second conductivity type region; a fifth step of selectively removing the oxide film to form a first opening in the oxide film exposing the first second conductivity type region; a sixth step of forming a metal material film by sequentially stacking a first nickel film, an aluminum film, and a metal film having a melting point higher than that of aluminum, the first nickel film being in contact with the first main surface of the semiconductor substrate at the first opening of the oxide film; a seventh step of reacting the metal material film with the semiconductor substrate by a first heat treatment to generate a compound layer in a self-aligned manner on the first main surface of the semiconductor substrate in the first opening of the oxide film using the oxide film as a mask; an eighth step of removing an excess portion of the metal material film excluding the compound layer after the seventh step; a ninth step of generating nickel silicide inside the compound layer by a second heat treatment at a temperature higher than that of the first heat treatment after the eighth step, thereby forming a silicide film that makes an ohmic contact with the semiconductor substrate; a tenth step of removing the oxide film sandwiched between the silicide films after the ninth step to form a contact hole connecting all of the first openings; an eleventh step of forming a first electrode by sequentially stacking a titanium film, the titanium film being in contact with the first conductivity type region and forming a Schottky junction with the first conductivity type region, and a metal electrode film containing aluminum on the first main surface of the semiconductor substrate inside the contact hole; a twelfth step of forming a second electrode on a second main surface of the semiconductor substrate; Including, In the fifth step, a width of the first opening is formed narrower than a width of the first second-conductivity type region, thereby forming the active region to be composed of an ohmic region where the first electrode contacts the silicide film, an ineffective region where the first electrode contacts the first second-conductivity type region, and a Schottky region where the first electrode contacts the first conductivity type region; Furthermore, in the fifth step, the ohmic region, the invalid region, and the Schottky region are formed in a stripe shape, and in the termination region, the second second conductivity type region is connected to the ohmic region and the invalid region.

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