Integrated structure with diffusion barrier layer and electronic device including same

Abstract

An integrated structure is provided having a diffusion barrier layer for reducing interfacial defects at a metal-semiconductor interface. The present invention includes a silicon or SOI (Silicon-on-insulator) substrate, a conductive layer containing a metal or a metal compound spaced apart from the substrate, and a diffusion barrier layer provided between the substrate and the conductive layer, the substrate and the diffusion barrier layer being in direct contact with each other to form a van der Waals bond. The diffusion barrier layer can block the movement of substances (atoms) between the substrate and the conductive layer to block the diffusion of metal atoms in the substrate lattice, and can also control hole injection from the conductive layer toward the substrate, thereby controlling metal-semiconductor interface defects to overcome the limitations of ultra-miniaturized and highly integrated semiconductors.

Description

[Technical field]

[0001] The present invention relates to an integrated structure having a diffusion barrier layer, and more particularly to an integrated structure having a diffusion barrier layer for reducing interfacial defects at a metal-semiconductor interface. [Background technology]

[0002] In order to realize the convergence technology of artificial intelligence and Internet of Things (IoT), the development of intelligent semiconductor synapse elements capable of low-power operation is being actively promoted worldwide. In particular, in the post-COVID era, autonomous control devices that autonomously collect information, learn, judge, and act on it are necessary for the advancement of the real-life non-face-to-face industry and the national security net. In addition, artificial intelligence technology, which is widely used in the 4th industry including big data analysis and autonomous driving cars, is becoming necessary for NPUs (Neural Processing Units) as artificial intelligence semiconductors optimized for the calculation of deep learning algorithms. As it is expected that most of the existing CPU (Central Processing Unit)-based computing semiconductors will be replaced by NPUs, which are artificial intelligence semiconductors, the importance of developing advanced semiconductors with driving performance that can process large amounts of information at high speed and low power operation is further strengthened.

[0003] The metal-semiconductor interface can have a direct effect on electron injection and current output, and is one of the factors that determine the performance of semiconductor devices, so technology is essential to reduce defects in the interface between metal materials used as electrodes, etc. and semiconductor channels, especially in the metal-semiconductor interface formed by diffusion, intermixing, etc. of materials (atoms). Furthermore, unlike the past, as current semiconductor process technology approaches the sub-nano (sub-1 nm) level, quasi-ideal interface design on an ultra-fine scale is very important to overcome the limitations of future ultra-fine and highly integrated semiconductors. Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been devised to solve the above-mentioned problems, and provides an integrated structure capable of controlling defects at a metal-semiconductor interface and an electronic device including the same in order to overcome the limitations of ultra-miniaturization and highly integrated semiconductors. [Means for solving the problem]

[0005] In order to achieve the above technical objective, an integrated structure according to a preferred embodiment of the present invention can include a silicon or SOI (Silicon-on-insulator) substrate, a conductive layer spaced apart from the substrate and containing a metal or a metal compound, and a diffusion barrier layer provided between the substrate and the conductive layer.

[0006] The substrate and the diffusion barrier layer can be in direct contact and form van der Waals bonds.

[0007] The diffusion barrier layer may include a p-type semiconducting material.

[0008] The diffusion barrier layer may be a monolayer.

[0009] The diffusion barrier layer may have a thickness of 0.1 to 10 Å.

[0010] The diffusion barrier layer may include a transition metal dichalcogenide material.

[0011] The transition metal dichalcogenide material may be represented by the general formula MX2, in which M is a transition metal element and may include Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, Ru, Co, Pd, Pt, Cu, Ga, In, Sn, Ge, Pb, or a combination of two or more selected from among these, and X is a chalcogen element and may include S, Se, Te, or a combination of two or more selected from among these.

[0012] The transition metal dichalcogenide material may include MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, ZrS2, ZrSe2, HfS2, HfSe2, NbSe2, ReSe2, PdTe2, or a combination of two or more selected therefrom.

[0013] The crystal structure of the transition metal dichalcogenide material may be a hexagonal structure in a planar direction.

[0014] The metals may include Ti, Ni, Cr / Au, Ag, and combinations of two or more selected therefrom.

[0015] The present invention is characterized in that the movement of substances (atoms) in the conductive layer and the substrate is blocked.

[0016] The injection of electrons from the substrate to the conductive layer is blocked.

[0017] The present invention is characterized in that holes are injected from the conductive layer to the substrate.

[0018] The present invention may also be an electronic device including any one of the integrated structures described above. Effect of the Invention

[0019] According to the present invention, an integrated structure according to a preferred embodiment of the present invention includes a silicon or SOI (Silicon-on-insulator) substrate, a conductive layer containing a metal or a metal compound spaced apart from the substrate, and a diffusion barrier layer provided therebetween. The substrate and the diffusion barrier layer can be in direct contact with each other to form van der Waals bonds. The diffusion barrier layer can block the movement of material (atoms) between the substrate and the conductive layer to block the diffusion of metal atoms into the substrate lattice, and can control hole injection from the conductive layer toward the substrate, thereby controlling metal-semiconductor interface defects to overcome the limitations of ultra-miniaturized and highly integrated semiconductors.

[0020] The effects of the present invention are not limited to those described above, and include other effects that are not explicitly mentioned, although they can be clearly understood by those skilled in the art from the general description of the specification. [Brief description of the drawings]

[0021] [Figure 1] FIG. 2 is a schematic diagram of actuation of a diffusion barrier layer in a cross-section of an integrated structure according to one embodiment of the present invention. [Diagram 2] 1 shows a transmission electron microscope (TEM) result of photographing a cross section of a metal-semiconductor interface for an integrated structure according to an embodiment of the present invention, an EDS-based elemental mapping result, and an elemental information analysis result of each component. [Diagram 3] FIG. 1 is a schematic diagram showing a cross-section of a metal-diffusion barrier layer-semiconductor interface for an integrated structure according to one embodiment of the present invention, showing the results of a transmission electron microscope (TEM) photograph of the cross-section of the metal-diffusion barrier layer-semiconductor interface and the results of EDS-based elemental mapping. [Figure 4] 1A and 1C are energy diagrams and CV graphs of a metal-semiconductor interface, and (b) and (d) are energy diagrams and CV graphs of a metal-diffusion barrier layer-semiconductor interface for an integrated structure according to one embodiment of the present invention. [Diagram 5] FIG. 1 is a schematic diagram of an electronic device having an integrated structure according to an embodiment of the present invention; (a) an IV graph showing the results of the presence or absence of a diffusion barrier layer, (b) the On / Off ratio, and (d) the maximum mobility, for an integrated structure according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Advantages and features of the present invention, as well as methods for achieving the same, will become apparent from the following detailed embodiments together with the accompanying drawings. The present invention is not limited to the following embodiments, and may be embodied in various different forms, and the present embodiments are provided only to fully disclose the present invention and to fully inform those skilled in the art of the present invention of the scope of the invention, and the present invention is only defined by the scope of the claims. The same reference numerals are used to refer to the same components throughout the specification. Unless otherwise defined, all terms (including technical and scientific terms) used herein may be used in the sense commonly understood by those having ordinary skill in the art to which the present invention belongs. In addition, terms defined in commonly used dictionaries are not interpreted ideally or excessively unless otherwise clearly defined. The terms used herein are intended to describe the embodiments and are not intended to limit the present invention. In the present specification, the singular form includes the plural form unless otherwise specified in the text. As used herein, components, steps, operations and / or elements referred to as "comprises" and / or "comprising" do not exclude the presence or addition of one or more other components, steps, operations and / or elements.

[0023] Integrated structure with diffusion barrier layer - Patents.com FIG. 1 is a schematic diagram illustrating a cross-section of an integrated structure 100 including a diffusion barrier layer 20 according to one embodiment of the present invention.

[0024] 1, an integrated structure 100 may include a silicon or SOI (Silicon-on-insulator) substrate 10, a conductive layer 30 containing a metal or metal compound spaced therefrom, and a diffusion barrier layer 20 provided therebetween. The diffusion barrier layer 20 is a thin film and may function to block the movement of substances (atoms, electrons, holes, etc.) between the substrate 10 and the conductive layer 30, for example, the movement of metal atoms from the conductive layer 30 to the substrate 10.

[0025] The substrate 10 may be a semiconductor material, such as silicon or a silicon-on-insulator (SOI) substrate, and more specifically, may be a p-type semiconductor material, such as p-type silicon. The substrate 10 may further be a material doped with a dopant, but is not limited thereto.

[0026] The conductive layer 30 may include a metal or a metal compound. The metal or metal compound may include metal elements such as Ti, Ni, Cr / Au, Ag, and combinations of two or more selected from these, and may be any type of metal that includes a type of metal element suitable for application to electronic devices such as a metal electrode and metal interconnection.

[0027] The substrate 10 and the diffusion barrier layer 20 may be in direct contact with each other to form a van der Waals bond due to van der Waals force (vdW). Specifically, the bond between the silicon lattice on the surface of the substrate 10 and the diffusion barrier layer 20 may be formed by a bond due to van der Waals force. The atoms of each layer may be crossed with each other and not mixed or penetrated, but each interface may be physically clearly separated, that is, a van der Waals gap may be formed between the substrate 10 and the diffusion barrier layer 20. In particular, in the manufacturing process of the diffusion barrier layer 20, a transfer process, more specifically, a wet transfer process may be applied to minimize physical damage to the surface and form a diffusion barrier layer 20 of a uniform thickness. By providing the diffusion barrier layer 20 formed by van der Waals bonding on the surface of the substrate 10, highly reactive dangling bonds on the surface of the substrate 10 can be removed and the inherent physical properties of the substrate 10 can be preserved, which can be advantageously applied to the realization of highly integrated devices.

[0028] The diffusion barrier layer 20 and the conductive layer 30 may also form a direct contact, but the interface between the two may ideally be one in which a van der Wals (vdW) bond can be formed, but in practice may include an intermixing region in the diffusion barrier layer 20 due to diffusion of metal atoms of the conductive layer 30 without the van der Wals (vdW) bond being formed.

[0029] The diffusion barrier layer 20 can control the movement / diffusion of materials (atoms) in the substrate 10 and the conductive layer 30, thereby controlling the injection of electrons. In the conventional metal-semiconductor interface forming direct contact, metal atoms may diffuse or penetrate into silicon crystals by a conventional deposition method for forming a metal electrode, resulting in the formation of defects due to intermixing of different elements. However, the integrated structure according to the present invention can block the diffusion of metal atoms from the conductive layer 30 into the lattice of the substrate 10 (e.g., in the direction of metal → Si) by providing the diffusion barrier layer 20. Therefore, the diffusion of metal atoms into the silicon substrate crystal to form intermixing bonds and the formation of silicide, which is a compound of silicon and metal, can be suppressed, thereby reducing the density of interface defects, and the injection of electrons in the reverse direction (e.g., in the direction of Si → metal) from the substrate 10 to the conductive layer 30 can be blocked. As a result, the contact resistance at the interface between the substrate 10 and the conductive layer 30 is reduced, the trap density is reduced, and the Schottky barrier height is reduced. Therefore, the leakage current of the electronic device is reduced through the diffusion barrier layer 20, the rectification characteristics are maximized, and a quasi-ideal interface is formed, thereby improving the electrical characteristics.

[0030] In addition, the hole injection from the conductive layer 30 to the substrate 10 can be controlled through the diffusion barrier layer 20. Specifically, the efficiency of hole injection from the metal of the conductive layer 30 to the substrate 10 (for example, metal → Si direction) can be improved through the diffusion barrier layer 20, and the ON / OFF ratio, which is the driving performance of the device, can be improved by more than 100 times. This is because the application of the diffusion barrier layer 20 suppresses the formation of a metal induced gap state due to the penetration of metal atoms into the silicon (Si) lattice, and the Fermi level can be freely controlled by voltage driving without the Fermi level pinning phenomenon at the metal / semiconductor interface. As a result, it can be explained that the efficiency of hole injection can be improved by fundamentally removing factors that hinder hole injection due to such causes.

[0031] In particular, the diffusion barrier layer 20 may be formed as a monolayer to enhance the efficiency of hole injection. If one or more layers are repeatedly stacked to form a multilayer of two or more layers, it is undesirable since the efficiency of hole injection may decrease. The thickness of the single-layer diffusion barrier layer 20 for enhancing the efficiency of hole injection may be shallow on the nano to sub-nano scale or less, and may be extremely thin at 1 nm or less, and may have a thin thickness and maintain excellent characteristics. The thickness of the diffusion barrier layer 20 may be 0.1 to 10 Å, specifically 0.3 to 9 Å, and more specifically 0.5 to 8 Å. In one embodiment, the thickness of the diffusion barrier layer 20 may be 7 Å, but is not limited thereto. Such a diffusion barrier layer 20 may be advantageously applied to the realization of a highly integrated device having a fine line width.

[0032] The diffusion barrier layer 20 is about 10 -2 Ω cm or less, specifically about 10 -4 ~10 -2The diffusion barrier layer 20 may have a low resistivity value of Ω·cm. Since the diffusion barrier layer 20 has a low resistivity, it may have excellent electrical conductivity at a level similar to that of a metal or semimetal. However, if the diffusion barrier layer 20 is extremely thin, for example, 1 nm or less, it may have a resistivity value at a semiconductor level.

[0033] The diffusion barrier layer 20 may be a semiconductor material and may include a transition metal dichalcogenide (TMD) material. The transition metal dichalcogenide material has various advantages, such as having a two-dimensional crystal structure, excellent diffusion prevention properties, and being able to be formed with a very thin thickness. The transition metal dichalcogenide (TMD) may be a material having n-type or p-type semiconductor properties without doping, and in particular, the transition metal dichalcogenide (TMD) may be a material having p-type semiconductor properties. In order to enhance the doping properties, an atom substitution process in a chalcogen atomic layer may be further performed.

[0034] The transition metal dichalcogenide (TMD) layer having p-type semiconductor characteristics can suppress silicon dioxide (SiO2), an insulator formed by chemically bonding silicon dangling bonds on the surface of the silicon substrate 10 with oxygen atoms in the air, by contacting the p-type silicon substrate 10, and can suppress the metal atoms of the conductive layer 30 from diffusing directly into the silicon lattice and the formation of silicide during the deposition process of the conductive layer 30, thereby essentially preventing the problem of heterogeneity of the silicon substrate. This prevents the formation of a metal induced gap state in the silicon band structure, thereby suppressing the Fermi level pinning phenomenon.

[0035] The transition metal dichalcogenide material is represented by the general formula MX2, where M is a transition metal element, for example, Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, Ru, Co, Pd, Pt, Cu, Ga, In, Sn, Ge, Pb, or a combination of two or more selected therefrom, and X is a chalcogen element, for example, S, Se, Te, or a combination of two or more selected therefrom. Specifically, the transition metal dichalcogenide material may include MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, ZrS2, ZrSe2, HfS2, HfSe2, NbSe2, ReSe2, PdTe2, or a combination of two or more selected therefrom. More specifically, the transition metal dichalcogenide material may include MoS2, MoSe2, WS2, WSe2, or a combination of two or more selected therefrom, and in one embodiment may include WSe2, but is not limited thereto.

[0036] The crystal structure of the transition metal dichalcogenide material has a hexagonal structure in the planar direction based on a covalent bond between the transition metal M and the chalcogen element X. The crystal structure may be changed by a further phase change step or doping step.

[0037] In addition, when the diffusion barrier layer 20 is made of the transition metal dichalcogenide material, there are no dangling bonds extending outside the layer, so that the inherent physical properties of the substrate 10 can be preserved when formed on the substrate 10, making it advantageously applicable to the realization of highly integrated devices.

[0038] FIG. 2 shows the results of a transmission electron microscope (TEM) photograph of a cross section of a metal-semiconductor interface in an integrated structure according to one embodiment of the present invention, as well as the results of element mapping and EDS analysis of the cross section.

[0039] Referring to FIG. 2, in an integrated structure in which a metal (Ni) electrode is in direct contact with a substrate without a WSe2 diffusion barrier layer, metal atoms diffuse or penetrate into the silicon crystal, resulting in the simultaneous presence of metal element (Ni) and oxygen (O) elements in the interfacial layer with the substrate, forming an intermixing region due to the mixing of different elements.

[0040] FIG. 3 is a schematic diagram showing a cross-section of a metal-diffusion barrier layer-semiconductor interface for an integrated structure according to one embodiment of the present invention, showing a transmission electron microscope (TEM) image of the cross-section of the metal-diffusion barrier layer-semiconductor interface and an EDS elemental mapping result for the cross-section.

[0041] Referring to FIG. 3, it can be seen that in the integrated structure in which a Si / WSe2 interface is formed with a WSe2 diffusion barrier layer and a metal (Ag) is laminated, no intermixing region is formed because the metal atoms cannot diffuse or penetrate into the silicon crystal.

[0042] The present invention will be described in more detail below with reference to examples and comparative examples. However, the following examples and comparative examples are for illustrative purposes only and are not intended to limit the scope of the present invention.

[0043] Example 1: WSe 2 Thin film synthesis method To synthesize tungsten diselenide (WSe2), a chemical vapor deposition (CVD) system with two heating zones was used. First, silicon dioxide (SiO2) was used as a substrate, and a quartz boat loaded with 480 mg of selenium (Se, 99.5%, Sigma-Aldrich) powder was placed in the left heating zone, and a quartz boat loaded with a mixture of 40 mg of NaCl (99%, Sigma-Aldrich) and 240 mg of tungsten oxide (WOx, 99.9%, Sigma-Aldrich) powder was placed in the right heating zone. Then, with the distance between the two quartz boats set to 40 cm, the temperature of each heating zone was set to 870°C in the left zone and 640°C in the right zone, and WSe2 was grown for 10 minutes. At this time, the flow rate of Ar / H2 gas as a carrier gas was 100 / 20sccm, and the process pressure in the synthesis step was optimized to 1 to 100 Torr.

[0044] Example 2: Wet transfer method to fabricate Si / WSe 2 Interface formation A PMMA (Poly(methyl methacrylate)) polymer solution was coated on the WSe2 thin film grown on the silicon dioxide (SiO2) substrate manufactured by the method of Manufacturing Example 1. After PMMA coating, the manufactured PMMA / WSe2 / SiO2 was immersed in a 3 wt% KOH solution to separate the PMMA / WSe2 layer from the SiO2 substrate. Meanwhile, a silicon (Si) substrate patterned by an exposure process was manufactured. The peeled PMMA / WSe2 layer was transferred onto a p-type silicon (Si) substrate patterned by an exposure process, and the PMMA and photosensitive solution (PR) were removed using acetone. Thus, a WSe2 thin film provided on a silicon (Si) substrate was manufactured by a wet transfer method, and a Si / WSe2 interface with van der Waals (vdW) bonds was prepared.

[0045] Example: Si / WSe bonded by van der Waals forces (vdW) 2 Schottky diodes and transistors including interfaces A Schottky diode and a silicon (Si) channel transistor were fabricated using the Si / WSe2 interface fabricated by the method of Fabrication Example 2. After performing an exposure process for patterning a metal electrode on a substrate including the Si / WSe2 interface, a metal electrode was deposited using an e-beam evaporator. At this time, the metals used for the metal electrode were Ti, Ni, Cr / Au, and Ag. Then, a Schottky diode was fabricated by forming a metal electrode using a lift-off method in which the patterned photoresist solution obtained in the exposure process was removed using acetone.

[0046] Meanwhile, the Si channel transistor was fabricated in a back-gating structure using an SOI (Silicon On Insulator) wafer. The Si / WSe2 interface fabricated by the method of Fabrication Example 2 was formed on a Si channel with a channel length of 10 μm and width of 2 μm, and a Ni electrode was deposited thereon by an electron beam evaporation method to bond the WSe2 layer directly under the Ni electrode. Here, the WSe2 / Ni interface can ideally be formed by van der Wals (vdW) bonding, but depending on issues such as the actual process, the van der Wals (vdW) bonding cannot be formed and the surface of the WSe2 layer may be damaged, and an intermixing region may be included due to the diffusion of Ni atoms into the WSe2 layer. After patterning the channel by an exposure process, the surface of the SOI wafer was lightly oxidized by a dry oxidation method using plasma, and then a metal (Ni) electrode was formed by the same method as the lift-off method described above.

[0047] Comparative example: Si / WSe 2 Fabrication of interface-free Schottky diodes and transistors A Schottky diode and a silicon (Si) channel transistor were manufactured using the same method as in the Example, except that the Si / WSe2 interface manufactured by the method of Preparation Example 2 was not included.

[0048] Test example: VanderWales (vdW) bonded Si / WSe 2 Measurements of Schottky diodes and transistors, including interfaces [Schottky barrier] To analyze the effect of reducing metal / semiconductor interface defects by forming a WSe2 interface at the metal / semiconductor interface, electrical characteristics of Schottky diodes were analyzed. Specifically, the I-V rectification characteristics, Schottky barrier height (SBH), and interface trap density (D it ) was calculated to verify the effect of inserting the WSe2 interface layer. The I-V rectification characteristics were obtained by applying a voltage (V) of -2V to 2V to obtain the current (I). The current of a Schottky diode can generally be determined by the following Equation 1.

[0049] [Number 1] I = I0 [exp(qV / ηkT)-1]...(1)

[0050] In the above formula 1, q is the charge amount, V is the applied voltage, η is the ideality factor, k is the Boltzmann constant, and T is the temperature. Furthermore, I0 (saturation current) is as shown in the following formula 2.

[0051] [Number 2] I0=AA * T 2 exp(-qφ0 / kT)...(2)

[0052] In the above formula 2, A is the diode area, A *is Richardson's constant, T is temperature, q is charge, k is Boltzmann's constant, and φ0 is Schottky barrier height (SBH). From this, it can be seen that the variables that make up the saturation current (I0) are temperature (T) and Schottky barrier height (φ0). Using this, the saturation current was measured at seven temperature points at 10°C intervals from room temperature (RT, 25°C) to 75°C to calculate the Schottky barrier height. In fact, the current flow of a Schottky diode is predominantly determined by the current flowing due to the low SBH, so it can be corrected and calculated through the Barrier Height Inhomogeneities (BHI) model that corrects the Schottky barrier height.

[0053] [Charge trap density D it ] Charge traps are mainly generated by interface defects, so changes in interface defects can be indirectly inferred through changes in trap density. Furthermore, because interface traps capture and release charges, changes in trap density were quantitatively calculated by measuring CV (Capacitance-Voltage) and GV (Conductance-Voltage). CV and GV measurements were performed by fixing the frequency in 100kHz increments from 100kHz to 1MHz and applying AC voltages from -2V to 2V to obtain changes in capacitance and conductance. Trap density D it can be quantitatively expressed by the following Equation 3.

[0054] [Number 3] D it =(2.5 / Aq)(G / ω) peak ...(3)

[0055] In the above formula 3, A is the diode area, q is the charge, G is the conductance, and ω is each frequency.

[0056] FIG. 4 shows (a) and (c) energy diagrams and CV graphs of a metal-semiconductor interface, and (b) and (d) energy diagrams and CV graphs of a metal-diffusion barrier layer-semiconductor interface for an integrated structure according to one embodiment of the present invention.

[0057] 4(a) and 4(c), in the metal-semiconductor interface that forms a direct contact, metal atoms may diffuse or penetrate into the silicon crystal by a general deposition method for forming a metal electrode, resulting in the formation of intermixing defects of different elements. Due to such intermixing defects, the intrinsic physical properties of the silicon (Si) substrate are deformed, forming a metal-induced gap state (MIGS) in the silicon (Si) band gap, which may cause a problem of Fermi level pinning during electrostatic drive through the gate. As a result, the contact resistance of the metal-semiconductor interface increases, the output current decreases, and the drive voltage of a device having the same increases, which may increase the stress of the interface and lead to degradation of the device.

[0058] On the other hand, as shown in Fig. 4(b) and Fig. 4(d), the effect of inserting a diffusion barrier layer (WSe2) between the substrate and the metal is a reduction in the Schottky barrier height and the interface trap density D it The decrease in trap density D after WSe2 insertion was confirmed. it It was confirmed that the defect density decreased by more than 10 times. In addition, the density was also decreased in various metals that can be used as electrodes, such as Ni, Ti, Au / Cr, and Ag, similar to the above results.

[0059] FIG. 5 is a schematic diagram of an electronic device (Si p-MOS) having an integrated structure according to an embodiment of the present invention, (a) an IV graph with and without a diffusion barrier layer, (b) an On / Off ratio, and (d) statistical results for maximum mobility, for an integrated structure according to an embodiment of the present invention.

[0060] As shown in FIG. 5, this is a Si device in which electrodes are formed as a WSe2 and metal stack structure on a SOI (silicon on insulator) substrate. When a drain voltage is applied, it can be seen that hole charges injected through the metal / WSe2 electrode are transmitted through the silicon channel to operate.

[0061] Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art will recognize that the present invention may be embodied in other specific forms without departing from the technical spirit or gist of the present invention. Therefore, the above-described embodiments are illustrative in all respects and are not limiting. [Explanation of symbols]

[0062] 100 Integrated Structure 10 Substrate 20 Diffusion Barrier Layer 30 Conductive layer

Claims

1. A p-type silicon or p-type SOI (Silicon-on-insulator) substrate, a conductive layer spaced apart from the substrate and including a metal or a metal compound; a diffusion barrier layer disposed between the substrate and the conductive layer and including a p-type semiconducting material; Including, the substrate and the diffusion barrier layer are in direct contact and form van der Waals bonds; The diffusion barrier layer blocks the injection of electrons from the substrate into the conductive layer and blocks the injection of holes from the conductive layer into the substrate. An integrated structure comprising:

2. The diffusion barrier layer is a monolayer. The integrated structure of claim 1 .

3. The thickness of the diffusion barrier layer is 0.1 to 10 Å. The integrated structure of claim 1 .

4. The diffusion barrier layer comprises a transition metal dichalcogenide material. The integrated structure of claim 1 .

5. The transition metal dichalcogenide material has the general formula MX ２ It is expressed as The M is a transition metal element, and includes Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, Ru, Co, Pd, Pt, Cu, Ga, In, Sn, Ge, Pb, or a combination of two or more selected from among these; The X is a chalcogen element, and includes S, Se, Te, or a combination of two or more selected therefrom. The integrated structure of claim 4 .

6. The transition metal dichalcogenide material is MoS ２ , MoSe ２ , MoTe ２ , W.S. ２ , WSe ２ , W.T.e ２ , ZrS ２ , ZrSe ２ , HfS ２ , HfSe ２ , NbSe ２ ,ReSe ２ , PdTe ２ or a combination of two or more selected from these. The integrated structure of claim 4 .

7. The crystal structure of the transition metal dichalcogenide material is a hexagonal structure in the planar direction. The integrated structure of claim 4 .

8. The metals include Ti, Ni, Cr / Au, Ag, and combinations of two or more selected therefrom. The integrated structure of claim 1 .

9. A semiconductor device comprising an integrated structure according to any one of claims 1 to 8. An electronic device characterized by:

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