POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING POWER SEMICONDUCTOR DEVICE

Abstract

To shift a trade-off characteristic between on-voltage and switching loss to a high-speed side regardless of a carrier lifetime control method in a power semiconductor device, and to achieve low off-loss and high temperature operation.SOLUTION: In an RFC diode 1001, a semiconductor substrate 20 includes an n- drift layer 7, an n buffer layer 8, and a diffusion layer provided between and in contact with the n buffer layer 8 and a second metal layer 11. The diffusion layer includes an n+ cathode layer 90 provided in contact with the n buffer layer 8 and the second metal layer 11 in a diode region. 31. The n+ cathode layer 90 includes a first n+ cathode layer 91 in contact with the second metal layer 11 and a second n+ cathode layer 92 provided between the first n+ cathode layer 91 and the n buffer layer 8 in contact with the n buffer layer 8. Crystal defect density of the first n+ cathode layer 91 is higher than crystal defect density of another diffusion layer.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to power semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a power diode having two n-buffer layers. Of the two n-buffer layers, a low carrier lifetime control layer is provided in the n-buffer layer that contacts the high-concentration n+ layer on the cathode side. This suppresses the tail current during the recovery operation of the power diode, i.e., reverse recovery switching operation, and as a result, the recovery loss is reduced. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-201644 A Summary of the Invention [Problem to be solved by the invention]

[0004] The power diode of Patent Document 1 is basically composed of two n-buffer layers with different carrier lifetimes. Therefore, the power diode of Patent Document 1 can shift the trade-off characteristic between the on-voltage and switching loss, which are performance indicators of power semiconductor devices, to the high-speed side without using a carrier lifetime control method. Here, the carrier lifetime control method is, for example, control using a charged particle system such as an electron beam, protons, or helium, or a heavy metal system such as platinum.

[0005] However, there was a problem in that the voltage holding ability when a reverse bias was applied to the main junction, which is the effect of the n-buffer layer, deteriorated, and the voltage blocking ability, which is a basic performance of power semiconductors, namely, reducing off-loss by reducing leakage current when holding voltage, deteriorated.

[0006] Furthermore, there is a problem in that the increase in leakage current when a voltage is held makes it difficult to realize high temperature operation, which is a trend in power semiconductor devices.

[0007] The present disclosure has been made to solve the above problems, and aims to shift the trade-off characteristics between on-voltage and switching loss to the higher speed side in a power semiconductor device without relying on a carrier lifetime control method, and to achieve low off-loss and high temperature operation. [Means for solving the problem]

[0008] The power semiconductor device of the present disclosure includes a semiconductor substrate having a first main surface and a second main surface opposed to each other, a first metal layer provided on the first main surface of the semiconductor substrate, and a second metal layer provided on the second main surface of the semiconductor substrate. The semiconductor substrate includes a drift layer of a first conductivity type, a buffer layer of the first conductivity type provided between the drift layer and the second main surface, and a diffusion layer provided between the buffer layer and the second metal layer in contact with both of them, a part of the region in a plan view is a diode region that operates as a diode, and the diffusion layer includes a cathode layer of the first conductivity type provided in contact with the buffer layer and the second metal layer in at least a part of the diode region, the cathode layer of the first conductivity type includes a first cathode layer having one impurity concentration peak point and in contact with the second metal layer, and a second cathode layer having one impurity concentration peak point and provided between the first cathode layer and the buffer layer in contact with the buffer layer, and the first cathode layer Complex defects consisting of SiCs and interstitial Si pairs in The crystal defect density is 、 Higher crystal defect density than other diffusion layers The crystal defects are detected by a photoluminescence method and include a first lattice defect, which is a complex defect C i C s , and a second lattice defect, which is an interstitial Si pair. The photon energy of the first lattice defect is 0.969 eV, and the photon energy of the second lattice defect is 1.018 eV. . Effect of the Invention

[0009] In the power semiconductor device of the present disclosure, the crystal defect density of the first cathode layer is higher than that of the other diffusion layers, and therefore it is possible to shift the trade-off characteristic between the on-voltage and switching loss to the high-speed side without relying on a carrier lifetime control technique, and to achieve low off-loss and high-temperature operation. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a plan view of a power semiconductor device. [Diagram 2] FIG. 2 is a cross-sectional view of a conventional RFC diode taken along line A1-A1′ in FIG. [Diagram 3] 2 is a cross-sectional view of the RFC diode according to the first embodiment taken along the line A1-A1' in FIG. [Figure 4] 4 is a diagram showing the impurity concentrations of the diffusion layers in the RFC diode 1001 taken along lines BB' and CC' in FIG. [Diagram 5] FIG. 1 is a diagram showing PL spectra in the cathode structures of the conventional RFC diode and the RFC diode according to the first embodiment. [Figure 6] FIG. 1 is a diagram showing the trade-off characteristics between on-voltage and switching loss for the conventional RFC diode and the RFC diode according to the first embodiment. [Figure 7] 4 is a diagram showing the output characteristics of the RFC diode according to the first embodiment, with the relationship between the doses of the second n+ cathode layer and the second p cathode layer as a parameter. FIG. [Figure 8] FIG. 1 is a diagram showing output characteristics of a conventional RFC diode and an RFC diode according to the first embodiment. [Figure 9] FIG. 11 is a diagram showing the operation temperature dependence of on-voltage for the conventional RFC diode and the RFC diode according to the first embodiment. [Figure 10] FIG. 1 is a diagram showing leakage characteristics when a reverse bias is applied to a main junction for a conventional RFC diode and an RFC diode according to the first embodiment. [Figure 11] FIG. 11 is a diagram showing waveforms during recovery operation in a small current mode for the conventional RFC diode and the RFC diode according to the first embodiment. [Figure 12] FIG. 1 is a diagram showing the relationship between the snap-off voltage and the power supply voltage during recovery operation for the conventional RFC diode and the RFC diode according to the first embodiment. [Figure 13] FIG. 11 is a diagram showing a change in on-voltage during a continuous current test for the conventional RFC diode and the RFC diode according to the first embodiment. [Figure 14] 2 is a cross-sectional view of the RFC diode of the second embodiment taken along the line A1-A1' in FIG. [Figure 15] 15 is a diagram showing impurity concentrations in a diffusion layer of the RFC diode according to the second embodiment taken along lines BB' and CC' in FIG. 14. [Figure 16] FIG. 11 is a diagram showing the relationship between the snap-off voltage and the power supply voltage during recovery operation in a small current mode for the RFC diodes of the first and second embodiments. [Figure 17] 1. FIG. 4 is a cross-sectional view of an RFC diode according to a third embodiment taken along line A1-A1′ in FIG. [Figure 18] 18 is a diagram showing impurity concentrations in a diffusion layer of the RFC diode according to the third embodiment taken along lines BB' and CC' in FIG. 17. [Figure 19] FIG. 13 is a diagram showing PL spectra in the first n buffer layer and the second n buffer layer of the RFC diode according to the third embodiment. [Figure 20] FIG. 13 is a graph showing the relationship between the PL intensity and the annealing temperature in traps B and C in the second n buffer layer. [Figure 21] FIG. 13 is a diagram showing the trade-off characteristics between the on-voltage and the switching loss for the conventional RFC diode and the RFC diode according to the third embodiment. [Figure 22] 1A to 1C are cross-sectional views showing a manufacturing method of an RFC diode according to a first embodiment. [Figure 23] 1A to 1C are cross-sectional views showing a manufacturing method of an RFC diode according to a first embodiment. [Figure 24] 1A to 1C are cross-sectional views showing a manufacturing method of an RFC diode according to a first embodiment. [Diagram 25]1A to 1C are cross-sectional views showing a manufacturing method of an RFC diode according to a first embodiment. [Figure 26] 1A to 1C are cross-sectional views showing a manufacturing method of an RFC diode according to a first embodiment. [Figure 27] 1A to 1C are cross-sectional views showing a manufacturing method of an RFC diode according to a first embodiment. [Figure 28] 1A to 1C are cross-sectional views showing a manufacturing method of an RFC diode according to a first embodiment. [Figure 29] 1A to 1C are cross-sectional views showing a manufacturing method of an RFC diode according to a first embodiment. [Diagram 30] 1A to 1C are cross-sectional views showing a manufacturing method of an RFC diode according to a first embodiment. [Diagram 31] 4 is a flowchart showing steps subsequent to the formation of a surface protection film in the method for manufacturing the RFC diode according to the first embodiment. [Diagram 32] 13 is a flowchart showing steps subsequent to the formation of a surface protection film in a manufacturing method for an RFC diode according to the third embodiment. [Diagram 33] FIG. 2 is a cross-sectional view of a conventional pin diode taken along line A1-A1′ in FIG. [Diagram 34] 1. FIG. 1 is a cross-sectional view of the pin diode of the sixth embodiment taken along the line A1-A1′ in FIG. [Diagram 35] 1. FIG. 2 is a cross-sectional view of a pin diode according to a modified example of the sixth embodiment, taken along the line A1-A1′ in FIG. [Diagram 36] FIG. 13 is a diagram showing the trade-off characteristics between on-voltage and switching loss for a conventional pin diode and the pin diodes according to the sixth embodiment and its modifications. [Figure 37] 13 is a flowchart showing processes subsequent to the step of forming a surface protective film in a method for manufacturing a pin diode according to a sixth embodiment. [Figure 38] 2 is a cross-sectional view of the RC-IGBT according to the seventh embodiment taken along the line AA' in FIG. [Figure 39] 2 is a cross-sectional view of an RC-IGBT according to a first modification of the seventh embodiment taken along the line AA' in FIG. [Diagram 40] 2 is a cross-sectional view taken along line AA' in FIG. 1 of an RC-IGBT according to a second modification of the seventh embodiment. [Diagram 41] 20 is a cross-sectional view of the RC-IGBT according to the eighth embodiment taken along the line AA' in FIG. [Diagram 42] 2 is a cross-sectional view of an RC-IGBT according to a first modification of the eighth embodiment taken along the line AA' in FIG. [Diagram 43] 2 is a cross-sectional view taken along line AA' in FIG. 1 of an RC-IGBT according to a second modification of the eighth embodiment. [Diagram 44] 20 is a cross-sectional view of the RC-IGBT according to the ninth embodiment taken along the line AA' in FIG. [Diagram 45] 2 is a cross-sectional view taken along line AA' in FIG. 1 of an RC-IGBT according to a first modified example of the ninth embodiment. [Figure 46] 2 is a cross-sectional view taken along line AA' in FIG. 1 of an RC-IGBT according to a second modified example of the ninth embodiment. [Figure 47] 21 is a cross-sectional view of the RC-IGBT according to the tenth embodiment taken along the line AA' in FIG. [Figure 48] 21 is a cross-sectional view of an RC-IGBT according to a first modification of the tenth embodiment taken along the line AA' in FIG. [Figure 49] 21 is a cross-sectional view taken along line AA' in FIG. 1 of an RC-IGBT according to a second modification of the tenth embodiment. [Figure 50] 21 is a cross-sectional view of the IGBT according to the eleventh embodiment taken along the line AA' in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the embodiments will be described with reference to the accompanying drawings. Note that the drawings are shown in schematic form, and the size and positional relationship of images shown in different drawings are not necessarily described accurately and may be changed as appropriate. In addition, in the following description, similar components are illustrated with the same reference numerals, and their names and functions are also the same. Therefore, detailed description thereof may be omitted.

[0012] In the following description, terms such as "upper", "lower", "side", "bottom", "front", or "back" may be used to denote specific positions and directions. However, these terms are used for convenience to facilitate understanding of the content of the embodiments and do not limit the directions during actual implementation.

[0013] In the following description, regarding the conductivity type of the semiconductor, the first conductivity type is defined as the n-type and the second conductivity type is defined as the p-type, but the reverse may also be true.

[0014] Regarding the conductivity type of the semiconductor, n- indicates that the n-type impurity concentration is lower than that of n, and n+ indicates that the n-type impurity concentration is higher than that of n. Similarly, p- indicates that the p-type impurity concentration is lower than that of p, and p+ indicates that the p-type impurity concentration is higher than that of p.

[0015] <A. Embodiment 1> <A-1. Configuration> FIG. 1 schematically shows a planar structure of a vertical power semiconductor device. As shown in the figure, a plurality of active cell regions R1 are formed in the central portion, a surface gate wiring portion R12 is provided between two active cell regions R1, and a gate pad portion R11 is provided in a part of the region.

[0016] An intermediate region R2 is formed surrounding the peripheries of the active cell region R1, the gate pad portion R11, and the surface gate wiring portion R12, and a termination region R3 is provided further surrounding the periphery of the intermediate region R2.

[0017] The above-mentioned active cell region R1 is an element formation region that guarantees the basic performance of the power semiconductor device. The peripheral region consisting of the intermediate region R2 and the terminal region R3 is provided for maintaining the breakdown voltage including reliability. Among them, the intermediate region R2 is a region where the active cell region R1 and the terminal region R3 are joined, and is a region that guarantees the breakdown resistance during dynamic operation of the power semiconductor and supports the original performance of the semiconductor element in the active cell region R1. The terminal region R3 maintains the breakdown voltage in a static state, guarantees the stability and reliability of the breakdown voltage characteristics, and suppresses defects in the breakdown resistance during dynamic operation, thereby supporting the original performance of the active cell region R1.

[0018] However, when the power semiconductor device is a diode, the front gate wiring portion R12 and the gate pad portion R11 may be omitted.

[0019] 2 and 3 show a cross-sectional configuration of an RFC (Relaxed Field of Cathode) diode, which is an example of a power semiconductor device, taken along line A1-A1' in FIG. 1. FIG. 2 is a cross-sectional view of a conventional RFC diode 1000, and FIG. 3 is a cross-sectional view of an RFC diode 1001 according to the first embodiment. In the figures, the conventional RFC diode 1000 may be referred to as a Con. RFC diode, and the RFC diode 1001 according to the first embodiment may be referred to as a New RFC diode 1.

[0020] First, a conventional RFC diode 1000 will be described. The RFC diode 1000 is configured to include a semiconductor substrate 20, a first metal layer 5, and a second metal layer 11. The semiconductor substrate 20 includes a first main surface 21 which is the upper main surface in FIGS. 2 and 3, and a second main surface 22 opposite to the first main surface 21. The first metal layer 5 is provided on the first main surface 21 of the semiconductor substrate 20, and the second metal layer 11 is provided on the second main surface 22 of the semiconductor substrate 20.

[0021] The semiconductor substrate 20 is composed of a p anode layer 6, an n- drift layer 7, an n buffer layer 8, an n+ cathode layer 9, and a p cathode layer 10. The p anode layer 6 is provided between the n- drift layer 7 and a first main surface 21. The surface of the p anode layer 6 constitutes the first main surface 21 of the semiconductor substrate 20. An n buffer layer 8 is provided between the n- drift layer 7 and a second main surface 22. The n+ cathode layer 9 and the p cathode layer 10 are provided between the n buffer layer 8 and the second main surface 22. The surfaces of the n+ cathode layer 9 and the p cathode layer 10 constitute the second main surface 22 of the semiconductor substrate 20, and are in contact with the second metal layer 11.

[0022] A pin diode region 31 is formed by a vertical region including the n+ cathode layer 9, i.e., the n+ cathode layer 9 and the n buffer layer 8, n- drift layer 7, and p anode layer 6 thereover. A pnp transistor region 32 is formed by a vertical region including the p cathode layer 10, i.e., the p cathode layer 10 and the n buffer layer 8, n- drift layer 7, and p anode layer 6 thereover. In this way, the RFC diode 1000 has a configuration in which the pin diode regions 31 and the pnp transistor regions 32 are alternately arranged in a plan view.

[0023] The n-drift layer 7 has an impurity concentration C n- is 1.0×10 12 atoms / cm 3 Above 1.0×10 15 atoms / cm 3 The semiconductor substrate 20 is formed using a Si wafer as follows. That is, the semiconductor substrate 20 is a Si substrate. The thickness of the semiconductor substrate 20 is a device thickness t device is 40 μm or more and 700 μm or less.

[0024] The p anode layer 6 has an impurity concentration of 1.0×10 16 atoms / cm 3 and the peak impurity concentration is 2.0×10 16 atoms / cm 3 Above 1.0×10 18 atoms / cm 3or less, and the depth is 2.0 μm or more and 10.0 μm or less.

[0025] The n-buffer layer 8 has a peak impurity concentration C nb,p is 1.0×10 15 atoms / cm 3 Above 5.0×10 16 atoms / cm 3 is less than or equal to depth X j,nb is 1.2 μm or more and 50 μm or less.

[0026] Next, an RFC diode 1001 according to the first embodiment will be described. The RFC diode 1001 is different from the conventional RFC diode 1000 in that it includes an n+ cathode layer 90 instead of the n+ cathode layer 9 and a p cathode layer 100 instead of the p cathode layer 10. In the RFC diode 1001, the n+ cathode layer 90 has a two-layer structure including a first n+ cathode layer 91 and a second n+ cathode layer 92, and the p cathode layer 100 has a two-layer structure including a first p cathode layer 101 and a second p cathode layer 102. The first p cathode layer 101 is also referred to as a first diffusion layer, and the second p cathode layer 102 is also referred to as a second diffusion layer.

[0027] Hereinafter, the first n+ cathode layer 91 may be referred to as the first cathode layer, and its conductivity type may be denoted as n+1 in the drawings. The second n+ cathode layer 92 may be referred to as the second cathode layer, and its conductivity type may be denoted as n+2 in the drawings. The conductivity type of the first p cathode layer 101 may be denoted as p1. The conductivity type of the second p cathode layer 102 may be denoted as p2.

[0028] The first n+ cathode layer 91 and the first p cathode layer 101 are in contact with the second metal layer 11. The second n+ cathode layer 92 and the second p cathode layer 102 are in contact with the n buffer layer 8. The lower surfaces of the first n+ cathode layer 91 and the first p cathode layer 101 in FIG. 3 constitute the second main surface 22 of the semiconductor substrate 20.

[0029] The first n+ cathode layer 91 has an impurity concentration of 1.0×10 18 atoms / cm 3 Above 1.0×10 20 atoms / cm 3 and the depth is 0.1 μm or more and 0.2 μm or less.

[0030] The second n+ cathode layer 92 has a peak impurity concentration of 1.0×10 17 atoms / cm 3 Above 1.0×10 19 atoms / cm 3 and the depth is 0.3 μm or more and 0.5 μm or less.

[0031] The first p-type cathode layer 101 has an impurity concentration of 1.0×10 17 atoms / cm 3 Above 1.0×10 19 atoms / cm 3 and the depth is 0.1 μm or more and 0.2 μm or less.

[0032] The second p-type cathode layer 102 has a peak impurity concentration of 1.0×10 16 atoms / cm 3 Above 1.0×10 18 atoms / cm 3 and the depth is 0.3 μm or more and 0.5 μm or less.

[0033] In this embodiment, n+ cathode layer 90 is composed of two layers, a first n+ cathode layer 91 and a second n+ cathode layer 92, and p cathode layer 100 is composed of two layers, a first p cathode layer 101 and a second p cathode layer 102. The purpose of each layer is as follows.

[0034] The first n+ cathode layer 91 and the first p cathode layer 101 are diffusion layers for improving the contact with the second metal layer 11. The crystal defect density of the first n+ cathode layer 91 is higher than that of the second n+ cathode layer 92, the first p cathode layers 101, 102, and the n buffer layer 8. The second n+ cathode layer 92 and the second p cathode layer 102 are diffusion layers for controlling the performance of the RFC diode 1001 and ensuring normal on-operation.

[0035] The impurity profile and depth of the diffusion layer can be determined by the range (RP) during ion implantation, based on the characteristics of the annealing technique during diffusion layer formation. Here, the range is defined as the depth from the second main surface 22 to the position of the peak concentration of each diffusion layer. Therefore, the ranges during ion implantation when forming the first n+ cathode layer 91, the second n+ cathode layer 92, the first p cathode layer 101, and the second p cathode layer 102 are determined by the following formula (1) so that the layers do not interfere with each other.

[0036] R n+2 / R n+1 =5.0, R P2 / R P1 =5.0…(1) Here, R n+1 , R n+2 , R p1 , R p2 represents the ranges (m) of the first n+ cathode layer 91, the second n+ cathode layer 92, the first p cathode layer 101, and the second p cathode layer 102, respectively.

[0037] Figure 4 shows the impurity concentration in the diffusion layer of the RFC diode 1001 along the B-B' line and C-C' line of Figure 3. The horizontal axis of Figure 4 shows the depth (μm) from the second main surface 22 of the semiconductor substrate 20, and the vertical axis shows the impurity concentration (atoms / cm 3 ). In Figure 4, the solid line shows the impurity concentration at the B-B' line, and the dashed line shows the impurity concentration at the C-C' line.

[0038] <A-2. Performance> The performance of the RFC diode 1001 according to the first embodiment will be described below. FIG. 5 shows PL spectra when the n+ cathode layer 9 and the p-cathode layer 10 in the conventional RFC diode 1000 and the first n+ cathode layer 91, the second n+ cathode layer 92, the first p-cathode layer 101, and the second p-cathode layer 102 in the RFC diode 1001 according to the first embodiment are analyzed by a photoluminescence (PL) method. The PL method is an analytical method in which a semiconductor is irradiated with light and light emitted when electrons and holes recombine via a defect level is observed. The horizontal axis of FIG. 5 indicates photon energy (eV), and the vertical axis of FIG. 5 indicates PL intensity normalized by the intensity at the band edge.

[0039] The analysis conditions for the PL method are as follows: A He-Ne laser with a wavelength of 633 nm is used. The temperature is 30 K. The output of the laser light irradiated on the sample surface is 4.5 mW. The diameter of the laser light is 1.3 μm. The intensity of the laser light on the sample surface is 0.339 MW / cm. 2 It is.

[0040] It can be seen from FIG. 5 that there are two peaks in the PL intensity in the first n+ cathode layer 91. The first peak is due to trap A with photon energy of 0.969 eV, and the second peak is due to trap B with photon energy: 1.018 eV. Traps A and B are energy levels derived from CiCs (G-center) and W-center, respectively. Trap A is also referred to as the first lattice defect, and trap B is also referred to as the second lattice defect.

[0041] Thus, two traps exist in the first n+ cathode layer 91. The second n+ cathode layer 92 is formed by a process described in a fourth embodiment, which will be described later. Traps A and B, which are crystal defects in the first n+ cathode layer 91, are formed by reaction with impurities in Si, such as oxygen, carbon, or hydrogen, through the following steps.

[0042] Step A: Ion implantation is performed on the second main surface 22 of the semiconductor substrate 20 to form vacancies (V) and interstitial Si pairs (I si ) and other lattice defects are formed.

[0043] Step B: The lattice defects formed in step A diffuse and self-aggregate, and V2 and interstitial Si pairs (I si :W-center) is formed.

[0044] Step C: Carbon atoms (C s ) and interstitial Si pairs (I si ) occurs, forming interstitial carbon (C i ).

[0045] Step D: Interstitial carbon (C i ) and lattice defects (vacancies (V)) diffuse to form lattice site substitution carbon (C s ) and interstitial Si pairs (I si ) reacts with impurities (oxygen, carbon, hydrogen) in silicon at room temperature, forming impurity defects (complex defects: C i C s ) is generated.

[0046] Step E: The annealing process restores the crystallinity, but some interstitial Si pairs (I si :W-center) and impurity defects (complex defects:C i C s ) remains.

[0047] Here, the subscript i stands for interstitial, and the subscript s stands for substitutional.

[0048] As described above, crystal defects exist in the first n+ cathode layer 91. These crystal defects improve the diode performance of the RFC diode 1001 and provide thermally stable performance, as will be shown below by the performance of a 1200V class diode.

[0049] FIG. 6 shows the on-voltage V F and switching loss E REC The figure shows the trade-off characteristics between the dose of the first n+ cathode layer 91 and the dose of the second n+ cathode layer 92. In the trade-off characteristics of the RFC diode 1001, the relationship between the dose of the first n+ cathode layer 91 and the dose of the second n+ cathode layer 92 is shown as a parameter. The trade-off characteristics of the RFC diode 1000 are the result of lifetime control using an electron beam, which is a charged particle. In the figure, Con. RFC diode 1 is an RFC diode 1000 without lifetime control using electron beam irradiation. Both Con. RFC diode 2 and Con. RFC diode 3 are RFC diodes 1000 that have undergone lifetime control using electron beam irradiation, but Con. RFC diode 3 has a greater dose of electron beam irradiation than Con. RFC diode 2.

[0050] In the RFC diode 1001, each layer is formed by the process described in embodiment 4 so that the relationship in the dose of the first n+ cathode layer 91 and the second n+ cathode layer 92 satisfies the following formula (2). This improves the contact between the first n+ cathode layer 91 and the second metal layer 11, and achieves stable electron injection from the first n+ cathode layers 91, 92 when the RFC diode 1001 is turned on.

[0051] D n+1 ≧0.3×D n+2 (2) Here, D n+1 is the number of atoms per unit area of ​​the first n+ cathode layer 91 (atoms / cm 2 ), and D n+2 is the number of atoms per unit area of ​​the second n+ cathode layer 92 (atoms / cm 2 ) represents the number of atoms per unit area (atoms / cm 2 ) is the number of atoms per unit volume (atoms / cm 3 ) in the diffusion layer region in the depth direction. 3) is an analytical value obtained by Secondary Ion Mass Spectrometry (SIMS).

[0052] Furthermore, in order for the RFC diode 1001 to perform a normal on-operation, the first n+ cathode layer 91 and the second p cathode layer 102 must satisfy the following formula (3) regarding the dose. The trade-off characteristics of the RFC diode 1001 shown in FIG. 6 are the result of a cathode structure that satisfies formula (3). As described above, the RFC diode 1001 can achieve the high-speed side of the curve of the trade-off characteristics that the conventional RFC diode 1000 achieved by lifetime control using an electron beam, without relying on lifetime control.

[0053] FIG. 7 shows the output characteristics of the RFC diode 1001 at 298K. In the RFC diode 1001, due to the relationship between the characteristic cathode structure shown in FIG. 3 and the process flow shown in the fourth embodiment, it is necessary to invert the first p cathode layer 101 and the second p cathode layer 102 to n layers to form the first n+ cathode layer 91 and the second n+ cathode layer 92. Therefore, in order for the RFC diode 1001 to perform a normal on-operation, the first n+ cathode layer 91 and the second p cathode layer 102 must satisfy the following equation (3) for the dose. This ensures a normal on-operation without causing a snap-back characteristic, as shown in FIG. 7.

[0054] D n+2 ≧2.0×D p2 (3) Here, D n+2 is the number of atoms per unit area of ​​the second n+ cathode layer 92 (atoms / cm 2 ), and D p2 is the number of atoms per unit area of ​​the second p-type cathode layer 102 (atoms / cm 2 )

[0055] Next, the diode performance of the RFC diode 1001 that satisfies the formulas (2) and (3) will be described.

[0056] Fig. 8 shows the output characteristics of a conventional RFC diode 1000 and an RFC diode 1001 according to embodiment 1. In Fig. 8 and the following figures, the RFC diode 1000 without lifetime control by electron beam is denoted as Con. RFC diode 1, and the RFC diode 1000 with lifetime control by electron beam is denoted as Con. RFC diode 2 or Con. RFC diode 3.

[0057] It can be seen from FIG. 8 that the RFC diode 1001 has a lower current density at the cross-point where the output characteristics at 298 K and the output characteristics at 423 K cross, compared to the conventional RFC diode 1000.

[0058] FIG. 9 shows the ON-state voltage V F The RFC diode 1001 has a lower on-voltage V F The operation temperature dependency of is positive. The conventional RFC diode 1000 without lifetime control by electron beam is denoted as Con. RFC diode 1 in FIG. 9. In the conventional RFC diode 1000 without lifetime control by electron beam, the on-voltage V F The operation temperature dependence of is negative. As shown in Con. RFC diode 3, when the lifetime control is performed on the conventional RFC diode 1000 by electron beam, the on-voltage V F The operation temperature dependence of changes, but the behavior is determined by the temperature dependence of the impurity defects generated by the electron beam. Here, the main impurity defects generated by the electron beam are complex defects C i O i or C-center with photon energy of 0.789 eV.

[0059] Power semiconductor devices such as RFC diodes are ultimately mounted on power modules and incorporated into inverter systems, so parallel operation must be guaranteed. In order to minimize the temperature difference between chips during on-state operation when multiple chips are operated in parallel, the cross-point current density must be low and the on-state voltage V F It is desirable that the operation temperature dependence of is positive. F If the operating temperature dependency of is negative, it is easy to induce a phenomenon of destruction due to current concentration in a specific chip. However, as in the RFC diode 1001, the on-voltage V F If the operation temperature dependency of is positive, destruction due to current concentration in a specific chip is suppressed, and normal parallel operation can be guaranteed. In other words, the characteristics of the RFC diode 1001 shown in Figures 8 and 9 are effective in terms of normal operation of the power module.

[0060] 10 shows the leakage characteristics when a reverse bias is applied to the main junction of a conventional RFC diode 1000 and an RFC diode 1001 according to the first embodiment. In FIG. 10, the horizontal axis represents the reverse voltage V R (V), and the vertical axis represents the leakage current density J R (A / cm 2 ) is shown.

[0061] In the conventional RFC diode 1000, lifetime control is performed by electron beams in order to control the performance toward the high-speed side of the trade-off curve in FIG. 6. In this case, impurity defects (complex defects) are formed inside the device by the electron beams, and the leakage current caused by these defects increases. As a result, the loss (off loss: J R ×V R ) increases, causing problems in the thermal design of the power module and problems with high-temperature operation.

[0062] On the other hand, the RFC diode 1001 according to the first embodiment has a first n+ cathode layer 91 with a high crystal defect density in order to control the performance toward the high-speed side of the trade-off curve, but impurity defects (complex defects) caused by the electron beam are not present in the n- drift layer 7 and the n buffer layer 8, where the depletion layer extends from the main junction to hold the voltage when a reverse bias is applied to the main junction. Therefore, as shown in FIG. 10, the leakage current of the RFC diode 1001 is equivalent to the leakage current of the conventional RFC diode 1000 in which lifetime control by the electron beam is not performed. That is, the RFC diode 1001 according to the first embodiment has a smaller leakage current than the conventional RFC diode 1000 while realizing high-speed operation, and is effective in terms of high-temperature operation and thermal stability.

[0063] FIG. 11 shows waveforms during recovery operation in the small current mode of the conventional RFC diode 1000 and the RFC diode 1001 according to the first embodiment.

[0064] FIG. 12 shows the snap-off voltage V snap-off and the power supply voltage V CC Snap-off voltage V snap-off is the anode-cathode voltage during recovery operation V AK The maximum value of the diode recovery action is the snap-off voltage V snap-off is small and the snap-off voltage V snap-off Power supply voltage V CC The less sensitive the dependence, the better the diode's breakdown resistance. Furthermore, the snap-off voltage V snap-off By setting the voltage to below the rated withstand voltage, the snap-off voltage V snap-off This makes it possible to control the voltage drop, thereby suppressing the breakdown of the diode caused by the voltage rising instantaneously above the rated voltage during recovery operation. In this embodiment, the RFC diode 1001 has a rating of 1200V.

[0065] This performance is evident in samples without lifetime control by electron beams, and therefore the conventional RFC diode 1000 compared in Figures 11 and 12 does not have lifetime control by electron beams. These figures show that the RFC diode 1001 is superior to the conventional RFC diode 1000 in terms of breakdown resistance.

[0066] FIG. 13 shows the ON-state voltage V during a continuous current test for the conventional RFC diode 1000 and the RFC diode 1001 according to the first embodiment. F In the conventional RFC diode 1000 (Con. RFC diode 3), in which lifetime control was performed by electron beam, impurity defects (complex defects) generated by the electron beam are repaired by self-heating during current flow in the diode, so the on-state voltage V F On the other hand, in the RFC diode 1001 according to the first embodiment, lifetime control is not performed using an electron beam, and traps A and B, which are crystal defects in the first n+ cathode layer 91, are thermally stable traps that do not change due to self-heating during current flow in the diode. Therefore, the on-state voltage V F does not degrade and the diode performance does not change over time.

[0067] As described above, the RFC diode 1001 according to the first embodiment utilizes the traps A and B, which are crystal defects in the first n+ cathode layer 91, to reduce the on-state voltage V F and switching loss E REC The trade-off characteristics of the above are controlled to the high-speed side without relying on the conventional lifetime control method, and low off-loss, improved breakdown resistance, and thermal stability are achieved.

[0068] The above-mentioned performance of the RFC diode 1001 can be realized not only when a Si wafer manufactured by the FZ (Floating Zone) method is used for the semiconductor substrate 20, but also when a Si wafer manufactured by the MCZ (Magnetic applied Czochralski) method, which has higher oxygen and carbon concentrations in the Si material, is used. The Si wafer manufactured by the MCZ method has an oxygen concentration of 1.0×1017 atoms / cm 3 7.0×10 or more 17 atoms / cm 3 and is below a certain level, and the carbon concentration is 1.0×10 14 atoms / cm 3 5.0×10 or more 15 atoms / cm 3 and is below a certain level. This is because the main crystal defect that controls the diode performance in the RFC diode 1001 is not an impurity defect, but an interstitial Si pair that is not formed by the reaction with residual oxygen and residual carbon in Si.

[0069] <A-3. Effect> The RFC diode 1001, which is a power semiconductor device according to Embodiment 1, includes a semiconductor substrate 20 having first and second main surfaces 21 and 22 facing each other, a first metal layer 5 provided on the first main surface 21 of the semiconductor substrate 20, and a second metal layer 11 provided on the second main surface 22 of the semiconductor substrate 20. The semiconductor substrate 20 includes an n-drift layer 7 that is a drift layer of the first conductivity type, an n-buffer layer 8 provided between the n-drift layer 7 and the second main surface 22, and a diffusion layer provided in contact with both between the n-buffer layer 8 and the second metal layer 11. In the RFC diode 1001, a part of the region in plan view is a pin diode region 31 that operates as a diode. In the RFC diode 1001, the diffusion layer includes an n+ cathode layer 90 provided in contact with the n-buffer layer 8 and the second metal layer 11 in at least a part of the pin diode region 31. The n+ cathode layer 90 includes a first n+ cathode layer 91 that has one impurity concentration peak point and is in contact with the second metal layer 11, and a second n+ cathode layer 92 that has one impurity concentration peak point and is provided in contact with the n-buffer layer 8 between the first n+ cathode layer 91 and the n-buffer layer 8. The crystal defect density of the first n+ cathode layer 91 is higher than that of other diffusion layers. Therefore, according to the RFC diode 1001, the on-voltage V F and the switching loss E RECControl the trade-off characteristics to the high-speed side without using the conventional lifetime control method, and achieve low turn-off loss, improved breakdown tolerance, and thermal stability.

[0070] <B. Embodiment 2> <B-1. Configuration> FIG. 14 shows a cross-sectional configuration of the RFC diode 1002 according to Embodiment 2 along the line A1-A1' of FIG. 1. In the following figures, the RFC diode 1002 according to Embodiment 2 may be denoted as New RFC diode 2. The RFC diode 1002 has a structure in which the first p cathode layer 101 is removed from the RFC diode 1001 according to Embodiment 1. In other words, in the RFC diode 1002, the p cathode layer 100 is the second p cathode layer 102. The structure of the RFC diode 1002 not particularly mentioned below is the same as that of the RFC diode 1001 according to Embodiment 1.

[0071] The n-drift layer 7 in the RFC diode 1002 has an impurity concentration C n- of 1.0×10 12 atoms / cm 3 or more and 1.0×10 15 atoms / cm 3 or less and is formed using the following Si wafer.

[0072] FIG. 15 shows the impurity concentration in the diffusion layer of the RFC diode 1002 along the lines B-B' and C-C' of FIG. 14. The horizontal axis in FIG. 15 indicates the depth (μm) from the second main surface 22 of the semiconductor substrate 20, and the vertical axis indicates the impurity concentration (atoms / cm 3 ). In FIG. 15, the solid line indicates the impurity concentration along the line B-B', and the broken line indicates the impurity concentration along the line C-C'.

[0073] The parameters of each diffusion layer constituting the RFC diode 1002 are as follows.

[0074] The p anode layer 6, the n buffer layer 8, the first n+ cathode layer 91, and the second n+ cathode layer 92 are the same as those in Embodiment 1.

[0075] The impurity concentration on the surface of the second p cathode layer 102 that contacts the second metal layer 11, i.e., the second main surface 22, is 1.0×10 17 atoms / cm 3 or more and 1.0×10 19 atoms / cm 3 or less, and the depth is 0.3 μm or more and 0.5 μm or less.

[0076] The relationship between the doping amounts of the first n+ cathode layer 91 and the second n+ cathode layer 92 satisfies Equation (2).

[0077] <B-2. Performance> FIG. 16 shows V during the recovery operation in the small current mode of the RFC diode 1001 according to Embodiment 1 and the RFC diode 1002 of Embodiment 2. snap-off and the power supply voltage V CC and shows the relationship therebetween.

[0078] It can be seen from FIG. 16 that, similar to the RFC diode 1001 according to Embodiment 1, the performance of the breakdown tolerance surface is also ensured in the RFC diode 1002.

[0079] Further, since the RFC diode 1002 has the same n+ cathode layer 90 as the RFC diode 1001 according to Embodiment 1, similar to the RFC diode 1001, the trade-off characteristics between the on-voltage V F and the switching loss E REC are controlled to the high-speed side without depending on the conventional lifetime control method, and low off-loss and thermal stability are realized.

[0080] <B-3. Effect> In the RFC diode 1002 according to Embodiment 2, the p cathode layer 100 is the second p cathode layer 102. That is, in the RFC diode 1002, the p cathode layer 100, which is a diffusion layer of the second conductivity type, has one impurity concentration peak point. Even with such a configuration, the RFC diode 1002 has a characteristic first n+ cathode layer 91, so that the on-voltage VF and switching loss E REC The trade-off characteristics of are controlled to the high-speed side without using the conventional lifetime control method, and low turn-off loss, improved breakdown tolerance, and thermal stability are realized.

[0081] <C. Embodiment 3> <C-1. Configuration> FIG. 17 shows a cross-sectional configuration of the RFC diode 1003 according to Embodiment 3 along the line A1-A1' in FIG. 1. In the following figures, the RFC diode 1003 according to Embodiment 3 may be denoted as New RFC diode 3. The RFC diode 1003 differs from the RFC diode 1001 according to Embodiment 1 in that it includes an n-buffer layer 80 instead of the n-buffer layer 8. The n-buffer layer 80 has a two-layer structure including a first n-buffer layer 81 and a second n-buffer layer 82. The structure of the RFC diode 1003 not particularly mentioned below is the same as that of the RFC diode 1001 according to Embodiment 1.

[0082] In the RFC diode 1003, the n-drift layer 7 has an impurity concentration C n- of 1.0×10 12 atoms / cm 3 or more and 1.0×10 15 atoms / cm 3 or less, and is formed using a Si wafer.

[0083] FIG. 18 shows the impurity concentration in the diffusion layer of the RFC diode 1003 along the lines B-B' and C-C' in FIG. 17. The horizontal axis in FIG. 18 indicates the depth (μm) from the second main surface 22 of the semiconductor substrate 20, and the vertical axis indicates the impurity concentration (atoms / cm 3 ). In FIG. 18, the solid line indicates the impurity concentration along the line B-B', and the broken line indicates the impurity concentration along the line C-C'.

[0084] The p-anode layer 6 is the same as in Embodiment 1.

[0085] The first n-buffer layer 81 has a peak impurity concentration C nb1,pis 1.0×10 15 or more and 5.0×10 16 atoms / cm 3 or less, and the depth X j,nb1 is 1.2 μm or more and 50 μm or less.

[0086] The 2n-th buffer layer 82 has a depth X j,nb2 equal to X j,nb1 +20 μm. Also, the peak impurity concentration C nb2,p of the 2n-th buffer layer 82 is 0.01 times or less of the peak impurity concentration C nb1,p of the 1n-th buffer layer 81. Thereby, the generation of the snap-back characteristic in the on-state as shown in FIG. 7 is suppressed, and the normal on-operation of the diode is guaranteed.

[0087] <C-2. Performance> FIG. 19 shows the PL spectrum when the 1n-th buffer layer 81 and the 2n-th buffer layer 82 of the RFC diode 1003 are analyzed by the PL method. The horizontal axis in FIG. 19 indicates the photon energy (eV), and the vertical axis in FIG. 19 indicates the PL intensity normalized by the intensity at the band edge.

[0088] The analysis conditions of the PL method in FIG. 19 are the same as those of the PL method in FIG. 5. From FIG. 19, it can be seen that there are two peaks in the PL intensity in the 2n-th buffer layer 82. The first peak is due to the trap B with a photon energy of 1.018 eV, and the second peak is due to the trap C with a photon energy of 1.039 eV. The trap B and the trap C are energy levels derived from the W-center and the X-center, which are Si pairs between the lattices, respectively.

[0089] FIG. 20 shows the relationship between the PL intensity at the traps B and C in the 2n-th buffer layer 82 and the annealing temperature. The annealing is performed for 120 minutes in a nitrogen atmosphere. The technology of the present embodiment is based on controlling the device performance of the power diode by the trap B. From FIG. 20, it can be seen that the annealing temperature for the trap B to become the main trap in the 2n-th buffer layer is 370° C. or less.

[0090] FIG. 21 shows the trade-off characteristics between the on-voltage V F and the switching loss E REC for each of the conventional RFC diode 1000 and the RFC diode 1003 according to Embodiment 3. The breakdown voltage of the RFC diode whose characteristics are shown in FIG. 21 is 4.5 kV.

[0091] The peak impurity concentration C nb2,p of the second n-buffer layer 82 is such that C nb1,p is less than or equal to 0.01 × C nb2,p with respect to the peak impurity concentration C nb1,p of the first n-buffer layer 81. By controlling the conditions during ion implantation when forming the second n-buffer layer 82 so as to satisfy this, it is possible to realize the high-speed side of the trade-off characteristic curve that the conventional RFC diode 1000 achieved by lifetime control by electron beam without adversely affecting other device performances of the diode.

[0092] In addition, since the RFC diode 1003 according to Embodiment 3 controls the power diode performance by utilizing the Si pairs between the lattices without lifetime control, similar to Embodiment 1, it realizes low off-loss, improved breakdown tolerance, and thermal stability.

[0093] <C-3. Effect> In the RFC diode 1003 according to Embodiment 3, the n-buffer layer 80 includes a first n-buffer layer 81 which is a first buffer layer having one impurity concentration peak point and in contact with the diffusion layer, and a second n-buffer layer 82 which is a second buffer layer having one impurity concentration peak point and in contact with the n-drift layer 7. And the crystal defects in the second n-buffer layer 82 are trap B which is the second lattice defect detected by the photoluminescence method and trap C which is the third lattice defect. Therefore, according to the RFC diode 1003, the trade-off characteristic between the on-voltage V F and the switching loss E REC is controlled to the high-speed side without relying on the conventional lifetime control method, and low off-loss, improved breakdown tolerance, and thermal stability are realized.

[0094] <D. Embodiment 4> <D-1. Manufacturing Method> In this embodiment, a manufacturing method of the RFC diode 1001 according to Embodiment 1 will be described. FIGS. 22 to 30 are cross-sectional views showing the manufacturing method of the RFC diode 1001. FIGS. 29 and 30 show a detailed process flow for forming the back surface side structure of the RFC diode 1001.

[0095] The features of the manufacturing method of the RFC diode 1001 are as follows. First, after ion implantation for forming the first p cathode layer 101 and the second p cathode layer 102, there are ion implantation and annealing for forming the first n+ cathode layer 91 and the second n+ cathode layer 92. Also, there is no lifetime control process. Further, the second metal layer 11 is for a two-layer diffusion layer structure.

[0096] Hereinafter, the manufacturing method of the RFC diode 1001 will be described along FIGS. 22 to 30. FIG. 22 shows an active cell region R1, and an intermediate region R2 and a termination region R3 formed so as to surround the active cell region R1. First, a semiconductor substrate 20 in which only the n-drift layer 7 is formed is prepared. Then, a plurality of p layers 52 are selectively formed on the surface of the n-drift layer 7 in the intermediate region R2 and the termination region R3. The p layer 52 is formed by ion implantation using a pre-formed oxide film 62 as a mask, and then annealing treatment is performed on the semiconductor substrate 20. Note that an oxide film 68 formed during the formation of the oxide film 62 is also formed on the second main surface 22 of the semiconductor substrate 20.

[0097] Next, as shown in FIG. 23, ion implantation and annealing treatment are performed on the surface of the n-drift layer 7 in the active cell region R1 to form a p anode layer 6.

[0098] 24, an n+ layer 56 is formed at the end of the termination region R3 on the first main surface 21 side of the semiconductor substrate 20. Next, a TEOS layer 63 is formed on the upper surface of the semiconductor base. Thereafter, a process is performed to remove the oxide film 68 and expose the second main surface 22 of the semiconductor substrate 20. Then, a doped polysilicon layer 65 doped with an impurity is formed so as to contact the n- drift layer 7 exposed on the second main surface 22 of the semiconductor substrate 20. The impurity of the doped polysilicon layer 65 is an atom capable of diffusing into Si to form an n+ layer, such as phosphorus, arsenic, or antimony. The doped polysilicon layer 65 has a doping density of 1×10 19 atoms / cm 3 The film is doped with the above-mentioned high concentration impurities and has a thickness of 500 nm or more. At this time, a doped polysilicon layer 64 is also formed on the first main surface 21 of the semiconductor substrate 20.

[0099] Next, the semiconductor substrate 20 is thermally annealed at 900°C to 1000°C in a nitrogen atmosphere. Furthermore, the heating temperature is lowered at an arbitrary rate from 600°C to 700°C in the nitrogen atmosphere, and low-temperature thermal annealing is performed, so that the impurities in the doped polysilicon layer 65 are diffused toward the second main surface 22 of the n-drift layer 7, as shown in FIG. 25, and a gettering layer 55 having crystal defects and impurities is formed on the second main surface 22 of the n-drift layer 7. Then, an annealing step is performed to capture the metal impurities, contaminant atoms, and damage in the n-drift layer 7 by the gettering layer 55. As a result, the carrier lifetime of the n-drift layer 7 that has decreased during the wafer process up to that point is restored, and the τ defined by the formula (4) is reduced. t The above values ​​are achieved. This process can be used for IGBTs or RC (Reverese Conductivity)-IGBTs in addition to RFC diodes.

[0100] τ t =1.5×10 -5 exp(5.4×10 3 t N- ) · · · (4) Here, t N- represents the thickness (m) of the n-drift layer 7. trepresents the carrier lifetime (sec) in the n-drift layer 7 at which the effect of the carrier lifetime on the on-voltage disappears.

[0101] The on-voltage of the RFC diode 1001 depends on the carrier lifetime of the n-drift layer 7. Equation (4) expresses the carrier lifetime τ t (s). The carrier lifetime τ t If this could be achieved, the effect of the carrier lifetime on switching loss could be minimized, which would be effective in reducing off-state loss and suppressing thermal runaway.

[0102] Thereafter, as shown in FIG. 26, the doped polysilicon layer 64 formed on the first main surface 21 side of the semiconductor substrate 20 is selectively removed using a liquid of hydrofluoric acid or mixed acid (for example, a mixed liquid of hydrofluoric acid / nitric acid / acetic acid).

[0103] 27, contact holes are formed in the first main surface 21 of the semiconductor substrate 20 to expose the p layer 52, the p anode layer 6, and the n+ layer 56. That is, the TEOS layer 63 is processed as shown in FIG. 27. Then, the aluminum wiring 5A containing Si at about 1% to 3% is formed by sputtering. The aluminum wiring 5A corresponds to the first metal layer 5 in FIG. 3.

[0104] Subsequently, as shown in FIG. 28, passivation films 46 and 47 are formed on the first main surface 21 side of the semiconductor substrate 20.

[0105] 29, a surface protective film 23 is formed on the first main surface 21 side of the semiconductor substrate 20. Then, the gettering layer 55 and the doped polysilicon layer 65 formed on the second main surface 22 of the semiconductor substrate 20 are removed by polishing or etching. This removal process makes the thickness tD of the semiconductor substrate 20 correspond to the withstand voltage class of the semiconductor device.

[0106] 30, an n buffer layer 8 is formed on the lower surface side of the n- drift layer 7. Thereafter, a first p cathode layer 101 and a second p cathode layer 102 are formed on the lower surface of the n buffer layer 8. Subsequently, in the active cell region R1, the conductivity types of a portion of the first p cathode layer 101 and the second p cathode layer 102 are inverted to form a first n+ cathode layer 91 and a second n+ cathode layer 92. The n buffer layer 8, the first p cathode layer 101, the second p cathode layer 102, the first n+ cathode layer 91 and the second n+ cathode layer 92 are diffusion layers formed by ion implantation and annealing treatment.

[0107] During the formation of the diffusion layer, aluminum wiring 5A and passivation films 46, 47 are present on the first main surface 21 side of semiconductor substrate 20. Therefore, annealing for forming the diffusion layer is performed using a laser with a wavelength that does not transfer heat to the first main surface 21 side, and has a temperature gradient in the device depth direction so that the temperature on the first main surface 21 side of semiconductor substrate 20 is lower than the melting point of aluminum, 660° C., used for aluminum wiring 5A.

[0108] FIG. 31 is a flow chart showing the manufacturing process in FIGS.

[0109] First, in step S101, a surface protective film 23 is formed on the first main surface 21 side of the semiconductor substrate 20. Next, in steps S102 and S103, the gettering layer 55 and the doped polysilicon layer 65 formed on the second main surface 22 of the semiconductor substrate 20 are removed by polishing and etching. This removal process reduces the thickness t D corresponds to the withstand voltage class of the semiconductor device.

[0110] Next, in step S104, ion implantation is performed to form n buffer layer 8. This ion implantation is also referred to as first ion implantation. Next, in step S105, annealing is performed to activate the ions implanted in step S104. The annealing in step S105 is also referred to as first annealing.

[0111] Then, in step S106, ion implantation is performed to form the second p-cathode layer 102. This ion implantation is also referred to as second ion implantation.

[0112] Next, in step S107, ion implantation is performed to form the first p cathode layer 101. This ion implantation is also referred to as the third ion implantation. The acceleration energies in the second ion implantation and the third ion implantation are determined so that the projected range satisfies formula (1). As a result, the first p cathode layer 101 and the second p cathode layer 102 are formed so as not to interfere with each other.

[0113] Next, in step S108, a mask is formed for forming the first n+ cathode layer 91 and the second n+ cathode layer 92 partially in the active cell region R1 by a photolithography process.

[0114] Then, in step S109, ion implantation is performed to form the second n+ cathode layer 92. This ion implantation is also referred to as fourth ion implantation.

[0115] Next, in step S110, ion implantation is performed to form the first n+ cathode layer 91. This ion implantation is also referred to as the fifth ion implantation. The acceleration energies in the fourth and fifth ion implantations are determined so that the projected range satisfies formula (1). As a result, the first n+ cathode layer 91 and the second n+ cathode layer 92 are formed without interfering with each other.

[0116] Next, in step S111, the resist for photolithography is removed.

[0117] Thereafter, in step S112, annealing is performed to activate the ions implanted in steps S106, S107, S109, and S110. By this annealing, the first p cathode layer 101, the second p cathode layer 102, the first n+ cathode layer 91, and the second n+ cathode layer 92 are formed. The annealing in step S112 is also referred to as the second annealing. The first annealing and the second annealing are performed by laser annealing or in a diffusion furnace at a low temperature below the melting point of the metal of the first metal layer 5. The feature of the annealing adopted here is to reproduce the impurity profile at the time of ion implantation even after activation after annealing.

[0118] Thereafter, in step S113, the surface protective film 23 is removed. Next, in step S114, the second main surface 22 is light-etched.

[0119] Thereafter, in step S115, the second metal layer 11 is formed on the second main surface 22 by sputtering. The second metal layer 11 is a laminated film composed of a plurality of metal films, for example, a laminated film of a metal in contact with Si, Ti, Ni, and Au. By using a monosilicide layer such as AlSi or NISi added with about 1% to 3% of Si as the metal layer in contact with Si, the effect of the cathode layer characteristic of the RFC diode 1001 is guaranteed.

[0120] Next, in step S116, annealing is performed at 350 °C to form an alloy layer or a silicide layer at the interface between the first p cathode layer 101 and the first n+ cathode layer 91 and the second metal layer 11. The annealing in step S116 is also referred to as the third annealing.

[0121] <D-2. Effect> According to the manufacturing method of the RFC diode 1001 described in Embodiment 4, a first metal layer 5 and a surface protective film 23 are formed on the first main surface 21 of the semiconductor substrate 20 having the n-drift layer 7. After the formation of the surface protective film 23, the thickness of the semiconductor substrate 20 is controlled to a desired thickness. After the thickness control of the semiconductor substrate 20, a first ion implantation and a first annealing for forming an n-buffer layer 8 are performed on the second main surface 22 of the semiconductor substrate 20. After the first annealing, a second ion implantation for forming a second p-cathode layer 102, which is a second diffusion layer of the second conductivity type, is performed on the second main surface 22 of the semiconductor substrate 20. After the second ion implantation, a third ion implantation for forming a first p-cathode layer 101, which is a first diffusion layer of the second conductivity type, is performed on the second main surface of the semiconductor substrate 20 at an acceleration energy smaller than that of the second ion implantation. After the third ion implantation, a fourth ion implantation for forming a second n+-cathode layer 92, which is a second cathode layer of the first conductivity type, is performed on the second main surface 22 of the semiconductor substrate 20. After the fourth ion implantation, a fifth ion implantation for forming a first n+-cathode layer 91, which is a first cathode layer of the first conductivity type, is performed on the second main surface 22 of the semiconductor substrate 20 at an acceleration energy smaller than that of the fourth ion implantation. After the fifth ion implantation, a second annealing for activating the ions implanted by the second, third, fourth, and fifth ion implantations is performed to form the second p-cathode layer 102, the first p-cathode layer 101, the second n+-cathode layer 92, and the first n+-cathode layer 91. After the second annealing, a second metal layer 11 is formed on the second main surface 22 of the semiconductor substrate 20. After the formation of the second metal layer 11, a third annealing is performed at 350°C in a nitrogen atmosphere. Thereby, the first p-cathode layer 101 and the second p-cathode layer 102 having different roles, and the first n+-cathode layer 91 and the second n+-cathode layer 92 can be formed so as to satisfy the relationships of formulas (1), (2), and (3), and the on-voltage V F and the switching loss E REC of the trade-off characteristics can be controlled to the high-speed side without depending on the conventional lifetime control method, and low off-loss, improved breakdown tolerance, and thermal stability can be realized.

[0122] <E. Embodiment 5> <E-1. Manufacturing Method> In the embodiment 5, a method for manufacturing the RFC diode 1003 according to the embodiment 3 will be described. Fig. 32 is a flow chart showing the process of the method for manufacturing the RFC diode 1003 after the step of forming the surface protective film 23.

[0123] Steps S101-103 in Fig. 32 are similar to those in Fig. 31. After step S103, in step S104A, ions are implanted to form the first n buffer layer 81. This ion implantation is also referred to as first ion implantation.

[0124] After step S104A, annealing is performed in step S105A to activate the ions implanted in step S104A. This annealing is also referred to as the first annealing. The first annealing forms the 1n buffer layer 81. The first annealing for forming the 1n buffer layer 81 needs to be performed at a higher temperature than the fourth annealing for forming the 2n buffer layer 82 described later.

[0125] After step S105A, in step S105B, ion implantation is performed to form the second n buffer layer 82. This ion implantation is also referred to as second ion implantation.

[0126] Steps S106-113 after step S105B are the same as those in Fig. 31. The ion implantation for forming the second p cathode layer 102 in step S106 is referred to as the third ion implantation. Moreover, the ion implantation for forming the first p cathode layer 101 in step S107 is referred to as the fourth ion implantation. Moreover, the ion implantation for forming the second n+ cathode layer 92 in step S109 is referred to as the fifth ion implantation. Moreover, the ion implantation for forming the first n+ cathode layer 91 in step S110 is referred to as the sixth ion implantation.

[0127] The second annealing in step S112 forms the 2n buffer layer 82, the 2p cathode layer 102, the 1p cathode layer 101, the 2n+ cathode layer 92, and the 1n+ cathode layer 91. In this process, the order in which the 1n buffer layer 81 and the 2n buffer layer 82 are formed is important. Also, in the ion implantation for forming the 2n buffer layer 82, the setting of the acceleration energy is important.

[0128] After step S113, a fourth annealing is performed in step S113A. According to Fig. 20, the annealing temperature in the fourth annealing step for making trap B the main trap is higher than the third annealing temperature and is equal to or lower than 370°C. By the fourth annealing, trap B, which is an interstitial Si pair, is controlled to become the main trap in the second n buffer layer 82.

[0129] Steps S114-116 after step S113A are the same as those in Fig. 31. In this way, the RFC diode 1003 according to the third embodiment is manufactured.

[0130] Phosphorus, arsenic, selenium, sulfur, or protons (H+) are used as the ion species for forming the first n-buffer layer 81. Protons or helium are used as the ion species for forming the second n-buffer layer 82. Protons or helium can be introduced into Si by irradiation technology using a cyclotron other than ion implantation.

[0131] When protons are used as the ion species for forming the first n-buffer layer 81, when the protons are introduced into Si, vacancies (v) generated during the introduction react with impurities in the Si, forming complex defects. These complex defects contain hydrogen and thus act as an electron supply source. The donor concentration increases due to an increase in the complex defect density caused by annealing, and the donor concentration increases due to a mechanism that promotes the thermal donor phenomenon caused by the ion implantation / irradiation process. As a result, a donor-converted n-layer with a higher impurity concentration than the n-drift layer 7 is formed as the first n-buffer layer 81, which contributes to the operation of the device.

[0132] On the other hand, among the composite defects formed when introducing protons into Si, there are also defects that become lifetime killers and reduce the carrier lifetime. When using protons as the ion species for forming the first n-buffer layer 81, considering the removal of the defects that become lifetime killers and the stability of the profile in the first n-buffer layer 81, the first annealing for forming the first n-buffer layer 81 needs to be performed at a higher temperature (375°C or higher and 425°C or lower, nitrogen atmosphere, 90 minutes or longer) than the fourth annealing for forming the second n-buffer layer 82.

[0133] <E-2. Effect> According to the manufacturing method of the RFC diode 1003 described in Embodiment 5, a first metal layer 5 and a surface protection film 23 are formed on the first main surface 21 of the semiconductor substrate 20 having the n-drift layer 7. After the formation of the surface protection film 23, the thickness of the semiconductor substrate 20 is controlled to a desired thickness. After the thickness control of the semiconductor substrate 20, a first ion implantation and a first annealing for forming a first n-buffer layer 81 are performed on the second main surface 22 of the semiconductor substrate 20. After the first annealing, a second ion implantation for forming a second n-buffer layer 82 is performed on the second main surface 22 of the semiconductor substrate 20. After the second ion implantation, a third ion implantation for forming a second p-cathode layer 102 is performed on the second main surface 22 of the semiconductor substrate 20. After the third ion implantation, a fourth ion implantation for forming a first p-cathode layer 101 is performed on the second main surface 22 of the semiconductor substrate 20 at an acceleration energy smaller than that of the third ion implantation. After the fourth ion implantation, a fifth ion implantation for forming a second n+-cathode layer 92 is performed on the second main surface 22 of the semiconductor substrate 20. After the fifth ion implantation, a sixth ion implantation for forming a first n+-cathode layer 91 is performed on the second main surface 22 of the semiconductor substrate 20 at an acceleration energy smaller than that of the fifth ion implantation. After the sixth ion implantation, a second annealing for activating the ions implanted by the second, third, fourth, fifth, and sixth ion implantations is performed to form the second n-buffer layer 82, the second p-cathode layer 102, the first p-cathode layer 101, the second n+-cathode layer 92, and the first n+-cathode layer 91. A third annealing is performed in a nitrogen atmosphere. After the third annealing, a second metal layer 11 is formed on the second main surface 22 of the semiconductor substrate 20. After the formation of the second metal layer 11, a fourth annealing is performed at 350°C in a nitrogen atmosphere. As a result, a first n-buffer layer 81 and a second n-buffer layer 82 in which the trap B of the Si pair between the lattices is the main trap component are formed, so that the on-voltage V F and the switching loss E REC of the trade-off characteristics are controlled to the high-speed side without depending on the conventional lifetime control method, and low off-loss, improved breakdown tolerance, and thermal stability are realized.

[0134] <F. Embodiment 6> <F-1. Configuration> Figures 33 and 34 show cross-sectional configurations of a pin diode, which is an example of a power semiconductor device, taken along line A1-A1' in Figure 1. Figure 33 is a cross-sectional view of a conventional pin diode 1010, and Figure 34 is a cross-sectional view of a pin diode 1011 according to embodiment 6. In the drawings, the conventional pin diode 1010 may be referred to as Con. pin diode, and the pin diode 1011 according to embodiment 6 may be referred to as New pin diode 1.

[0135] A conventional pin diode 1010 shown in Fig. 33 has the same configuration as the left half, including the pin diode region 31, of the conventional RFC diode 1000 shown in Fig. 2. A pin diode 1011 according to the sixth embodiment shown in Fig. 34 has the same configuration as the left half, including the pin diode region 31, of the RFC diode 1001 according to the first embodiment shown in Fig. 3. Parameters of each layer of the pin diodes 1010, 1011 not specifically mentioned below are the same as those in the RFC diodes 1000, 1001.

[0136] The n-drift layer 7 has an impurity concentration C n- is 1.0×10 12 atoms / cm 3 Above 1.0×10 15 atoms / cm 3 It is formed using the following Si wafer.

[0137] The p-anode layer 6, the n-buffer layer 8, the first n+cathode layer 91, and the second n+cathode layer 92 are the same as those in the first embodiment.

[0138] Fig. 35 is a cross-sectional view of a pin diode 1012 according to a modification of the sixth embodiment, taken along the line A1-A1' in Fig. 1. Compared to pin diode 1011, pin diode 1012 includes a third n+ cathode layer 93 instead of first n+ cathode layer 91. Third n+ cathode layer 93 contains traps A and B that can be detected by the PL method described in Fig. 5.

[0139] FIG. 36 shows the trade-off characteristics between the on-voltage V F and the switching loss E REC for the conventional pin diode 1010 and the pin diodes 1011 and 1012 according to Embodiment 6 and its modified examples. For the conventional pin diode 1010, trade-off characteristics controlled by an electron beam are shown.

[0140] From FIG. 36, it can be seen that the pin diodes 1011 and 1012 according to Embodiment 6 and its modified examples achieve the high-speed side of the trade-off characteristics similar to those of the conventional pin diode 1010 controlled by an electron beam. This is because the pin diodes 1011 and 1012 according to Embodiment 6 and its modified examples are provided with a first n+ cathode layer 91 or a third n+ cathode layer 93 having a trap B, similar to the RFC diode 1001 according to Embodiment 1.

[0141] <F-2. Manufacturing Method> Hereinafter, the manufacturing method of the pin diode 1011 will be described, showing the parts different from the manufacturing method of the RFC diode 1001 according to Embodiment 1. FIG. 37 is a flowchart showing the process after the formation step of the surface protection film 23 in the manufacturing method of the pin diode 1011. The flowchart of FIG. 37 is obtained by deleting steps S106 to S108 and step S111 regarding the formation of the first p cathode layer 101 and the second p cathode layer 102 and photolithography from the flowchart regarding the manufacturing method of the RFC diode 1001 shown in FIG. 31.

[0142] <F-3. Effects> Since the pin diode 1011 according to Embodiment 6 is provided with the first n+ cathode layer 91 and the second n+ cathode layer 92 similar to those of the RFC diode 1001 according to Embodiment 1, the trade-off characteristics between the on-voltage V F and the switching loss E REC are controlled to the high-speed side without relying on the conventional lifetime control method, and low off-loss, improved breakdown tolerance, and thermal stability are realized.

[0143] The pin diode 1012 according to the modification of Embodiment 6 also includes a third n+ cathode layer 93 having traps A and B similar to the second n+ cathode layer 92 instead of the second n+ cathode layer 92, and thus exhibits the same effects as the pin diode 1011.

[0144] Thus, even in the case of a pin diode, it is possible to suppress the influence of impurity defects due to the Si material.

[0145] <G. Embodiment 7> <G-1. Configuration> FIG. 38 is a cross-sectional view of an RC-IGBT 1021, which is a power semiconductor device according to Embodiment 7, taken along the line A-A' of FIG. 1. The RC-IGBT 1021 has the same cathode structure as the RC-IGBT 1001 according to Embodiment 1.

[0146] As shown in FIG. 38, the RC-IGBT 1021 includes a semiconductor substrate 20, a first metal layer 5, and a second metal layer 11. The semiconductor substrate 20 has a first main surface 21 and a second main surface 22 facing each other. The first metal layer 5 is formed on the first main surface 21 of the semiconductor substrate 20, and the second metal layer 11 is formed on the second main surface 22 of the semiconductor substrate 20.

[0147] Also, the RC-IGBT 1021 is divided into an IGBT region 33 that operates as an IGBT and a diode region 34 that operates as a diode in a plan view.

[0148] The semiconductor substrate 20 includes an n-drift layer 7, an n layer 26, a p-base layer 6A, an n+ emitter layer 24, and a p+ layer 25. The n layer 26 is formed on the first main surface 21 side of the n-drift layer 7. The p-base layer 6A is formed on the first main surface 21 side of the n layer 26. The n+ emitter layer 24 is formed on the first main surface 21 side of the p-base layer 6A in the IGBT region 33. The p+ layer 25 is formed on the first main surface 21 side of the p-base layer 6A in the diode region 34.

[0149] In the IGBT region 33, a trench 41 is formed penetrating from the first main surface 21 of the semiconductor substrate 20 through the n+ emitter layer 24, the p base layer 6A and the n layer 26. A gate electrode 43 is buried in the trench 41 with a gate insulating film 42 interposed therebetween. An interlayer insulating film 29 for insulating the gate electrode 43 from the first metal layer 5 is formed on the gate electrode 43.

[0150] In the diode region 34, a trench 44 is formed penetrating from the first main surface 21 of the semiconductor substrate 20 through the p+ layer 25, the p base layer 6A and the n layer 26. A dummy gate electrode 45 is buried in the trench 44 via a gate insulating film 42. Unlike the trench 41, the internal electrode of the trench 44 becomes the dummy gate electrode 45 because it is in contact with the emitter electrode 5 and has the same potential.

[0151] Furthermore, the semiconductor substrate 20 includes an n buffer layer 8, an n+ cathode layer 90, and a p collector layer 100 A. The n buffer layer 8 is formed on the second main surface 22 side of the n− drift layer 7.

[0152] The n+ cathode layer 90 is formed in the diode region 34, and has a two-layer structure consisting of a first n+ cathode layer 91 and a second n+ cathode layer 92. The second n+ cathode layer 92 is formed between the n buffer layer 8 and the second main surface 22, in contact with the n buffer layer 8. The first n+ cathode layer 91 is formed between the second n+ cathode layer 92 and the second metal layer 11, in contact with both of them. The lower surface of the first n+ cathode layer 91 constitutes the second main surface of the semiconductor substrate 20.

[0153] The p collector layer 100A is formed in the IGBT region 33, and has a two-layer structure consisting of a first p collector layer 101A and a second p collector layer 102A. The second p collector layer 102A is formed between the n buffer layer 8 and the second main surface 22, in contact with the n buffer layer 8. The first p collector layer 101A is formed between the second p collector layer 102A and the second metal layer 11, in contact with both of them. The lower surface of the first p collector layer 101A constitutes the second main surface of the semiconductor substrate 20.

[0154] Parameters of each layer of RC-IGBT 1021 that are not specifically mentioned below are the same as the parameters of the corresponding layers in embodiment 1. n-drift layer 7, n buffer layer 8, first n+cathode layer 91, and second n+cathode layer 92 are the same as those in embodiment 1.

[0155] The peak impurity concentration of the p-base layer 6A is 1.0×10 16 atoms / cm 3 Above 1.0×10 18 atoms / cm 3 The junction depth of the p-base layer 6A is made deeper than the n+ emitter layer 24 and shallower than the n layer 26.

[0156] The peak impurity concentration of the n-layer 26 is 1.0×10 15 atoms / cm 3 Above 1.0×10 17 atoms / cm 3 The junction depth of the n layer 26 is set to be about 0.5 μm or more and 1.0 μm or less deeper than the p base layer 6A.

[0157] The peak impurity concentration of the n+ emitter layer 24 is 1.0×10 18 atoms / cm 3 Above 1.0×10 21 atoms / cm 3 The junction depth of the n+ emitter layer 24 is set to be equal to or greater than 0.2 μm and equal to or less than 1.0 μm.

[0158] The impurity concentration at the surface of the p+ layer 25 in contact with the first metal layer 5, i.e., the first main surface 21, is 1.0×10 18 atoms / cm 3 Above 1.0×10 21 atoms / cm 3 The junction depth of the p+ layer 25 is set to be equal to or greater than the junction depth of the n+ emitter layer 24.

[0159] The depth of the trenches 41 and 44, i.e., trench depth D trench is made deeper than the n layer 26.

[0160] The surface of the first p collector layer 101A that contacts the second metal layer 11, i.e., the impurity concentration on the second main surface 22, is 1.0×10 17 atoms / cm 3 or more and 1.0×10 18 atoms / cm 3 or less, and the depth is 0.1 μm or more and 0.2 μm or less.

[0161] The second p collector layer 102A has a peak impurity concentration of 1.0×10 16 atoms / cm 3 or more and 1.0×10 20 atoms / cm 3 or less, and the depth is 0.3 μm or more and 0.5 μm or less.

[0162] Here, the first n+ cathode layer 91, the second n+ cathode layer 92, and the first p collector layer 101A and the second p collector layer 102A satisfy the relationships of formulas (1), (2), and (3). However, in formula (1), R p1 is read as the range (m) of the first p collector layer 101A, and R p2 is read as the range (m) of the second p collector layer 102A. Also, in formula (3), D p2 is read as the number of atoms per unit area (atoms / cm 2 ) of the second p collector layer 102A.

[0163] <G-2. Modified Example 1> FIG. 39 is a cross-sectional view taken along the line A-A' of FIG. 1 of an RC-IGBT 1022 which is a power semiconductor device according to Modified Example 1 of Embodiment 7. The RC-IGBT 1022 is different from the RC-IGBT 1021 of Embodiment 7 only in that a p cathode layer 100 is provided in a part of the diode region 34. That is, in the RC-IGBT 1022, the p cathode layer 100 which is a diffusion layer of the second conductivity type is provided in contact with the n buffer layer 8 and the second metal layer 11 also in a part of the diode region 34. In the RC-IGBT 1022, the p cathode layer 100 has a two-layer structure composed of a first p cathode layer 101 and a second p cathode layer 102.

[0164] The second p - cathode layer 102 is formed in contact with the n - buffer layer 8 between the n - buffer layer 8 and the second main surface 22. The first p - cathode layer 101 is formed in contact with both the second p - cathode layer 102 and the second metal layer 11 therebetween. The lower surface of the first p - cathode layer 101 constitutes the second main surface of the semiconductor substrate 20.

[0165] Parameters such as the impurity concentration and depth of the first p - cathode layer 101 and the second p - cathode layer 102 in the diode region 34 are the same as those of the first p - collector layer 101A and the second p - collector layer 102A in the IGBT region 33.

[0166] <G - 3. Modification Example 2> FIG. 40 is a cross - sectional view of an RC - IGBT 1023, which is a power semiconductor device according to Modification Example 2 of Embodiment 7, taken along line A - A' of FIG. 1. The RC - IGBT 1023 is different from the RC - IGBT 1022 according to Modification Example 1 of Embodiment 7 only in that in the IGBT region 33, the p - collector layer 100A is composed of one layer of the second p - collector layer 102A, and in the diode region 34, the p - cathode layer 100 is composed of one layer of the second p - cathode layer 102.

[0167] The impurity concentration of the second p - collector layer 102A and the second p - cathode layer 102 in the RC - IGBT 1023 is 1.0×10 17 atoms / cm 3 or more and 1.0×10 19 atoms / cm 3 or less on the second main surface 22, and the depth is 0.3 μm or more and 0.5 μm or less.

[0168] <G - 4. Effect> The RC-IGBTs 1021, 1022, and 1023 according to Embodiment 7 and its Modification Examples 1 and 2 are configured such that the collector structure in the IGBT region 33 and the cathode structure in the diode region 34 satisfy the relationships of formulas (1), (2), and (3) in the same manner as the manufacturing method of the RFC diode 1001 described in Embodiment 4. Therefore, also in the RC-IGBTs 1021, 1022, and 1023, the trade-off characteristics between the on-voltage V F and the switching loss E REC are controlled to the high-speed side without depending on the conventional lifetime control method, and low off-loss, improved breakdown tolerance, and thermal stability are realized.

[0169] <H. Embodiment 8> <H-1. Configuration> FIG. 41 is a cross-sectional view of an RC-IGBT 1024, which is a power semiconductor device according to Embodiment 8, taken along line A-A' of FIG. 1. The RC-IGBT 1024 differs from the RC-IGBT 1021 according to Embodiment 7 only in that the p+ layer 25 is not present in the diode region 34. That is, in the RC-IGBT 1024, the p-base layer 6A is in contact with the first metal layer 5 in the diode region 34.

[0170] Each diffusion layer and trench of the RC-IGBT 1024 are set to have the following parameters.

[0171] Regarding the p-base layer 6A in the IGBT region 33, the parameters are as follows. The peak impurity concentration is 1.0×10 16 atoms / cm 3 or more and 1.0×10 18 atoms / cm 3 or less. The junction depth is deeper than the n+ emitter layer 24 and shallower than the n layer 26.

[0172] Regarding the p-base layer 6A in the diode region 34, the parameters are as follows. The impurity concentration on the surface in contact with the first metal layer 5 of the p-base layer 6A, that is, on the first main surface 21, is 1.0×10 16 atoms / cm 3Assume the above. The peak impurity concentration is 2.0×10 16 atoms / cm 3 or more and 1.0×10 18 atoms / cm 3 or less. The junction depth is deeper than the n+ emitter layer 24 and shallower than the n layer 26.

[0173] In addition, the parameters regarding the n layer 26, n+ emitter layer 24, trench depth, n buffer layer 8, first n+ cathode layer 91, second n+ cathode layer 92, first p collector layer 101A, and second p collector layer 102A are the same as those in Embodiment 7.

[0174] <H-2. Modification Example 1> FIG. 42 is a cross-sectional view of an RC-IGBT 1025, which is a power semiconductor device according to Modification Example 1 of Embodiment 8, taken along line A-A' in FIG. 1. The RC-IGBT 1025 differs from the RC-IGBT 1021 of Embodiment 7 only in that a p cathode layer 100 is provided in a part of the diode region 34. In the RC-IGBT 1022, the p cathode layer 100 has a two-layer structure composed of a first p cathode layer 101 and a second p cathode layer 102.

[0175] The second p cathode layer 102 is formed in contact with the n buffer layer 8 between the n buffer layer 8 and the second main surface 22. The first p cathode layer 101 is formed in contact with both the second p cathode layer 102 and the second metal layer 11 therebetween. The lower surface of the first p cathode layer 101 constitutes the second main surface of the semiconductor substrate 20.

[0176] The parameters such as the impurity concentration and depth of the first p cathode layer 101 and the second p cathode layer 102 in the diode region 34 are the same as those of the first p collector layer 101A and the second p collector layer 102A in the IGBT region 33.

[0177] <H-3. Modification Example 2> FIG. 43 is a cross-sectional view of an RC-IGBT 1026, which is a power semiconductor device according to Modification 2 of Embodiment 8, taken along line A-A' of FIG. 1. The RC-IGBT 1026 differs from the RC-IGBT 1025 according to Modification 1 of Embodiment 8 only in that in the IGBT region 33, the p collector layer 100A is composed of a single layer of the second p collector layer 102A, and in the diode region 34, the p cathode layer 100 is composed of a single layer of the second p cathode layer 102.

[0178] The second p collector layer 102A and the second p cathode layer 102 in the RC-IGBT 1026 have a surface impurity concentration on the second main surface 22 of 1.0×10 17 atoms / cm 3 or more and 1.0×10 19 atoms / cm 3 or less, and a depth of 0.3 μm or more and 0.5 μm or less.

[0179] <H-4. Effects> The RC-IGBTs 1024, 1025, and 1026 according to Embodiment 8 and its Modifications 1 and 2 are configured such that the collector structure in the IGBT region 33 and the cathode structure in the diode region 34 satisfy the relationships of formulas (1), (2), and (3) in the same manner as the manufacturing method of the RFC diode 1001 described in Embodiment 4. Therefore, also in the RC-IGBTs 1024, 1025, and 1026, the trade-off characteristics between the on-voltage V F and the switching loss E REC can be controlled to the high-speed side without depending on the conventional lifetime control method, and it is possible to achieve low off-loss, improved breakdown tolerance, and thermal stability.

[0180] Also, due to the absence of the p+ layer 25, the diode region 34 of the RC-IGBTs 1024, 1025, and 1026 can achieve the same performance as the pin diode region 31 of the RFC diode 1001 according to Embodiment 1 shown in FIG. 3 and the pin diode 1011 according to Embodiment 6 shown in FIG. 34.

[0181] <I. Embodiment 9> <I-1. Configuration> FIG. 44 is a cross-sectional view of an RC-IGBT 1027, which is a power semiconductor device according to Embodiment 9, taken along line A-A' in FIG. 1. The RC-IGBT 1027 differs from the RC-IGBT 1021 of Embodiment 7 only in that the n buffer layer 80 is composed of a two-layer structure of a first n buffer layer 81 and a second n buffer layer 82 in the same manner as the RFC diode 1003 according to Embodiment 3.

[0182] The parameters of the first n buffer layer 81 and the second n buffer layer 82 are the same as those in the RFC diode 1003 according to Embodiment 3.

[0183] <I-2. Modification Example 1> FIG. 45 is a cross-sectional view of an RC-IGBT 1028, which is a power semiconductor device according to Modification Example 1 of Embodiment 9, taken along line A-A' in FIG. 1. The RC-IGBT 1028 differs from the RC-IGBT 1027 of Embodiment 9 only in that a p cathode layer 100 is provided in a part of the diode region 34. In the RC-IGBT 1028, the p cathode layer 100 has a two-layer structure composed of a first p cathode layer 101 and a second p cathode layer 102.

[0184] The second p cathode layer 102 is formed in contact with the n buffer layer 8 between the n buffer layer 8 and the second main surface 22. The first p cathode layer 101 is formed in contact with both the second p cathode layer 102 and the second metal layer 11 therebetween. The lower surface of the first p cathode layer 101 constitutes the second main surface of the semiconductor substrate 20.

[0185] The parameters such as the impurity concentration and depth of the first p cathode layer 101 and the second p cathode layer 102 in the diode region 34 are the same as those of the first p collector layer 101A and the second p collector layer 102A in the IGBT region 33.

[0186] <I-3. Modification Example 2> FIG. 46 is a cross-sectional view of an RC-IGBT 1029, which is a power semiconductor device according to Modification 2 of Embodiment 9, taken along line A-A' in FIG. 1. The RC-IGBT 1029 differs from the RC-IGBT 1028 according to Modification 1 of Embodiment 9 only in that the p collector layer 100A is composed of a single layer of the second p collector layer 102A in the IGBT region 33, and the p cathode layer 100 is composed of a single layer of the second p cathode layer 102 in the diode region 34.

[0187] The second p collector layer 102A and the second p cathode layer 102 in the RC-IGBT 1029 have a surface impurity concentration on the second main surface 22 of 1.0×10 17 atoms / cm 3 or more and 1.0×10 19 atoms / cm 3 or less, and a depth of 0.3 μm or more and 0.5 μm or less.

[0188] <I-4. Effect> The RC-IGBTs 1027, 1028, and 1029 according to Embodiment 9 and its Modifications 1 and 2 include a first n buffer layer 81 and a second n buffer layer 82 similar to those of the RFC diode 1003 according to Embodiment 3. In the second n buffer layer 82, trap B due to the Si pair between the lattices becomes the main trap component. Therefore, according to the RC-IGBTs 1027, 1028, and 1029, similar to the RFC diode 1003, the trade-off characteristics between the on-voltage V F and the switching loss E REC are controlled to the high-speed side without relying on the conventional lifetime control method, and low off-loss, improved breakdown tolerance, and thermal stability are realized.

[0189] <J. Embodiment 10> <J-1. Configuration> FIG. 47 is a cross-sectional view of an RC-IGBT 1030, which is a power semiconductor device according to Embodiment 10, taken along line A-A' of FIG. 1. The RC-IGBT 1030 differs from the RC-IGBT 1027 according to Embodiment 9 only in that the p+ layer 25 is not present in the diode region 34. That is, in the RC-IGBT 1030, the p-base layer 6A contacts the first metal layer 5 in the diode region 34.

[0190] The parameters regarding each diffusion layer and trench of the RC-IGBT 1030 are as follows. The p-base layer 6A in the IGBT region 33 and the diode region 34 is the same as in Embodiment 8. The n layer 26, the n+ emitter layer 24, the trench depth D trench , the first n-buffer layer 81, the second n-buffer layer 82, the first n+ cathode layer 91, the second n+ cathode layer 92, the first p-collector layer 101A, and the second p-collector layer 102A are the same as in Embodiment 9.

[0191] <J-2. Modification 1> FIG. 48 is a cross-sectional view of an RC-IGBT 1031, which is a power semiconductor device according to Modification 1 of Embodiment 10, taken along line A-A' of FIG. 1. The RC-IGBT 1031 differs from the RC-IGBT 1030 of Embodiment 10 only in that a p-cathode layer 100 is provided in a part of the diode region 34. In the RC-IGBT 1030, the p-cathode layer 100 has a two-layer structure composed of a first p-cathode layer 101 and a second p-cathode layer 102.

[0192] The second p-cathode layer 102 is formed in contact with the n-buffer layer 8 between the n-buffer layer 8 and the second main surface 22. The first p-cathode layer 101 is formed in contact with both the second p-cathode layer 102 and the second metal layer 11 therebetween. The lower surface of the first p-cathode layer 101 constitutes the second main surface of the semiconductor substrate 20.

[0193] The parameters such as the impurity concentration and depth of the first p-cathode layer 101 and the second p-cathode layer 102 in the diode region 34 are the same as those of the first p-collector layer 101A and the second p-collector layer 102A in the IGBT region 33.

[0194] <J-3. Variant Example 2> Figure 49 is a cross-sectional view of an RC-IGBT 1032, which is a power semiconductor device according to Variant Example 2 of Embodiment 10, taken along line A-A' of FIG. 1. The RC-IGBT 1032 differs from the RC-IGBT 1031 according to Variant Example 1 of Embodiment 10 only in that the p collector layer 100A is composed of one layer of the second p collector layer 102A in the IGBT region 33, and the p cathode layer 100 is composed of one layer of the second p cathode layer 102 in the diode region 34.

[0195] The second p collector layer 102A and the second p cathode layer 102 in the RC-IGBT 1031 have an impurity concentration of 1.0×10 17 atoms / cm 3 or more and 1.0×10 19 atoms / cm 3 or less on the second main surface 22, and a depth of 0.3 μm or more and 0.5 μm or less.

[0196] <J-4. Effects> The RC-IGBTs 1030, 1031, and 1032 according to Embodiment 10 and its Variant Examples 1 and 2 include the same first n buffer layer 81 and second n buffer layer 82 as the RFC diode 1003 according to Embodiment 3. In the second n buffer layer 82, trap B due to the Si pair between the lattices becomes the main trap component. Therefore, according to the RC-IGBTs 1027, 1028, and 1029, similar to the RFC diode 1003, the trade-off characteristics between the on-voltage V F and the switching loss E REC are controlled to the high-speed side without relying on the conventional lifetime control method, and low off-loss, improved breakdown tolerance, and thermal stability are realized.

[0197] Also, due to the absence of the p+ layer 25, the diode regions 34 of the RC-IGBTs 1030, 1031, and 1032 can achieve the same performance as the pin diode region 31 of the RFC diode 1001 according to Embodiment 1 shown in FIG. 3 and the pin diode 1011 according to Embodiment 6 shown in FIG. 34.

[0198] <K. Embodiment 11> <K-1. Configuration> FIG. 50 is a cross-sectional view of an IGBT 1033, which is a power semiconductor device according to Embodiment 11, taken along line A-A' of FIG. 1. The IGBT 1033 has a trench gate structure.

[0199] The IGBT 1033 is similar in configuration to the IGBT region 33 of the RC-IGBT 1027 according to Embodiment 9.

[0200] The n-drift layer 7 in the IGBT 1033 is the same as the n-drift layer 7 in the RC-IGBT 1027 according to Embodiment 9.

[0201] In the IGBT 1033, a part of the gate electrode 43 in the trench 41 is at the same potential as the first metal layer 5 having an emitter potential. Thereby, the saturation current density of the IGBT is suppressed. Also, by controlling the capacitance characteristics, oscillation in the no-load short-circuit state is suppressed. As a result, not only is the short-circuit withstand improved, but also a reduction in the ON voltage is achieved due to an increase in the carrier concentration on the emitter side.

[0202] The p-base layer 6A, n-layer 26, n+ emitter layer 24, p+ layer 25, first n-buffer layer 81, second n-buffer layer 82, first p-collector layer 101A, second p-collector layer 102A, and trench depth D in the IGBT 1033 trench are the same as those in the RC-IGBT 1027 according to Embodiment 9.

[0203] <K-2. Effects> An IGBT1033 which is a power semiconductor device according to an eleventh embodiment includes a semiconductor substrate 20 having a first main surface 21 and a second main surface 22 which face each other, a first metal layer 5 provided on the first main surface 21 of the semiconductor substrate 20, and a second metal layer 11 provided on the second main surface 22 of the semiconductor substrate 20. The semiconductor substrate 20 includes an n-drift layer 7 which is a drift layer of a first conductivity type, an n-buffer layer 8 which is a buffer layer of a first conductivity type provided between the n-drift layer 7 and the second main surface 22, and a p-collector layer 100A which is a collector layer of a second conductivity type provided between the n-buffer layer 8 and the second main surface 22. The n-buffer layer 8 includes a first n-buffer layer 81 which is a first buffer layer in contact with the second metal layer 11, and a second n-buffer layer 82 which is a second buffer layer in contact with the n-drift layer 7. The crystal defects in the second n buffer layer 82 are trap B, which is a second lattice defect, and trap C, which is a third lattice defect, which are detected by the photoluminescence method.

[0204] Thus, the IGBT 1033 includes the first n-buffer layer 81 and the second n-buffer layer 82 similar to those of the RFC diode 1003 according to the third embodiment. In the second n-buffer layer 82, the traps B due to interstitial Si pairs are the main trap components. Therefore, according to the IGBT 1033, like the RFC diode 1003, the on-voltage V F and switching loss E REC The trade-off characteristics of the above are controlled to the high-speed side without relying on the conventional lifetime control method, and low off-loss, improved breakdown resistance, and thermal stability are achieved.

[0205] It should be noted that the embodiments can be freely combined, and each embodiment can be modified or omitted as appropriate. [Explanation of symbols]

[0206] 5 First metal layer, 5A Aluminum wiring, 6 p anode layer, 6A p base layer, 7 n- drift layer, 8,80 n buffer layer, 9,90 n+ cathode layer, 10,100 p cathode layer, 11 Second metal layer, 20 Semiconductor substrate, 21 First main surface, 22 Second main surface, 23 Surface protection film, 24 n+ emitter layer, 25 p+ layer, 26 n layer, 29 Interlayer insulating film, 31 pin diode region, 32 pnp transistor region, 33 IGBT region, 34 Diode region, 41 Trench, 42 Gate insulating film, 43 Gate electrode, 44 Trench, 45 Dummy gate electrode, 46,47 Passivation film, 52 p layer, 55 Gettering layer, 56 n+ layer, 62,68 Oxide film, 63 TEOS layer, 64,65 Doped polysilicon layer, 81 1st n buffer layer, 82 2nd n buffer layer, 91 1st n+ cathode layer, 92 2nd n+ cathode layer, 93 3rd n+ cathode layer, 100A p collector layer, 101 1st p cathode layer, 101A 1st p collector layer, 102 2nd p cathode layer, 102A 2nd p collector layer, 1000, 1001, 1002, 1003 RFC diodes, 1010, 1011, 1012 pin diodes, 1021-1032 RC-IGBT, 1033 IGBT.

Claims

1. a semiconductor substrate having a first main surface and a second main surface opposed to each other; a first metal layer provided on the first major surface of the semiconductor substrate; a second metal layer provided on the second main surface of the semiconductor substrate; The semiconductor substrate is A drift layer of a first conductivity type; a buffer layer of a first conductivity type provided between the drift layer and the second major surface; a diffusion layer provided between the buffer layer and the second metal layer in contact with both of them, a diode region in which a part of the region operates as a diode in a plan view; the diffusion layer includes a cathode layer of a first conductivity type provided in contact with the buffer layer and the second metal layer in at least a portion of the diode region; The cathode layer of the first conductivity type is a first cathode layer having one impurity concentration peak point and in contact with the second metal layer; a second cathode layer having one impurity concentration peak point and provided between the first cathode layer and the buffer layer in contact with the buffer layer; a density of crystal defects consisting of complex defects C1C2 and interstitial Si pairs in the first cathode layer is higher than a density of the crystal defects in the other diffusion layers; The crystal defects are detected by a photoluminescence method and include a first lattice defect which is a complex defect C i C s and a second lattice defect which is an interstitial Si pair; The photon energy of the first lattice defect is 0.969 eV; The photon energy of the second lattice defect is 1.018 eV. Power semiconductor device.

2. The dose of the first cathode layer is 0.3 times or more the dose of the second cathode layer. The power semiconductor device according to claim 1 .

3. transistor regions operating as transistors are arranged alternately with the diode regions in a plan view; the diffusion layer includes a second conductivity type diffusion layer provided in contact with the buffer layer and the second metal layer in the transistor region; The power semiconductor device according to claim 1 or 2.

4. The second conductivity type diffusion layer is a first diffusion layer having one impurity concentration peak point and in contact with the second metal layer; a second diffusion layer having one impurity concentration peak point and provided between the first diffusion layer and the buffer layer in contact with the buffer layer; The power semiconductor device according to claim 3 .

5. the dose of the second cathode layer is at least twice the dose of the second diffusion layer; The power semiconductor device according to claim 4.

6. the second conductive type diffusion layer has one impurity concentration peak point; The power semiconductor device according to claim 3 .

7. The buffer layer is a first buffer layer having one impurity concentration peak point and in contact with the diffusion layer; a second buffer layer having one impurity concentration peak point and in contact with the drift layer; The crystal defects in the second buffer layer are second lattice defects and third lattice defects detected by a photoluminescence method. The power semiconductor device according to claim 4 or 5.

8. The photon energy of the second lattice defect is 1.018 eV; The photon energy of the third lattice defect is 1.039 eV; In the second buffer layer, a photoluminescence intensity of the second lattice defect is higher than a photoluminescence intensity of the third lattice defect. The power semiconductor device according to claim 7.

9. The peak impurity concentration of the second buffer layer is 0.01 times or less than the peak impurity concentration of the first buffer layer. The power semiconductor device according to claim 7 or 8.

10. an anode layer of a second conductivity type provided between the drift layer and the first main surface; The power semiconductor device according to claim 1 or 2.

11. a base layer of a second conductivity type provided between the drift layer and the first main surface in the diode region and the transistor region; The power semiconductor device according to any one of claims 3 to 9.

12. the second conductive type diffusion layer is provided in contact with the buffer layer and the second metal layer even in a part of the diode region; The power semiconductor device according to claim 11.

13. the base layer is in contact with the first metal layer; The power semiconductor device according to claim 11 or 12.

14. a semiconductor substrate having a first main surface and a second main surface opposed to each other; a first metal layer provided on the first major surface of the semiconductor substrate; a second metal layer provided on the second main surface of the semiconductor substrate; The semiconductor substrate is A drift layer of a first conductivity type; a buffer layer of a first conductivity type provided between the drift layer and the second major surface; a collector layer of a second conductivity type provided between the buffer layer and the second major surface, The buffer layer is a first buffer layer in contact with the collector layer; a second buffer layer in contact with the drift layer, the crystal defects in the second buffer layer are second lattice defects and third lattice defects detected by a photoluminescence method; The second lattice defect and the third lattice defect are interstitial Si pairs. Power semiconductor device.

15. forming a first metal layer and a surface protection film on a first main surface of a semiconductor substrate having a first conductivity type drift layer; After forming the surface protective film, the thickness of the semiconductor substrate is controlled to a desired thickness; After controlling the thickness of the semiconductor substrate, a first ion implantation and a first annealing are performed to form a buffer layer of a first conductivity type on the second main surface of the semiconductor substrate; After the first annealing, a second ion implantation is performed to form a second diffusion layer of a second conductivity type in the second main surface of the semiconductor substrate; after the second ion implantation, a third ion implantation is performed to form a first diffusion layer of a second conductivity type in the second main surface of the semiconductor substrate with an acceleration energy lower than that of the second ion implantation; After the third ion implantation, a fourth ion implantation is performed to form a second cathode layer of a first conductivity type on the second main surface of the semiconductor substrate; after the fourth ion implantation, a fifth ion implantation is performed to form a first cathode layer of a first conductivity type on the second main surface of the semiconductor substrate with an acceleration energy lower than that of the fourth ion implantation; After the fifth ion implantation, a second annealing is performed to activate the ions implanted in the second, third, fourth, and fifth ion implantations, thereby forming the second diffusion layer, the first diffusion layer, the second cathode layer, and the first cathode layer; forming a second metal layer on the second major surface of the semiconductor substrate after the second anneal; After the second metal layer is formed, a third annealing is performed at 350° C. in a nitrogen atmosphere. The method for manufacturing a power semiconductor device according to claim 4 .

16. forming a first metal layer and a surface protection film on a first main surface of a semiconductor substrate having a first conductivity type drift layer; After forming the surface protective film, the thickness of the semiconductor substrate is controlled to a desired thickness; After controlling the thickness of the semiconductor substrate, a first ion implantation and a first annealing are performed to form a first buffer layer of a first conductivity type on the second main surface of the semiconductor substrate; After the first annealing, a second ion implantation is performed on the second main surface of the semiconductor substrate to form a second buffer layer of a first conductivity type; after the second ion implantation, a third ion implantation is performed to form a second diffusion layer of a second conductivity type in the second main surface of the semiconductor substrate; after the third ion implantation, a fourth ion implantation is performed to form a first diffusion layer of a second conductivity type in the second main surface of the semiconductor substrate with an acceleration energy lower than that of the third ion implantation; After the fourth ion implantation, a fifth ion implantation is performed to form a second cathode layer of a first conductivity type on the second main surface of the semiconductor substrate; after the fifth ion implantation, a sixth ion implantation is performed to form a first cathode layer of a first conductivity type on the second main surface of the semiconductor substrate, with an acceleration energy lower than that of the fifth ion implantation; After the sixth ion implantation, a second annealing is performed to activate the ions implanted in the second, third, fourth, fifth, and sixth ion implantations, thereby forming a second buffer layer, the second diffusion layer, the first diffusion layer, the second cathode layer, and the first cathode layer; A fourth anneal is performed in a nitrogen atmosphere. forming a second metal layer on the second major surface of the semiconductor substrate after the fourth annealing; After the second metal layer is formed, a third annealing is performed at 350° C. in a nitrogen atmosphere. The method for manufacturing a power semiconductor device according to any one of claims 7 to 9.

17. The temperature of the third annealing is 350° C. or more and 370° C. or less. The method for manufacturing a power semiconductor device according to claim 16.

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