Capacitive microfabricated ultrasonic transducer and method for manufacturing the same

Abstract

The capacitive micromachined ultrasonic transducer includes a lower electrode, an upper electrode, and a membrane disposed between the lower electrode and the upper electrode and attached to the upper electrode. Anchors are connected to the membrane and the lower electrode such that a cavity is defined between the lower electrode and the membrane. One or more posts are disposed in the cavity, with the posts partially embedded in the membrane and extending toward the lower electrode. A method for manufacturing the capacitive micromachined ultrasonic transducer includes forming an oxide growth layer on a device layer of undoped silicon and removing portions of the oxide growth layer to form a plurality of anchors extending beyond an outer surface of the device layer and a plurality of posts partially embedded in the post holes and extending beyond the outer surface of the device layer.

Description

Technical Field

[0001] This application claims the benefit of U.S. Provisional Application No. 62 / 768,188, filed on Nov. 16, 2018, and the entire disclosure of the provisional application is incorporated herein by reference.

[0002] The present invention relates to an innovative wafer bonding process, which is optimized in terms of the phenomenon of charge trapping, and is particularly suitable for manufacturing on highly doped substrates.

Background Art

[0003] Capacitive micromachined ultrasonic transducers (CMUTs) are promising ultrasonic medical imaging devices to replace traditional piezoelectric transducers. This technology has been studied in the academic community since its development in 1994, and its entry into the ultrasonic market is imminent. However, medical probes using CMUTs have a minimum lifespan of seven years with daily use, so the reliability of this technology is still a concern for manufacturers. The main cause of failure is well known in the field of capacitive microelectromechanical systems and is due to charge injection into the dielectric layer, which can ultimately cause dielectric breakdown, performance degradation, and device failure. Basically, a CMUT transducer consists of two electrodes, one fixed on a substrate and the other suspended and movable above a vacuum cavity. These two electrodes are insulated by a thin layer of dielectric, which is an insulating layer, to avoid the risk of shorting during operation. Due to the narrow space between the two electrodes and the high electric field required for operation, charge carriers move from one electrode to the other and generally remain trapped within the insulating layer. This causes significant changes in operation, greatly reduces performance, and often causes permanent damage to the device. Since the charging phenomenon is very complex and causes powerful malfunctions, many groups developing CMUT transducers, and even MEMS, are working to avoid or at least reduce the influence of this spurious effect.

[0004] Many solutions for dealing with charge trapping have been proposed, published, and patented by several academic and industrial groups over the years. One of the most common solutions found in the literature is based on patterning the insulating layer such that the insulating layer is replaced by isolation posts. According to such a structure, since the contact surface between the two electrodes is limited by the surface of the posts, charge trapping is reduced [1]-[7].

[0005] For example, Fig. 1A shows the structure of a traditional CMUT10 with a normal insulating layer 12, and Fig. 1B shows the structure of an improved CMUT20 with built-in isolation posts 22. The CMUT20 in Fig. 1B has the great advantage of being very easy to fabricate. However, since the permittivity of vacuum is at least four times inferior to that of the insulating layer (considering an insulating layer made of silicon dioxide), it is accompanied by a decrease in the capacitance of the device. Furthermore, in this structure, although the amount of charge injected between the electrodes can be reduced, the charging mechanism itself cannot be reduced. That is, the charge still moves inside the posts more easily (since it is necessary to slightly increase the electric field to compensate for the loss of electrostatic force). For these reasons, this solution is combined with patterning the upper or lower electrode so that there is no electrode above or below the isolation post. This reduces the electrical stress inside the isolation post and reduces the movement of charge. This solution has been patented by Hitachi as a sacrificial layer release process [4], in which the isolation posts 32, 42 hang under the membrane instead of lying at the bottom of the cavity as in the CMUT30, 40 shown in Figs. 2A and 2B.

[0006] This solution is particularly safe because the electrical stress inside the post is significantly reduced. However, in this solution, it is necessary to pattern at least one electrode, which is not always easy and is impossible in a fusion-based process. Similar approaches have also been proposed by the group at North Carolina State University [7] and the group at the University of Alberta [6]. In fact, separating the mechanical function and the electrostatic function is a good method, but it is very difficult to create the essential structure of the CMUT cell. For example, as shown in the schematic diagram of Figure 3, the international patent publication WO2006 / 123301 of Kolo Technologies, Inc. describes a specific structure of a CMUT50 that follows this idea.

[0007] According to this structure, the membrane 52 used for ultrasonic radiation is very hard, and in order to enable displacement like a piston, the membrane 52 is placed on a smaller membrane 54 that is used as a spring. The mechanical gap h m is smaller than the electrical gap h e then the insulating layer between the electrodes can be completely removed. Therefore, the problem of charge trapping is suppressed. The complexity of this structure is the biggest problem because it is expected to lead to an increase in cost and a decrease in manufacturing yield. Furthermore, it is necessary to thoroughly understand the mechanical behavior of such a unique structure.

[0008] The properties of the dielectric material are an important parameter for the problem of charge trapping. Generally, the insulating layer is silicon nitride (Si x N y ) or silicon dioxide (SiO 2) It is made by. The reduction of charge trapping is improved by using a high-quality dielectric with a low defect density and a large bandgap. This depends greatly on the manufacturing method, even though silicon dioxide is theoretically superior to silicon nitride in this regard. More generally, the band diagram of the entire stack is an important parameter to consider for reducing charge trapping. Philips Innovation has obtained a patent for a CMUT device with a specially developed oxide-nitride-oxide multilayer stack to reduce the charging effect [8]. A research group at the University of Rome III has replaced part of the nitride layer with silicon dioxide to utilize a high bandgap [9]. The quality of the insulating layer is strongly degraded by partial plasma etching. Furthermore, in the case of naturally occurring silicon dioxide as the insulating material, when grown on a highly doped substrate, defects occur inside the crystal structure due to the influence of dopants. However, highly doped substrates are user-friendly, especially in devices that require a 3D package and employ Si through electrodes.

[0009] In addition to these two proposals, several other methods have been proposed to reduce the trapping of charges, such as reducing the height of the cavity to reduce the electric field and the movement of charges, and removing the insulating layer completely. These methods are considered to be almost impossible to implement industrially or to degrade the performance of the device. Maintaining the acoustic performance while reducing the trapping of charges has been the main difficulty of this work. For example, reducing the height of the cavity significantly reduces the sensitivity.

Summary of the Invention

Problems to be Solved by the Invention

[0010] Various solutions proposed in the literature are generally considered to be accompanied by a degradation in performance. This is clearly a major drawback and is unacceptable in many cases where CMUT transducers are exposed to intense competition with piezoelectric technology.

Means for Solving the Problem

[0011] The present invention relates to a unique wafer bonding process optimized for the charge trapping phenomenon and particularly suitable for manufacturing on highly doped substrates. This new process maintains or improves acoustic performance compared to traditional structures and has several interesting features: (1) deviation of a plurality of isolation posts such that a plurality of isolation posts are partially buried within the structure of the transducer; (2) a dedicated manufacturing strategy for growing an optimal oxide layer on a highly doped substrate by patterning only the SOI wafer and manufacturing the device; (3) reduction of parasitic capacitance.

[0012] According to some exemplary embodiments of the present invention, a capacitive micromachined ultrasonic transducer includes a lower electrode, an upper electrode, and a membrane disposed between the lower electrode and the upper electrode and attached to the upper electrode. The anchor is connected to the membrane and the lower electrode such that a cavity is defined between the lower electrode and the membrane. One or more posts are disposed within the cavity, and a portion of the post is embedded within the membrane and extends towards the lower electrode.

[0013] In some exemplary embodiments, a portion of the anchor is embedded within the membrane. In some specific embodiments, each of the plurality of anchors includes a central member that is partially embedded within the membrane and extends to the lower electrode, and a guard ring that is substantially embedded within the membrane and surrounds the central member. In some specific embodiments, the central member and the guard ring are made of the same material. In some other embodiments, the central member is made of a first material and the guard ring is made of a second material. In still other embodiments, an empty guard ring is defined by the membrane surrounding the central member.

[0014] In some exemplary embodiments, each of the plurality of posts includes a central member that is partially embedded within the membrane and extends towards the lower electrode, and a guard ring that is substantially embedded within the membrane and surrounds the central member. In some specific embodiments, the central member and the guard ring are made of the same material. In some other embodiments, the central member is made of a first material and the guard ring is made of a second material. In still other embodiments, an empty guard ring is defined by the membrane surrounding the central member.

[0015] In some embodiments of the present invention, the lower electrode is a wafer of highly doped silicon.

[0016] In some embodiments of the present invention, the membrane defines a plurality of post holes that partially extend inside the membrane, and one of the one or more posts is located inside each of the plurality of post holes so as to extend outside the post hole. In some specific embodiments, a gap is formed between the side wall of each of the one or more posts and the inner wall of each post hole.

[0017] According to an exemplary embodiment of the present invention, a method for manufacturing a capacitive microfabricated ultrasonic transducer begins with preparing a device layer of undoped silicon having an exposed outer surface. Then, the outer surface of the device layer is etched to form post holes that partially extend inside the device layer. An oxide growth layer is formed on the device layer to fill the post holes and cover the outer surface of the device layer, and a part of the oxide growth layer is removed to form a plurality of anchors that extend beyond the outer surface of the device layer and a plurality of posts that are partially embedded inside the post holes and extend beyond the outer surface of the device layer. Then, the plurality of anchors are adhered to a first electrode to form a cavity defined by the first electrode, the device layer, and the anchors. The posts are disposed within the cavity. Also, an upper electrode is deposited on the surface of the device layer opposite to the outer surface of the device layer.

[0018] According to some exemplary embodiments, the outer surface of the device layer is etched to form anchor holes that partially extend into the device layer, and the anchors are partially embedded inside the anchor holes.

[0019] According to some specific embodiments, the step of forming an oxide growth layer on the device layer is performed by high-temperature thermal oxidation of the device layer. For example, the high-temperature thermal oxidation is performed in a temperature range of about 800°C to about 1200°C, more preferably at about 1100°C.

[0020] According to some exemplary embodiments, the oxide growth layer is formed to a thickness greater than the depth of the post holes or equal to the depth of the post holes. According to some other specific embodiments, the oxide growth layer is formed to a thickness greater than the height of the anchors or equal to the height of the anchors.

[0021] According to some exemplary embodiments, the method further includes the step of planarizing the oxide growth layer. In some specific embodiments, the oxide growth layer is planarized until it reaches the same height as the outer surface of the device layer. In some other specific embodiments, the oxide growth layer is planarized until the oxide growth layer has the same thickness as the height of the anchors.

[0022] According to some exemplary embodiments, plasma etching is used to remove a portion of the oxide growth layer to form the anchors and the posts.

[0023] According to some exemplary embodiments, the method further includes the step of chemically etching the oxide growth layer outside the post holes.

[0024] According to some exemplary embodiments, the method further includes the step of forming a second oxide growth layer on the device layer to fill the post holes and cover the outer surface of the device layer. Then, a portion of the second oxide growth layer is removed to form the anchors and the posts.

[0025] According to some exemplary embodiments, the method further comprises the step of planarizing the anchor.

[0026] According to some exemplary embodiments, the method further comprises the step of plasma etching the posts and lowering the height of the posts until the height is lower than the height of the anchor. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Hereinafter, embodiments of the present specification will be described together with the accompanying drawings provided for illustrative purposes only and not for limiting the scope of the claims.

[0028]

Figure 1A

Figure 1B

Figure 2A

Figure 2B

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

Figure 23

Figure 24

Figure 25

Figure 26

Figure 27

Figure 28

Figure 29

Figure 30

Figure 31

Figure 32

Figure 33A

Figure 33B

Figure 34A

Figure 34B

Figure 34C

Figure 35

[0029] The present invention relates to a unique wafer bonding process optimized for the charge trapping phenomenon and is particularly suitable for manufacturing on highly doped substrates. This new process maintains or improves acoustic performance compared to traditional structures and has several interesting features: (1) deviation of a plurality of isolation posts such that the plurality of isolation posts are partially buried within the structure of the transducer, (2) a dedicated manufacturing strategy for growing an optimal oxide layer on a highly doped substrate by patterning only the SOI wafer and manufacturing the device, (3) reduction of parasitic capacitance.

[0030] The present invention examines three different CMUT structures and related manufacturing methods based on wafer bonding, which have the specificity of manufacturing the main steps on an SOI wafer.

[0031] Referring first to FIG. 15, one exemplary CMUT 180 made in accordance with the present invention includes a lower electrode 172, an upper electrode 174, and a membrane 116 attached to the upper electrode 174 and disposed between the lower electrode 172 and the upper electrode 174. An anchor 152 is connected to the membrane 116 and the lower electrode 172 so as to define a cavity between the lower electrode 172 and the membrane 116, and one or more posts 154 are disposed within the cavity. As will be further discussed below, the anchor 152 and the isolation posts 154 are formed on the membrane 116 and are partially embedded within the membrane 116. In another embodiment, referring now to FIG. 25, a CMUT 280 made in accordance with the present invention similarly includes a lower electrode 272, an upper electrode 274, and a membrane 216 having an anchor 252 and isolation posts 254 formed on and partially embedded within the membrane 216. In yet another embodiment, referring now to FIG. 32, a CMUT 380 made in accordance with the present invention includes a lower electrode 372, an upper electrode 374, and a membrane 316 having an anchor 352 and isolation posts 354 formed on and partially embedded within the membrane 316. As shown in FIGS. 15, 25, and 32, in each embodiment, the posts 154, 254, 354 are partially embedded within their respective membranes 116, 216, 316. In the first and second embodiments, the anchors 152, 252 are similarly partially embedded within their respective membranes 116, 216. However, in the third embodiment, the anchor 352 is not embedded within the membrane 316.

[0032] Each structure retains the main object of the present invention of reducing the charge trapping phenomenon while at the same time retaining sufficient electromechanical performance (e.g., high useful capacitance, low parasitic capacitance, etc.).

[0033] The three structures and related methods share the following three characteristics that totally reduce the charging effect when compared with the reference process. (1) "Insulator post" principle: Instead of filling the entire surface of the membrane, this insulator exists only in one or several posts. Therefore, even for the same strength of charging (regarding the charging per unit volume), the influence of charging (measured by the change of the bias of the CMUT) is much smaller. (2) These insulator posts are thicker because they are partially embedded in the membrane. This reduces the vertical electric field inside the posts. (3) By growing this insulator on the SOI side, that is, on the undoped silicon, the presence of dopants (i.e., traps) in the oxide is avoided. Also, the advantages of one or more embodiments and their manufacturing methods will be described below.

[0034] First Embodiment In addition to the characteristics common to the three structures and related methods, the first embodiment of the structure shown in FIG. 15 has the following advantages. (1) The isolation posts are partially embedded inside the CMUT structure. This allows the use of tall posts and reduces the electrical stress while maintaining the capacitance of the device. (2) In the manufacturing method of the CMUT of the first embodiment, since partial etching of the insulator layer is not required, deterioration caused by the etching plasma can be avoided. (3) Since the anchor is partially embedded inside the CMUT membrane, the parasitic capacitance is reduced and the performance is improved. (4) The anchor can be made such that the membrane produces a displacement like a piston, and the sensitivity can be improved.

[0035] According to a first exemplary method of manufacturing the first embodiment of the CMUT of the present invention, referring here to FIG. 4, the process starts from a traditional silicon-on-insulator (SOI) wafer 110 including a handle 112, a buried oxide (BOX) layer 114, and a device layer 116 having an exposed outer surface 118, from bottom to top. In some exemplary embodiments, the device layer 116 is an undoped silicon layer 116.

[0036] Next, referring to FIG. 5, a first resist pattern 120 having an opening 122 defined through the resist 120 is deposited on the outer surface 118 of the device layer 116, exposing the outer surface 118 of the device layer 116. As will be further described below, the isolation posts 154 and anchors 152 of the CMUT 180 resulting from the above-described with respect to FIG. 15 are formed at the positions of the openings 122 of the first resist pattern 120. In particular, the lateral dimensions of the posts 154 and anchors 152 are determined at this point. The first resist pattern 120 corresponds to a first photolithography mask.

[0037] Next, referring to FIG. 6, a first (deep) reactive ion etching, i.e., (D)RIE, is performed on the outer surface 118 of the device layer 116 to form an anchor hole 126 and a post hole 128 that partially extend into the device layer 116 at positions corresponding to the openings 122 of the resist 120 shown in FIG. 4. When the holes 126, 128 are formed, the resist 120 is stripped, leaving the device layer 116 having the holes 126, 128 shown in FIG. 6.

[0038] According to some exemplary embodiments, the widths of the isolation posts 154 and anchors 152 formed correspond to the widths of the respective holes 126, 128 defined in the device layer 116. Similarly, the depths of the holes 126, 128 determine the heights of the isolation posts 154 and anchors 152.

[0039] In some embodiments, the anchor hole 126 and the post hole 128 are formed with different dimensions. For example, in some preferred embodiments, the difference in the depth of the holes 126, 128 defines the height difference between the anchor 152 and the post 154 (typically in the range of 10 nm to 500 nm). The deeper etching of the device layer 116 in these holes 126, 128 increases the isolation of the resulting post 154 and anchor 152, but also decreases the mechanical strength of the resulting membrane 116. Thus, the depth of the holes 126, 128 is typically kept less than about 80% of the thickness of the device layer 116. In some embodiments, the lateral dimension of the holes 126, 128 is calculated by adding n times the lateral dimension of the non-embedded portion of the resulting anchor or post to the depth of the hole, where n is typically a factor of about 2.0.

[0040] Referring now to FIG. 7, a first oxide growth layer 130 is formed on the device layer 116 so as to fill each of the holes 126, 128 and cover the outer surface 118 of the device layer 116. In particular, in some preferred embodiments, a first high-temperature thermal oxidation is performed in a dry atmosphere in which the first oxide growth layer 130 is formed on the device layer 116. In some embodiments, the first high-temperature thermal oxidation is performed at a temperature in the range of about 800° C. to about 1200° C., more preferably at a temperature of about 1100° C. This process can result in a high-quality oxide. In some specific embodiments, for example when the device layer 116 comprises undoped silicon, the first oxide growth layer 130 comprises silicon dioxide, however other oxides are possible without departing from the spirit and scope of the present invention. The thickness of the first oxide growth layer 130 should preferably be equal to or greater than the depth of the holes 126, 128 defined in the device layer 116.

[0041] Referring now to FIG. 8, chemical mechanical planarization (CMP) is performed to remove the remaining oxide growth layer 130 until it reaches the same height as the outer surface 118 of the device layer 116. In other words, after this planarization step, the first oxide growth layer 130 is filled only within the holes 126, 128 defined in the device layer 116.

[0042] Next, referring to FIG. 9, a second resist pattern 140 is deposited onto the current planar surface formed from the outer surface 118 of the device layer 116 and the remaining portions of the first oxide growth layer 130 filled within the holes 126, 128 defined in the device layer 116. The second resist pattern 140 defines an opening 142 that passes through the resist 140. In this exemplary embodiment, the opening 142 is provided only above the location where the post 154 is to be formed (i.e., above the post hole 128) so as to expose the first oxide growth layer 130 at the bottom. Also, the second resist pattern 140 serves as a second photolithography mask.

[0043] Next, referring to FIG. 10, complete etching of the oxide filling the post hole 128 is performed. In some preferred embodiments, this etching is carried out by chemical etching (e.g., HF etching), but other etching means are also possible without departing from the spirit and scope of the present invention. When the etching is complete, the resist 140 is removed, and the post hole 128 is empty while the device layer 116 remains in a state where the anchor hole 126 is still filled with the first oxide growth layer 130 as shown in FIG. 9.

[0044] Next, referring to FIG. 11, a second high-temperature thermal oxidation is performed in a dry atmosphere to form a second oxide growth layer 150 on the device layer 116. In some embodiments, the second high-temperature thermal oxidation is performed at a temperature in the range of about 800° C. to about 1200° C., more preferably at a temperature of about 1100° C. In some specific embodiments, for example, when the device layer 116 includes undoped silicon, the second oxide growth layer 150 includes silicon dioxide, but other oxides are also possible without departing from the spirit and scope of the present invention. The thickness of the second oxide growth layer 150 is preferably the same as or higher than the height of the non-embedded portion of the final anchor 152.

[0045] Next, referring to FIG. 12, a third resist pattern 160 having openings everywhere except above the locations where the post 154 and the anchor 152 are to be formed is deposited on the upper surface of the oxide growth layer 150. In other words, the third resist 160 is disposed only above the anchor hole 126 and the post hole 128. The lateral dimension of the third resist pattern 160 defines the lateral dimension at the outer surface of the second oxide growth layer 150 that will ultimately form the anchor 152 and the post 154. In particular, in some exemplary embodiments, the third resist pattern 160 can be made slightly narrower than each of the anchor hole 126 and the post hole 128. The third resist pattern 160 serves as a third photolithography mask.

[0046] Referring to FIG. 13, etching is performed to remove all of the unmasked oxide. In some preferred embodiments, this etching is performed by plasma etching. In any case, this etching preferably removes the unmasked oxide growth layer 150 down to the device layer 116, resulting in the formation of an anchor 152 partially embedded within the anchor hole 126 of the device layer 116 and a post 154 partially embedded within the post hole 128 of the device layer 116. As described above, in some exemplary embodiments, the third resist 160 is slightly narrower than each of the post holes 128. Therefore, the plasma etching creates a gap between the sidewall of the post 154 and the inner wall of the post hole 128. Similarly, in some exemplary embodiments, the third resist 160 is also slightly narrower than each of the anchor holes 126 such that a similar gap exists between the sidewall of the anchor 152 and the inner wall of the anchor hole 126. In embodiments where the lateral dimension of the third resist 160 is the same size as the anchor holes 126 and the post holes 128, such a gap is not formed and the oxide growth layer 150 is etched down to the outer surface 118 of the device layer 116. Further, of course, the oxide can be etched to various thicknesses by selective etching, and in some embodiments, this thickness can create a gap between the sidewall of the post 154 and the inner sidewall of the post hole 128, as well as the gap between the sidewall of the anchor 152 and the inner sidewall of the anchor hole 126 as described above. In other embodiments where the etching is not selective, other shapes may result due to the oxide being etched uniformly over a given distance. For example, in non-selective etching, a gap can form around the post but not around the anchor. In practice, depending on the relevant dimensions (e.g., the width of the holes defined in the device layer, the thickness of the oxide layer, and the width of the resist), a step may be formed in the anchor, where the lower portion of the anchor is the width of the anchor hole and the upper portion of the anchor is the narrower width of the resist formed over the anchor hole.

[0047] In any case, when the etching is completed, the resist 160 is removed, and the device layer 116 having the anchors 152 and posts 154 shown in FIG. 13 remains.

[0048] Referring now to FIG. 14, a second CMP is performed on the anchors 152. This planarization step reduces the height of the anchors to define the height of the vacuum cavities of the CMUTs 180, while at the same time providing the best planarization and surface roughness of the anchors 152. Depending on the application, the height of the anchors 152 (and thus the height of the cavities) is reduced to a range from several tens of nanometers to several hundreds of nanometers, but in all examples, the height of the anchors 152 is higher than the height of the posts 154.

[0049] Referring now to FIG. 15, the SOI 110 of FIG. 14, i.e., the handle 112 having the partially buried anchors 152 and posts 154, the BOX layer 114, and the device layer 116, is inverted, and the anchors 152 are bonded (e.g., fused) onto a lower wafer of silicon doped at a high concentration (i.e., the lower electrode 172). The handle 112 and the BOX layer 114 are removed, and the upper electrode 174 is deposited on the device layer 116. Thereby, a final CMUT 180 is obtained having a lower electrode 172, an upper electrode 174, and a membrane 116 (i.e., the device layer 116) having the anchors 152 and isolation posts 154 formed on the membrane 116 and partially buried within the membrane 116.

[0050] It should be noted that by varying the thickness of the device layer 116, the duration of the two oxidations, the depth of the two (D)RIEs, and the duration of the CMP, the desired height of the anchors (i.e., the height of the cavities), the desired height of the posts, and the desired lateral dimensions of both the anchors and the posts buried within the membrane can be defined.

[0051] Second Embodiment According to a second exemplary method of manufacturing a CMUT of the second embodiment of the present invention, referring now to FIG. 16, the process begins with a conventional SOI wafer 210 having, from bottom to top, a handle 212, a buried oxide (BOX) layer 214, and a device layer 216 with an exposed outer surface 218. In some exemplary embodiments, the device layer 216 is an undoped silicon layer 216.

[0052] Referring now to FIG. 17, a first resist pattern 220 having an opening 222 defined therethrough to expose the outer surface 218 of the device layer 216 is deposited on the outer surface 218 of the device layer 216. As will be described later, the isolation posts 254 and the anchors 252, which are features of the CMUT 280, are formed at the positions of the openings 222 of the first resist pattern 220. In particular, the lateral dimensions of the posts 254 and the anchors 252, which will be described later, are determined at this point. Note that the first resist pattern 220 corresponds to a first photolithography mask.

[0053] Referring next to FIG. 18, a first (deep) reactive ion etching, i.e., (D)RIE, is performed on the outer surface 218 of the device layer 216 to form an anchor hole 226 and a post hole 228 that extend partially into the device layer 216 at positions corresponding to the openings 222 of the resist 220 shown in FIG. 17. When the holes 226, 228 are formed, the resist 220 is removed, leaving the device layer 216 having the holes 226, 228 shown in FIG. 18.

[0054] According to some exemplary embodiments, the widths of the isolation posts 254 and the anchors 252 to be formed are determined in this step by the dimensions of the holes 226, 228 defined in the device layer 216. Similarly, the depths of the holes 226, 228 determine the depths of the portions of the final posts 254 and the anchors 252 that are embedded within the device layer 216.

[0055] The deep etching of these holes 226, 228 within the device layer 216 increases the isolation of the ultimately obtained posts / anchors, but also reduces the mechanical strength of the ultimately obtained membrane. Thus, the depth of the holes 226, 228 is typically kept less than about 80% of the thickness of the device layer 116. The lateral dimension of the holes 226, 228 is calculated by adding n times the lateral dimension of the non-embedded portion of the ultimately remaining anchor or post to the depth of the holes, where n is typically a factor of about 2.0.

[0056] Referring now to FIG. 19, a first oxide growth layer 230 is formed on the device layer 216 so as to fill each of the holes 226, 228 and cover the outer surface 218 of the device layer 216. In particular, in some preferred embodiments, high-temperature dry oxidation is performed on the entire SOI wafer (i.e., the handle 212, the BOX layer 214, and the device layer 216) in a dry atmosphere to form the first oxide growth layer 230. The thickness of the first oxide growth layer 230 is equal to or greater than the height of the non-buried portion of the ultimately obtained anchor 252. In some embodiments, the high-temperature thermal oxidation is performed at a temperature in the range of about 800°C to about 1200°C, more preferably about 1100°C.

[0057] Referring now to FIG. 20, chemical mechanical planarization (CMP) is performed to planarize the first oxide growth layer 230. The distance between the upper surface 218 of the device layer 216 and the upper surface 232 of the planarized first oxide growth layer 230 defines the height of the final anchor 252. Depending on the application, the height of the anchor is typically in the range of several tens of nanometers to several hundreds of nanometers.

[0058] Referring now to FIG. 21, a second resist pattern 240 is deposited on the upper surface 232, which is the current planar surface of the first oxide growth layer 230. The second resist pattern 240 is disposed only at locations where the isolation posts 254 and the anchors 252 are to be formed. Accordingly, the resist pattern 240 corresponds to the lateral dimensions of the final posts 254 and anchors 252. The second resist pattern 240 serves as a second lithography mask.

[0059] Referring next to FIG. 22, plasma etching is performed to the outer surface 218 of the device layer 216 to remove the first oxide growth layer 230 not covered by the second resist pattern 240. After the etching step, the second resist pattern is then stripped, leaving the finally obtained anchors 252 and the finally obtained isolation posts 254 together with the cavities between the plurality of anchors 252.

[0060] Referring now to FIG. 23, a third resist pattern 260 having openings only at locations where the isolation posts 254 are to be partially etched is deposited. That is, the third resist pattern 260 covers the exposed outer surface 218 of the device layer 216 and the anchors 252, but does not cover the posts 254. The third resist pattern 260 corresponds to a third photolithography mask.

[0061] Referring next to FIG. 24, a second plasma etching (i.e., partial etching) is performed to lower the height of the posts 254. After this etching step, the third resist 260 is stripped, leaving the final anchors 252 and posts 254 having a height difference between the outer surface (or contact surface) of the posts 254 and the outer surface of the anchors 252 that defines the gap of the CMUT device 280 (i.e., the maximum displacement of the membrane 216).

[0062] Referring now to FIG. 25, the SOI 210, i.e., the handle 212, the BOX layer 214, and the device layer 216 having the partially buried anchors 252 and posts 254, is inverted, and the anchor 252 is bonded (e.g., fused) onto a lower wafer of highly doped silicon (i.e., the lower electrode 272), the handle 212 and the BOX layer 214 are removed, and the upper electrode 274 is deposited. As a result, a final CMUT 280 is obtained having the lower electrode 272, the upper electrode 274, the membrane 216 (i.e., the device layer 216), and the anchors 252 and isolation posts 254 formed on the membrane 216 and partially buried within the membrane 216.

[0063] When compared to the first method of the present invention described above with reference to FIGS. 4 - 15, the second exemplary method of the present invention requires fewer steps and is simpler. The resulting CMUT 280 maintains all the advantages of the CMUT 180 manufactured according to the first embodiment, except that the contact surface of the isolation post 254 is partially etched, and this etching may deteriorate the contact surface of the post 254 and inject charges.

[0064] Third Embodiment A third exemplary method of manufacturing a CMUT according to the third embodiment of the present invention is a simplified variant that includes fewer intermediate steps. In the third method, only two photolithography masks are used. In addition, since an oxide layer is obtained with only one oxidation step, there is an advantage of obtaining a higher quality oxide layer. Further, in the third embodiment, the partial etching step is avoided.

[0065] Referring now to FIG. 26, the third method starts with a conventional SOI wafer 310 including, from bottom to top, a handle 312, a buried oxide (BOX) layer 314, and a device layer 316 having an exposed outer surface 318. In some exemplary embodiments, the device layer 316 is an undoped silicon layer 316.

[0066] Next, referring to FIG. 27, a first resist pattern 320 having an opening 322 defined by penetrating through the resist 320 is deposited on the outer surface 318 of the device layer 316 to expose the outer surface 318 of the device layer 316. As will be described later, the isolation post 354 is formed at the position of the opening 322 of the first resist pattern 320. Different from the first and second embodiments, the opening of the first resist pattern 320 does not correspond to the position of the anchor 352. The first resist pattern 320 corresponds to the first photolithography mask.

[0067] Referring now to FIG. 28, partial dry etching (i.e., reactive ion etching) is performed on the outer surface 318 of the device layer 316 to form the well 328. The depth of the well 328 directly becomes the final gap height (i.e., the maximum vertical displacement of the membrane 316 before contacting the lower electrode 372). The lateral dimension of the well 328 corresponds to the lateral dimension of the final cavity in which the post 354 is embedded. When the well 328 is formed, the resist 320 is peeled off, leaving the device layer 316 having the well 328 shown in FIG. 28.

[0068] Next, referring to FIG. 29, an oxide growth layer 330 is formed on the device layer 316 so as to fill each of the wells 328 and cover the outer surface 318 of the device layer 316. In particular, in some preferred embodiments, high-temperature dry oxidation is performed on the entire SOI wafer (i.e., the handle 312, the BOX layer 314, and the device layer 316) in a dry atmosphere to form the oxide growth layer 330. In some embodiments, the high-temperature thermal oxidation is performed at a temperature in the range of about 800 °C to 1200 °C, more preferably about 1100 °C. The thickness of the oxide growth layer 330 corresponds to the height of the final anchor 352.

[0069] Here, referring to FIG. 30, a second resist pattern 340 is applied on the oxide growth layer 330. The second resist pattern 340 is disposed only at locations where the isolation posts 354 and the anchors 352 are to be formed. Therefore, the resist pattern 340 corresponds to the lateral dimensions of the final posts 354 and anchors 352. The second resist pattern 340 serves as the second lithography mask.

[0070] Next, referring to FIG. 31, the oxide growth 330 is patterned by high anisotropic plasma etching to remove the oxide growth layer 330 not covered by the second resist pattern 340 down to the device layer 216. After the etching step, next, the second resist pattern 340 is removed, leaving the finally obtained anchors 352 and the finally obtained isolation posts 354 partially embedded in the wells 328 between the plurality of anchors 352.

[0071] Next, referring to FIG. 32, the SOI 310 (i.e., the handle 312 with the anchors 352 and the partially embedded posts 354, the BOX layer 314, and the device layer 316) is inverted, and the anchors 352 are bonded (e.g., fused) onto the lower wafer of highly doped silicon (i.e., the lower electrode 372), the handle 312 and the BOX layer 314 are removed, and the upper electrode 374 is deposited. As a result, a final CMUT 380 is obtained having the lower electrode 372, the upper electrode 374, the membrane 316 (i.e., the device layer 316), and the anchors 352 and isolation posts 354 formed on the membrane 316 and partially embedded in the membrane 316.

[0072] As a result of simplifying the process in this way, the height of the isolation posts 354 is the same as the height of the anchors 352. Therefore, the parasitic capacitance in the anchors 352 is not reduced.

[0073] Comparison of Embodiments As reflected in Table 1 below, the first exemplary method requires four photolithography masks, has no partial etching of silicon dioxide (e.g., the ultimately obtained anchors 152 and isolation posts 154), reduces the parasitic capacitance in the anchors 152, and involves growing silicon dioxide (e.g., oxide growths 130, 150) on an undoped silicon layer (e.g., device layer 116). Further, the second exemplary method requires three photolithography masks, results in partial etching of silicon dioxide (e.g., the ultimately obtained anchors 252 and isolation posts 254), reduces the parasitic capacitance in the anchors 252, and involves growing silicon dioxide (e.g., oxide growth 230) on an undoped silicon layer (e.g., device layer 216). The third exemplary method requires two photolithography masks, has no partial etching of silicon dioxide (e.g., the ultimately obtained anchors 352 and isolation posts 354), does not reduce the parasitic capacitance in the anchors 250, and involves growing silicon dioxide (e.g., oxide growth 330) on an undoped silicon layer (e.g., device layer 316).

[0074]

Table 1

[0075] Partially Embedded Post Most of the features expected to improve the performance of the CMUT device of the present invention and reduce charge trapping are due, at least in part, to the partially buried posts and the protection guard rings used to avoid electrical breakdown from the sides of the posts.

[0076] Next, referring to FIGS. 33A and 33B showing an isolation post 454, which is an example of one or more of the posts 154, 254, 354 described above, as illustrated, the post 454 is partially buried within the membrane 416 so as to be spaced from the upper electrode 474. The post 454 includes a central member 456 surrounded by a guard ring 458.

[0077] The central member 456 of the post 454 of the present invention is partially embedded within the membrane 416 as described above and is configured to be surrounded by a guard ring 458 for enhancing protection. This particular topology is a novel invention. This new post 454 (i.e., the central member 456 and the guard ring 458) has an overall mushroom-like shape. During the thermal oxidation of the silicon layer (e.g., the formation of the oxide growth layers 130, 230, 330 on the device layers 116, 216, 316 described above), when this process is carried out in dry oxygen, it has been found that the horizontal and vertical planes of the silicon layer change to smooth oxides. This is mainly due to the non-uniform growth at the convex and concave corners of the cavities formed in the silicon layer.

[0078] As shown in FIG. 33B, this exemplary post 454 is substantially circular, but the posts of the present invention can also have a rectangular shape or any other geometric shape while still including the same overall mushroom-like shape shown in FIG. 33A. This structure can be used to fabricate not only the isolation posts 454 but also the anchors (e.g., anchors 152, 252, 352) that define the edges of the CMUT cells and cavities.

[0079] Referring now to FIGS. 34A, 34B, and 34C, in some embodiments (FIG. 34A), the guard ring 458a is made of the same material as the central member 456 of the post 454. However, depending on the main role and intended use of the post 454, the guard ring 458c can be made of a different material (FIG. 34C), or an equal empty channel 458b can be provided around the post 454 (FIG. 34B). Here, the use of the term "empty" means that the guard ring has the same composition as, for example, a vacuum / air gap.

[0080] The modification shown in FIG. 34A can be obtained, for example, by the method of the second embodiment. On the other hand, the modification shown in FIG. 34B can be obtained, for example, by the method of the first embodiment or the third embodiment. Finally, the modification of FIG. 34C only requires a very slight change in the manufacturing process. Starting from the configuration of FIG. 34B, a second material is deposited (e.g., by sputtering) over the entire outer surfaces of the membrane 416 and the post 454 to completely fill the empty guard ring 458b. Next, this second material is removed in a partial selective etching step except in the region of the guard ring, leaving a guard ring 458c made of the second material.

[0081] Some exemplary materials for use as a guard ring belong to the category of solid insulating materials such as silicon nitride, metal oxides (e.g., aluminum oxide, zirconium oxide, hafnium oxide), or any other dielectric material used in the semiconductor industry, and these prepared materials are deposited by a deposition process and partially removed by a selective etching process, i.e., this etching step does not remove the material of the central member 456 or the membrane 416 as described above.

[0082] In a traditional CMUT structure (e.g., CMUT 10 shown in FIG. 1A), the capacitance of the device is given by Equation 1.

[0083]

Equation

[0084] Here, h gap is the height of the cavity (i.e., the distance between the membrane and the insulating layer 12), h iso is the height of the insulating layer 12, S is the total surface area of the membrane, ε 0 is the permittivity of free space, and ε iso is the permittivity of the insulating layer.

[0085] For a CMUT cell designed with traditional isolation posts (e.g., CMUT 20 shown in FIG. 1B), the capacitance is given by Equation 2.

[0086] [Number]

[0087] Here, S 2 is the entire surface of post 22, and S 1 is equal to S minus S 2 . Since S 1 > S 2 (S 1 ≈ S), the second term can be reasonably ignored. Therefore, in this acoustic structure (where S and h gap are the same), it can be easily seen that by using traditional isolation posts such that h gap + h iso > h gap + h iso / ε iso , the capacitance of the device decreases. Furthermore, since a sufficient height is required to avoid breakdown of the post, the thickness h iso of the insulating layer cannot be further reduced.

[0088] In the partially embedded isolation posts of the present invention, referring again to FIG. 33A, while maintaining the total height (h iso ) of post 454 that is high enough to avoid breakdown, the height (h exceed ) of post 454 protruding from the membrane can be reduced. This is achieved by increasing the height (h buried ) of post 454 embedded in membrane 416. In such a structure, the capacitance can be maintained, or if h exceed < h gap + h iso / ε iso , the capacitance can also be increased.

[0089] Furthermore, h exceed can be arbitrarily increased while keeping h buried at a low value. This means that the total height h isoIt means that it can be made larger than that used in the traditional structure (e.g., FIGS. 1A and 1B), and thus, the electric field across the isolation post can be significantly reduced. It is well known that the trapping of charges is directly related to the electric field across the dielectric material. Therefore, this new structure allows the use of tall isolation posts without degrading the overall performance and can reduce the charging phenomenon.

[0090] Finally, when the isolation post is embedded in the membrane, it is necessary to keep in mind that dielectric breakdown may occur at the interface between the isolation post and the membrane on the side surface of the isolation post. This restricts the reduction of h exceed To solve this problem, the present invention proposes the use of a guard ring. In the use of the guard ring, dielectric breakdown is avoided when the shortest distance between the potential of the upper electrode and the potential of the lower electrode is sufficiently large. In other words, referring back to FIG. 33A, even in the worst case where the isolation post is in contact with the bottom of the cavity (i.e., the lower electrode), the distance from each point on the end face of the central member 456 of the post 454 (i.e., the contact surface of the post 454) to each point on the embedded surface of the guard ring 458 of the post 454 must be large enough to avoid dielectric breakdown (see FIG. 33B). This can be ensured by using the guard ring 458. Furthermore, since the embedded surface of the guard ring 458 has a natural round shape, this structure can significantly reduce the risk of the lightning rod effect.

[0091] In some configurations, the structure of the partially embedded post 360 described above can be used together with the anchors (e.g., anchors 152, 252, 352) that define the CMUT cell and, in some cases, has a vacuum guard ring. In this case, the membrane near the anchor of the cell is significantly thinner than the central part of the membrane. This can be utilized to cause a piston-like displacement of the membrane in order to reduce the stiffness of the membrane adjacent to the anchor. This improves the transmission sensitivity of the device.

[0092] In particular, referring to FIG. 35, different possible configurations of the partially embedded anchor are shown, which can be used to cause a piston-like displacement of the membrane. Each configuration shown in FIG. 35 only shows the right side of the cell, but the same structure is equally applicable to the left side of the cell.

[0093] Configuration I shows a traditional anchor where the membrane has a uniform thickness.

[0094] Configuration II shows one anchor of the present invention having a vacuum guard ring.

[0095] Configuration III shows another anchor of the present invention similar to Configuration II, but the vacuum guard ring has a greater width.

[0096] Configuration IV shows another anchor of the present invention similar to Configuration II, but the silicon membrane remaining on the anchor has a thinner thickness.

[0097] Configuration V shows another anchor of the present invention similar to Configuration IV, but the upper electrode is patterned to improve the piston-like displacement.

[0098] The above description of the partially embedded isolation posts and anchors is provided with respect to capacitive microfabricated ultrasonic transducers, but it is contemplated that similar structures and concepts are applicable to other capacitive MEMS as well.

[0099] Those skilled in the art will recognize that additional embodiments are possible without departing from the teachings of the present invention. This detailed description, particularly the specific details of the exemplary embodiments disclosed therein, is provided primarily for clarity of understanding, and it is apparent that those skilled in the art reading this disclosure can make modifications without departing from the spirit or scope of the present invention, so no unnecessary limitations are to be understood from this disclosure.

[0100] References [1] Y. Huang, E. O. Haeggstrom, X. Zhuang, A. S. Ergun, and B. T. Khuri-Yakub, "Solutions to the Charging Problem of Capacitive Micromachined Ultrasonic Transducers", IEEE Trans. Ultrason. Ferroelectr. Freq. Control, vol. 52, no. 4, pp. 578-80, Apr. 2005. [2] Y. Huang, X. Zhuang, E. O. Haeggstrom, a. S. Ergun, C. H. Cheng, and B. T. Khuri-Yakub, "Capacitive Micromachined Ultrasonic Transducers (CMUTs) with Isolation Posts", Ultrasonics, vol. 48, no. 1, pp. 74-81, 2008. [3] Y. Huang and B. T. Khuri-yakub, "Capacitive Ultrasonic Transducer with Isolation Posts", 2009. [4] S. Machida, H. Enomoto, Y. Tadaki, and T. Nagata, "Ultrasonic Transducer and Method of Manufacturing the Same", Publication n° US8198782, 2012. [5] S. Machida, T. Takezaki, T. Kobayashi, H. Tanaka, and T. Nagata, "Highly Reliable CMUT Cell Structure with Reduced Dielectric Charging Effect", in IEEE International Ultrasonics Symposium, IUS, 2015, pp. 1-4. [6] B. Greenlay and R. Zemp, "CMUT Isolated by Isolation Posts", in 2017 IEEE International Ultrasonics Symposium. [7] M. M. Mahmud et al., "Improved CMUT Structure and Dual-Frequency Acoustic Angiography Operation Method" in 2017 IEEE International Ultrasonics Symposium, no. 1160483, pp. 2-5. [8] J. Klootwijk, P. Dirksen, M. Mulder, and E. Moonen, "Capacitive Micromachined Ultrasonic Transducer", US20150162851A1, 2015 [9] A. S. Savoia, B. Mauti, G. Caliano, L. Maiolo, A. Minotti, and A. Pecora, "Optimization of Efficiency and Reliability of Inverse-Processed CMUT Arrays" in 2017 IEEE International Ultrasonics Symposium.

Claims

1. A capacitive microfabricated ultrasonic transducer comprising a lower electrode, an upper electrode, a membrane disposed between the lower electrode and the upper electrode and attached to the upper electrode, a plurality of anchors connected to the membrane and the lower electrode so that a cavity is defined between the lower electrode and the membrane, and one or more insulating isolation posts disposed within the cavity, wherein a portion of the isolation post is embedded within the membrane and extends towards the lower electrode, there is no material present between the lower end of the isolation post and the lower electrode, the membrane is made of a first material, and the anchors and the isolation posts are made of a second material.

2. The capacitive microfabricated ultrasonic transducer according to claim 1, wherein a portion of the anchor is embedded within the membrane.

3. The capacitive microfabricated ultrasonic transducer according to claim 2, wherein each of the plurality of anchors includes a central member partially embedded within the membrane and extending to the lower electrode, and a guard ring embedded within the membrane and surrounding the central member.

4. The capacitive microfabricated ultrasonic transducer according to claim 1, wherein each of the plurality of isolation posts includes a central member partially embedded within the membrane and extending towards the lower electrode, and a guard ring embedded within the membrane and surrounding the central member.

5. The capacitive microfabricated ultrasonic transducer according to claim 4, wherein the central member and the guard ring are made of the same material.

6. The capacitive microfabricated ultrasonic transducer according to claim 4, wherein the central member is made of a second material and the guard ring is made of a third material.

7. The capacitive microfabricated ultrasonic transducer according to claim 1, wherein each of the plurality of isolation posts includes a central member partially embedded within the membrane and extending towards the lower electrode, and an empty guard ring defined by the membrane surrounding the central member.

8. The capacitive microfabricated ultrasonic transducer according to claim 1, wherein the lower electrode is a highly doped silicon wafer.

9. The membrane defines a plurality of post holes that partially extend inside the membrane, The capacitive microfabricated ultrasonic transducer according to claim 1, wherein one of the isolation posts of the one or more insulators is located inside each of the plurality of post holes so as to extend outside the post holes.

10. The capacitive microfabricated ultrasonic transducer according to claim 9, wherein a gap is formed between the side walls of each of the isolation posts of the one or more insulators and the inner walls of each of the post holes.

11. A method for manufacturing a capacitive microfabricated ultrasonic transducer according to claim 1, comprising: preparing a device layer of undoped silicon having an exposed outer surface; etching the outer surface of the device layer to form post holes that partially extend into the device layer; forming an oxide growth layer on the device layer so as to cover the outer surface of the device layer and fill the post holes; removing a part of the oxide growth layer to form a plurality of anchors that extend beyond the outer surface of the device layer and a plurality of isolation posts of insulators that are partially embedded inside the post holes and extend beyond the outer surface of the device layer; adhering the plurality of anchors to a first electrode to form a cavity defined by the first electrode, the device layer, and the anchors, and disposing the isolation posts within the cavity; depositing an upper electrode on the surface of the device layer opposite to the outer surface of the device layer. A method for manufacturing a capacitive microfabricated ultrasonic transducer.

12. The method according to claim 11, wherein the outer surface of the device layer is etched to form anchor holes that partially extend into the device layer, and the anchors are partially embedded inside the anchor holes.

13. The method according to claim 11, wherein the step of forming the oxide growth layer on the device layer is performed by high-temperature thermal oxidation of the device layer.

14. The method according to claim 13, wherein the high-temperature thermal oxidation is performed in a temperature range of 800°C to 1200°C.

15. The method according to claim 11, wherein the oxide growth layer is formed to a thickness greater than or equal to the depth of the post holes.

16. The method according to claim 11, wherein the oxide growth layer is formed to a thickness greater than or equal to the height of the anchor.

17. The method according to claim 11, further comprising the step of planarizing the oxide growth layer.

18. The method according to claim 17, wherein the oxide growth layer is planarized until it reaches the same height as the outer surface of the device layer.

19. The method according to claim 17, wherein the oxide growth layer is planarized until the oxide growth layer has the same thickness as the height of the anchor.

20. The method according to claim 11, wherein the step of removing a portion of the oxide growth layer includes the step of plasma etching the oxide growth layer to form the anchor and the isolation post.

21. The method according to claim 18, further comprising the step of chemically etching the oxide growth layer outside the post hole.

22. The method further comprises forming a second oxide growth layer on the device layer so as to fill the post hole and cover the outer surface of the device layer. The method according to claim 21, wherein a portion of the second oxide growth layer is removed to form the anchor and the isolation post.

23. The method according to claim 21, further comprising the step of planarizing the anchor.

24. The method according to claim 11, further comprising the step of plasma etching the isolation post to reduce the height of the isolation post until it is lower than the height of the anchor.

Images