Tampering Detection Circuit and Tampering Detection Method

Abstract

To detect falsification of wiring and insertion of a malicious circuit that extracts noise signals superimposed on a power supply in order to analyze an encryption key.SOLUTION: An alteration detection circuit 20A of an IC chip 1A measures and stores a first noise waveform of a power supply voltage of a digital circuit 10A and a power supply circuit 30A when the digital circuit 10A performs a predetermined operation. Then, the alteration detection circuit 20A receives the second noise waveform measured in the IC chip 1B via a noise waveform data sharing bus B1, and calculates a cross-correlation value between the first noise waveform stored in the alteration detection circuit 20A and the received second noise waveform. When the calculated cross-correlation value is equal to or greater than a predetermined threshold compared with the past cross-correlation value, it is possible to detect falsification of wiring and insertion of a malicious circuit.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a forgery detection circuit and a forgery detection method capable of efficiently detecting fraud associated with the insertion of a malicious circuit (hereinafter referred to as a "malicious circuit") or the like.

Background Art

[0002] Conventionally, there are known fraudulent techniques of applying an illegal voltage to the power supply of a board on which an IC (Integrated Circuit) chip is mounted to malfunction the circuit, or reading an internal signal such as power supply noise to extract an encryption key.

[0003] For example, Patent Document 1 discloses a technique of a backside embedded wiring structure that prevents security attacks such as noise observation and fault injection through the backside silicon substrate of an IC chip and detects a physical attack from the backside, that is, an exposure attack.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in the case of the above Patent Document 1, when a plurality of IC chips are mounted on a substrate and a malicious circuit is inserted into a power supply wiring that supplies power to each IC chip, the insertion of the malicious circuit cannot be detected and there is a possibility that an internal signal is extracted from the power supply noise flowing through the power supply wiring. For this reason, how to efficiently detect fraud associated with the insertion of a malicious circuit or the like has become an important issue.

[0006] The present invention has been made to solve the above-described problems (issues) of the prior art, and an object thereof is to provide a forgery detection circuit and a forgery detection method that can efficiently detect fraud associated with the insertion of a malicious circuit or the like.

Means for Solving the Problem

[0007] In order to solve the above-described problems and achieve the object, the present invention includes a first IC chip having at least a first digital circuit and a first power supply circuit that supplies voltage to the first digital circuit, and a second digital circuit and a second power supply circuit that supplies voltage to the second digital circuit. A forgery detection circuit for detecting forgery of a substrate on which the first digital circuit and the second digital circuit perform a predetermined operation, the first measurement circuit measuring a first noise signal superimposed on the voltage supplied to the first power supply circuit, and the first measurement circuit A first storage circuit that stores the first noise waveform measured by the second measurement circuit, a second measurement circuit that measures a second noise signal superimposed on the voltage supplied to the second power supply circuit, and a second storage circuit that stores the second noise waveform measured by the second measurement circuit, and the first noise waveform is received, and a calculation circuit that calculates a correlation between the received first noise waveform and the second noise waveform, and based on the correlation, the substrate And a determination circuit for determining the presence or absence of forgery of the substrate.

[0008] Further, in the present invention, the calculation circuit calculates a cross-correlation value between the first noise waveform and the second noise waveform.

[0009] Further, in the present invention, the second storage circuit stores a past cross-correlation value calculated by the calculation circuit, and the determination circuit calculates a difference between the cross-correlation value calculated by the calculation circuit and the past cross-correlation value stored in the second storage circuit. When the value is equal to or greater than a predetermined threshold value, it is determined that forgery of the substrate has been performed.

[0010] Further, in the present invention, in the above invention, when the difference between the cross-correlation value calculated by the calculation circuit and the past cross-correlation value stored in the second storage circuit is equal to or greater than a predetermined threshold value, it is determined that there may be a malicious circuit inserted into the common power supply line to which the first power supply circuit and the second power supply circuit are connected.

[0011] Further, in the present invention, in the above invention, the first measurement circuit measures the first noise waveform upon receipt of a reset signal input to the digital circuit of the first IC chip, and the second measurement circuit measures the second noise waveform upon receipt of a reset signal input to the digital circuit of the first IC chip.

[0012] Further, in the present invention, in the above invention, the apparatus further includes a generation circuit that generates predetermined test data, and causes the first digital circuit and the second digital circuit to perform a predetermined operation by inputting the test data thereto.

[0013] Further, in the present invention, in the above invention, the calculation circuit includes a plurality of low-pass filter circuits each having a different cut-off frequency and removing high-frequency components from the first noise waveform based on the cut-off frequency, and a plurality of correlation value calculation circuits that calculate correlation values between a plurality of third noise waveforms from which high-frequency components have been removed from the first noise waveform by the plurality of low-pass filter circuits and the second noise waveform, respectively, and calculates a cut-off frequency at which the correlation value is maximized from the correlation values respectively calculated by the plurality of correlation value calculation circuits.

[0014] Further, in the present invention, in the above invention, the first measurement circuit and the first storage circuit are formed in the first IC chip, and the second measurement circuit, the second storage circuit, the calculation circuit, and the determination circuit are formed in the second IC chip.

[0015] Further, the present invention relates to a forgery detection method in a forgery detection circuit that detects forgery of a substrate on which a first IC chip having at least a first digital circuit and a first power supply circuit that supplies voltage to the first digital circuit, and a second IC chip having a second digital circuit and a second power supply circuit that supplies voltage to the second digital circuit are mounted. The method includes: a first measurement step in which the first IC chip measures a first noise signal superimposed on the voltage supplied to the first power supply circuit; a first storage step in which the first IC chip stores the first noise waveform measured in the first measurement step in a first storage circuit; a second measurement step in which the second IC chip measures a second noise signal superimposed on the voltage supplied to the second power supply circuit; a second storage step in which the second IC chip stores the second noise waveform measured in the second measurement step in a second storage circuit; a calculation step in which the first noise waveform is received and the correlation between the received first noise waveform and the second noise waveform is calculated; and a determination step in which the presence or absence of forgery of the substrate is determined based on the correlation.

Advantages of the Invention

[0016] According to the present invention, it is possible to efficiently detect fraud associated with the insertion of malicious circuits and the like.

Brief Description of the Drawings

[0017]

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[0018] Hereinafter, embodiments of the forgery detection circuit and the forgery detection method according to the present invention will be described in detail with reference to the drawings.

[0019] [Embodiment 1] <Outline of the forgery detection circuit> First, the outline of the forgery detection circuit according to Embodiment 1 will be described. In Embodiment 1, a case where a plurality of IC chips are mounted on a substrate and a malicious circuit is inserted into a common power supply line that supplies power from the outside to the power supply circuits of the respective IC chips will be described.

[0020] In recent years, there has been a threat (on-board tampering) of wiring forgery or malicious circuit insertion on a printed circuit board for the purpose of causing malfunction of a circuit or reading internal information of an IC chip on a substrate on which a plurality of IC chips are mounted. Also, inside the IC chip, there is a risk of unintentional tampering (on-chip tampering) by microfabrication technology for failure analysis.

[0021] In the first embodiment, a plurality of IC chips are mounted on a substrate. In the tampering detection circuit of the first IC chip, when the first IC chip performs a predetermined operation, the first noise waveform is measured and stored. Also, the second noise waveform when the first IC chip measured in the second IC chip performs a predetermined operation is received via the noise waveform sharing bus, and the cross-correlation value between the measured first noise waveform and the received second noise waveform is calculated. Then, by comparing the calculated cross-correlation value with the stored past cross-correlation value, it is possible to detect whether tampering has been performed on the substrate on which the IC chip is mounted.

[0022] FIG. 1 is an explanatory diagram for explaining the outline of the tampering detection circuit according to the first embodiment. As shown in FIG. 1, the IC chip 1A and the IC chip 1B are mounted on the interposer 40. The interposer 40 is a substrate used to expand the input / output terminals arranged at a fine interval of the IC chip to an interval at which they can be mounted on the printed circuit board. The IC chip 1A and the IC chip 1B are connected to the common power line L1 and the noise waveform data sharing bus B1 realized on the interposer 40. Also, the malicious circuit 80 is connected to the node N3 of the common power line L1 of the interposer 40.

[0023] IC chip 1A has a digital circuit 10A, a forgery detection circuit 20A, and a power supply circuit 30A. The digital circuit 10A is a circuit that can be used in a tablet terminal, a wearable device, a drone device, or an IoT terminal, etc. Further, the digital circuit 10A may include a circuit for encryption and decryption to enhance the confidentiality of signals. Also, IC chip 1B has a digital circuit 10B, a forgery detection circuit 20B, and a power supply circuit 30B.

[0024] The forgery detection circuit 20A of IC chip 1A measures and stores the first noise waveform of the power supply voltages of the digital circuit 10A and the power supply circuit 30A when the digital circuit 10A performs a predetermined operation. Then, the forgery detection circuit 20A receives, via the noise waveform data sharing bus B1, the second noise waveform measured in the forgery detection circuit 20B of IC chip 1B when the digital circuit 10A performs a predetermined operation, and calculates the cross-correlation value between the first noise waveform stored in the forgery detection circuit 20A and the received second noise waveform. When the calculated cross-correlation value is equal to or greater than a predetermined threshold compared with the past cross-correlation values, it is determined that forgery has been performed.

[0025] Specifically, the forgery detection of the common power supply line L1 that supplies power to the power supply circuits 30A and 30B of IC chip 1A and IC chip 1B will be described. IC chip 1A and IC chip 1B are each supplied with power to their respective power supply circuits 30A and 30B by the common power supply line L1 on the interposer 40. The forgery detection circuit 20A measures and stores the first noise waveform at the node N1 on the common power supply line L1 of the power supply circuit 30A when the digital circuit 10A performs a predetermined operation. Then, the forgery detection circuit 20B measures and stores the second noise waveform at the node N2 on the common power supply line L1 of the power supply circuit 30B when the digital circuit 10A performs a predetermined operation. Thereafter, the forgery detection circuit 20A receives, via the noise waveform data sharing bus B1, the second noise waveform of the node N2 stored in the forgery detection circuit 20B, calculates the cross-correlation value between the first noise waveform of the node N1 stored in the forgery detection circuit 20A and the received second noise waveform of the node N2, and stores it.

[0026] The impedances of node N1 and node N2 on the common power line L1 are different before the malicious circuit 80 is connected and when the malicious circuit 80 is connected at node N3 due to the influence of the malicious circuit 80. Therefore, since the first noise waveform measured at node N1 and the second noise waveform measured at node N2 are different from the case where there is no malicious circuit 80, the cross-correlation value calculated by the forgery detection circuit 20A indicates a value different from the cross-correlation value when the malicious circuit 80 is not connected. Then, by comparing the past cross-correlation value when the malicious circuit 80 is not connected with the cross-correlation value when the malicious circuit 80 is connected, it is possible to detect that forgery has been performed on the common power line L1 when the difference in the cross-correlation values is equal to or greater than a predetermined threshold value.

[0027] Also, since the operations of the forgery detection circuit 20A of the IC chip 1A and the forgery detection circuit 20B of the IC chip 1B are interchangeable, based on the result of forgery detection performed by the forgery detection circuit 20A of the IC chip 1A and the result of forgery detection performed by the forgery detection circuit 20B of the IC chip 1B, it is also possible to improve the accuracy of forgery detection by mutually detecting forgery.

[0028] <Configuration of forgery detection circuit> Next, the configuration of the forgery detection circuit 20A will be described. FIG. 2 is a configuration diagram showing the configuration of the forgery detection circuit 20A shown in FIG. 1. As shown in FIG. 2, the forgery detection circuit 20A includes a noise measurement circuit 21A, a noise storage circuit 24A, and a noise analysis circuit 25A. The noise measurement circuit 21A includes a plurality of measurement circuits 22A and measures, for example, the core power supply voltage, the core ground voltage, the substrate potential of the IC chip 1A, and the voltage of the common power line L1 of the power supply circuit 30A.

[0029] The noise memory circuit 24A stores the noise waveform measured by the noise measurement circuit 21A. It also stores the cross-correlation value calculated by the noise analysis circuit 25A. The noise analysis circuit 25A receives the first noise waveform measured by the noise measurement circuit 21A and the second noise waveform stored in the noise memory circuit 24B of another IC chip, for example, IC chip 1B, via the noise waveform data sharing bus B1, calculates the cross-correlation value between the received second noise waveform and the measured first noise waveform, and stores it in the noise memory circuit 24A. Further, the noise analysis circuit 25A compares the calculated cross-correlation value with the cross-correlation value stored in the past, and determines whether forgery has occurred by comparing the difference between the cross-correlation values with a threshold value.

[0030] <Noise waveform data and correlation value data> Next, the noise waveform data and correlation value data stored in the noise memory circuit 24A will be described. FIG. 3 is a diagram showing an example of the noise waveform data and correlation value data stored in the noise memory circuit 24A shown in FIG. 2. As shown in FIG. 3(a), the noise waveform data stores the time and voltage in association with the node. In FIG. 3(a), for node n, at time "t n+2 ", voltage "V n+2 ", at time "t n+1 ", voltage "V n+1 ", at time "t n ", voltage "V n ", at time "t n-1 ", voltage "V n-1 ", at time "t n-2 ", voltage "V n-2 " are associated with each other.

[0031] Also, for node k, at time "t k+2 ", voltage "V k+2 ", at time "t k+1 ", voltage "V k+1 ", at time "t k ", voltage "V k ", at time "t k-1 ", voltage "V k-1 ", at time "t k-2 ", voltage "Vk-2 shows the situation of associating with "」. Also, for node i, at time "t i+2 ", voltage "V i+2 ", at time "t i+1 ", voltage "V i+1 ", at time "t i ", voltage "V i ", at time "t i-1 ", voltage "V i-1 ", at time "t i-2 ", voltage "V i-2 ", shows the situation of associating with "」.

[0032] Also, as shown in Fig. 3(b), the correlation value data stores, for each node, the time and the correlation value in association. In Fig. 3(b), for node n, at time "t n+2 ", correlation value "C12 n+2 ", at time "t n+1 ", correlation value "C12 n+1 ", at time "t n ", correlation value "C12 n ", at time "t n-1 ", correlation value "C12 n-1 ", at time "t n-2 ", correlation value "C12 n-2 ", shows the situation of associating with "」.

[0033] Also, for node k, at time "t k+2 ", correlation value "C11 k+2 ", at time "t k+1 ", correlation value "C11 k+1 ", at time "t k ", correlation value "C11 k ", at time "t k-1 ", correlation value "C11 k-1 ", at time "t k-2 ", correlation value "C11 k-2 ", shows the situation of associating with "」. Also, for node i, at time "t i+2 ", correlation value "C11 i+2 ", at time "t i+1 ", correlation value "C11 i+1 ", at time "t i」, the correlation value "C11 i 」, the time "t i-1 」, the correlation value "C11 i-1 」, the time "t i-2 」, the correlation value "C11 i-2 」 shows the situation where they are associated. Here, the correlation value C12 represents the cross-correlation value, and the correlation value C11 represents the autocorrelation value. The autocorrelation value is, for example, for the noise waveform of the core power supply voltage of the digital circuit 10A of the IC chip 1A. The noise waveform at the time of factory shipment is stored in the noise memory circuit 24A in advance, and when the IC chip 1A is powered on, the correlation between the noise waveform at the time of factory shipment and the measured noise waveform is taken.

[0034] <Configuration of the Noise Analysis Circuit> Next, the configuration of the noise analysis circuit 25A will be described. FIG. 4 is a configuration diagram showing the configuration of the noise analysis circuit 25A shown in FIG. 2. As shown in FIG. 4, the noise analysis circuit 25A includes a noise waveform cross-correlation circuit 26A, a noise waveform autocorrelation circuit 26B, a noise waveform frequency spectrum analysis circuit 26C, and a forgery determination circuit 26D. The noise waveform cross-correlation circuit 26A is a circuit that calculates the cross-correlation value of the noise waveforms of the same measurement nodes of two IC chips, for example, the common power supply line L1. Specifically, it calculates the cross-correlation value between the first noise waveform of the node N1 of the common power supply line L1 of the IC chip 1A and the second noise waveform of the node N2 of the common power supply line L1 of the IC chip 1B received via the noise waveform data sharing bus B1, and stores it in the noise memory circuit 24A.

[0035] The noise waveform autocorrelation circuit 26B is a circuit that calculates the autocorrelation value of the noise waveform of the same measurement node on the IC chip, for example, the core power supply voltage node of the digital circuit 10A. Specifically, it calculates the autocorrelation value between the noise waveform of the core power supply voltage node of the digital circuit 10A of the IC chip 1A and the noise waveform of the core power supply voltage node of the digital circuit 10A of the past IC chip 1A, and stores it in the noise memory circuit 24A. Note that the past noise waveform may be the noise waveform measured in advance at the time of factory shipment.

[0036] The noise waveform frequency spectrum analysis circuit 26C is a circuit that analyzes the frequency spectrum of the noise waveform measured by the measurement circuit 22A. Specifically, it analyzes the frequency components included in the noise waveform, calculates the absolute value of the signal for each frequency, and stores it in the noise storage circuit 24A.

[0037] The forgery determination circuit 26D compares the correlation values and frequency spectrum data calculated by the noise waveform cross-correlation circuit 26A, the noise waveform autocorrelation circuit 26B, and the noise waveform frequency spectrum analysis circuit 26C with the past data and the measured data, and determines whether forgery has occurred based on whether the difference obtained from the comparison exceeds a predetermined threshold value.

[0038] <Measurement of Noise Waveform> Next, the measurement of the noise waveform of the noise measurement circuit 21A will be described. FIG. 5(a) is an explanatory diagram for explaining the measurement of the noise waveform of the noise measurement circuit 21A shown in FIG. 2. As shown in FIG. 5(a), the noise measurement circuit 21A has a plurality of measurement circuits 22A, and the measurement circuit 22A includes an amplifier circuit 23A, an ADC (Analog Digital Converter) 23B, and a control circuit 23C. Here, the case of measuring the noise waveform of the common power supply line L1 when the malicious circuit 80 is not connected to the common power supply line L1 that supplies power from the external power supply circuit 31A to the power supply circuit 30A will be described.

[0039] The amplifier circuit 23A amplifies the noise signal superimposed on the common power supply voltage. The ADC 23B converts the analog noise signal into a digital signal. The control circuit 23C starts the measurement of the noise waveform of the common power supply voltage triggered by the reset signal of the digital circuit 10A, and stops the operation after performing the measurement for a predetermined time. Next, the noise waveform measurement when the malicious circuit 80 is connected will be described. As shown in FIG. 5(b), the malicious circuit 80 is inserted between the power supply circuit 30A and the external power supply circuit 31A. Also in this case, the operation of the measurement circuit 22A is the same as when the malicious circuit 80 is not inserted, but since the impedance of the node N1 of the common power supply line L1 changes due to the insertion of the malicious circuit 80, the measured noise waveform also changes.

[0040] Next, the operation when the noise measurement circuit 21A measures the noise waveform will be described. FIG. 6 is a timing chart when measuring the noise waveform of the noise measurement circuit 21A shown in FIG. 2. As shown in FIG. 6, the noise waveform of the external power supply voltage is reset by the reset signal input to the digital circuit 10A when the external power supply voltage is turned on at t1 and at the time t2 when the external power supply voltage is sufficiently stabilized. Then, the measurement of the noise waveform is started from the time t3 when the reset signal rises. Since the impedance of the measurement node changes when tampering such as connecting the malicious circuit 80 is performed, the measured noise waveform is different from the noise waveform of the circuit without tampering, as shown in FIG. 6.

[0041] As described above, in the first embodiment, the tampering detection circuit 20A of the IC chip 1A measures and stores the first noise waveform of the power supply of the digital circuit 10A and the power supply circuit 30A when the digital circuit 10A performs a predetermined operation. Then, the tampering detection circuit 20A receives the second noise waveform measured when the digital circuit 10A performs a predetermined operation in the tampering detection circuit 20B of the IC chip 1B via the noise waveform data sharing bus B1, and calculates the cross-correlation value between the first noise waveform stored in the tampering detection circuit 20A and the received second noise waveform. And since it is configured to determine that tampering has been performed when the difference between the calculated cross-correlation value and the past cross-correlation value is equal to or greater than a predetermined threshold value, it is possible to efficiently detect fraud associated with wiring tampering or insertion of malicious circuits.

[0042] [Second Embodiment] By the way, in the first embodiment described above, the operation of the digital circuit 10A when measuring the noise waveform is not specified. Therefore, in the second embodiment, the case where specific test data is generated and operated in the digital circuit 10A when measuring the noise waveform will be described.

[0043] [Outline of Tampering Detection Circuit] The outline of the forgery detection circuit according to Embodiment 2 will be described. FIG. 7 is an explanatory diagram for explaining the outline of the forgery detection circuit according to Embodiment 2. The IC chips 1C and 1D are mounted on the interposer 40. The IC chip 1C has a digital circuit 10C, a forgery detection circuit 20C, and a power supply circuit 30A. The IC chip 1D has a digital circuit 10D, a forgery detection circuit 20D, and a power supply circuit 30B.

[0044] The forgery detection circuit 20C of the IC chip 1C includes a noise measurement circuit 21A, a noise storage circuit 24A, a noise analysis circuit 25A, a detection control circuit 27A, and a test data generation circuit 28A. Here, the noise measurement circuit 21A, the noise storage circuit 24A, and the noise analysis circuit 25A are the same as those in Embodiment 1. The detection control circuit 27A performs the setting of test data on the test data generation circuit 28A in order to calculate the cross-correlation value.

[0045] Then, the detection control circuit 27A transmits a trigger signal for noise generation to the test data generation circuit 28A, causes the digital circuit 10C to execute the test data, and measures the noise waveform. Specifically, for example, when the digital circuit 10C of the IC chip 1C is operating with test data, the noise measurement circuit 21A measures the first noise waveform of the node N1 on the common power supply line L1 of the power supply circuit 30A of the IC chip 1C. Also, in the IC chip 1D, when the digital circuit 10C is operating with test data, the noise measurement circuit 21B measures the second noise waveform of the node N2 on the common power supply line L1 of the power supply circuit 30B of the IC chip 1D and stores it in the noise storage circuit 24B. Then, the noise analysis circuit 25A of the IC chip 1C receives the second noise waveform measured in the IC chip 1D from the noise waveform - detection control data sharing bus B2 of the noise storage circuit 24B of the IC chip 1D, and calculates the cross-correlation value between the first noise waveform measured in the IC chip 1C and the received second noise waveform. Then, the calculated cross-correlation value is compared with the past cross-correlation value, and if the difference in the cross-correlation value is greater than a predetermined threshold value, it is determined that forgery has been performed.

[0046] Next, the operation procedures of the forgery detection circuit 20C and the forgery detection circuit 20D according to the second embodiment will be described. FIG. 8 is a sequence chart for explaining the operation of the forgery detection circuit 20C shown in FIG. 7. As shown in FIG. 8, the forgery detection circuit 20C of the IC chip 1C sets test data of noise in the test data generation circuit 28A (S1). Next, the forgery detection circuit 20C of the IC chip 1C transmits a trigger for noise generation to the test data generation circuit 28A of the IC chip 1C and the forgery detection circuit 20D of the IC chip 1D (S2).

[0047] The forgery detection circuit 20D of the IC chip 1D receives the noise generation trigger (S3). When the test data generation circuit 28A receives the noise generation trigger, it generates test data and causes the digital circuit 10C to execute the test data (S4). Then, the forgery detection circuit 20D of the IC chip 1D measures and stores the second noise waveform at the measurement node of the IC chip 1D (S5). Also, the noise measurement circuit 21C of the IC chip 1C measures and stores the first noise waveform at the measurement node of the IC chip 1C (S6).

[0048] Then, the forgery detection circuit 20D of the IC chip 1D transmits the second noise waveform stored in the noise memory circuit 24D of the IC chip 1D via the noise waveform·detection control data sharing bus B2 (S7), and the forgery detection circuit 20C of the IC chip 1C calculates the cross-correlation value between the received second noise waveform and the measured first noise waveform (S8). Then, the forgery detection circuit 20C of the IC chip 1C compares the calculated cross-correlation value with the stored past cross-correlation value. If the difference in the cross-correlation value is greater than a predetermined threshold, it is determined that forgery has been performed. If the difference is smaller than the predetermined threshold, it is determined that no forgery has been performed (S9).

[0049] In this way, the forgery detection circuit according to the second embodiment includes the test data generation circuit 28A, so that the noise waveform can be measured in a state where the same test data is always operated in the digital circuit 10A, and thus the accuracy of the cross-correlation value can be improved.

[0050] [Embodiment 3] Incidentally, in the above-described Embodiments 1 and 2, the similarity of the noise waveforms is used as the correlation value. In Embodiment 3, a case will be described in which the cross-correlation value of the noise waveforms is associated with the cut-off frequency of the low-pass filter circuit.

[0051] <Outline of the forgery detection circuit> The outline of the forgery detection circuit according to the present Embodiment 3 will be described. FIG. 9 is an explanatory diagram for explaining the outline of the forgery detection circuit according to the present Embodiment 3. As shown in FIG. 9, the first noise waveforms each have a different cut-off frequency, and a plurality of third noise waveforms from which high-frequency components have been removed are calculated by a plurality of low-pass filter circuits 32 that remove high-frequency components from the first noise waveforms based on the cut-off frequencies. Then, the correlation value calculation circuit 33 calculates the correlation values at each cut-off frequency between the plurality of third noise waveforms and the second noise waveform. From the calculated correlation values at each cut-off frequency, the cut-off frequency (fc PDN ) at which the correlation value is maximized is calculated. This cut-off frequency (fc PDN ) is stored as a feature value of the common power supply line L1, that is, an evaluation value corresponding to the cross-correlation value.

[0052] Next, an example of a third noise waveform with frequency components above the cut-off frequency removed by low-pass filter circuits 32 with different cut-off frequencies will be described for the first noise waveform. FIG. 10 is a diagram showing an example of a third noise waveform obtained by removing frequency components above the cut-off frequency of a low-pass filter circuit from the first noise waveform. As shown in FIG. 10, here, the case of using four low-pass filter circuits 32 with different cut-off frequencies is shown. FIG. 10(a) shows the first noise waveform of node N1 of the common power supply line L1 of the first IC chip. Further, FIG. 10(b) shows the second noise waveform of the common power supply line L1 of the second IC chip. The second noise waveform measured in the second IC chip in this way forms a parasitic low-pass filter due to the parasitic impedance of the common power supply line L1 in the interposer 40 on which the first IC chip and the second IC chip are mounted, and has the effect of a low-pass filter on the propagation of the power supply noise waveform, resulting in a waveform with high-frequency components removed.

[0053] FIG. 10(c) shows a third noise waveform obtained by removing frequency components of 1 MHz or higher from the first noise waveform by a low-pass filter circuit 32 with a cut-off frequency of 1 MHz. FIG. 10(d) shows a third noise waveform obtained by removing frequency components of 10 MHz or higher from the first noise waveform by a low-pass filter circuit 32 with a cut-off frequency of 10 MHz. FIG. 10(e) shows a third noise waveform obtained by removing frequency components of 25 MHz or higher from the first noise waveform by a low-pass filter circuit 32 with a cut-off frequency of 25 MHz. FIG. 10(f) shows a third noise waveform obtained by removing high-frequency components of 100 MHz or higher from the first noise waveform by a low-pass filter circuit 32 with a cut-off frequency of 100 MHz.

[0054] The correlation value is not calculated for the entire time of the first noise waveform, but is calculated within a range by setting a correlation window near a peak waveform caused by the rising edge of a clock signal after resetting a digital circuit of the first IC chip, as shown in Fig. 10(b). When calculating the correlation value between the first noise waveform and the second noise waveform, the correlation window is set by calculating an offset value in the time direction of the correlation window of the second noise waveform so that the correlation value is maximized. The correlation window may be set based on a peak waveform caused by the falling edge of a clock signal or a peak waveform corresponding to a ringing component.

[0055] Next, an example of the change in the cutoff frequency of the tamper detection circuit will be described. FIG. 11 is a diagram showing an example of the change in the cutoff frequency of the tamper detection circuit shown in FIG. 9. As shown in FIG. 11, a case is shown in which a low-pass filter circuit 32 having 20 different cutoff frequencies is used. When a malicious circuit 80 is connected to the common power line L1, the characteristics of the cutoff frequency vs. correlation value change. FIG. 11 shows a state in which the cutoff frequency with the maximum correlation value of the common power line L1 that has not been tampered with is 29 MHz, whereas the cutoff frequency with the maximum correlation value of the common power line L1 with the malicious circuit 80 inserted therein changes to 23 MHz.

[0056] In this way, the tamper detection circuit of embodiment 3 calculates the correlation values ​​between the second noise waveform and multiple third noise waveforms in which high-frequency components above the cutoff frequency of the first noise waveform have been removed using multiple low-pass filter circuits 32 with different cutoff frequencies, and from each of the calculated correlation values, calculates the cutoff frequency at which the correlation value is maximum and sets this as the feature of the common power supply line L1, and can detect tampering such as connecting a malicious circuit 80 to the common power supply line L1 based on a change in the feature.

[0057] In the above-described Embodiments 1, 2, and 3, the forgery detection circuits 20A, 20B, 20C, and 20D are formed in the respective IC chips 1A, 1B, 1C, and 1D. However, the forgery detection circuit may be formed in an independent IC chip.

[0058] <Modification Example 1> Incidentally, in each of the above embodiments, the case where the IC chips 1A, 1B, 1C, and 1D are connected by the interposer 40 has been described. Here, the case where the IC chips 1A and 1B are mounted and connected to a printed circuit board will be described.

[0059] First, the case where a plurality of IC chips on which the forgery detection circuit 20A according to Modification Example 1 is mounted are mounted on a printed circuit board will be described. FIG. 12 is an explanatory diagram for explaining the outline of Modification Example 1. As shown in FIG. 12, the IC chips 1A and 1B are encapsulated in packages 50A and 50B. Here, the package is a resin package using resin molding or a ceramic package using ceramic.

[0060] Then, a plurality of packages 50A are mounted on a single printed circuit board 60. The common power supply line L1 and the noise waveform data sharing bus B1 applied to the IC chips 1A and 1B are realized as wirings on the printed circuit board 60, and the terminals of the common power supply line L1 and the noise waveform data sharing bus B1 of the packages 50A and 50B are connected to the printed circuit board 60 by solder or solder bumps. The operation of the forgery detection circuit 20A is the same as that of Embodiment 1, and thus the description thereof is omitted. However, when a malicious circuit 80 is inserted into the printed circuit board 60, the forgery detection circuit 20A can detect that forgery has been performed.

[0061] <Modification Example 2> Next, in Modification 2, a case where an electronic module is configured using a plurality of printed circuit boards on which IC chips are mounted will be described. FIG. 13 is an explanatory diagram for explaining the outline of Modification 2. As shown in FIG. 13, the IC chips 1A and 1B are respectively encapsulated in packages 50A and 50B, and are respectively mounted on printed circuit boards 61 and 62. Between the respective printed circuit boards 61 and 62, a common power line L1 and a noise waveform data sharing bus B1 are connected by a cable or the like to constitute an electronic module 70.

[0062] The tampering detection circuit 20A of the IC chip 1A measures and stores the first noise waveform of the node N1 of the common power line L1 of the power supply circuit 30A of the IC chip 1A. Then, the tampering detection circuit 20B of the IC chip 1B measures and stores the second noise waveform of the node N2 of the common power line L1 of the power supply circuit 30B of the IC chip 1B. The tampering detection circuit 20A of the IC chip 1A calculates the cross-correlation value between the first noise waveform of the node N1 and the second noise waveform of the node N2 received from the tampering detection circuit 20B of the IC chip 1B via the noise waveform data sharing bus B1, and compares it with the past cross-correlation value. When the difference in the cross-correlation value is greater than a predetermined threshold value, it is determined that tampering has been performed on the cable connecting the printed circuit board 61 and the printed circuit board 62. When the difference in the cross-correlation value is less than a predetermined threshold value, it is determined that no tampering has been performed. In this way, the tampering detection circuit 20A can also detect tampering performed on a cable or the like connecting between the printed circuit board 61 and the printed circuit board 62.

[0063] <Modification 3> Next, in Modification 3, a case where three packages 50A, 50B, and 50C each mounting an IC chip are mounted on a printed circuit board 63 will be described. FIG. 14 is an explanatory diagram for explaining the outline of Modification 3. As shown in FIG. 14, IC chips 1A, 1B, and 1C are respectively encapsulated in packages 50A, 50B, and 50C, and the three packages 50A, 50B, and 50C are mounted on one printed circuit board 63. The common power line L1 and the noise waveform data sharing bus B1 of each of the packages 50A, 50B, and 50C are realized as wirings on the printed circuit board 63.

[0064] The forgery detection circuit 20A of the IC chip 1A measures and stores the first noise waveform of the node N1 of the common power line L1 of the power supply circuit 30A of the IC chip 1A. Then, the forgery detection circuit 20B of the IC chip 1B measures and stores the second noise waveform of the node N2 of the common power line L1 of the power supply circuit 30B of the IC chip 1B. The forgery detection circuit 20A of the IC chip 1A calculates the cross-correlation value between the first noise waveform of the node N1 and the second noise waveform of the node N2 received from the forgery detection circuit 20B of the IC chip 1B via the noise waveform data sharing bus B1, and compares it with the past cross-correlation value. When the difference in the cross-correlation value is greater than a predetermined threshold value, it is determined that forgery has been performed on the wiring between the IC chip 1A and the IC chip 1B.

[0065] Also, the forgery detection circuit 20B of the IC chip 1B measures and stores the second noise waveform of the node N2 of the common power line L1 of the power supply circuit 30B of the IC chip 1B. Then, the forgery detection circuit 20C of the IC chip 1C measures and stores the fourth noise waveform of the node N4 of the common power line L1 of the power supply circuit 30C of the IC chip 1C. The forgery detection circuit 20B of the IC chip 1B calculates the cross-correlation value between the second noise waveform of the node N2 and the noise waveform of the fourth node N4 received from the forgery detection circuit 20C of the IC chip 1C via the noise waveform data sharing bus B1, and compares it with the past cross-correlation value. When the difference in the cross-correlation value is greater than a predetermined threshold value, it is determined that forgery has been performed on the wiring between the IC chip 1B and the IC chip 1C.

[0066] Further, the forgery detection circuit 20C of the IC chip 1C measures and stores the fourth noise waveform of the node N4 of the common power supply line L1 of the power supply circuit 30C of the IC chip 1C. Then, the forgery detection circuit 20A of the IC chip 1A measures and stores the first noise waveform of the node N1 of the common power supply line L1 of the power supply circuit 30A of the IC chip 1A. The forgery detection circuit 20C of the IC chip 1C calculates the cross-correlation value between the fourth noise waveform of the node N4 and the first noise waveform of the node N1 received from the forgery detection circuit 20A of the IC chip 1A via the noise waveform data sharing bus B1, and compares it with the past cross-correlation value. When the difference in the cross-correlation value is greater than a predetermined threshold value, it is determined that forgery has been performed on the wiring between the IC chip 1C and the IC chip 1A. Note that it is also possible to estimate the location where forgery has occurred by comparing the forgery detection results of the IC chips 1A and 1B, the forgery detection results of the IC chips 1B and 1C, and the forgery detection results of the IC chips 1C and 1A.

[0067] Each configuration illustrated in the above-described embodiments and each modification is functionally schematic, and it is not necessarily physically configured as illustrated. That is, the form of distribution and integration of each device is not limited to that illustrated, and all or part of it can be functionally or physically distributed and integrated in arbitrary units according to various loads, usage situations, and the like.

Industrial Applicability

[0068] The forgery detection circuit and the forgery detection method according to the present invention are suitable for efficiently detecting fraud associated with the insertion of malicious circuits and the like.

Explanation of Reference Numerals

[0069] B1 Noise waveform data sharing bus B2 Noise waveform / detection control data sharing bus L1 Common power supply line 1A, 1B, 1C, 1D IC chips 10A, 10B, 10C, 10D Digital circuits 20A, 20B, 20C, 20D Forgery detection circuits 21A, 21B, 21C Noise Measurement Circuit 22A Measurement Circuit 23A Amplification Circuit 23B ADC 23C Control Circuit 24A, 24B, 24C Noise Memory Circuit 25A, 25B, 25C Noise Analysis Circuit 26A Noise Waveform Cross-Correlation Circuit 26B Noise Waveform Auto-Correlation Circuit 26C Noise Waveform Frequency Spectrum Analysis Circuit 26D Tampering Detection Circuit 27A, 27B Detection Control Circuit 28A, 28B Test Data Generation Circuit 30A, 30B, 30C Power Supply Circuit 31 External Power Supply Circuit 32 Low-Pass Filter Circuit 33 Correlation Value Calculation Circuit 40 Interposer 50A, 50B, 50C Package 60, 61, 62, 63 Printed Circuit Board 70 Electronic Module 80 Malicious Circuit

Claims

1. A first IC chip having at least a first digital circuit and a first power supply circuit for supplying a voltage to the first digital circuit, and a second IC chip having a second digital circuit and a second power supply circuit for supplying a voltage to the second digital circuit are mounted, and a forgery detection circuit for detecting forgery of a substrate on which the first digital circuit and the second digital circuit perform a predetermined operation, a first measurement circuit for measuring a first noise signal superimposed on the voltage supplied to the first power supply circuit, a first storage circuit for storing the first noise waveform measured by the first measurement circuit, a second measurement circuit for measuring a second noise signal superimposed on the voltage supplied to the second power supply circuit, a second storage circuit for storing the second noise waveform measured by the second measurement circuit, a calculation circuit for receiving the first noise waveform and calculating a correlation relationship between the received first noise waveform and the second noise waveform, and a determination circuit for determining the presence or absence of forgery of the substrate based on the correlation relationship A forgery detection circuit characterized by comprising.

2. The calculation circuit, The forgery detection circuit according to claim 1, characterized in that a cross-correlation value between the first noise waveform and the second noise waveform is calculated.

3. The second storage circuit, stores the past cross-correlation value calculated by the calculation circuit, The determination circuit, determines that forgery of the substrate has been performed when the difference between the cross-correlation value calculated by the calculation circuit and the past cross-correlation value stored in the second storage circuit is equal to or greater than a predetermined threshold value The forgery detection circuit according to claim 2, characterized by the above.

4. The determination circuit, When the difference between the cross-correlation value calculated by the calculation circuit and the past cross-correlation value stored in the second storage circuit is equal to or greater than a predetermined threshold value, it is determined that there is a possibility that a malicious circuit has been inserted into a common power supply line to which the first power supply circuit and the second power supply circuit are connected. The forgery detection circuit according to claim 3, characterized by the above.

5. The first measurement circuit measures the first noise waveform when a reset signal input to the digital circuit of the first IC chip is triggered, The second measurement circuit measures the second noise waveform when a reset signal input to the digital circuit of the first IC chip is triggered The forgery detection circuit according to any one of claims 1 to 4, characterized in that...

6. Further comprising a generation circuit for generating predetermined test data, The forgery detection circuit according to any one of claims 1 to 5, characterized in that a predetermined operation is caused by inputting the test data to the first digital circuit and the second digital circuit.

7. The calculation circuit is A plurality of low-pass filter circuits each having a different cut-off frequency and removing high-frequency components from the first noise waveform based on the cut-off frequency, A plurality of correlation value calculation circuits for calculating correlation values between a plurality of third noise waveforms from which high-frequency components have been removed from the first noise waveform by the plurality of low-pass filter circuits and the second noise waveform, respectively, Calculating a cut-off frequency at which the correlation value is maximized from the correlation values respectively calculated by the plurality of correlation value calculation circuits The forgery detection circuit according to any one of claims 1 to 6, characterized in that...

8. The first measurement circuit and the first storage circuit are formed in the first IC chip, The second measurement circuit, the second storage circuit, the calculation circuit, and the determination circuit are formed in the second IC chip The forgery detection circuit according to any one of claims 1 to 7, characterized in that...

9. A first IC chip having at least a first digital circuit and a first power supply circuit for supplying a voltage to the first digital circuit, and a second IC chip having a second digital circuit and a second power supply circuit for supplying a voltage to the second digital circuit are mounted. A forgery detection method in a forgery detection circuit for detecting forgery of a substrate on which the first digital circuit and the second digital circuit perform a predetermined operation, comprising: A first measurement step in which the first IC chip measures a first noise signal superimposed on the voltage supplied to the first power supply circuit; A first storage step in which the first IC chip stores the first noise waveform measured in the first measurement step in a first storage circuit; A second measurement step in which the second IC chip measures a second noise signal superimposed on the voltage supplied to the second power supply circuit; A second storage step in which the second IC chip stores the second noise waveform measured in the second measurement step in a second storage circuit; A calculating step of receiving the first noise waveform and calculating a correlation between the received first noise waveform and the second noise waveform; A determining step of determining whether there is forgery on the substrate based on the correlation; A forgery detection method characterized by including the above.

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