Semiconductor device and equipment

Abstract

To provide a technology that is advantageous for enhancing a value of a semiconductor device.SOLUTION: A semiconductor device comprises: a first semiconductor component that has a cell array 1234 and a plurality of wiring lines; and a semiconductor component 201 that has a plurality of pads which are connected to a semiconductor component 101 having the cell array 1234. A row pad 41 that is connected to a row wiring line 11 connected to a cell 1 and a cell 2, a row pad 42 that is connected to a row wiring line 12 connected to a cell 3 and a cell 4, and a column pad 43 that is connected to a column wiring line 21 connected to the cell 1 and the cell 3 are arranged such that a straight line connecting between the row pad 41 and the column pad 43 intersects with a straight line connecting between the row pad 42 and the column pad 43.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device including a plurality of semiconductor components.

Background Art

[0002] By stacking another semiconductor component on a semiconductor component having a cell array and electrically connecting the other semiconductor component to the cell array, it is possible to improve the performance of the semiconductor device, miniaturize the semiconductor device, or improve the integration degree of the semiconductor device.

[0003] Patent Document 1 discloses a solid-state imaging device in which a first chip on which a plurality of pixels are formed and a second chip on which a plurality of pixel driving circuits are formed and stacked on the first chip are electrically connected via connection pads.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In Patent Document 1, the arrangement of the connection pads is insufficiently studied, and there is room for improving the characteristics of the wiring between the chips and the yield. Therefore, an object of the present invention is to provide an advantageous technique for enhancing the value of a semiconductor device.

Means for Solving the Problems

[0006] Means for solving the above problems include a first semiconductor component having a cell array and a plurality of wirings, and a second semiconductor component having a plurality of pads connected to the first semiconductor component, and the semiconductor device in which the first semiconductor component and the second semiconductor component overlap, wherein the cell array includes a plurality of cells arranged in a first direction and a second direction intersecting the first direction, the plurality of pads are arranged in a plane along the first direction and the second direction so as to overlap the cell array, the plurality of cells include a first cell, a second cell aligned with the first cell in the first direction, a third cell aligned with the first cell in the second direction, and a fourth cell aligned with the third cell in the first direction and aligned with the second cell in the second direction, the plurality of wirings include a first wiring connected to the first cell and the second cell, a second wiring connected to the third cell and the fourth cell, and a third wiring connected to the first cell and the third cell, the plurality of pads include a first pad connected to the first wiring, a second pad connected to the second wiring, and a third pad connected to the third wiring, and the first pad, the second pad, and the third pad are arranged such that a straight line connecting the first pad and the third pad intersects a straight line connecting the second pad and the third pad.

[0007] Also, a means for solving the above problems includes a first semiconductor component having a cell array and a plurality of wirings, and a second semiconductor component having a pad array connected to the first semiconductor component, and the first semiconductor component and the second semiconductor component overlap with each other. In the semiconductor device, the cell array includes a plurality of cells arranged in a matrix, the pad array includes a plurality of pads arranged in a matrix so as to overlap the cell array, and each of the plurality of wirings is connected to two or more cells in the same cell row of the cell array, and includes a plurality of row wirings provided corresponding to each cell row of the cell array, and each of the plurality of wirings is connected to two or more cells in the same cell column of the cell array, and includes a plurality of column wirings provided corresponding to each cell column of the cell array. A first row pad connected to a first row wiring among the plurality of row wirings and a second row pad connected to a second row wiring among the plurality of row wirings are arranged in different pad columns of the pad array.

Advantages of the Invention

[0008] According to the present invention, it is possible to provide a technology advantageous for enhancing the value of a semiconductor device.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Embodiments for Carrying Out the Invention

[0010] Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. In the following description and drawings, common configurations across multiple drawings are denoted by common reference numerals. Therefore, the common configurations will be described with reference to multiple drawings, and the description of the configurations denoted by common reference numerals will be omitted as appropriate.

[0011] FIG. 1(a) is a cross-sectional schematic diagram of a semiconductor device 930, and FIG. 1(b) is a plan schematic diagram of the semiconductor device 930. As shown in FIG. 1(a), the semiconductor device 930 includes a semiconductor component 101 and a semiconductor component 201. The semiconductor component 101 includes a semiconductor layer 100 and a wiring structure 110 on the semiconductor layer 100. The wiring structure 110 of the semiconductor component 101 includes a plurality of conductive layers including a conductive layer 10, a conductive layer 20, and a conductive layer 30, and an insulator member 120 around the plurality of conductive layers. The semiconductor component 201 includes a semiconductor layer 200 and a wiring structure 210 on the semiconductor layer 200. The wiring structure 210 of the semiconductor component 201 includes a plurality of conductive layers including a conductive layer 40, and an insulator member 220 around the plurality of conductive layers. In this example, the semiconductor component 101 and the semiconductor component 201 are joined to each other at a joining surface 300.

[0012] As shown in FIG. 1(b), the semiconductor component 101 has a cell array 1234. The cell array 1234 extends in the X direction and the Y direction. The Y direction intersects the X direction. In this example, the Y direction is orthogonal to the X direction, but the Y direction may be an oblique direction of the X direction.

[0013] As shown in FIG. 1(a), the semiconductor component 201 overlaps the semiconductor component 101 in the Z direction. The Z direction intersects the X direction and the Y direction. In this example, the Z direction is orthogonal to the X direction and the Y direction, but the Z direction may be an oblique direction of the X direction and the Y direction.

[0014] As shown in FIG. 1(b), the cell array 1234 includes a cell 1, a cell 2, a cell 3, and a cell 4. The cell 2 is aligned with the cell 1 in the X direction. The cell 3 is aligned with the cell 1 in the Y direction. The cell 4 is aligned with the cell 3 in the X direction. The cell 4 is aligned with the cell 2 in the Y direction. A group including a plurality of cells aligned in the X direction is called a cell row, and a group including a plurality of cells aligned in the Y direction is called a cell column.

[0015] Each cell of the cell array 1234 includes at least one semiconductor element. Here, the semiconductor element is typically a transistor, but it may also be a diode or a thyristor. Further, the semiconductor element is not limited to an active element, and may be a passive element such as a resistor or a capacitor. The cell 1 includes a semiconductor element 61, the cell 2 includes a semiconductor element 62, the cell 3 includes a semiconductor element 63, and the cell 4 includes a semiconductor element 64. The semiconductor elements 61, 62, 63, and 64 may have equivalent functions to each other. The cell 1 includes a semiconductor element 71, the cell 2 includes a semiconductor element 72, the cell 3 includes a semiconductor element 73, and the cell 4 includes a semiconductor element 74. The semiconductor elements 71, 72, 73, and 74 may have equivalent functions to each other, but this is not the only case. The semiconductor elements 61, 62, 63, and 64 may have functions different from those of the semiconductor elements 71, 72, 73, and 74, but this is not the only case.

[0016] The semiconductor component 101 has a plurality of wirings. The wiring that connects at least two cells included in the same cell row is called a row wiring, and the wiring that connects at least two cells included in the same cell column is called a column wiring. A plurality of wirings composed of row wirings and column wirings are called matrix wirings. The plurality of wirings (matrix wirings) of the semiconductor component 101 include a row wiring 11, a row wiring 12, a column wiring 21, and a column wiring 22. The row wiring 11 is connected to the cell 1 and the cell 2. The row wiring 12 is connected to the cell 3 and the cell 4. The column wiring 21 is connected to the cell 1 and the cell 3. The column wiring 22 is connected to the cell 2 and the cell 4. Instead of being connected to the cell 4, the column wiring 22 may be connected to the cell 2 and other cells aligned with the cell 2 in the Y direction. That is, a certain cell row includes the cells 1 and 2 connected by the row wiring 11, and another cell row includes the cells 3 and 4 connected by the row wiring 12. Also, a certain cell column includes the cells 1 and 3 connected by the column wiring 21, and another cell column includes the cells 2 and 4 connected by the column wiring 22.

[0017] The connection between the cells and the wirings will be described in more detail. The row wiring 11 is commonly connected to the semiconductor element 61 of the cell 1 and the semiconductor element 62 of the cell 2. The row wiring 12 is commonly connected to the semiconductor element 63 of the cell 3 and the semiconductor element 64 of the cell 4. The column wiring 21 is commonly connected to the semiconductor element 71 of the cell 1 and the semiconductor element 73 of the cell 3. The column wiring 22 is commonly connected to the semiconductor element 72 of the cell 2 and the semiconductor element 74 of the cell 4.

[0018] For example, a common signal is input from the row wiring 11 to the semiconductor elements 61 and 62, and a common signal is input from the row wiring 12 to the semiconductor elements 63 and 64. Also, for example, signals from the semiconductor elements 71 and 73 are output to the column wiring 21, and signals from the semiconductor elements 72 and 74 are output to the column wiring 22. Hereinafter, for the sake of convenience, it will be described as if a signal is input from the row wiring to the cell and the signal of the cell is output to the column wiring, but it is not limited to this, and a signal may be input from the column wiring to the cell and the signal of the cell may be output to the row wiring.

[0019] The semiconductor component 201 has a pad array 4321. The pad array 4321 has a number of conductive pads arranged in the X-Y plane. The pad array 4321 includes a plurality of conductive pads arranged to overlap the cell array 1234 in the X-Y plane. Each of the plurality of conductive pads arranged to overlap the cell array 1234 in the X-Y plane is referred to as an overlapping pad. The number of conductive pads of the pad array 4321 can include at least one non-overlapping pad arranged so as not to overlap the cell array 1234, in addition to the plurality of overlapping pads arranged to overlap the cell array 1234 in the X-Y plane. All the conductive pads of the pad array may be arranged so as to overlap the cell array 1234.

[0020] The plurality of overlapping pads of the semiconductor component 201 include a row pad 41, a row pad 42, a column pad 43, and a column pad 44. The row pad 41, the row pad 42, the column pad 43, and the column pad 44 are arranged to overlap the cell array 1234 in the Z direction where the semiconductor components 101 and 201 overlap. The row pad 41 is connected to the row wiring 11. The row pad 42 is connected to the row wiring 12. The column pad 43 is connected to the column wiring 21. The column pad 44 is connected to the column wiring 22. The row pad 41 and the column pad 43 can be arranged along one of the X direction and the Y direction (in this example, the Y direction). Also, the row pad 42 and the column pad 44 can be arranged along the other of the X direction and the Y direction (in this example, the X direction). However, since the plurality of pads of the pad array can be arranged independently of the arrangement of the cells of the cell array, it is not necessarily required that the pads be arranged along the direction in which the cells are arranged. For example, the row pads and the column pads may be arranged obliquely with respect to the cell columns or cell rows.

[0021] More specifically, the semiconductor component 201 includes a circuit 51, a circuit 52, a circuit 53, and a circuit 54. The row pad 41 is connected to the circuit 51. The row pad 42 is connected to the circuit 52. The column pad 43 is connected to the circuit 53. The column pad 44 is connected to the circuit 54.

[0022] The semiconductor component 101 has a pad array. The pad array has a number of conductive pads arranged in the X-Y plane. The pad array includes a plurality of conductive pads arranged to overlap the cell array 1234 in the X-Y plane. Each of the plurality of conductive pads arranged to overlap the cell array 1234 in the X-Y plane is referred to as an overlapping pad. The number of conductive pads of the pad array can include at least one non-overlapping pad arranged so as not to overlap the cell array 1234, in addition to the plurality of overlapping pads arranged to overlap the cell array 1234 in the X-Y plane. All the conductive pads of the pad array may be arranged so as to overlap the cell array 1234.

[0023] The plurality of overlapping pads of the semiconductor component 101 include a row pad 31, a row pad 32, a column pad 33, and a column pad 34. The row pad 31, the row pad 32, the column pad 33, and the column pad 34 are arranged to overlap the cell array 1234 in the Z direction in which the semiconductor component 101 and the semiconductor component 201 overlap. The row pad 31 is connected to the row wiring 11. The row pad 32 is connected to the row wiring 12. The column pad 33 is connected to the column wiring 21. The column pad 34 is connected to the column wiring 22.

[0024] The row pad 31 and the row pad 41 are electrically connected, the row pad 32 and the row pad 42 are electrically connected, the column pad 33 and the column pad 43 are electrically connected, and the column pad 34 and the column pad 44 are electrically connected. As a result, as described above, the row pads 41 and 42 are connected to the row wirings 11 and 12, and the column pads 43 and 44 are connected to the column wirings 21 and 22. Then, the circuits 51 and 52 are connected to the row wirings 11 and 12 via the row pads 41 and 42 and the row pads 31 and 32. Also, the circuits 53 and 54 are connected to the column wirings 21 and 22 via the column pads 43 and 44 and the column pads 33 and 34.

[0025] In this example, pads 41, 42, 43, and 44 are directly joined to the corresponding pads 31, 32, 33, and 34 at the joint surface 300. The joining of pads 41, 42, 43, 44 and pads 31, 32, 33, 34 can be made by metal bonding. Examples of materials for the conductive pads suitable for such direct joining by metal bonding include copper, gold, or their alloys, but other conductive materials other than copper and gold may also be used. Further, bumps such as solder may be arranged between pads 41, 42, 43, 44 and pads 31, 32, 33, 34, and pads 41, 42, 43, 44 and pads 31, 32, 33, 34 may be joined via the bumps. Also, in this example, the insulator member 120 of the wiring structure 110 is directly joined to the insulator member 220 of the wiring structure 210 at the joint surface 300. The joining of the insulator member 120 and the insulator member 220 can be made by covalent bonding. Examples of materials for the insulator member suitable for such direct joining by covalent bonding include silicon oxide and silicon nitride, but other insulating materials other than silicon oxide and silicon nitride may also be used. Further, an adhesive material such as resin may be arranged between the insulator member 120 and the insulator member 220, and the insulator member 120 and the insulator member 220 may be joined via the adhesive material.

[0026] The pad array 4321 may include circuits of the semiconductor component 201 and dummy pads not connected to the circuits of the semiconductor component 101. The dummy pads included in the pad array 4321 can be joined to the dummy pads included in the pad array of the semiconductor component 101. Providing dummy pads is advantageous in enhancing the uniformity of the joint surface 300 and improving the mechanical and / or electrical reliability of the joining between components.

[0027] This embodiment is characterized by the arrangement of the row pads 41, 42 and the column pads 43, 44. Note that since the row pads 31, 32 are to be joined to the row pads 41, 42, the arrangement of the row pads 31, 32 is the same as the arrangement of the row pads 41, 42. Also, since the column pads 33, 34 are to be joined to the column pads 43, 44, the arrangement of the column pads 33, 34 is the same as the arrangement of the column pads 43, 44. Therefore, the description of the arrangement of the row pads 31, 32 and the column pads 33, 34 is omitted.

[0028] The row pads 41, 42 and the column pad 43 are arranged such that in the X-Y plane perpendicular to the Z direction, a straight line A connecting the row pad 41 and the column pad 43 intersects a straight line B connecting the row pad 42 and the column pad 43. The row pad 41, the column pad 43 and the column pad 44 are arranged such that in the X-Y plane perpendicular to the Z direction, a straight line C connecting the row pad 41 and the column pad 44 intersects a straight line D connecting the row pad 42 and the column pad 44. Here, it should be noted that any of the straight lines A, B, C, D is a straight line connecting a row pad connected to a row wiring and a column pad connected to a column wiring. Moreover, it should also be noted that the row wiring and the column wiring to which each of the two pads forming the straight lines A, B, C, D is connected are connected to the same cell. For example, the row wiring 11 and the column wiring 21 to which each of the row pad 41 and the column pad 43 forming the straight line A is connected are connected to the same cell 1. For example, the row wiring 12 and the column wiring 21 to which each of the row pad 42 and the column pad 43 forming the straight line B is connected are connected to the same cell 3. Thus, the arrangement of the three pads defined by the straight line A and the straight line B, or the three pads defined by the straight line C and the straight line D is called a triangular arrangement. This is because a triangle can be formed by connecting the three pads constituting the triangular arrangement. The triangle at this time is typically a right triangle, but is not limited thereto, and may be an equilateral triangle or an isosceles triangle. Note that the row pad 41, the row pad 42 and the column pad 44 are also in a triangular arrangement, and the row pad 42, the column pad 43 and the column pad 44 are also in a triangular arrangement. By adopting the triangular arrangement, a plurality of overlapping pads can be arranged well.

[0029] For example, unlike FIG. 1(b), consider the case where the row pad 42 is placed above cell 3. Moreover, when the column pad 43 is placed above cell 3, the distance between the column pad 43 and the row pad 42 can become extremely narrow. Alternatively, when the column pad 43 is not placed above cell 3, it becomes necessary to place a non-overlapping pad instead of the column pad 43 at a position that does not overlap with the cell array 1234. Alternatively, it is also conceivable to place the column pad 43 above cell 4, but in that case, the wiring path between the column pad 43 and the column wiring 21 becomes long, increasing the wiring resistance and wiring capacitance, and causing RC delay. On the other hand, by shifting the row pad 42 in the X direction with respect to the row pad 41, that is, by moving the row pad 42 above cell 4 to the right of cell 3 instead of above cell 3, the column pad 43 can be placed above cell 3. Here, since the row pad 42 is connected to the row wiring 12, the wiring path between the row pad 42 and the row wiring 12 does not become long even when the row pad 42 is shifted in the X direction. By adopting such a triangular arrangement, the pads 41, 42, 43, 44 that overlap with the cell array 1234 can be appropriately arranged. That is, it is possible to both shorten the wiring paths between the pads 41, 42, 43, 44 and the wirings 11, 12, 21, 22 and increase the distance between the pads 41, 42, 43, 44.

[0030] The row pad 41, the row pad 42, the column pad 43, and the column pad 44 are arranged in the X-Y plane perpendicular to the Z direction such that a straight line E connecting the row pad 41 and the row pad 42 passes between the column pad 43 and the column pad 44. Similarly, the row pad 41, the row pad 42, the column pad 43, and the column pad 44 are arranged in the X-Y plane perpendicular to the Z direction such that a straight line F connecting the column pad 43 and the column pad 44 passes between the row pad 41 and the row pad 42. In this way, the arrangement of the row pad 41, the row pad 42, the column pad 43, and the column pad 44 defined by the straight line E and / or the straight line F is referred to as a cross arrangement.

[0031] Such a cross arrangement can provide a technique that is advantageous for improving the performance of a semiconductor device. The first advantage of the cross arrangement is that it can suppress the extreme reduction in the spacing between the pads 41, 42, 43, and 44. If the reduction in the spacing between the pads 41, 42, 43, and 44 can be suppressed, the yield can be improved and the parasitic capacitance can be reduced. The second advantage of the cross arrangement is that it can suppress the increase in the wiring path length from the pads 41, 42, 43, and 44 to the row wirings 11, 12, or the column wirings 21, 22. The third advantage of the cross arrangement is that it can suppress the complication of the wiring path from the pads 41, 42, 43, and 44 to the row wirings 11, 12, 21, and 22. If the increase in the wiring path length and the complication of the wiring path can be suppressed, the yield can be improved and the RC delay of the wiring can be reduced.

[0032] For example, in FIG. 1(b), when the column pad 44 disposed at a position overlapping the cell 2 is moved to a position overlapping the cell 3, the straight line A no longer passes between the column pad 43 and the column pad 44. That is, the cross arrangement is no longer present. At this time, since the column pads 43 and 44 are located at positions overlapping the cell 3, the spacing between the column pad 43 and the column pad 44 becomes smaller than in the case of FIG. 1(b). Then, there is a possibility that a short circuit or crosstalk may occur between the column pad 43 and the column pad 44. In addition, the column pad 44 moved to a position overlapping the cell 3 has a larger distance from the column wiring 22 than in the case of FIG. 1(b). Then, the wiring path length from the column pad 44 to the column wiring 22 increases or the wiring path becomes complicated.

[0033] In FIG. 1(b), the 2×2 cell array 1234 was examined, but the number of cells included in the cell array 1234 can be arbitrarily set. In FIGS. 2(a) and (b), the 3×3 cell array 1234 will be examined. Row wirings 11, 12, and 13 corresponding to each cell row, and column wirings 21, 22 corresponding to each cell column are provided. Regarding the connection between the row wirings 11, 12 and the column wirings 21, 22 and the cells and pads, it may be the same as the form described in FIG. 1(b), so detailed description thereof will be omitted. Cells 5, 6, and 05 are arranged in the X direction, and the row wiring 13 is connected to the cells 5, 6, and 05. Cells 01, 02, and 03 are arranged in the Y direction, and the column wiring 23 is connected to the cells 01, 02, and 03. Cell 01 is arranged in the X direction with cell 1, and cell 02 is arranged in the X direction with cell 2. A row pad 41 is connected to the row wiring 11, a column pad 44 is connected to the row wiring 12, and a row pad 45 is connected to the row wiring 13. A column pad 43 is connected to the column wiring 21, a column pad 44 is connected to the column wiring 22, and a column pad 47 is connected to the column wiring 23. Also, it is assumed that the pads 41, 32, 33, 34, 35, and 36 are arranged so as to overlap different cells respectively.

[0034] In the form of FIG. 2(a), in addition to the straight line E passing between the column pad 43 and the column pad 44, the straight line E also passes between the column pad 43 and the column pad 47. Also, a straight line G connecting the row pad 42 and the row pad 45 passes between the column pad 43 and the column pad 47. Further, a straight line G connecting the row pad 42 and the row pad 45 passes between the column pad 44 and the column pad 47.

[0035] In the form of FIG. 2(a), the row pads 41, 42, and 45 do not exist on a straight line. That is, the row pad 41 is away from the straight line G connecting the row pad 42 and the row pad 45, the row pad 42 is away from the straight line connecting the row pad 41 and the row pad 45, and the row pad 45 is away from the straight line E connecting the row pad 41 and the row pad 42. Such an arrangement of the row pads 41, 42, and 45 is referred to as a non-linear arrangement.

[0036] Suppose the row pads 41, 42, and 45 are arranged in cells 1, 4, and 5 as shown in Fig. 2(a) so that the row pads 41, 42, and 45 are in a non-linear arrangement. Then, the column pad 43 connected to the column wiring 21 by the shortest wiring path cannot be arranged in cells 1 and 4 and is arranged in cell 3. Therefore, the degree of freedom in arranging the column pad 43 is 1. The column pad 44 connected to the column wiring 22 is arranged in cell 2 in Fig. 2(a), but it can also be arranged in cell 6. Therefore, the degree of freedom in arranging the column pad 44 is 2. The column pad 47 connected to the column wiring 23 is arranged in cell 03 in Fig. 2(a), but it can also be arranged in cell 01 or cell 05. Therefore, the degree of freedom in arranging the column pad 47 is 3. Thus, the degree of freedom in arranging the column pads 43, 44, and 47 is 1×2×3 = 6.

[0037] In Fig. 2(b), the row pads 41, 42, and 45 are on a straight line. The row pad 42 is located between the row pads 41 and 45, and the straight line connecting the row pads 41 and 45 passes through the row pad 42. Such an arrangement of the row pads 41, 42, and 45 is called a linear arrangement. When the linear arrangement is adopted for the arrangement of the row pads 41, 42, and 45, the degree of freedom in arranging the column pads 43, 44, and 47 is improved.

[0038] Suppose the row pads 41, 42, and 45 are arranged in cells 1, 4, and 05 as shown in Fig. 2(a) so that the row pads 41, 42, and 45 are in a linear arrangement. Then, the column pad 43 connected to the column wiring 21 is arranged in cell 5 in Fig. 2(a), but it can also be arranged in cell 3. Therefore, the degree of freedom in arranging the column pad 43 is 2. The column pad 44 connected to the column wiring 22 is arranged in cell 2 in Fig. 2(a), but it can also be arranged in cell 6. Therefore, the degree of freedom in arranging the column pad 44 is 2. The column pad 47 connected to the column wiring 23 is arranged in cell 03 in Fig. 2(a), but it can also be arranged in cell 01. Therefore, the degree of freedom in arranging the column pad 47 is 2. Thus, the degree of freedom in arranging the column pads 43, 44, and 47 is 2×2×2 = 8, which is an improvement in the degree of freedom compared to the case of adopting the non-linear arrangement.

[0039] In FIGS. 3(a) and 3(b), a 4-row and 4-column cell array 1234 is considered. Row wirings 11, 12, 13, and 14 corresponding to each cell row are provided. Cells 7, 8, 07, and 08 are arranged in the X direction, and the row wiring 14 is connected to cells 7, 8, 07, and 08. Cells 02, 04, 06, and 08 are arranged in the Y direction, and the column wiring 24 is connected to cells 02, 04, 06, and 08. A row pad 46 is connected to the row wiring 14, and a column pad 49 is connected to the column wiring 24. Also, pads 41, 42, 43, 44, 45, 46, 47, and 48 are arranged so as to overlap with different cells respectively.

[0040] In the form shown in FIG. 3(a), the row pads 41, 42, 43, and 44 are in a cross arrangement. The row pads 41, 45, and 46 are in a linear arrangement, and the row pad 42 is arranged away (shifted) from the straight line connecting any two of the row pads 41, 45, and 46. The column pads 44, 47, and 48 are in a linear arrangement, and the column pad 43 is arranged away (shifted) from the straight line connecting any two of the column pads 44, 47, and 48.

[0041] Also in the form shown in FIG. 3(b), the row pads 41, 42 and the column pads 43, 44 are in a cross arrangement. Further, the row pads 45, 46 and the column pads 47, 48 are in a cross arrangement. The row pads 41, 42, 45, and 46 are in a linear arrangement, and the column pads 43, 44, 47, and 48 are in a linear arrangement.

[0042] In the forms of FIGS. 1(b), 2(b), and 3(b), the distances from two or more cells (e.g., cells 1, 3, 5, 7) in the same cell column to the row pads (e.g., row pads 41, 42, 45, 46) connected to the cell are different for each row pad. Therefore, the wiring path length from the cell column to the row pads can be different for each cell row. As a result, the delay amount of the signal input from the row wiring to the cell can be different for each cell row. When many row pads are arranged in a straight line, the variation in the wiring path length from the cell column to the row pads expands. For example, in the form of FIG. 2(b), the distance from cell 5 to row pad 45 is about twice the distance from cell 3, which belongs to the same cell column as cell 5, to row pad 42. For example, in the form of FIG. 3(b), the distance from cell 07 to row pad 46 is about three times the distance from cell 01, which belongs to the same cell column as cell 07, to row pad 41. On the other hand, when non-linear arrangement is applied to row pads 41, 42, 45, 46 as in the forms of FIGS. 2(a) and 3(a), the variation in the wiring path length from the cell column to the row pads can be reduced. In FIGS. 2(a) and 3(a), the differences in the distances from two or more cells (e.g., cells 1, 5, 7) in the same cell column to some row pads (e.g., row pads 41, 45, 46) connected to the cell are made equal.

[0043] In the forms shown in FIGS. 4(a) and 4(b), the fact that a plurality of row wirings are provided in one cell row and / or a plurality of column wirings are provided in one cell column is different from the forms shown in FIGS. 3(a) and 3(b). Regarding the row wirings, cells 1, 2, 01, and 02 belonging to the same cell row are connected to row wiring 11 and also to row wiring 16. Specifically, row wiring 11 is connected to the first type of semiconductor element 60 included in cell 1 and the first type of semiconductor element 60 included in cell 2. Also, row wiring 16 is connected to a second type of semiconductor element (not shown) included in cell 1 and a second type of semiconductor element (not shown) included in cell 2. Row wiring 11 is a signal line for transmitting a first type of signal, and row wiring 16 is a signal line for transmitting a second type of signal. The plurality of overlapping pads include row pad 41, which is a connection pad connected to row wiring 11 that is a signal line, and row pad 91, which is a connection pad connected to row wiring 16 that is a signal line. The same applies to other row wirings. Cells 3, 4, 03, and 04 belonging to the same cell row are connected to row wiring 12 and also to row wiring 17. Cells 5, 6, 05, and 06 belonging to the same cell row are connected to row wiring 13 and also to row wiring 18. Cells 7, 8, 07, and 08 belonging to the same cell row are connected to row wiring 14 and also to row wiring 19. Row pad 92 is connected to row wiring 17, row pad 95 is connected to row wiring 18, and row pad 96 is connected to row wiring 19.

[0044] Regarding the column wirings, cells 1, 5, 3, and 7 belong to the same cell column. Cells 1 and 3 are connected to column wiring 21, and cells 5 and 7 are connected to column wiring 26. Similarly, cells 6 and 8 are connected to column wiring 27, cells 05 and 07 are connected to column wiring 28, and cells 06 and 08 are connected to column wiring 28. Column pad 93 is connected to column wiring 26 connected to cells 5 and 7. Column pad 94 is connected to column wiring 27 connected to cells 6 and 8. Column pad 97 is connected to column wiring 28 connected to cells 05 and 07. Column pad 98 is connected to column wiring 29 connected to cells 06 and 08.

[0045] In the form of FIG. 4(b), the row pad 41 is located between the column pads 43, 94 and the row pad 91. And the row pad 45 is located between the column pads 44, 93 and the row pad 95, the row pad 92 is located between the column pads 47, 48 and the row pad 42, and the row pad 96 is located between the column pads 97, 98 and the row pad 46. Thus, when the column pads are arranged on one side of two row pads connected to the same cell row, the bias in the arrangement of the column pads occurs, and the influence of the fixed pattern noise tends to increase. In the form of FIG. 4(a), the column pad 44 is located between the row pad 41 and the row pad 91. And the column pad 44 is located between the row pad 45 and the row pad 95, the column pad 44 is located between the row pad 42 and the row pad 92, and the column pad 47 is located between the row pad 46 and the row pad 96. Thus, by arranging the column pads between two row pads connected to the same cell row, the bias in the arrangement of the column pads can be reduced.

[0046] In the forms of FIGS. 4(a) and 4(b), a straight line O connecting column pads 43 and 93 connected to different column wirings, a distance P between the straight line O and row pad 41, a distance Q between the straight line O and row pad 42, and a distance R between row pad 41 and row pad 42 are defined. When the difference between the distance P and the distance Q is larger than the distance R (R < |P - Q|), the difference in the wiring path lengths from two cells 1 and 3 connected to the same column wiring 21 to the row pads 41 and 42 corresponding to the cells 1 and 3 becomes large. Then, a difference occurs in the delay amounts of the signals transmitted through the row wirings of the cells 1 and 3, and the variation in the outputs of the cells 1 and 3 becomes large. On the other hand, in the forms of FIGS. 4(a) and 4(b), the difference between the distance P and the distance Q is smaller than the distance R (|P - Q| < R). By doing so, the difference in the wiring path lengths from two cells 1 and 3 connected to the same column wiring 21 to the row pads 41 and 42 corresponding to the cells 1 and 3 can be reduced. Therefore, the difference in the delay amounts of the signals transmitted through the row wirings of the cells 1 and 3 can be reduced, and the variation in the outputs of the cells 1 and 3 can be reduced. In the form of FIG. 4(b), the difference between the distance P and the distance Q is about 1 / √2 of the distance R, but it is preferable that the difference between the distance P and the distance Q is 1 / 2 or less of the distance R (|P - Q| ≦ R / 2). In the form of FIG. 4(a), the distance P and the distance Q are equal, and the difference between the distance P and the distance Q is zero. Also, it is preferable that the distance P and the distance Q are smaller than the distance R (P < R, Q < R). In the form of FIG. 4(b), since the distance Q is smaller than the distance R but the distance P is larger than the distance R, the output variation between the cells 1 and 3 is likely to occur. On the other hand, in the form of FIG. 4(a), since the distance Q and the distance P are smaller than the distance R, the output variation between the cells 1 and 3 can be reduced.

[0047] Furthermore, define the distance S between the straight line O and the row pad 45, the distance T between the straight line O and the row pad 46, and the distance U between the row pad 45 and the row pad 46. Similar to the distances P, Q, and R, it is preferable that the difference between the distance S and the distance T is smaller than the distance U (|S - T| < U). It is also preferable that the difference between the distance S and the distance T is equal to or less than half of the distance U (|S - T| ≤ U / 2). It is also preferable that the distances S and T are smaller than the distance U (S < U, T < U). By doing so, the possibility of variation in the outputs of the cell 5 connected to the row pad 45 and the cell 7 connected to the row pad 46 can be reduced.

[0048] Furthermore, it is preferable that the difference between the distance S and the distance T is smaller than the distance R (|S - T| < R), and it is also preferable that the difference between the distance S and the distance T is equal to or less than half of the distance R (|S - T| ≤ R / 2). It is also preferable that the distances S and T are smaller than the distance R (S < R, T < R). Also, it is preferable that the difference between the distance P and the distance Q is smaller than the distance U (|P - Q| < U), and it is also preferable that the difference between the distance P and the distance Q is equal to or less than half of the distance U (|P - Q| ≤ U / 2). It is also preferable that the distances P and Q are smaller than the distance U (P < U, Q < U). By doing so, the possibility of variation between the output from the column pad 43 via the column wiring 21 and the output from the column pad 93 via the column wiring 26 can be reduced. For example, in the form of Fig. 4(a), the distances S and T are about half of the distance R, and the distances P and Q are equal to or less than one-fourth of the distance U.

[0049] Here, the column pads 43 and 93 are used to define the straight line O, but the definition of the straight line O may be any straight line that connects two column pads associated with two column wirings to which two or more cells belonging to the same cell column are respectively connected. In other words, each of the two column pads that define the straight line corresponding to the straight line O only needs to be connected to a cell belonging to the same cell column. Therefore, for the straight line connecting the column pad 44 and the column pad 94, the row pads 41, 42 and / or the row pads 45, 46 can be arranged so as to satisfy the relationships such as the above-described distances P, Q, R, S, T, and U. The same applies to the straight line connecting the column pad 47 and the column pad 97 and the straight line connecting the column pad 48 and the column pad 98.

[0050] Also, here, the row pads 41, 42, 45, and 46 connected to the wirings 11, 12, 13, and 14 have been described. Similarly, for the row pads 91, 92, 95, and 96 connected to the wirings 16, 17, 18, and 19, they can be arranged so as to satisfy relationships such as the distances P, Q, R, S, T, and U described above, so that the difference in the distances from the straight line corresponding to the straight line O does not increase.

[0051] The type of cells constituting the cell array 1234 may be appropriately set according to the use of the semiconductor device 930. For example, the cells can be pixel cells. A cell array 1234 composed of pixel cells can perform imaging or display. The pixel cells for performing imaging may include a photoelectric conversion element.

[0052] The photoelectric conversion element can adopt a photodiode, a photogate, or a configuration in which a photoelectric conversion film is sandwiched between electrode pairs. The pixel cells for performing display may include an optical element. The optical element can adopt an electroluminescence (EL) element, a cathodoluminescence (CL) element, a liquid crystal element, a mirror element, or the like. For example, the cells can be memory cells. A cell array 1234 composed of memory cells operates as a memory. The memory cells can be SRAM cells, DRAM cells, or flash memory cells.

[0053] One of the row wiring and the column wiring can be a signal line (drive signal line) for transmitting a drive signal for driving the cell. The drive signal line is typically connected to the gate of the transistor included in the cell and controls the operation timing of the cell. When the cell is a memory cell, the drive signal line is a word line. The other of the row wiring and the column wiring can be a signal line (information signal line) for transmitting an information signal including information handled by the cell. The information signal line is typically connected to the source or drain of the transistor included in the cell. When the cell is a pixel cell, the information signal is a pixel signal, and the pixel signal can indicate a signal level corresponding to the charge generated by the photoelectric conversion element or a signal level corresponding to the luminance level to be displayed on the display element. When the cell is a memory cell, the information signal line is a bit line, which reads the data recorded in the memory cell or writes data to the memory cell.

[0054] In addition, the column wiring and / or the row wiring are not limited to the wiring for transmitting a signal whose signal level changes over time, and may be a wiring (potential supply line) for supplying a fixed potential such as a power supply potential, a ground potential, a reference potential, or a reference potential.

[0055] The circuit connected to the information signal line of the semiconductor component 101 among the semiconductor components 201 can be a processing circuit for processing information. The circuit connected to the drive signal line of the semiconductor component 101 among the semiconductor components 201 can be a drive circuit for generating a drive signal.

Example

[0056] A form common to Examples 1 to 5 below will be described. FIG. 5(a) is a schematic diagram according to an embodiment of a semiconductor device. In the cell array 1234 of the semiconductor component 101, cells 102 are arranged in a matrix. A plurality of cells in the same cell column are connected by a column wiring 103, and a signal from the cell 102 is output via the column wiring 103. A plurality of cells in the same cell row are connected by a row wiring 104, and a signal to the cell 102 is input via the row wiring 104. Each of the plurality of row wirings 104 is connected to two or more cells in the same cell row of the cell array 1234, and each is provided corresponding to each cell row of the cell array 1234. Each of the plurality of column wirings 103 is connected to two or more cells in the same cell column of the cell array 1234, and each is provided corresponding to each cell column of the cell array 1234.

[0057] In the semiconductor component 201 of FIG. 5(b), a control circuit 202 that outputs at least a drive signal for driving the cell 102 and a processing circuit 203 that processes a signal output from the cell 102 are arranged. By stacking the semiconductor component 101 and the semiconductor component 201, a stacked semiconductor device is configured. Further, the control circuit 202 is connected to the corresponding row wiring 104, and the processing circuit 203 that processes the output signal from the cell 102 is connected to the corresponding column wiring 103.

[0058] FIG. 5(c) shows a configuration example of the cell 102. The cell 102 includes a photodiode PD which is a photoelectric conversion element, a transfer transistor M2 that transfers the charge of the photodiode PD to a detection node FD formed of a floating diffusion, and a reset transistor M1 that resets the detection node FD. The detection node FD is connected to the gate of an amplification transistor M3, and a power supply voltage is supplied to the amplification transistor M3 and the reset transistor M1. A selection transistor M4 is connected to the source of the amplification transistor M3, and the selection transistor M4 is connected to a column wiring 103. Drive signals of a reset signal PRES, a transfer signal PTS, and a selection signal PSEL are input to the gates of the reset transistor M1, the transfer transistor M2, and the selection transistor M4, respectively, from a control circuit 202 via a plurality of signal lines included in a row wiring 104. A power supply potential Vdd is supplied to the reset transistor M1 and the amplification transistor M3 from a power supply potential supply line as a row wiring. Here, an example in which the pixel cell is composed of four transistors is shown, but the selection transistor M4 may be omitted and the pixel cell may be composed of three transistors, or transistors for realizing various additional functions may be added in addition to the four transistors.

Example

[0059] Figs. 6(a) and 6(b) show the relationship between row wirings 104_1 to 104_3 corresponding to the control circuit 202_1 and row pads 302_1 to 302_3 connected to the row wirings 104_1 to 104_3. Figs. 6(a) and 6(b) also show the relationship between column wiring 103_1 corresponding to the processing circuit 203 and column pad 301 connected to the column wiring 103_1. In the pad array 4321, the column pads 301 and / or row pads 302 are arranged in a matrix. The pad array 4321 includes a plurality of pads arranged in a matrix so as to overlap the cell array 1234. The columns in which the column pads 301 and / or row pads 302 are arranged are referred to as pad columns, and the rows in which the column pads 301 and / or row pads 302 are arranged are referred to as pad rows. Figs. 6(a), 6(b), and 6(c) show a plurality of pad rows including M + 1 rows and a plurality of pad columns including N columns. In the semiconductor component 101, there is one column wiring 103_1 arranged in each cell column. The matrix wiring includes a plurality of row wirings 104 each connected to two or more cells in the same cell row. There are three row wirings 104_1, 104_2, and 104_3 arranged in each cell row. The plurality of pads include some row pads 302_1, 302_2, and 302_3 connected to each of the plurality of row wirings 104_1, 104_2, and 104_3. The row wiring 104_1 transmits the reset signal PRES and is connected to the gate of the reset transistor M1 of the cell 102. The row wiring 104_2 transmits the selection signal PSEL and is connected to the gate of the selection transistor M4 of the cell 102. The row wiring 104_3 transmits the transfer signal PTS and is connected to the gate of the transfer transistor M2 of the cell 102.

[0060] In Fig. 6(c), the positions of the row pads corresponding to each cell row are indicated by "r", "s", and "t". "r" in Fig. 6(c) indicates the position of the row pad 302_1 connected to the row wiring 104_1, for example, "s" indicates the position of the row pad 302_2 connected to the row wiring 104_2, and "t" indicates the position of the row pad 302_3 connected to the row wiring 104_3. In Fig. 6(c), the position of the column pad corresponding to each cell column is indicated by "o".

[0061] In the semiconductor component 201, a plurality (v) of control circuits 202_1 to 202_v corresponding to each row are arranged at a pitch equivalent to the row pitch of the cells in the control circuit 202. 301 is a pad of the column wiring 103_1 connected to the processing circuit 203. 302_1 to 302_3 are pads of the row wirings 104_1 to 104_3 connected to the control circuit 202_1. One column pad 301 and one row pad 302 can be arranged per cell. The pad array 4321 may include dummy pads that are neither row pads 302 nor column pads 301. In FIG. 6(b), dummy pads may be arranged in a pad row or a pad column where none of "r", "s", "t", and "o" are denoted.

[0062] The arrangement of the column pads 301 will be described. The column pads 301 are arranged for each cell column and for each column wiring 103. Regarding the column pads 301 arranged for each column wiring 103, the symbols of the row pads 302_1 to 302_3 are not shown in FIGS. 6(a) and 6(b) except for N - 2 columns. Therefore, refer to FIG. 6(c) for the detailed pad arrangement. In order to suppress the degradation of image quality, it is preferable to maintain the correspondence between the group (cell row, cell column) of the cells 102 arranged in the semiconductor component 101 and the peripheral circuits. For this purpose, the column wiring 103 connected to each cell column is connected to the corresponding cell column and to the processing circuit 203 of the semiconductor component 201. Therefore, the column pads 301 can be arranged on the control circuit 202. Furthermore, it is desirable that the lengths of each wiring path from the processing circuit 203 of the semiconductor component 201 to the column pads 301 be equal.

[0063] The arrangement of row pads 302_1 to 302_3 will be described. The row pads 302_1 to 302_3 are arranged for each cell row and for each row wiring 104. The row pads 302_1 to 302_3 in the M-th row are connected to a certain row wiring 104 among the plurality of row wirings 104, and the row pads 302_1 to 302_3 other than the M-th row are connected to another row wiring 104 among the plurality of row wirings 104. Regarding the row pads 302_1 to 302_3 arranged for each cell row, since the symbols of the row pads 302_1 to 302_3 are not shown in FIGS. 6(a) and 6(b) except for the (M - 2)-th row, please refer to FIG. 6(c). When the column pads 301 are not on the control circuit 202, the row pads 302_1 to 302_3 of each row can be arranged in the N-th to (N + 2)-th columns of the pad array 4321 for the entire row, but in this embodiment, the column pads 301 are arranged on the control circuit 202. That is, the column pads 301 are arranged in the M-th row and the N-th to (N + 2)-th columns of the pad array 4321. Therefore, since the row pads 302_1 to 302_3 cannot be arranged in the M-th row and the N-th to (N + 2)-th columns, the row pads 302_1 to 302_3 in the M-th row are arranged in the (N + 3)-th to (N + 5)-th columns, avoiding the N-th to (N + 2)-th columns. That is, the row pads 302_1 to 302_3 are discontinuous between the (N + 2)-th column and the (N + 3)-th column, and the arranged pad rows are shifted. In this way, the row pads 302_1 to 302_3 in the M-th row and the row pads 302_1 to 302_3 other than the M-th row are arranged in separate pad columns ((N + 3)-th to (N + 5)-th columns and N-th to (N + 2)-th columns) of the pad array 4321.

[0064] By configuring as described above, the column pads 301_1 to 301_3 and the row pads 302_1 to 302_3 can be arranged at positions overlapping the cell array 1234 in a plan view. And through the column pads 301_1 to 301_3, the column wiring 103_1 of the semiconductor component 101 and the processing circuit of the semiconductor component 201 can be well connected. Also, through the row pads 302_1 to 302_3, the row wirings 104_1 to 104_3 of the semiconductor component 101 and the control circuit 202 of the semiconductor component 201 can be joined.

[0065] Then, column pads 301 are arranged in the M+1-th row and N+3-th to N+5-th columns of the pad array 4321. Since column pads 301 cannot be arranged in the M-th row and N+3-th to N+5-th columns, the column pads 301 in the N+3-th to N+5-th columns are arranged in the M+1-th row and N+3-th to N+5-th columns, avoiding the M-th row. In this way, in the pad columns of the N+3-th to N+5-th columns of the pad array 4321, including the row pads 302_1 to 302_3 in the M-th row, column pads 301 connected to the cells connected to the row pads 302_1 to 302_3 in the M-th row are arranged (in the M+1-th row). Also, in the pad columns of the N-th to N+2-th columns, including the row pads 302_1 to 302_3 other than the M-th row, column pads 301 connected to the cells connected to the row pads 302_1 to 302_3 other than the M-th row are arranged.

[0066] In the above example, the case where the control circuits 202 are arranged in each row at a pitch equivalent to the row pitch of the cells is shown. However, in a relationship where there is one or less column pad 301, 302_1 to 302_3 per cell pitch, the control circuits corresponding to each row of the control circuit 202 may be arranged at a pitch different from the row pitch of the cell rows. Also, in the above example, the case where there are three row wirings 104_1 to 104_3 and one column wiring 103_1 is shown, but the present invention is not limited to this relationship. The arrangement of this embodiment is an example, and the positions where the arrangements of the column pads 301 and the row pads 302_1 to 302_3 are discontinuous are not limited to the positions shown in this example.

Embodiment

[0067] Embodiment 2 will be described with reference to FIG. 7. In FIG. 7, the parts corresponding to those in FIG. 6 are denoted by the same reference numerals and the description thereof is omitted. The relationship between FIGS. 7(a), (b) and FIG. 7(c) is the same as the relationship between FIGS. 6(a), (b) and FIG. 6(c).

[0068] In Embodiment 2, the column pads 301 are arranged with a shift of one row for each pad column. Therefore, the wiring to the column pads 301 that connect the processing circuit 203 and the corresponding column wiring 103_1 is facilitated. In the case of Embodiment 1, it is necessary to pass a plurality of wirings for each control circuit corresponding to each row arranged in the control circuit 202 through the wiring that connects the processing circuit 203 and the corresponding column wiring 103_1. Furthermore, it is necessary to route the control circuits corresponding to each row arranged in the control circuit 202 over a plurality of rows.

[0069] The arrangement of the row pads 302_1 to 302_3 will be described. The row pads 302 other than the rows from row M to row M + 2 are arranged in columns from column N to column N + 2. In Embodiment 2, the column pads 301 are arranged at the M-th row and N-th column, the (M + 1)-th row and (N + 1)-th column, and the (M + 2)-th row and (N + 2)-th column of the pad array 4321. Therefore, any of the row pads 302_1 to 302_3 cannot be arranged at the M-th row and N-th column, the (M + 1)-th row and (N + 1)-th column, and the (M + 2)-th row and (N + 2)-th column. Therefore, at least one of the row pads 302_1 to 302_3 in each row from row M to row M + 2 needs to be shifted to a pad column other than columns N to N + 2. Therefore, for rows M to M + 2, the row pad 302_3 is arranged at column N + 3.

[0070] In the above example, the case where the control circuits 202_1 corresponding to each row are arranged at a pitch equivalent to the row pitch of the cells in the control circuit 202 is shown. However, in a relationship where the column pads 301 and 302_1 to 302_3 are each one or less per cell pitch, the control circuits corresponding to each row of the control circuit 202 may be arranged at a pitch different from the row pitch of the cells. Also, in the above example, the case where there are three row wirings 104_1 to 104_3 and one column wiring 103_1 is shown, but the present invention is not limited to this relationship. The arrangement of this embodiment is an example, and the positions where the arrangements of the column pads 301 and the row pads 302_1 to 302_3 are discontinuous are not limited to the positions shown in this example.

Embodiment

[0071] Example 3 will be described with reference to FIG. 8. In FIG. 8, the parts corresponding to those in FIG. 6 are denoted by the same reference numerals and the description thereof will be omitted. The relationship among FIGS. 8(a), (b) and 8(c) is the same as that among FIGS. 6(a), (b) and 6(c).

[0072] In Example 3, there are two column wirings in the same cell column of column wirings 103_1 and 103_2. Therefore, the pads of the column wirings 103_1 and 103_2 corresponding to the processing circuit 203 are column pads 301_1 and 301_2. In FIG. 8(c), the positions of the column pads corresponding to each cell column are indicated by "a" and "b". "a" in FIG. 8(c) indicates the position of the column pad 301_1 connected to, for example, the column wiring 103_1, and "b" indicates the position of the column pad 301_2 connected to, for example, the column wiring 103_2.

[0073] The arrangement of the column pads 301_1 and 301_2 will be described. In order to suppress the deterioration of the image quality, it is preferable to maintain the correspondence between the group of cells 102 arranged in the semiconductor component 101 and the peripheral circuit. Therefore, the column wirings 103_1 and 103_2 in each cell column are connected to the processing circuit 203 of the semiconductor component 201 in the corresponding cell column. Therefore, the column pads 301_1 and 301_2 can be arranged on the control circuit 202.

[0074] The arrangement of row pads 302_1 to 302_3 will be described. The row pads 302_1 to 302_3 are arranged for each cell row. When the column pads 301_1 and 301_2 are not on the control circuit 202, the row pads 302_1 to 302_3 of each row can be arranged in N columns to N + 2 columns for the entire row. However, in this embodiment, the column pads 301_1 and 301_2 are arranged on the control circuit 202. That is, the column pads 301_1 and 301_2 are arranged in M rows N columns to M rows N + 2 columns and M + 1 rows N columns to M + 1 rows N + 2 columns. Therefore, the row pads 302_1 to 302_3 cannot be arranged in M rows N columns to M rows N + 2 columns and M + 1 rows N columns to M + 1 rows N + 2 columns. Thus, the row pads 302_1 to 302_3 of M rows and M + 1 rows are arranged in N + 3 columns to N + 5 columns, avoiding N columns to N + 2 columns. That is, the row pads 302_1 to 302_3 are arranged with a shift in N + 3 columns to N + 5 columns in the same number of pad rows (two rows of M rows and M + 1 rows) as the number of column wirings 103 (two).

[0075] With the above configuration, the column pads 301_1, 301_2 and the row pads 302_1 to 302_3 can be arranged so as to overlap the cell array 1234. Then, the column wirings 103_1, 103_2 of the semiconductor component 101 and the processing circuit of the semiconductor component 201 can be connected via the column pads 301_1, 301_2. Also, the row wirings 104_1 to 104_3 of the semiconductor component 101 and the control circuit 202 of the semiconductor component 201 can be connected via the row pads 302_1 to 302_3. Also, in the above example, the case where the control circuit 202 is arranged with the control circuit 202_1 corresponding to each row at a pitch equivalent to the row pitch of the cells is shown. However, in a relationship where the column pads 301_1, 301_2, 302_1 to 302_3 are each one or less per cell pitch, the control circuits corresponding to each row of the control circuit 202 may be arranged at a pitch different from the row pitch of the cells. Also, in the above example, the case where there are three row wirings 104_1 to 104_3 and two column wirings 103_1, 103_2 is shown, but the present invention is not limited to this relationship. The arrangement of this embodiment is an example, and the positions where the arrangement of the column pads 301_1, 301_2 and the row pads 302_1 to 302_3 becomes discontinuous are not limited to the positions shown in this example.

Example

[0076] Example 4 will be described with reference to FIG. 9. In FIG. 9, parts corresponding to those in FIG. 6 are denoted by the same reference numerals and description thereof will be omitted. The relationship among FIGS. 9(a), (b) and 9(c) is the same as that among FIGS. 6(a), (b) and 6(c).

[0077] In Example 4, for the same cell column, six connection lines of column wirings 103_1 to 103_6 are provided for the column wiring 103. Then, the processing circuit 203 and the six column wirings 103_1 to 103_6 are connected by six column pads 301_1 to 301_6.

[0078] Cells connected to the row pads 302_1 to 302_3 in the M + m-th row and cells connected to the row pads 302_1 to 302_3 in the M + m + 6-th row are connected to the same column wiring 103_m. Here, m is any one of 1 to 6. Cells connected to the row pads 302_1 to 302_3 in the M + 1-th row (m = 1) and cells connected to the row pads 302_1 to 302_3 in the M + 7-th row (m = 1) are connected to the same column wiring 103_1. Cells connected to the row pads 302_1 to 302_3 in the M + 2-th row (m = 2) and cells connected to the row pads 302_1 to 302_3 in the M + 8-th row (m = 2) are connected to the same column wiring 103_2 (m = 2). Cells connected to the row pads 302_1 to 302_3 in the M + 2-th row (m = 3) and cells connected to the row pads 302_1 to 302_3 in the M + 9-th row (m = 3) are connected to the same column wiring 103_3 (m = 3). Cells connected to the row pads 302_1 to 302_3 in the M + 1-th row (m = 4) and cells connected to the row pads 302_1 to 302_3 in the M + 10-th row (m = 4) are connected to the same column wiring 103_4 (m = 4). Cells connected to the row pads 302_1 to 302_3 in the M + 2-th row (m = 5) and cells connected to the row pads 302_1 to 302_3 in the M + 11-th row (m = 5) are connected to the same column wiring 103_5 (m = 5). Cells connected to the row pads 302_1 to 302_3 in the M + 2-th row (m = 6) and cells connected to the row pads 302_1 to 302_3 in the M + 12-th row (m = 6) are connected to the same column wiring 103_6 (m = 6).

[0079] In FIG. 9(c), the positions of column pads 301_1 to 301_6 connected to each column wiring 03_1 to 103_6 are indicated by "a", "b", "c", "d", "e", and "f". "c" in FIG. 9(c) indicates the position of column pad 301_1 connected to column wiring 103_1, for example, and "d" indicates the position of column pad 301_4 connected to column wiring 103_4, for example. "e" in FIG. 9(c) indicates the position of column pad 301_5 connected to column wiring 103_4, for example, and "f" indicates the position of column pad 301_6 connected to column wiring 103_6, for example.

[0080] The arrangement of column pads 301_1 to 301_6 and row pads 302_1 to 302_3 in this embodiment will be described.

[0081] Row pads 302_1 to 302_3 connected to row wirings 104_1 to 104_3 corresponding to the same cell row are arranged in the same pad row. For example, in row M + 1, row pads 302_1 to 302_3 are arranged in columns N to N + 2. In row M + 6, row pads 302_1 to 302_3 are arranged in columns N + 5 to N + 7.

[0082] Row pads 302_1 to 302_3 in some (two in this example) pad rows are arranged in the same pad column. And the arrangement of row pads 302_1 to 302_3 in a certain pad row is repeated every seven pad rows (in a six-row cycle). For example, in row M + 7, similar to row M + 1, row pads 302_1 to 302_3 are arranged in columns N to N + 2. In row M + 12, similar to row M + 6, row pads 302_1 to 302_3 are arranged in columns N + 5 to N + 7.

[0083] Column pads 301_1 to 301_6 connected to column wirings 103_1 to 103_6 corresponding to the same cell column are arranged in the same pad column. For example, in N columns, column pads 301_1 to 301_3 are arranged in rows M + 2 to M + 4, and column pads 301_4 to 301_6 are arranged in rows M + 8 to M + 10. In N + 1 columns, column pads 301_1 to 301_3 are arranged in rows M + 3 to M + 5, and column pads 301_4 to 301_6 are arranged in rows M + 9 to M + 11. In N + 5 columns, column pads 301_1 to 301_3 are arranged in rows M + 8 to M + 10, and column pads 301_4 to 301_6 are arranged in rows M + 1 to M + 3.

[0084] Column pads 301_1 to 301_6 in some (two in this example) pad columns are arranged in the same pad row. And the arrangement of column pads 301_1 to 301_6 in a certain pad column is repeated every seven pad columns (with a six-column period). For example, in N + 6 columns and N + 12 columns, similar to N columns, column pads 301_1 to 301_3 are arranged in rows M + 2 to M + 4, and column pads 301_4 to 301_6 are arranged in rows M + 8 to M + 10. In N + 7 columns, similar to N + 1 columns, column pads 301_1 to 301_3 are arranged in rows M + 3 to M + 5, and column pads 301_4 to 301_6 are arranged in rows M + 9 to M + 11. In this way, row pads 302_1 to 302_3 are arranged in the same pad column in rows M + 1 and M + 7, M + 2 and M + 8, M + 3 and M + 9, M + 4 and M + 10, M + 5 and M + 11, M + 6 and M + 12 respectively.

[0085] Here, pay attention to several row wirings 104 to which several row pads 302 arranged in the same pad column are respectively connected. Among the cells connected to such several row wirings 104, several cells belonging to the same cell column are connected to the same column wiring 103.

[0086] More specifically, attention is paid to two row wirings 104_1 to which the row pads 302_1 of M + m rows and M + m + 6 rows arranged in the same N + m - 1 columns are respectively connected. Among the cells connected to such two row wirings 104_1, several cells belonging to the same cell column are connected to the same column wiring 103_m.

[0087] In the example of m = 1, attention is paid to two row wirings 104_1 to which the row pads 302_1 of M + 1 row and M + 7 rows arranged in the same N columns are respectively connected. Among the cells connected to such two row wirings 104_1, several cells belonging to the same cell column are connected to the same column wiring 103_m.

[0088] Similarly, in the example of m = 2, attention is paid to several row wirings 104_1 to which the row pads 302_1 of M + 2 rows and M + 8 rows arranged in the same N + 1 columns are respectively connected. Among the cells connected to such two row wirings 104_1, several cells belonging to the same cell column are connected to the same column wiring 103_2.

[0089] In other words, when paying attention to several cells connected to the same column wiring 103, the row pads 302 connected to several row wirings 104 corresponding to such several cells are arranged in the same pad column.

[0090] More specifically, when paying attention to two cells connected to the same column wiring 103_m, the row pads 302_1 of M + m rows and the row pads 302_1 of M + m + 6 are connected to the two row wirings 104_m corresponding to such two cells. The row pads 302_1 of M + m rows and the row pads 302_1 of M + m + 6 are arranged in the same N + m columns.

[0091] In the example of m = 1, when paying attention to two cells connected to the same column wiring 103_1, the row pads 302_1 of M + 1 row and the row pads 302_1 of M + 7 are connected to the two row wirings 104_1 corresponding to such two cells. The row pads 302_1 of M + 1 row and the row pads 302_1 of M + 7 are arranged in the same N columns.

[0092] Similarly, in the example of m = 2, when paying attention to two cells connected to the same column wiring 103_2, two row wirings 104_1 corresponding to such two cells are connected to the row pads 302_1 of M + 2 rows and the row pads 302_1 of M + 8. The row pads 302_1 of M + 2 rows and the row pads 302_1 of M + 8 are arranged in the same N + 1 columns.

[0093] And in the example of m = 6, when paying attention to two cells connected to the same column wiring 103_6, two row wirings 104_1 corresponding to such two cells are connected to the row pads 302_1 of M + 6 rows and the row pads 302_1 of M + 12 rows. The row pads 302_1 of M + 6 rows and the row pads 302_1 of M + 12 are arranged in the same N + 6 columns.

[0094] In this way, by arranging several row pads 302 connected to several row wirings 104 connected to several cells connected to the same column wiring 103 in the same pad column, the difference in the wiring path length from several row pads 302 to several cells can be reduced. As a result, the difference in the operations of several cells connected to the same row wiring 104 can be reduced, and the output variation from several cells can be reduced.

[0095] This corresponds to what was described with reference to FIG. 4(a). That is, the straight line O corresponds to one cell column. And arranging several row pads 302 corresponding to the same column wiring 103 in the same pad column corresponds to reducing the difference between distance P and distance Q or the difference between distance S and distance T.

[0096] Furthermore, when paying attention to several column pads 301 arranged in the same pad column, the wiring path length from the cells connected to each column pad 301 to the corresponding row pad 302 is different according to the pad row in which the column pad 301 is arranged.

[0097] For more specific description, pay attention to two column pads 301_m and 301_n arranged in the same N + m - 1 columns. Here, n is any one of 1 to 6 different from m. The row pad 302_m corresponding to the cell connected to the column pad 301_m is arranged in the M + m rows of the N + m - 1 columns. The row pad 302_1 corresponding to the cell connected to the column pad 301_n is arranged in the M + n rows of the N + n - 1 columns. Here, let the wiring path length from the cell connected to the column pad 301_2 to the row pad 302_1 in the M + n rows of the N + n - 1 columns be length J, and the wiring path length from the cell connected to the column pad 301_1 to the row pad 302_1 in the M + m rows of the N + m - 1 columns be length K. The length J will be larger than the length K by |n - m| pad columns.

[0098] As an example of m = 1 and n = 2, pay attention to two column pads 301_1 and 301_2 arranged in the same N columns. The row pad 302_1 corresponding to the cell connected to the column pad 301_1 is arranged in the M + 1 rows of the N columns.

[0099] The row pad 302_1 corresponding to the cell connected to the column pad 301_2 is arranged in the M + 2 rows of the N + 1 columns. Then, the wiring path length from the cell connected to the column pad 301_2 to the row pad 302_1 in the M + 2 rows of the N + 1 columns is larger than the wiring path length from the cell connected to the column pad 301_1 to the row pad 302_1 in the M + 1 rows of the N columns by one pad column.

[0100] As an example of m = 1 and n = 6, pay attention to two column pads 301_1 and 301_6 arranged in the same N columns. The row pad 302_1 corresponding to the cell connected to the column pad 301_1 is arranged in the M + 1 rows of the N columns.

[0101] The row pad 302_6 corresponding to the cell connected to the column pad 301_2 is arranged in the M + 6 rows of the N + 5 columns. Then, the wiring path length from the cell connected to the column pad 301_2 to the row pad 302_1 in the M + 2 rows of the N + 1 columns is larger than the wiring path length from the cell connected to the column pad 301_1 to the row pad 302_1 in the M + 1 rows of the N columns by five pad columns.

[0102] The row pads 302_1 to 302_3 are arranged in the same pattern every seven row pads (in a six-row cycle). And the pads 302_1 to 302_3 in the M+2 row and the M+8 row corresponding to the row wirings 104 connected to two cells connected to the same column wiring 103 (for example, column wiring 103_1) are arranged in the same pad columns (N+1 to N+3 columns).

[0103] Specifically, for either the M+2 row or the M+8 row, the row pad 302_1 is arranged in the N+1 column, the row pad 302_2 is arranged in the N+2 column, and the row pad 302_3 is arranged in the N+3 column.

[0104] The row pads 302_1 to 302_3 connected to the cells connected to each of the column wirings 103_1 to 103_6 are arranged in different pad columns. Then, for each cell row in the six-row cycle, the wiring path lengths from the row pads 302_1 to 302_3 to the cells are different for each of the column wirings 103_1 to 103_6. As a result, fixed pattern noise in the six-row cycle may occur. For example, if the row connected to the column wiring 103_1 has the row pad 302_1 arranged in the same column, the path lengths of the signal lines (row wirings 104_1) for each row in the six-row cycle that transmit the reset signal PRES are different, and fixed pattern noise in the six-row cycle may occur. However, for such fixed pattern noise in the six-row cycle, by performing a predetermined correction process with signals from correction cells (for example, optical black cells) formed around the cell array, the fixed pattern noise can be removed.

[0105] In the above example, the case of three row wirings 104_1 to 104_3 and six column wirings 103_1 to 103_6 is shown, but the present invention is not limited to this relationship.

Example

[0106] Example 5 will be described with reference to FIG. 10. Matters that may be the same as those in Example 4 are omitted herein. Note that the relationship among FIGS. 10(a), 10(b), and 10(c) is the same as the relationship among FIGS. 9(a), 9(b), and 9(c).

[0107] The arrangement of the column pads 301_1 to 301_6 and the row pads 302_1 to 302_3 in this example will be described.

[0108] The row pads 302_1 to 302_3 connected to the row wirings 104_1 to 104_3 corresponding to the same cell row are arranged in the same pad row, which is the same as in Example 4.

[0109] The row pads 302_1 to 302_3 in several (six in this example) pad rows are arranged in the same pad column. And the arrangement of the row pads 302_1 to 302_3 in a certain pad row is repeated every other pad row (with a two-row period). For example, in rows M + 1, M + 3, M + 5, M + 7, M + 9, and M + 11, the row pads 302_1 to 302_3 are arranged in columns N, N + 2, and N + 4. And in rows M + 2, M + 4, M + 6, M + 8, M + 10, and M + 12, the row pads 302_1 to 302_3 are arranged in columns N + 1, N + 3, and N + 5.

[0110] The column pads 301_1 to 301_6 connected to the column wirings 103_1 to 103_6 corresponding to the same cell column are arranged in the same pad column, which is the same as in Example 4.

[0111] Column pads 301_1 to 301_6 in several (six in this example) pad columns are arranged in the same pad row. And the arrangement of column pads 301_1 to 301_6 in a certain pad column is repeated every other pad column (with a two-column period). For example, in columns N, N + 2, N + 4, N + 6, N + 8, N + 10, N + 12, column pads 301_1 to 301_6 are arranged in rows M + 1, M + 3, M + 5, M + 7, M + 9, M + 11. In columns N + 1, N + 3, N + 5, N + 7, N + 9, N + 11, column pads 301_1 to 301_6 are arranged in rows M + 2, M + 4, M + 6, M + 8, M + 10, M + 12.

[0112] In this embodiment as well, for the same reason as in Embodiment 4, fixed-pattern noise with a two-row period may occur. However, by performing a predetermined correction process in the same manner as in Embodiment 4, the fixed-pattern noise can be removed. Also, because the fixed-pattern noise has a two-row period, the spatial frequency of the fixed-pattern noise becomes high, and the deterioration of the image quality can be made less than that in Embodiment 4. Therefore, there may be cases where the correction process does not need to be performed.

[0113] In the above example, the case of three row wirings 104_1 to 104_3 and six column wirings 103_1 to 103_6 is shown. However, if there is one or an even number of column wirings, a similar application to this embodiment is possible.

[0114] As described above, the embodiments described can be appropriately changed without departing from the spirit of the present invention.

[0115] Hereinafter, the device 9191 including the semiconductor device 930 shown in FIG. 11 will be described in detail. As described above, the semiconductor device 930 can include, in addition to the semiconductor device 910 having the semiconductor layer 100, a package 920 that houses the semiconductor device 910. The package 920 can include a substrate to which the semiconductor device 910 is fixed and a lid such as glass facing the semiconductor device 910. The package 920 can further include a bonding member such as a bonding wire or a bump that connects a terminal provided on the substrate and a terminal provided on the semiconductor device 910.

[0116] The device 9191 can include at least any one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 corresponds to the semiconductor device 930. The optical device 940 is, for example, a lens, a shutter, or a mirror. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0117] The processing device 960 processes a signal output from the semiconductor device 930. The processing device 960 is a semiconductor device such as a CPU or an ASIC for constituting an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays information (image) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or a semiconductor device that stores information (image) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as SRAM or DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0118] The mechanical device 990 has movable parts or propulsion parts such as motors and engines. In the device 9191, the signal output from the semiconductor device 930 is displayed on the display device 970 or transmitted externally by a communication device (not shown) provided in the device 9191. For this purpose, it is preferable that the device 9191 further includes a storage device 980 and a processing device 960 separately from the storage circuit and arithmetic circuit included in the semiconductor device 930. The mechanical device 990 may be controlled based on the signal output from the semiconductor device 930.

[0119] In addition, the device 9191 is suitable for electronic devices such as information terminals having a photographing function (for example, smartphones and wearable terminals) and cameras (for example, interchangeable-lens cameras, compact cameras, video cameras, surveillance cameras). The mechanical device 990 in the camera can drive the components of the optical device 940 for zooming, focusing, and shutter operations. Alternatively, the mechanical device 990 in the camera can move the semiconductor device 930 for anti-vibration operation.

[0120] Also, the device 9191 can be a transportation device such as a vehicle, a ship, or an aircraft. The mechanical device 990 in the transportation device can be used as a moving device. The device 9191 as a transportation device is suitable for those that transport the semiconductor device 930 or those that assist and / or automate driving (operation) by means of a photographing function. The processing device 960 for assisting and / or automating driving (operation) can perform processing for operating the mechanical device 990 as a moving device based on the information obtained by the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analysis device such as an electron microscope, or an office device such as a copier.

[0121] According to this embodiment, the characteristics of the wiring between the semiconductor component 101 and the semiconductor component 201 can be improved. Therefore, the value of the semiconductor device can be increased. The increase in value here includes at least any one of function addition, performance improvement, characteristic improvement, reliability improvement, manufacturing yield improvement, environmental load reduction, cost reduction, miniaturization, and weight reduction.

[0122] Therefore, if the semiconductor device according to this embodiment is used in equipment, the value of the equipment can also be improved. For example, when the semiconductor device is mounted on a transportation device to perform external shooting or measurement of the external environment of the transportation device, excellent performance can be obtained. Therefore, in manufacturing and selling transportation devices, deciding to mount the semiconductor device according to this embodiment on the transportation device is advantageous for improving the performance of the transportation device itself.

[0123] As described above, the embodiments described can be appropriately changed without departing from the technical idea. Note that the disclosure content of this specification includes not only what is described in this specification but also all matters that can be grasped from this specification and the drawings attached to this specification. Also, the disclosure content of this specification includes the complementary set of the concepts described in this specification. That is, for example, if this specification describes that "A is larger than B", even if the description that "A is not larger than B" is omitted, it can be said that this specification discloses that "A is not larger than B". Because when the description that "A is larger than B" is given, it is premised that the case where "A is not larger than B" is considered.

Explanation of Reference Numerals

[0124] 1234 cell array 101 semiconductor component 201 semiconductor component 4321 pad array 1, 2, 3, 4 cells 11, 12 row wirings 21, 22 column wirings 41, 42 row pads 43, 44 column pads

Claims

1. a first semiconductor component having a cell array, a plurality of wirings, a plurality of pads, and a first insulator; a second semiconductor component having a plurality of pads and a second insulator; a semiconductor device in which the first semiconductor component and the second semiconductor component are bonded to each other, the pads of the first semiconductor component and the pads of the second semiconductor component are directly bonded to each other at a bonding surface between the first semiconductor component and the second semiconductor component, and the first insulator and the second insulator are directly bonded to each other at the bonding surface, the cell array includes a plurality of cells arranged in a first direction and a second direction intersecting the first direction, the plurality of pads of the first semiconductor component and the plurality of pads of the second semiconductor component are arranged in a plane along the first direction and the second direction so as to overlap the cell array; The plurality of cells include A first cell, a second cell, and a third cell, Including, the first cell, the second cell, and the third cell are arranged in this order along the first direction, The plurality of wirings include A first wiring connected to the first cell; A second wiring connected to the first cell and the third cell; A third wiring connected to the third cell; Including, The plurality of pads of the second semiconductor component include A first pad connected to the first wiring; A second pad connected to the second wiring; a third pad connected to the third wiring; Including, The semiconductor device is characterized in that the first pad, the second pad, and the third pad are arranged in this order along the first direction.

2. The second semiconductor component is provided with a control circuit for controlling the cell array and a processing circuit for processing a signal output from the cell array, the first cell is connected to the control circuit via the first pad and the first wiring; the first cell and the third cell are connected to the processing circuit via the second pad and the second wiring; The semiconductor device according to claim 1 , wherein said third cell is connected to said control circuit via said third pad and said third wiring.

3. The plurality of cells includes a fourth cell and a fifth cell, the fourth cell, the first cell, and the fifth cell are arranged in this order along the second direction, the fourth cell and the fifth cell are connected to the first wiring; The semiconductor device according to claim 2 , wherein the fourth cell and the fifth cell are connected to the control circuit via the first pad and the first wiring.

4. the plurality of wirings include a fourth wiring connected to the fourth cell and a fifth wiring connected to the fifth cell; the plurality of pads of the second semiconductor component include a fourth pad arranged to overlap the fourth cell and connected to the fourth wiring, and a fifth pad arranged to overlap the fifth cell and connected to the fifth wiring, 4. The semiconductor device according to claim 3, wherein the fourth pad, the first pad, and the fifth pad are arranged in this order along the second direction.

5. the first cell is connected to the control circuit via the fourth pad and the fourth wiring; The semiconductor device according to claim 4 , wherein said first cell is connected to said control circuit via said fifth pad and said fifth wiring.

6. 6. The semiconductor device according to claim 4, wherein the first wiring, the third wiring, the fourth wiring, and the fifth wiring are arranged along the second direction, and the second wiring is arranged along the first direction.

7. the plurality of cells includes a sixth cell, the first cell, the sixth cell, the second cell, and the third cell are arranged in this order along the first direction, the plurality of wirings includes a sixth wiring connected to the sixth cell, the plurality of pads of the second semiconductor component include a sixth pad that is arranged to overlap the sixth cell and is connected to the sixth wiring; 6. The semiconductor device according to claim 2, wherein the first pad, the sixth pad, the second pad, and the third pad are arranged in this order along the first direction.

8. The semiconductor device according to claim 7 , wherein the sixth cell is connected to the processing circuit via the sixth pad and the sixth wiring.

9. 9. The semiconductor device according to claim 7, wherein the first wiring and the third wiring are arranged along the second direction, and the second wiring and the sixth wiring are arranged along the first direction.

10. the second cell is connected to the second wiring; The semiconductor device according to claim 2 , wherein the second cell is connected to the processing circuit via the second pad and the second wiring.

11. 11. The semiconductor device according to claim 2, wherein a first signal transmitted from the control circuit to the first cell via the first pad and the first wiring and a third signal transmitted from the control circuit to the third cell via the third pad and the third wiring are the same type of control signal.

12. 11. The semiconductor device according to claim 2, wherein a first signal transmitted from the control circuit to the first cell via the first pad and the first wiring and a third signal transmitted from the control circuit to the third cell via the third pad and the third wiring are different types of control signals.

13. 13. The semiconductor device according to claim 11, wherein the first signal and the third signal are transmitted at different timings.

14. 14. The semiconductor device according to claim 1, wherein the first pad is arranged so as to overlap the first cell, the second pad is arranged so as to overlap the second cell, and the third pad is arranged so as to overlap the third cell.

15. The semiconductor device according to claim 1 , wherein the first wiring and the second wiring cross each other, and the third wiring and the second wiring cross each other.

16. 16. The semiconductor device according to claim 1, wherein at least one of the plurality of cells is not arranged such that the plurality of pads of the first semiconductor component and the plurality of pads of the second semiconductor component overlap the cell.

17. The semiconductor device according to claim 1 , wherein each of the plurality of cells includes a photoelectric conversion element.

18. A semiconductor device as described in any one of claims 1 to 17, wherein the first direction is perpendicular to the second direction.

19. A semiconductor device according to any one of claims 1 to 18, an optical device corresponding to the semiconductor device; A control device for controlling the semiconductor device; a processing device that processes a signal output from the semiconductor device; a display device for displaying information obtained from the semiconductor device; a storage device for storing information obtained from the semiconductor device; a mechanical device that operates based on information obtained from the semiconductor device; An apparatus comprising at least one of the following six:

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