Memory device (projection type memory device having a reduced minimum conductance state)

Abstract

To provide a memory device enabling a reduced minimal conductance state.SOLUTION: The device comprises a first electrode, a second electrode, and a phase-change material between the first electrode and the second electrode, where the phase-change material enables a plurality of conductivity states depending on the ratio between crystalline and amorphous phases of the phase-change material. The memory device additionally comprises a projection layer portion in a region between the first electrode and the second electrode. Thereby, an area directly covered by the phase-change material in the amorphous phase in a reset state of the memory device is larger than an area of the projection layer portion oriented to the phase-change material, so that a discontinuity in the conductance states of the memory device is created and a reduced minimal conductance state of the memory device in a reset state is enabled.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention generally relates to phase change memories, and more specifically to memory devices that enable a reduced minimum conductance state.

Background Art

[0002] Universities and industrial research institutes are constantly investigating new materials and methods to increase the storage density in semiconductor devices while simultaneously reducing the power consumption per stored information. In this context, resistive memory devices such as phase change memories and conductive bridge memory switches that can reverse-switch between multiple conductance states are becoming increasingly popular for multi-level data storage, as well as for in-memory and neuromorphic computing hardware.

Summary of the Invention

Problems to be Solved by the Invention

[0003] There are a few key issues for the realization of efficient drift and noise in multi-levels. The cell efficiency aspect addresses the ability to program and read the device at various levels with very low current / power consumption. The drift and noise aspect addresses the effects of drift and noise resulting from the inherent material physics that adversely affect resistive readout.

[0004] These issues have been addressed recently by a new concept of memory cells referred to as projected phase change memories, in which the phase change material is fixed to a conductive material in a projected component. In the projected memory cell, the physical mechanism of resistive storage is basically separated from the information retrieval process. The read current can bypass the amorphized phase change material, thereby flowing through a more conductive projected material with no drift and less noise.

[0005] Even if the reduced drift and read noise are highly beneficial, the concept of the device has drawbacks. The minimum conductance of the device may substantially increase. The dynamic range of the device may decrease, and the idle device (G-0) may pass more current during reading. Therefore, if the device cannot be programmed to be in an appropriate off state (G = 0), the energy efficiency of the array may decrease during reading, and the network function may be inhibited.

Means for Solving the Problem

[0006] Additional aspects or advantages or both may be described in part in the following description, in part will be apparent from the description, or may be recognized by the practice of the present invention.

[0007] According to one aspect of the present invention, a memory device may be provided that enables a reduced minimum conductance state. The device may include a first electrode, a second electrode, and a phase change material between the first electrode and the second electrode. Thereby, the phase change material may enable a plurality of conductivity states according to the ratio between the crystalline phase and the amorphous phase of the phase change material.

[0008] The memory device may also include a projection layer portion in the region between the first electrode and the second electrode. Thereby, in the reset state of the memory device, the region directly covered by the amorphous phase change material may be larger than the region of the projection layer portion directed towards the phase change material. In this way, a discontinuity in the conductance state of the memory device may be formed, and a reduced minimum conductance state of the memory device in the reset state may be realized.

Brief Description of the Drawings

[0009] The above and other aspects, features, and advantages of specific exemplary embodiments of the present invention will become more apparent from the following description when taken in conjunction with the accompanying drawings.

[0010]

Figure 1

[0011]

Figure 2

[0012]

Figure 3A

[0013]

Figure 3B

[0014]

Figure 4

[0015]

Figure 5

[0016]

Figure 6

[0017]

Figure 7

[0018] (C) and (D) show the resistance of the liner with respect to (A) and (B).

[0019] (E) and (F) show different characteristics of the read current with respect to (A) and (B).

DETAILED DESCRIPTION OF THE INVENTION

[0020] The following description is provided with reference to the accompanying drawings to assist in a comprehensive understanding of exemplary embodiments of the present invention defined by the claims and their equivalents. The following description includes various specific details for the purpose of assisting such understanding, but these should be considered merely as examples. Accordingly, those skilled in the art will recognize that various changes and modifications to the embodiments described herein are possible without departing from the scope and spirit of the present invention. Further, descriptions of well-known functions and structures may be omitted for clarity and conciseness.

[0021] The terms and words used in the following description and claims are not limited to bibliographical meanings, but are merely used to enable a clear and consistent understanding of the present invention. Accordingly, it will be apparent to those skilled in the art that the following description of exemplary embodiments of the present invention is provided for illustrative purposes only and not for the purpose of limiting the present invention defined by the appended claims and their equivalents.

[0022] The singular forms "a", "an", and "the" are understood to include plural referents unless the context clearly dictates otherwise. Thus, for example, a reference to "the component surface" includes a reference to one or more such surfaces unless the context clearly dictates otherwise.

[0023] In the context of this description, the following conventions, terms or expressions, or combinations thereof may be used.

[0024] The term "memory device" may here in particular refer to a memory cell for storing one or more bits based on a phase change material. Phase change memory (PCM) is known as a type of non-volatile random access memory. This is often based on the behavior specific to chalcogenide glass. However, the use of other materials has also been successful. The effect is based on the change in conductivity between the crystalline and amorphous phases of the PCM. The phase change may be induced by heat, for example, an electric current flowing through the device. PCMs are also sometimes referred to as memristors. These may be used not only as memory elements but also as the basis of active computing devices.

[0025] The term "minimum conductance state" may refer to the reset state of a PCM cell. In a PCM cell, when all or most of the PCM material is in the amorphous phase, the resistance increases to the highest value that the PCM can take. This state may represent a state having the minimum conductance for each PCM cell.

[0026] The term "projection layer part" or in another word "liner" may refer to a more or less conductive material that is located parallel to the phase change material of the PCM cell and in particular in one embodiment is in contact with one of the two electrodes of the cell, i.e., can be a mushroom version. In the case of other embodiments, in particular in the horizontal confinement version, the projection layer part is not in contact with either of the electrodes. The projection layer part may also be referred to as a confinement-type liner or confinement-type projection that does not extend over the entire length of the volume of the phase change memory.

[0027] In a projection-type memory cell, the projection layer may serve to separate the physical mechanism of resistive storage from the information retrieval process. The read current bypasses the amorphous phase change material and flows through the projection material with no drift, little noise, and higher conductivity. In contrast to the newly proposed concept of a confinement-type projection or liner herein, conventional projection-type memory cells also have drawbacks. The minimum conductance of the device may substantially increase. Thus, the dynamic range of the device decreases, and the reset device (G is about 0) may draw more current during reading. Therefore, since the cell cannot be programmed to an appropriate off state (G = 0), the power efficiency of the memory cell may decrease during reading.

[0028] Therefore, the projection layer portion that can potentially cover only a part of the phase change material in the reset state may be a layer portion with potentially larger or very low conductivity, i.e., a "confinement-type projection" within the non-projection portion. Thus, the projection layer portion may construct the projection layer together with the non-projection portion.

[0029] The term "non-projection portion" may refer to a portion of the projection layer of a phase change memory cell having a conductivity much lower than that of the confinement-type projection portion or liner.

[0030] The term "reset state" may refer to a state of a phase change memory cell in which the conductivity is as low as possible, i.e., low enough that most of the phase change material is in the amorphous phase.

[0031] The term "discontinuity in the conductance state" may refer to the conductance state of a phase change memory cell. Alternatively, at a specific point where the amorphous phase change material covers an area larger than the maximum area of the liner or projection layer portion, a stepwise increase or decrease can be observed in the current-voltage line (depending on the perspective).

[0032] The proposed memory device that enables a reduced minimum conductance state may provide multiple advantages, contributions, and technical effects.

[0033] Substantially lower drift and conductance variations result from 1 / f of the memory cell or memory device (f = frequency). This is a result of the fact that most of the read current bypasses the amorphous volume in the reset state of the memory cell.

[0034] The absolute noise level of the reset cell state is related to the use of the device, for example, neuromorphic computing, training, and inference of conventional deep neural networks based on phase change memory. This effect may be advantageously used in crossbar arrays of memristive cells. These applications may benefit from a low conductance (G MIN ) device state for several reasons. Many weights in deep neural networks are small or close to zero. To encode such weights, low G MIN may be required.

[0035] G MIN If it is too high, two devices of different configurations must be programmed to the same conductance representing zero. It can be very difficult to program two devices to exactly the same conductance, and thus this method results in unacceptably high noise at zero weight, which can be completely avoided if the device can be programmed to a sufficiently low G MIN .

[0036] Furthermore, if small or near-zero weights can be encoded by the G MIN (reset) device state, the power consumption of the associated deep neural network can be substantially reduced because G MIN is reduced by at least one order of magnitude.

[0037] Improvements over conventional approaches also include achieving the projection in an intermediate conductance range that may be associated with multi-level programming of the memory device by confining the projection layer or liner to an area smaller than the active volume (the maximum amorphous volume formed during device reset). However, this is not achieved in the low conductance state G MIN . Thus, relaxation of drift can be achieved in the intermediate and high conductance states. Accordingly, a substantially reduced G MIN may allow for a higher dynamic range, whereby drift and noise in G MIN may become irrelevant in the described (and other) uses of the memory device.

[0038] In this way, the advantages of the projection type phase change memory cell can be realized, and it may also be successful in avoiding disadvantages.

[0039] According to an advantageous embodiment of the memory device, the projection layer portion may cover one of the first and second electrodes. Such a design may typically be referred to as a "mushroom cell type". The reason is that typically the lower electrode can penetrate the dielectric and the liner or projection layer portion can be located on top of the lower electrode, i.e., the bottom electrode. The amorphous phase change material may expand hemispherically above the liner and take on the appearance of a mushroom (together with the lower electrode).

[0040] According to an embodiment of the memory device, both the first electrode and the second electrode may be in contact with the dielectric layer in areas where the first electrode and the second electrode are not in contact with the phase change material, the projection layer portion may extend laterally above the dielectric layer, and the surface of the projection layer portion facing the surface of the projection layer that is not facing the dielectric material may be in contact with the phase change material. Such a phase change memory cell design may be referred to as a "lateral cell design".

[0041] According to an embodiment of the memory device, the dielectric layer portion may surround the phase change material (in particular, only a part thereof, from the top to the bottom electrode). This cell design may be defined as a "constrained" phase change memory cell design. The phase change material may be located in the middle and may be partially surrounded by a projection layer portion that is completely enclosed by the dielectric material. The first and second electrodes that can be implemented as the top and bottom electrodes may be in contact with the phase change material. As a result, according to an improved embodiment of the memory device, the projection layer portion may be located around the phase change material, and the projection layer portion may be surrounded by the dielectric material.

[0042] According to a preferred embodiment of the memory device, the projection layer portion is Ti x N y , Ta x N y or may contain amorphous carbon. These materials may be advantageously used as liner materials due to their conductivity that can be clearly defined according to the doping level.

[0043] According to an additional embodiment of the memory device, the projection layer portion may be extended by a non-projection portion having a (significantly) lower conductivity than the projection layer portion. Both, i.e., the projection layer portion and the non-projection portion, may construct one projection layer and a non-projection layer portion having a region of higher conductivity (i.e., the projection layer portion) and a region of lower or non-conductivity. Both portions may be located on the dielectric material. The different conductivity characteristics may be realized by different doping processes of different portions of the projection layer. Alternatively, the non-projection portion of the projection layer may be completely omitted.

[0044] According to a preferred embodiment of the memory device, the following conditions may be satisfied. R NON-PROJECTING >>R AMORPHOUS >>R PROJECTION Here, R NON-PROJECTING = Resistance of the non-projection portion R AMORPHOUS = Resistance of the phase change material when the region covered by the crystalline phase of the phase change material can cover the entire projection layer portion R PROJECTION = Resistance of the projected layer part Therefore, when the volume of the phase change material is large enough, i.e., it grows to cover the entire liner, the current can no longer bypass the amorphous part of the phase change material through the liner, and thus a discontinuity in the current-voltage curve may occur.

[0045] According to an embodiment of the memory, the projected layer part and the non-projected layer part may be doped differently. The doping concentration of the material may depend on whether the conductivity increases or decreases. Exemplarily, H 2 or N 2 may be used as the doping material.

[0046] According to an embodiment of the memory device, the non-projected layer part and the projected layer part may be doped such that the device current can be at least halved compared to the state where the entire projected liner part (i.e., the liner) can be covered by the amorphous phase change material (when the amorphous phase change material can cover the entire projected layer part). This can also be seen as a result of the relationship between the resistances of different materials, i.e., the non-projected part, the projected part, and the amorphous phase change material.

[0047] According to an embodiment of the memory device, the doping between the projected layer part and the non-projected layer of the projected layer may change according to a predetermined gradient. Therefore, a higher degree of dependence between the current flowing through the projected layer and the amorphous phase change material may be formed.

[0048] According to an embodiment of the memory device, the projected layer part or the non-projected layer part or both may be doped with hydrogen or nitrogen. These materials have been proven to be practical for the design of these types of memory cells and confinement-type projected layers. These may increase or decrease the conductivity of the materials of the respective layers. Known mask processes may be used to control the doping process.

[0049] According to an embodiment of the memory device, the dopant concentration that increases the conductivity may be higher in the projected layer portion (i.e., the liner) compared to the non-projected layer portion. This is a logical result of the design principle used here. The projected layer portion enables the current flowing through this part of the device to flow easily. The opposite event applies to the non-projected portion.

[0050] According to an embodiment of the memory device, the dopant concentration that decreases the conductivity may be higher in the non-projected portion compared to the projected portion. Again, this may be a logical result of the proposed cell design.

[0051] According to an embodiment of the memory device, during a read operation to the memory device, R CRYST <<R PROJECTION where R CRYST is the resistance of the crystalline phase change material, and R PROJECTION is the resistance of the projected layer portion. Therefore, most of the current flowing through the cell may flow through the crystalline phase change material instead of flowing through the projected layer portion.

[0052] According to a further embodiment of the memory device, R AMORPHOUS >>R PROJECTION This relationship may help the read operation to function properly.

[0053] The following shows a detailed description of the figures. In the figures, all instructions are schematic. In particular, a block diagram of an embodiment of the memory device according to the present invention that enables a reduced minimum conductance state is shown.

[0054] FIG. 1 shows a block diagram of an embodiment of a memory device 100 according to the present invention that enables a reduced minimum conductance state. The memory device 100 (here in the form of a single cell) shows liner layers 110, 118 patterned on a dielectric material 102. A bottom electrode 106 is in contact with an intermediate portion of the liner, i.e., the projection layer portion 110. On the projection layer portion 110, phase change materials in a crystalline state 108 and amorphous states 112, 114, 116 are shown. An upper electrode 104 exists on the phase change material 108.

[0055] Reduced G MIN The state can be formed by patterning the projection layers 110, 118 into a projection layer portion 110 and a non-projection layer portion 118. The letter G refers to conductivity (1 / resistance). The liner 110 at the center of the volume of the active device has a low resistance and enables projection (especially in the non-reset state), whereby, for example, less than about 10% of the read current analyzes the amorphous volumes 112, 114, 116.

[0056] Thereby, the dimensions of the low-resistance liner are limited to a region smaller than the maximum dimension of the amorphous dome of the illustrated mushroom-type cell design. This is indicated by a boundary line 120 between the projection layer portion 110 and the non-projection layer portion 118. As a result of the constrained liner or projection layer portion 110, once an amorphous volume of critical dimensions is formed, i.e., once the region of the amorphous portion of the phase change material in contact with the projection becomes larger than the low-resistance projection layer portion 110, the programming curve of the device shows a discontinuity. This is shown in FIG. 2.

[0057] FIG. 2 shows a graph 200 of the conductivity of a conventional projection-type liner compared to the patterned projection proposed here. Line 202 is the conductivity G of the cell CELLis shown by comparing it with the write current I for different states of the cell. When the volume of the amorphous portion of the phase change material once grows larger than the horizontal extension of the projection layer portion 110 (i.e., the amorphous dome blocks the entire projection layer portion 110), the cell conductivity significantly decreases (the two conductivity states are shown as black-filled circles on the right side of the dashed line). Therefore, the reset conductance is significantly smaller than that of a conventional projection-type memory cell.

[0058] FIG. 3A shows again, as background art, a typical design of a conventional projection-type memory device 300. This includes a top electrode 302 and a bottom electrode 304. Between these, a projection layer 306 surrounding a phase change material 308 is shown.

[0059] During the write process, a current (represented by a straight dotted line from the top electrode 302 to the bottom electrode 304) passes through the crystalline phase change material 308 and constructs an amorphous phase 310 somewhere in the middle between the top electrode and the bottom electrode. The graph in FIG. 3B shows that thereby the resistance R CRYST is much smaller than the resistance R PROJECTION of the projection layer portion, i.e., R CRYST << R PROJECTION which indicates that during the read process, since R AMORPHOUS >> R PROJECTION the current (represented by the second dashed line) from the top electrode 302 to the bottom electrode 304 may surround the amorphous portion 310 of the phase change material 308.

[0060] Due to this projection concept, the physical mechanism of resistance storage is separated from the information retrieval process, i.e., reading. This utilizes the inherent electrical transport and structural dynamics in the memory material, i.e., the phase change material.

[0061] This is again shown by a graph 312 showing a current I that depends on the voltage supplied to the phase change memory cell. The projection layer shows a constant resistance (flat line). At a specific point of the resistance of the amorphous phase (AMOR), there is a point where the cell resistance changes abruptly. The portion of the curve indicated as "AMOR, ON" is the point where the phase change material changes at least partially to the crystalline phase, thereby reducing the resistance, i.e., increasing the conductance.

[0062] FIG. 4 shows a crossbar array 400 of neural network cells that may be used as a basis for programming weight values for, for example, a deep neural network (DNN). The above-described effects can be particularly advantageous when mapping a deep neural network structure to the crossbar array 400 of phase change memory cells. In many cases, only a smaller portion 402 of a larger crossbar array 400 of phase change memory cells may be used in an actual implementation. Thus, more phase change memory cells are available in such a device than are actually needed and used. In these unused phase change memory cells, their conductivities in the reset state (i.e., a large amorphous volume) exhibit only very small conductivities and are best equal to zero in an ideal case.

[0063] This clearly minimizes the power consumption of the array during reading, and thus increases the network efficiency. The reason for this is that most of the weights of a deep neural network that can be encoded by the phase change memory cells of the array are typically zero, or at least close to zero. Improved G MIN states make it possible to directly map these weights to the device state without adding any electronic components. Thus, different device configurations are not required. Since the network efficiency is improved, the deep neural network efficiency can also be significantly improved, particularly in relation to inference applications.

[0064] In addition to the mushroom type device design of FIG. 1, FIG. 5 shows a lateral cell design 500 above the dielectric layer 502. A crystalline phase change material 508 is positioned between a first electrode 504 and a second electrode 506. A patterned projection liner 510 is shown below the amorphous phase change materials 512, 514, 516. In the same layer, the region 518 (i.e., non-projection layer portion) outside the projection layer portion 510 has a much higher resistance (i.e., much lower conductance) than the central projection 510.

[0065] The amorphous phases of the phase change material are shown as having different diameters 512, 514, 516 indicative of different states of the phase change memory cell. The two exemplary states shown by the volumes 512 and 514 of the phase change memory do not completely cover the projection layer portion 510. However, when the amorphous volume 516 of the phase change memory covers a region larger than the projection layer portion 510, the reset state (G MIN ) is reached. This is because the current from the first electrode 504 to the second electrode 506 must mainly flow through the amorphous phase change material.

[0066] FIG. 6 shows a constrained design of a phase change memory cell or device based on the concept proposed herein. Here, a crystalline phase change material 608 is positioned between a top electrode 604 and a bottom electrode 606. The entire device is surrounded by a dielectric layer 602. It can also be seen that a projection layer portion 610 surrounds an intermediate portion of the phase change material 608. Different volumes 612, 614, 616 of the amorphous phase of the phase change material of the memory cell are also shown. When the amorphous portion 616 of the phase change memory material grows larger than the region covered by the projection layer portion 610, the device 600 reaches the reset state, i.e., G MIN . It is also explained that the region 618 (i.e., non-projection layer portion) has a much higher resistance than the projection layer portion 610.

[0067] Therefore, in the horizontal type (Figure 5) and the constrained cell design (Figure 6), the lengths of the projection layer portions 510 and 610 are each limited to be smaller than the length of the longest amorphous that can be formed in the device during reset. In comparison, in the mushroom cell (comparing Figure 1), the projection area 104 is constrained to the area completely covered by the amorphous hemisphere formed in the device during reset.

[0068] Furthermore, it is also possible to use a stepped liner layer having a core projection portion in the middle of the liner. By doing so, the transition between the uncovered liner portion and the completely covered liner can be made smoother. For this purpose, a liner 704 having a doping concentration gradient may be used. The liner 704 becomes more resistive from the center of the amorphous volume to each end. This is shown in the contrast comparison 700 in Figures 7(A) and (B) between the version of the cell described in the context of Figure 1 and the version of the gradient-type liner on the right side of Figure 7. Therefore, Figure 7(A) repeats the mushroom cell design from Figure 1, and Figure 7(B) relates to the doping concentration gradient of the liner 710.

[0069] Note that the reference numbers are those used in Figure 1 in a broad range, and the mushroom cell design on the left has a distinct vertical line 120 between the projection layer portion 110 of the liner and the remaining portion 118 (non-projection portion) of the projection layer. The cell design as a comparison in Figure 7(B) on the right shows rising and falling ends between the central portion (i.e., the liner) of the projection portion 710 and the remaining portion 118 (non-projection portion).

[0070] As a result, the resistance of the liner regarding the left design (Figure 7(C)) shows a sharp increase and decrease in resistance, and the right design shows that the resistance of the liner portion increases and decreases step by step (Figure 7(D)). This can also be understood as different characteristics of the read current I READ In the left design (Figure 7(E)), the volume of the amorphous portion of the phase change material AMOR)Accordingly, the decrease in the read current is steep. In contrast, in the memory cell design on the right side (Fig. 7(F)), the decrease in the read current exhibits a much smoother (smaller slope) characteristic due to the growth of the volume of the amorphous phase of the phase change material.

[0071] The descriptions of the various embodiments of the present invention are presented for illustrative purposes, but are not intended to be exhaustive or to limit the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, a practical application to technologies found in the market or a technical improvement, or to enable other skilled artisans to understand the embodiments disclosed herein.

[0072] The present invention may be embodied with a system, the use of a memory device or a computer program product or both, and associated methods. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions for causing a processor to execute aspects of the present invention.

[0073] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0074] The flowchart and / or block diagram of the figures, either alone or in combination, illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It should also be noted that each block of the block diagrams and / or flowchart illustrations, and combinations of blocks in the block diagrams and / or flowchart illustrations, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

[0075] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises" and / or "comprising", when used herein, specify the presence of the stated function, integer, step, operation, element, and / or component, but do not preclude the presence or addition of one or more other functions, integers, steps, operations, elements, components, and / or groups thereof.

[0076] All means or steps plus function elements described in the following claims, corresponding structures, materials, acts, and equivalents thereof, are intended to include any structure, material, or act for performing the functions, as specifically claimed, in combination with other elements recited in the claims. The description of the invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limiting. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. Embodiments are selected and described in order to best explain the principles of the invention and practical applications, to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.

[0077] Based on the foregoing description, a computer system, method, and computer program product have been disclosed. However, numerous modifications and substitutions can be made without departing from the scope of the invention. Accordingly, the invention has been disclosed by way of example and not limitation.

[0078] The invention has been illustrated and described with reference to specific exemplary embodiments thereof, but it will be understood by those of ordinary skill in the art that various changes in form and detail can be made therein without departing from the spirit and scope of the invention as defined by the appended claims and their equivalents.

[0079] The description of various embodiments of the invention has been presented for purposes of illustration, but is not intended to be exhaustive or to limit the invention to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein have been selected to best explain the principles of one or more embodiments, practical applications, or technical improvements found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A memory device enabling a reduced minimum conductance state, the memory device comprising: a first electrode, a second electrode, a phase change material between the first electrode and the second electrode, a projection layer provided in a region between the first electrode and the second electrode, the projection layer having a projection layer portion and a non-projection portion having a lower conductivity than the projection layer portion, wherein R NON-PROJECTING >> R AMORPHOUS >> R PROJECTION, R NON-PROJECTING is the resistance of the non-projection portion, R AMORPHOUS is the resistance of the phase change material when a region covered by the crystalline phase of the phase change material covers the entire projection layer portion, R PROJECTION is the resistance of the projection layer portion, in the reset state of the memory device, a region directly covered by the amorphous phase of the phase change material is larger than a region of the projection layer portion directed toward the phase change material, thereby forming a discontinuity in the conductance state of the memory device and enabling a reduced minimum conductance state of the memory device in the reset state. A memory device.

2. A memory device enabling a reduced minimum conductance state, the memory device comprising: a first electrode, a second electrode, a phase change material between the first electrode and the second electrode, a projection layer provided in a region between the first electrode and the second electrode, the projection layer having a projection layer portion and a non-projection portion having a lower conductivity than the projection layer portion, wherein the projection layer portion and the non-projection portion are doped differently, the doping of the non-projection portion and the projection layer portion is such that when the amorphous phase of the phase change material covers the entire projection layer portion, the device current is at least halved compared to the state where the projection layer portion is covered by the amorphous phase of the phase change material, in the reset state of the memory device, a region directly covered by the amorphous phase of the phase change material is larger than a region of the projection layer portion directed toward the phase change material, thereby forming a discontinuity in the conductance state of the memory device and enabling a reduced minimum conductance state of the memory device in the reset state. A memory device.

3. A memory device enabling a reduced minimum conductance state, wherein the memory device comprises: a first electrode, a second electrode, a phase change material between the first electrode and the second electrode, a projection layer provided in a region between the first electrode and the second electrode, the projection layer having a projected layer portion and a non-projected portion having a lower conductivity than the projected layer portion and the projected layer portion and the non-projected portion are doped differently, the doping between the projected layer portion and the non-projected portion of the projection layer varies according to a predetermined gradient, in a reset state of the memory device, a region directly covered by the amorphous-phase phase change material is larger than a region of the projected layer portion facing the phase change material, thereby forming a discontinuity in the conductance state of the memory device and enabling a reduced minimum conductance state of the memory device in the reset state. A memory device. **Claim 4** The memory device according to any one of claims 1 to 3, wherein the projected layer portion covers one of the first electrode and the second electrode. **Claim 5** The projection layer is provided between the phase change material and the first electrode, further comprising a dielectric layer provided adjacent to the first electrode and the projection layer, an upper surface of the dielectric layer is in contact with a lower surface of the projection layer, a side surface of the dielectric layer is in contact with a side surface of the first electrode, and an upper surface of the first electrode is smaller than a lower surface of the projected layer portion, The memory device according to claim 4. **Claim 6** Both the first electrode and the second electrode are in contact with a dielectric layer in a region where the first electrode and the second electrode are not in contact with the phase change material, the projected layer portion extends laterally above the dielectric layer, a surface of the projected layer portion facing a surface of the projected layer portion not facing the dielectric layer is in contact with the phase change material The memory device according to any one of claims 1 to 3. **Claim 7** The memory device according to claim 6, wherein the dielectric layer surrounds the phase change material. **Claim 8** The memory device according to claim 7, wherein the projected layer portion is located around the phase change material, and the projected layer portion is surrounded by the dielectric layer. **Claim 9** The projection layer part is Ti ｘ N ｙ , Ta ｘ N ｙ The memory device according to any one of claims 1 to 8, including amorphous carbon. **Claim 10** The non-projected portion extends over the dielectric layer. The memory device according to claim 5 or 6. **Claim 11** The memory device according to claim 1, wherein the projection layer portion and the non-projection portion are doped differently. **Claim 12** The memory device according to any one of claims 2, 3, or 11, wherein the projection layer portion, the non-projection portion, or both are doped with hydrogen or nitrogen. **Claim 13** The memory device according to claim 12, wherein the dopant concentration for increasing the conductivity is higher in the projection layer portion than in the non-projection portion. **Claim 14** The memory device according to claim 12, wherein the dopant concentration for decreasing the conductivity is higher in the non-projection portion than in the projection layer portion. **Claim 15** During the read operation to the memory device, R ＣＲＹＳＴ <<R ＰＲＯＪＥＣＴＩＯＮ where R ＣＲＹＳＴ is the resistance of the phase change material in the crystalline phase, and R ＰＲＯＪＥＣＴＩＯＮ is the resistance of the projection layer portion, the memory device according to any one of claims 1 to 14. **Claim 16** The memory device according to any one of claims 1 to 15, wherein the non-projection portion is in contact with the phase change material in the amorphous phase and the phase change material in the crystalline phase.

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