Latch Circuit Device and Port Sampling System

Abstract

To provide technology that, when a plurality of input signals are input to a microcomputer, suppresses the number of input ports occupied for input and enables a signal generated during sleep of the microcomputer to be input after wakeup.SOLUTION: A latch circuit device includes: a latch circuit that latches an input signal to a microcomputer; a detection circuit that detects the input signal during a sleep period when the microcomputer is in a sleep state; a wake-up circuit that transmits, when the input signal is detected during the sleep period, a wake-up signal to the microcomputer; a sampling circuit that reads the input signal from the latch circuit; a transmission circuit that transmits, on the basis of the wake-up signal, the input signal read by the sampling circuit, to the microcomputer that returns from the sleep state; and a release circuit that releases, after reading the input signal, a latch state of the latch circuit.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a latch circuit device and a port sampling system.

Background Art

[0002] Patent Document 1 discloses a device that periodically changes the output level of an output port based on a sampling period set in a register by a CPU, and when a data latch unit latches data given to an input port based on a timing signal starting from the change in the output level, stores the latched data in a data register.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] For example, in a microcomputer used in an in-vehicle device, with the increasing functionality of the device, the number of input signals tends to increase. However, the number of input ports of the microcomputer is limited, and there is a problem that not all required signals can be input. Therefore, it is conceivable to convert a plurality of input signals from parallel to serial and input them to the microcomputer via a serial communication path. However, when inputting to a microcomputer in a sleep state, it is conceivable that the value of the input signal changes before the microcomputer is restored from the sleep state, the input signal is converted, and input to the microcomputer, and there is a problem that the input cannot be performed appropriately.

[0005] The object of the present invention is to provide a technology that suppresses the number of input ports occupied for input when a plurality of input signals are input to a microcomputer, and enables the input of signals generated during the sleep of the microcomputer after wake-up.

Means for Solving the Problems

[0006] To solve the above problems, the latch circuit device of the present disclosure includes: a latch circuit that latches an input signal to a microcomputer; a detection circuit that detects that the input signal has been input to the latch circuit during a sleep period in which the microcomputer is in a sleep state; a wake-up circuit that transmits a wake-up signal to the microcomputer when the input of the input signal is detected during the sleep period; a sampling circuit that reads the input signal from the latch circuit; a transmission circuit that transmits the input signal read by the sampling circuit to the microcomputer that has returned from the sleep state based on the wake-up signal; a release circuit that releases the latch state of the latch circuit after the input signal is read; and is provided with.

Advantages of the Invention

[0007] According to the present invention, when a plurality of input signals are input to a microcomputer, it is possible to provide a technology that suppresses the number of input ports occupied for input and enables the input of signals generated during the sleep of the microcomputer after wake-up.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Best Mode for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The configurations of the following embodiments are examples, and the present invention is not limited to the configurations of the embodiments.

[0010] FIG. 1 is a diagram showing the configuration of a port sampling system 1. The port sampling system 1 of the present embodiment includes a microcomputer 10 and a latch circuit device 20 that latches an input signal to the microcomputer 10 and transmits the latched input signal to the microcomputer 10. The latch circuit device 20 includes a latch circuit 21 and a multi-input IC 22. Further, the port sampling system 1 may include a power supply or may be configured to receive power supply from an external power supply. The port sampling system 1 of the present embodiment is used in an in-vehicle device, receives power supply from a vehicle-side battery, and an input signal is input from an ECU (Electronic Control Unit). Note that the port sampling system 1 is not limited to being used in an in-vehicle device. The stem 1 is not limited to being used in an in-vehicle device.

[0011] <Microcomputer> The microcomputer 10 includes a control unit 11, an interrupt circuit 12, a serial communication circuit 13, an output circuit 14, and ports P11 to P19. The microcomputer 10 is a so-called one-chip microcomputer in which these configurations are provided in one IC.

[0012] The control unit 11 is composed of a processor and a memory, and comprehensively executes various arithmetic processes in the microcomputer 10. The processor is, for example, a CPU (Central Processing It is arithmetic processing means such as a unit, a DSP (Digital Signal Processor), or an FPGA (Field-Programmable Gate Array). The storage unit is, for example, a RAM (Random Access Memory) or a ROM (Read Only Memory), and is used as a main storage unit or an auxiliary storage unit.

[0013] The control unit 11 periodically transmits a read request for the input signal to the latch circuit device 20 via the serial communication circuit 13. Also, the control unit 11 acquires the input signal read in response to the read request from the multi-input IC 22 via the serial communication circuit 13, and executes processing according to the input signal. Further, the control unit 11 performs processing for shifting the microcomputer 10 to the normal state or the sleep state in response to an interrupt signal such as a wake-up signal or a sleep signal. Regarding the transition to the sleep state, the control unit 11 may comprehensively judge and transition based on the latch circuit device 20 and other input signals.

[0014] When the interrupt circuit 12 receives an interrupt signal, it inputs this to the control unit 11. For example, when receiving a wake-up signal as an interrupt signal, it notifies the control unit 11 and causes the wake-up processing for transitioning from the sleep state to the normal state to be performed. Also, when receiving a sleep signal as an interrupt signal, it notifies the control unit 11 and causes the sleep processing for transitioning from the normal state to the sleep state to be performed. Note that the interrupt circuit 12 monitors the interrupt signal even during sleep. Also, when the interrupt circuit 12 receives a wake-up signal, it may operate the relay for power supply to start the power supply to each functional unit such as the control unit 11, the serial communication circuit 13, and the output circuit 14. Also, when the sleep processing by the control unit 11 is completed, the interrupt circuit 12 may open the relay for power supply to stop the power supply to each functional unit such as the control unit 11, the serial communication circuit 13, and the output circuit 14. supply may be stopped.

[0015] The serial communication circuit 13 performs serial communication with the multi-input IC 22 of the latch circuit device 20. The serial communication circuit 13 is a form of a receiving circuit that receives an input signal from the multi-input IC 22 or a transmitting circuit that transmits a signal to the multi-input IC 22.

[0016] The output circuit 14 is a circuit that outputs a signal to an external device. For example, when the microcomputer 10 receives an input signal from the multi-input IC 22, it sends a latch clear signal (release signal) to the latch circuit 21 to release the latched state.

[0017] The ports P11 to P19 are terminals that connect to external signal lines and are used for inputting signals into the microcomputer or outputting signals from the microcomputer to the outside.

[0018] <Latch circuit device> In the latch circuit device 20, a plurality of input signals D1 to D9 for the microcomputer 10 are input from other devices such as an ECU. Among these, the input signals D4 to D9 are signals (hereinafter also referred to as wake-up target signals) that, when input while the microcomputer 10 is in a sleep state, send a wake-up signal to wake up the microcomputer 10. In FIG. 1, the input signals D1 to D3 are directly input to the input ports P21 to P23 of the multi-input IC 22 via the signal lines L1 to L3. On the other hand, the input signals D4 to D9 are input to the latch circuit 21 via the signal lines L4 to L9 and then input from the latch circuit 21 to the ports P24 to P29 of the multi-input IC 22.

[0019] The latch circuit 21 is a circuit that holds an input signal when the input signal is input. For example, when the state where the input signal is not input is Lo and becomes Hi when the input signal is input, this Hi state is held. Also, the latch circuit 21 may be configured to hold the Lo state when the state where the input signal is not input is Hi and becomes Lo when the input signal is input. The latch circuit 21 is, for example, a flip-flop. Further, the latch circuit 21 includes a clear terminal 211, and this clear terminal 211 is connected to the output port P19 of the microcomputer 10, and when the microcomputer 10 completes receiving the input signal, a clear signal is transmitted to the latch circuit 21. The latch circuit 21 includes a release circuit 212 that releases the latch state of the latch circuit 21 and sets it to the state where the input signal is not input (initial state) when it receives the clear signal from the output port P19 of the microcomputer 10.

[0020] The multi-input IC 22 includes a port sampling circuit 23, a CR oscillation circuit 24, a serial communication circuit 25, and ports P21 to P29, P31 to P34.

[0021] The port sampling circuit 23 reads the input signals D1 to D9 in response to a read request. Also, the port sampling circuit 23 reads the input signals D1 to D9 at a timing based on the clock signal generated by the CR oscillation circuit 24. Since the microcomputer 10 periodically transmits a read request to the multi-input IC 22 via the serial communication circuit 13, the port sampling circuit 23 periodically reads the input signals D1 to D9.

[0022] Also, the port sampling circuit 23 detects that the input signals D4 to D9 are input to the latch circuit 21 during the sleep period when the microcomputer 10 is in the sleep state. That is, the port sampling circuit 23 of the present embodiment is a form of the detection circuit. Further, when the input of the input signals D4 to D9 is detected during the sleep period, the port sampling circuit 23 transmits a wake-up signal to the microcomputer 10. That is, the port sam pling circuit 23 is a form of the wake-up circuit.

[0023] The serial communication circuit 25 transmits the input signal read by the port sampling circuit 23 to the microcomputer. Here, when the input signal is input during the sleep period of the microcomputer 10, the microcomputer 10 performs wake-up processing in response to the wake-up signal and transmits it to the microcomputer 10 that has returned from the sleep state. The serial communication circuit 25 of the present embodiment is a form of the transmission circuit.

[0024] The serial communication circuit 25 of the multi-input IC 22 and the serial communication circuit 13 of the microcomputer 10 are connected by a serial communication line 30. The serial communication line 30 has communication lines 31 to 35. One ends of the communication lines 31 to 34 are connected to the ports P11 to P14 of the microcomputer 10, and the other ends are connected to the ports P31 to P34 of the multi-input IC 22. A clock signal for synchronizing communication is transmitted from the microcomputer 10 through the communication line 31. The communication line 32 is a line through which the microcomputer 10 transmits data, that is, a line through which the multi-input IC 22 receives data. The communication line 33 is a line through which the multi-input IC 22 transmits data, that is, a line through which the microcomputer 10 receives data. The communication line 34 is a line through which the microcomputer 10 transmits a chip select signal to indicate the communication partner.

[0025] As described above, in this embodiment, four communication lines 31 to 34 are used for serial communication between the microcomputer 10 and the multi-input IC 22, but the configuration is not limited to this. For example, a part of the communication lines 31 to 34 may be omitted. One end of the communication line 35 is connected to the port P15 of the microcomputer 10, and the other end is connected to another IC chip 39. The communication lines 31 to 33 are also connected to the IC chip 39 and are shared by the IC chip 39 and the multi-input IC 22. The communication line 35 is a line (select communication line) for sending a chip select signal when the microcomputer 10 communicates with the IC chip 39. When communicating with an IC chip other than the multi-input IC 22 in this way, the communication lines 31 to 33 can be shared, and the number of select communication lines can be increased by the number of IC chips. The microcomputer 10 transmits a chip select signal to the select communication line of the communication partner, for example, and the IC chip that receives the chip select signal communicates with the microcomputer 10 using the communication lines 31 to 33.

[0026] Also, the serial communication circuit 25 performs parallel / serial conversion on the input signals read through the input ports P21 to P29. FIG. 2 is an explanatory diagram of the process of parallel / serial conversion of the input signal. As shown in FIG. 2, the serial communication circuit 25 arranges the input signals D1 to D9 read in parallel from the input ports P21 to P29 in a predetermined order serially to form a serial signal 42. Perform parallel / serial conversion. The read input signal is converted into a serial signal, and the returned serial signal is transmitted to the microcomputer 10 via the communication line 33. Thereby, nine types of input signals can be input to one input port via one communication line 33, and the number of input ports occupied when transmitting a plurality of input signals can be suppressed.

[0027] <Operation> FIG. 3 is a time chart showing the timings of serial communication, port sampling, latch clear, and wake-up in the port sampling system 1. In FIG. 3, the horizontal axis represents the passage of time. In FIG. 3, timing T1 is the time when the power is connected to the port sampling system 1. For example, the timing when an in-vehicle device equipped with the latch circuit device 20 and the microcomputer 10 of the port sampling system 1 is mounted on a vehicle and the in-vehicle device is connected to the battery on the vehicle side is T1. By connecting this power supply, the latch circuit device 20 and the microcomputer 10 perform initial settings. For example, among the ports P24 to P29 of the multi-input IC22, when there is an input to which port, the microcomputer 10 is woken up, whether the edge when the input signals D4 to D9 change from Lo to Hi is the valid edge or the edge when they change from Hi to Lo is the valid edge, or when the input signals D1 to D9 are in what state, the microcomputer 10 is set to the sleep state, etc. The setting information is set in the register. Among ports P24 to P29 of multi-input IC22, when there is an input to which port, the microcomputer 10 is woken up, whether the edge when the input signals D4 to D9 change from Lo to Hi is the valid edge or the edge when they change from Hi to Lo is the valid edge, or when the input signals D1 to D9 are in what state, the microcomputer 10 is set to the sleep state, etc. The setting information is set in the register.

[0028] After the timing T2 when the initial setting is completed, the latch circuit device 20 and the microcomputer 10 perform normal operations. For example, the microcomputer 10 issues a read request to the multi-input IC22 via the serial communication circuit 13. The multi-input IC22 that has received the read request reads (samples) the input signals input to the input ports P21 to P29 and transmits the read input signals to the microcomputer 10 via the serial communication circuit 25. When the reception of the input signal is completed, the microcomputer 10 transmits a clear signal 41 from the output port P19 to the clear terminal 211 of the latch circuit 21. The latch circuit 21 that has received the clear signal 41 clears the state of the latched input signal. The processing from this read request to the clearing of the latch circuit 21 is repeated at a predetermined cycle while the microcomputer 10 is in the normal state, that is, until it enters the sleep state.

[0029] When the microcomputer 10 enters the sleep state (T3), the microcomputer 10 does not perform normal operations such as serial communication, but periodically reads (samples) the input signals input to the input ports P21 to P29 by the multi-input IC 22. Then, when the read input signal satisfies the wake-up condition, for example, when any of the wake-up target signals is input, the multi-input IC 22 transmits a wake-up signal to the microcomputer 10.

[0030] When the microcomputer 10 that has received the wake-up signal performs wake-up processing and wakes up (T4), the microcomputer 10 and the latch circuit device 20 perform the processing from the read request to the clear of the latch circuit 21 in the same manner as in the normal operation.

[0031] <Advantages of the Embodiment> As described above, in the port sampling system 1 of the present embodiment, when an input signal is input during the sleep period of the microcomputer 10 and latched by the latch circuit 21, a wake-up signal is transmitted to the microcomputer 10 to wake it up, and the input signal latched by the microcomputer 10 after wake-up is transmitted.

[0032] Thereby, the port sampling system 1 of the present embodiment can appropriately send the input signal input during the sleep period of the microcomputer 10 to the microcomputer 10.

[0033] The port sampling system 1 of this embodiment converts a plurality of input signals read from the latch circuit 21 into serial signals and transmits them to the microcomputer 10 via the serial communication line 30. Thereby, the port sampling system 1 of this embodiment can suppress the number of input ports occupied even when a large number of input signals are input to the microcomputer 10. For example, in this embodiment, serial communication is performed using four communication lines 31 to 34, and nine input signals (six of which are wake-up target signals) can be transmitted using the ports P11 to P14 of the microcomputer 10, suppressing the number of ports P11 to P14 used by five. Further, in the port sampling system 1 of this embodiment, the multi-input IC 22 shares the serial communication lines 31 to 34 with other IC chips, and the port P14 of the microcomputer 10 occupied for transmitting the input signal is substantially one, effectively suppressing the number of input ports occupied.

[0034] When the microcomputer 10 is in the normal state, the port sampling circuit 23 of the port sampling system 1 of this embodiment periodically receives a read request signal from the microcomputer 10, reads the input signal from the latch circuit in response to the read request signal, and transmits the read input signal to the microcomputer. Further, after the input signal is received by the microcomputer 10, the release circuit releases the latch state of the latch circuit. Thereby, the port sampling system 1 of this embodiment can transmit the input signal to the microcomputer 10 in the normal state as well as during the sleep period described above, and can suppress the number of input ports occupied even when a large number of input signals are input to the microcomputer 10.

[0035] When the release circuit 212 of the latch circuit 21 of the port sampling system 1 of this embodiment receives a release signal 41 from the microcomputer 10 that has received the input signal, the release circuit 212 releases the latch state of the latch circuit 21. Thereby, it is possible to repeatedly and continuously perform processing such as once latching the wake-up target signal and inputting it to the microcomputer 10.

[0036] The embodiments of the present invention have been described above, but these are merely examples and the present invention is not limited thereto. Various modifications based on the knowledge of those skilled in the art are possible without departing from the spirit of the claims.

Explanation of Reference Numerals

[0037] 1 Port sampling system 10 Microcomputer 11 Control unit 12 Interrupt circuit 13 Serial communication circuit 14 Output circuit 15 Port 20 Latch circuit device 21 Latch circuit 23 Port sampling circuit 24 CR oscillation circuit 25 Serial communication circuit 30 Serial communication line 31 - 35 Communication lines 41 Clear signal 42 Serial signal 211 Clear terminal 212 Release circuit D1 - D9 Input signals 22 Multi - input IC L1 - L9 Signal lines P11 - P19 Ports P21 - P29 Ports P31 - P34 Ports

Claims

1. A latch circuit for latching an input signal to a microcomputer; A detection circuit for detecting that the input signal has been input to the latch circuit during a sleep period in which the microcomputer is in a sleep state; A wake-up circuit for transmitting a wake-up signal to the microcomputer when the input of the input signal is detected during the sleep period; A sampling circuit for reading the input signal from the latch circuit; A transmission circuit for transmitting the input signal read by the sampling circuit to the microcomputer that has returned from the sleep state based on the wake-up signal; A release circuit for releasing the latch state of the latch circuit after the input signal is read; A latch circuit device comprising the above.

2. The latch circuit device according to claim 1, wherein the transmission circuit converts a plurality of input signals read from the latch circuit into a serial signal and transmits the serial signal to the microcomputer via a serial communication line.

3. When the microcomputer is in a normal state where it is not in the sleep state, the sampling circuit receives a read request signal periodically from the microcomputer, reads the input signal from the latch circuit upon the read request signal, the transmission circuit transmits the input signal read by the sampling circuit to the microcomputer, and after the input signal is received by the microcomputer, the release circuit releases the latch state of the latch circuit. The latch circuit device according to claim 1 or 2.

4. The latch circuit device according to any one of claims 1 to 3, wherein the release circuit releases the latch state of the latch circuit when it receives a release signal from the microcomputer that has received the input signal. The latch circuit device according to any one of claims 1 to 3.

5. A port sampling system comprising a microcomputer and a latch circuit device that latches an input signal to the microcomputer and then transmits the input signal to the microcomputer, wherein the microcomputer comprises a control unit for shifting the microcomputer to a normal state or a sleep state, a receiving circuit for receiving the input signal from the latch circuit device, and the latch circuit device comprises a latch circuit for latching an input signal to the microcomputer A detection circuit that detects that the input signal has been input to the latch circuit during a sleep period in which the microcomputer is in a sleep state; A wake-up circuit that transmits a wake-up signal to the microcomputer when the input of the input signal is detected during the sleep period; A sampling circuit that reads the input signal from the latch circuit; A transmission circuit that transmits the input signal read by the sampling circuit to the microcomputer that has returned from the sleep state based on the wake-up signal; A release circuit that releases the latch state of the latch circuit after the input signal is read, and A port sampling system.

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