Phase Change Memory Using Multiple Stacks of PCM Materials

Abstract

A method for improving the linearity of a phase-change memory (PCM) cell structure is presented. The method includes forming a bottom electrode on a substrate, building a PCM stack on the bottom electrode including multiple PCM layers each having a different crystallization temperature, and forming a top electrode on the PCM stack. The crystallization temperatures vary in ascending order from the bottom electrode to the top electrode.

Description

Technical Field

[0001] The present invention generally relates to semiconductor devices, and more particularly to phase change memory (PCM) cells using multiple stacks of Ge-Sb-Te (germanium-antimony-tellurium or "GST") materials with different crystallization temperatures or resistivities or both to improve the linearity of the devices.

Background Art

[0002] Phase change memory (PCM) is one of the next-generation non-volatile memory devices expected to meet the increasing demand for high-performance and low-power semiconductor memory devices. In a PCM device, data can be stored or erased by heating or cooling the phase change layer therein. PCM devices can also be used for analog computing applications because multiple states can exist within a cell. Weights can be stored in PCM cells during the training or inference of neural networks. However, the linearity of the states of PCM is one of the problems in the deployment of PCM for artificial intelligence (AI) applications.

Summary of the Invention

[0003] According to one embodiment, a method for improving the linearity of a phase change memory (PCM) cell structure is provided. The method includes forming a bottom electrode on a substrate, constructing a PCM stack including a plurality of PCM layers with different crystallization temperatures on the bottom electrode, and forming a top electrode on the PCM stack. The crystallization temperature varies in ascending order from the bottom electrode to the top electrode.

[0004] According to another embodiment, a method for improving the linearity of a phase change memory (PCM) cell structure is provided. The method includes forming a bottom electrode on a substrate, constructing a PCM stack including a plurality of PCM layers having different crystallization temperatures on the bottom electrode, and forming a top electrode on the PCM stack. The crystallization temperature of the central region of the PCM stack is at a low point, and the crystallization temperatures in the top and bottom regions of the PCM stack are at high points.

[0005] According to yet another embodiment, a semiconductor device for improving the linearity of a phase change memory (PCM) cell structure is provided. The semiconductor device includes a bottom electrode disposed on a substrate, a PCM stack including a plurality of PCM layers having different crystallization temperatures disposed on the bottom electrode, and a top electrode disposed on the PCM stack. The crystallization temperature varies in descending order within a part or the whole of the PCM stack.

[0006] According to yet another embodiment, a semiconductor structure including a bottom electrode disposed on a substrate, a PCM stack including a plurality of PCM layers having different crystallization temperatures disposed on the bottom electrode, and a top electrode disposed on the PCM stack, wherein the crystallization temperature of the central region of the PCM stack is at a low point, and the crystallization temperatures in the top and bottom regions of the PCM stack are at high points, is provided.

[0007] Note that exemplary embodiments are described with reference to various subjects. In particular, some embodiments are described with reference to method-type claims, and other embodiments are described with reference to apparatus-type claims. However, those skilled in the art will presume that, from the above and following descriptions, unless otherwise notified, in addition to any combination of features belonging to one type of subject, any combination between features related to different subjects, particularly between the features of method-type claims and the features of apparatus-type claims, will also be regarded as described in this document.

[0008] These and other features and advantages will become apparent from the following detailed description of the exemplary embodiments, which should be read in conjunction with the accompanying drawings.

[0009] The present invention provides details of preferred embodiments with reference to the following drawings in the following description.

Brief Description of the Drawings

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[0011] Throughout the drawings, the same or similar reference numerals represent the same or similar elements.

[0012] Embodiments according to the present invention provide methods and devices for constructing a phase change memory structure or a phase change memory (PCM) cell having multiple stacks of Ge-Sb-Te (germanium-antimony-tellurium or "GST") materials with different crystallization temperatures or resistivity or both to improve the linearity of the device. Mushroom GST structures and confinement cell GST structures are introduced where the crystallization temperature varies in ascending order, or descending order, or a combination of ascending / descending order.

[0013] Embodiments according to the present invention provide methods and devices for using multiple layers of phase change materials with different crystallization temperatures to form a single PCM device for better linearity. A diffusion barrier or passivation layer is not used between the phase change material layers.

[0014] Embodiments in accordance with the present invention provide a method and device for using a phase change based material in a PCM cell. Phase change materials, such as chalcogenides, can be phase changed between an amorphous state and a crystalline state by the application of a current at a level suitable for implementation in an integrated circuit. Generally, the amorphous state is characterized by a higher resistivity than the crystalline state, which can be easily sensed to indicate data.

[0015] The phase change material can be switched between a first structural state where the material is generally an amorphous solid phase and a second structural state where the material is generally a crystalline solid phase in the active region of the cell. The term "amorphous" is used to refer to a structure that is less regular and has a relatively low degree of order compared to a single crystal and has detectable properties such as a higher electrical resistivity than the crystalline phase. The term "crystalline" is used to refer to a structure that is more regular and has a relatively high degree of order compared to an amorphous structure and has detectable properties such as a lower electrical resistivity than the amorphous phase. Other material properties affected by the change between the amorphous and crystalline phases include atomic arrangement, free electron density, and activation energy. The material can be switched to different solid phases or a mixture of two or more solid phases, providing a gray scale between a fully amorphous state and a fully crystalline state.

[0016] The change from the amorphous state to the crystalline state is generally a lower current operation and requires a current sufficient to raise the phase change material to a level between the phase transition temperature and the melting temperature. The change from crystalline to amorphous, referred to as "reset", is generally a higher current operation and includes a short high current density pulse to melt or break the crystalline structure, after which the phase change material rapidly cools to quench the phase change process, whereby at least a portion of the phase change structure can be stabilized in the amorphous state.

[0017] The present invention is described from the perspective of a given exemplary architecture, but it should be understood that other architectures, structures, substrate materials, and process features as well as steps / blocks may vary within the scope of the present invention. It should be noted that a feature may not be shown in all figures for clarity. This is not intended to be construed as a limitation of any particular embodiment, illustration, or claim.

[0018] FIG. 1 is a cross-sectional view of a semiconductor structure including a bottom electrode formed on a substrate according to an embodiment of the present invention.

[0019] The semiconductor structure 5 includes a bottom electrode 12 formed on the substrate 10. The bottom electrode 12 may be formed within the substrate 10.

[0020] The substrate 10 can be crystalline, semi-crystalline, microcrystalline, or amorphous. The substrate 10 can be essentially (e.g., excluding contaminants) a single element (e.g., silicon), mainly (e.g., with doping) a single element, such as silicon (Si) or germanium (Ge), or the substrate 10 can include a compound, such as GaAs, SiC, or SiGe. The substrate 10 can also have multiple material layers. In some embodiments, the substrate 10 includes, but is not necessarily limited to, semiconductor materials such as silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), Si:C (carbon-doped silicon), silicon germanium carbide (SiGeC), carbon-doped silicon germanium (SiGe:C), group III-V (e.g., GaAs, AlGaAs, InAs, InP, etc.), group II-V compound semiconductors (e.g., ZnSe, ZnTe, ZnCdSe, etc.) or other similar semiconductors. In addition, multiple layers of semiconductor materials can be used as the semiconductor material of the substrate 10. In some embodiments, the substrate 10 includes both a semiconductor material and a dielectric material. The semiconductor substrate 10 can also include an organic semiconductor or a layered semiconductor such as Si / SiGe, silicon-on-insulator, SiGe-on-insulator, etc. A part or the whole of the semiconductor substrate 10 can be amorphous, polycrystalline, or single-crystalline. In addition to the aforementioned types of semiconductor substrates, the semiconductor substrate 10 used in the present invention can also include a hybrid oriented (HOT) substrate, a HOT semiconductor substrate having surface regions of different crystal orientations.

[0021] The bottom electrode 12 can be formed from, for example, Ta, Ti / TiN, W, WN, TaN, polysilicon, doped polysilicon, amorphous silicon, doped amorphous silicon, or any other suitable material, or any other conductive material. Alternatively, the bottom electrode 12 can be, for example, any suitable single or plural conductive materials, such as Ag, Al, Cu, Ta, TaN, Ti, TiN, Al, W or any other suitable material, and can be deposited or formed in any suitable manner.

[0022] Figure 2 is a cross-sectional view of the semiconductor structure of FIG. 1 in which a heater element according to an embodiment of the present invention is deposited and patterned.

[0023] In various embodiments, the heater element 14 is deposited and patterned.

[0024] The heater element 14 is located laterally to the dielectric layer 16. The heater element 14 includes a thin layer of refractory material having a relatively high resistivity between about 100 ohm-centimeters (Ωcm) to about 10,000 Ωcm, for example between about 500 Ωcm to about 3,000 Ωcm, and a thickness between about 5 nanometers (nm) to about 100 nm. Suitable refractory materials include, but are not limited to, tantalum nitride (TaN) and the metal of the chemical formula Ta x Si y N z where x, y, and z are each between 0 to about 1.

[0025] The heater element 14 may include a conductive material that is chemically inert upon contact with the materials used for the PCM stack and the top electrode. Examples of such conductive but chemically inert materials include carbon, TiN, and TaN. Both titanium nitride and tantalum nitride have a low diffusion rate of metal elements. As a result, forming the heater element 14 from these materials prevents the metal elements contained in the top electrode from diffusing into the PCM stack.

[0026] The dielectric material of layer 16 may include, but is not limited to, ultra-low-k (ULK) materials such as porous silicate, carbon-doped oxide, silicon dioxide, silicon nitride, silicon oxynitride, carbon-doped silicon oxide (SiCOH) and its porous variants, silsesquioxane, siloxane, or other dielectric materials having a dielectric constant in the range of, for example, about 2 to about 4. The dielectric layer 16 may be the same thickness as the heater element 14.

[0027] Figure 3 is a cross-sectional view of the semiconductor structure of FIG. 2 in which a resist liner according to an embodiment of the present invention is deposited.

[0028] In various exemplary embodiments, a resist liner 18 is deposited. The resist liner 18 can be a metal nitride layer such as titanium nitride (TiN), for example. The resist liner 18 is used for resist drift correction.

[0029] In another embodiment, the resist liner 18 can be TaN with different resistance values by different types of deposition such as PVD, CVD, ALD, etc. This material is not limited to other metal types such as TiN, W, or amorphous carbon (a-C), and Al 2 O 3 、HfO 2 、SiN、ZrO 2 and other dielectrics.

[0030] FIG. 4 is a cross-sectional view of the semiconductor structure of FIG. 3 in which a Ge-Sb-Te (germanium-antimony-tellurium or "GST") stack according to an embodiment of the present invention is formed.

[0031] In various exemplary embodiments, a phase change material stack 20 is deposited. The phase change material stack 20 can be a GST stack. The GST stack 20 can include a first layer 22, a second layer 24, a third layer 26, and a fourth layer 28.

[0032] In one example, the first layer 22 can be GST with a low germanium (Ge) concentration (Ge content less than 20%). The second layer 24 can be GST with a medium to low Ge concentration (Ge content between 20% and 40%). The third layer 26 can be GST with a medium Ge concentration (Ge content between 40% and 70%). The fourth layer 28 can be GST with a high Ge concentration (Ge content greater than 60%). No diffusion barrier or passivation layer is used between the layers 22, 24, 26, 28. Thus, a plurality of phase change materials with different crystallization temperatures, such as GST, form a single PCM device 30 for better linearity.

[0033] The GST stack 20 can have different Ge / Te concentrations so as to have a melting T gradient, and the region closer to the heater 14 requires different N concentrations such that the melting T and Rs are different, and N can be implanted or co-sputtered.

[0034] FIG. 5 is a cross-sectional view of the semiconductor structure of FIG. 4 with the upper electrode formed according to an embodiment of the present invention.

[0035] In various exemplary embodiments, the ILD 34 is deposited and the upper electrode 32 is formed within the ILD 34. The GST stack 20 can be patterned to form the GST stack 30. Thus, the upper electrode 32 is in direct contact with the patterned GST stack 30.

[0036] The structure 35 shows the GST stack 30 formed between the upper electrode 32 and the bottom electrode 12. Thus, the structure 35 uses a plurality of GST materials with different crystallization temperatures or resistivity or both to improve the linearity of the device. The structure 35 can be referred to as a mushroom structure having a higher crystallization temperature at the upper part of the GST stack 30 and a lower crystallization temperature at the lower part of the GST stack 30. In other words, the crystallization temperature increases with each added layer. Thus, the crystallization temperature increases as it moves from the lower part to the upper part of the structure 35. The crystallization temperature varies in ascending order from the bottom electrode to the upper electrode, or alternatively, the crystallization temperature varies in descending order from the upper electrode to the bottom electrode. The different crystallization temperatures can be achieved by doping or different material contents or both.

[0037] The upper electrode 32 can be formed from, for example, Ta, Ti / TiN, W, WN, TaN, polysilicon, doped polysilicon, amorphous silicon, doped amorphous silicon, or any other suitable material, or any other conductive material. Alternatively, the upper electrode 32 can be, for example, any suitable single or plural conductive materials, such as Ag, Al, Cu, Ta, TaN, Ti, TiN, Al, W or any other suitable material, and can be deposited or formed in any suitable manner.

[0038] ILD34 may include any material known in the art, such as porous silicate, carbon-doped oxide, silicon dioxide, silicon nitride, silicon oxynitride, or other dielectric materials, etc. ILD34 may be formed using any method known in the art, such as chemical vapor deposition, plasma chemical vapor deposition, atomic layer deposition, or physical vapor deposition, etc. ILD34 may have a thickness in the range of about 25 nm to about 200 nm.

[0039] Phase change materials can be changed from one phase state to another by the application of an electrical pulse. Shorter, higher-amplitude pulses tend to change the phase change material to an amorphous state and are called reset pulses. Longer, lower-amplitude pulses tend to change the phase change material to a crystalline state and are called program pulses. The energy of shorter, higher-amplitude pulses is high enough to melt the material in the active volume and short enough to solidify the material in an amorphous state.

[0040] Phase change materials can include chalcogenide-based materials and other materials. Chalcogens include any of the four elements oxygen (O), sulfur (S), selenium (Se), and tellurium (Te), which form part of Group VI of the periodic table. Chalcogenides include compounds of chalcogens with more electropositive elements or groups. Chalcogenide alloys include combinations of chalcogenides with other materials such as transition metals. Chalcogenide alloys typically include one or more elements from the sixth column of the periodic table of elements such as germanium (Ge) and tin (Sn). Chalcogenide alloys often include combinations that include one or more of antimony (Sb), gallium (Ga), indium (In), and silver (Ag). Memory materials based on phase change can include alloys of Ga / Sb, In / Sb, In / Se, Sb / Te, Ge / Te, Ge / Sb / Te, In / Sb / Te, Ga / Se / Te, Sn / Sb / Te, In / Sb / Ge, Ag / In / Sb / Te, Ge / Sn / Sb / Te, Ge / Sb / Se / Te, and Te / Ge / Sb / S. In the family of Ge / Sb / Te alloys, a wide range of alloy compositions may be feasible.

[0041] In some embodiments, chalcogenides and other phase change materials are doped with impurities to modify the conductivity, transition temperature, melting temperature, and other properties of the memory device using doped chalcogenides. Representative impurities used for doping chalcogenides include nitrogen, silicon, oxygen, silicon dioxide, silicon nitride, copper, silver, gold, aluminum, aluminum oxide, tantalum, tantalum oxide, tantalum nitride, titanium, and titanium oxide.

[0042] In this example, the phase change material stack 30 preferably includes a Ge-Sb-Te (germanium-antimony-tellurium or "GST") alloy. Alternatively, other suitable materials for the phase change material stack 30 optionally include Si-Sb-Te alloys, Ga-Sb-Te alloys, As-Sb-Te alloys, Ag-In-Sb-Te alloys, Ge-In-Sb-Te alloys, Ge-Sb alloys, Sb-Te alloys, Si-Sb alloys, and combinations thereof.

[0043] FIG. 6 is a cross-sectional view of a semiconductor structure including a bottom electrode formed on a substrate according to another embodiment of the present invention.

[0044] The semiconductor structure 5' includes a bottom electrode 12 formed on the substrate 10. The bottom electrode 12 can be formed within the substrate 10.

[0045] FIG. 7 is a cross-sectional view of the semiconductor structure of FIG. 6 with a GST stack formed on the bottom electrode according to an embodiment of the present invention.

[0046] In various exemplary embodiments, a phase change material stack 40 is deposited. The phase change material stack 40 can be a GST stack. The GST stack 40 can include a first layer 42, a second layer 44, a third layer 46, a fourth layer 48, a fifth layer 50, a sixth layer 52, and a seventh layer 54.

[0047] In one example, the first layer 42 can be, for example, GST with a high germanium (Ge) concentration (Ge content exceeding 60%). The second layer 44 can be, for example, GST with a medium Ge concentration (Ge content between 40% and 70%). The third layer 46 can be, for example, GST with a medium to low Ge concentration (Ge content between 20% and 40%). The fourth layer 48 can be, for example, GST with a low Ge concentration (Ge content less than 20%). The fifth layer 50 can be, for example, GST with a medium to low Ge concentration (Ge content between 20% and 40%). The sixth layer 52 can be, for example, GST with a medium Ge concentration (Ge content between 40% and 70%). The seventh layer 54 can be, for example, GST with a high germanium (Ge) concentration (Ge content exceeding 60%). No diffusion barrier is used between the layers 42, 44, 46, 48, 50, 52, 54. Thus, a plurality of layers of phase change materials with different crystallization temperatures, such as GST, form a single PCM device 40 for better linearity. In the structure 40, the crystallization temperature of the central or middle or intermediate region is the lowest.

[0048] FIG. 8 is a cross-sectional view of the semiconductor structure of FIG. 7 in which the phase change material stack according to an embodiment of the present invention is patterned.

[0049] In various embodiments, the phase change material stack 40 is patterned to form the GST stack 40'.

[0050] FIG. 9 is a cross-sectional view of the semiconductor structure of FIG. 8 in which a resist liner is deposited on the patterned phase change material stack according to an embodiment of the present invention.

[0051] In various embodiments, a resist liner 60 is deposited on the patterned phase change material stack 40'. The resist liner 60 is used for resist drift correction.

[0052] The resist liner 60 can be a metal nitride layer such as titanium nitride (TiN), for example.

[0053] In another embodiment, the resist liner 60 can be TaN with different resistance values by different types of deposition such as PVD, CVD, ALD, etc. This material can be other metal types such as TiN, W, or amorphous carbon (a-C), and Al 2 O 3 , HfO 2 , SiN, ZrO 2 etc., and is not limited to dielectrics.

[0054] FIG. 10 is a cross-sectional view of the semiconductor structure of FIG. 9 in which an interlayer dielectric (ILD) has been deposited and planarized according to an embodiment of the present invention.

[0055] In various exemplary embodiments, the ILD 62 is deposited such that the upper surface of the seventh layer 54 is exposed and planarized, for example, by chemical mechanical polishing (CMP).

[0056] FIG. 11 is a cross-sectional view of the semiconductor structure of FIG. 10 in which an upper electrode is formed on the patterned phase change material stack according to an embodiment of the present invention.

[0057] In various exemplary embodiments, an upper electrode 64 is formed on the patterned phase change material stack 40'. The upper electrode 64 can be formed within the dielectric layer 66. In one example, the dielectric layer 66 can be an ILD layer. The structure 70 shows the GST stack 40' formed between the upper electrode 64 and the bottom electrode 12. The upper and bottom electrodes 64, 12 are in direct contact with the GST stack 40'. The upper electrode 64 is also in direct contact with the resist liner 60.

[0058] The structure 70 uses a plurality of GST materials with different crystallization temperatures or resistivity or both to improve the linearity of the device. The structure 70 can be referred to as a confinement cell GST structure that has a higher crystallization temperature at the top of the GST stack 30 and a lower crystallization temperature in the middle or center of the GST stack 30. In other words, the crystallization temperature decreases to a point where there is a crystallization temperature for each layer added and then increases. Thus, as moving from the lower part to the middle of the structure 70, the crystallization temperature decreases to the midpoint. At the midpoint, as moving from the middle to the upper part of the structure 70, the crystallization temperature increases to the top level. The crystallization temperature varies in descending order from the bottom electrode to the middle electrode and in ascending order from the middle electrode to the upper electrode. Different crystallization temperatures can be achieved by doping or different material contents or both.

[0059] In summary, the structure of the exemplary embodiment of the present invention can be a mushroom GST structure having a plurality of GST stacks with different crystallization temperatures, where the crystallization temperatures are arranged from high to low from the top to the bottom, and different crystallization temperatures can be achieved by doping or different material contents or both. The method of the exemplary embodiment of the present invention includes a confinement cell GST structure having a plurality of GST stacks with different crystallization temperatures, where the crystallization temperatures are arranged from high to low from the top and bottom to the center, and different crystallization temperatures can be achieved by doping or different material contents or both. As a result, the exemplary embodiments of the present invention create a plurality of stacks or continuous stacks of PCM films with various G pair set-pulse characteristics through chemical doping of the same material or a gradual change in material composition or both. G varies from low to high from the top to the bottom. By manipulating the gradient or thickness or both of the layer composition, an improvement in the linearity of G with respect to the set-pulse number can be achieved. In addition, the same pulse is used throughout the stack.

[0060] Furthermore, exemplary embodiments of the present invention use PCM that can be used in neuromorphic computing applications, as described below with reference to FIGS. 12 and 13. For the purpose of neuromorphic computing, the linearity of conductance is beneficial for weight updates. Thus, the improved linearity of the mushroom and confinement cell devices described herein can be beneficial for neuromorphic computing applications.

[0061] FIG. 12 is a block / flow diagram of an exemplary neuromorphic and synaptomorphic network including a crossbar of electronic synapses interconnecting electronic neurons and axons according to an embodiment of the present invention.

[0062] Tile circuit example 100 has a crossbar 112 according to an embodiment of the present invention. In one example, the entire circuit can include an "ultra-high density crossbar array" whose pitch can range from about 0.1 nm to 10 μm. Neuromorphic and synaptomorphic circuit 100 includes a crossbar 112 that interconnects a plurality of digital neurons 111 including neurons 114, 116, 118, and 120. These neurons 111 are also referred to herein as "electronic neurons". For illustrative purposes, circuit example 100 provides symmetric connections between two neuron pairs (e.g., N1 and N3). However, embodiments of the present invention are useful not only with such symmetric neuron connections, but also with asymmetric neuron connections (neurons N1 and N3 do not have to be connected at the same connection). The crossbar in the tile provides an appropriate ratio of synapses to neurons and thus does not have to be square.

[0063] In circuit example 100, neuron 111 is connected to crossbar 112 via dendrite paths / wires (dendrites) 113 such as dendrites 126 and 128. Neuron 111 is also connected to crossbar 112 via axon paths / wires (axons) 115 such as axons 134 and 136. Neurons 114 and 116 are dendrite neurons, and neurons 118 and 120 are axon neurons connected to axon 115. In particular, for neurons 114 and 116, outputs 122 and 124 are connected to dendrites (e.g., bit lines) 126 and 128, respectively. For axon neurons 118 and 120, outputs 130 and 132 are connected to axons (e.g., word lines or access lines) 134 and 136, respectively.

[0064] When any of neurons 114, 116, 118, and 120 fires, it sends a pulse to their axon connections and dendrite connections. Each synapse provides a contact between the axon of one neuron and the dendrite of another neuron, and with respect to the synapse, the two neurons are referred to as presynaptic and postsynaptic, respectively.

[0065] Each connection between the dendritic protrusions 126, 128 and the axons 134, 136 is made through a digital synaptic device 131 (synapse). The junction where the synaptic device is located may be referred to herein as a "cross-point junction". Generally, according to one embodiment of the present invention, neurons 114 and 116 "fire" (transmit a pulse) in response to an input received from an axonal input connection (not shown) exceeding a threshold. Neurons 118 and 120 usually "fire" (transmit a pulse) in response to an input received from an external input connection (not shown) from other neurons exceeding a threshold. In one embodiment, when neurons 114 and 116 fire, they maintain a decaying post-synaptic STDP (post-STDP) variable. For example, in one embodiment, the decay period can be 50 ms. The post-STDP variable is used to achieve STDP by encoding the time since the last firing of the associated neuron. Such STDP is used to control long-term potentiation or "potentiation", defined as an increase in synaptic conductivity in this context. When neurons 118, 120 fire, they maintain a pre-STDP (pre-synaptic STDP) variable that decays in a manner similar to that of neurons 114 and 116.

[0066] The pre-STDP and post-STDP variables can decay according to, for example, an exponential function, a linear function, a polynomial function, or a quadratic function. In another embodiment of the present invention, the variable can increase instead of decreasing over time. In either case, this variable can be used to achieve STDP by encoding the time since the last firing of the associated neuron. STDP is used to control long-term depression or "depression", defined as a decrease in synaptic conductivity in this context. Note that the roles of the pre-STDP and post-STDP variables can be reversed such that the pre-STDP implements potentiation and the post-STDP implements depression.

[0067] An external bidirectional communication environment can supply sensory input and consume motor output. A digital neuron 111 implemented using complementary metal oxide semiconductor (CMOS) logic gates receives spike inputs and integrates them. In one embodiment, the neuron 111 includes a comparator circuit that generates a spike when the integrated input exceeds a threshold. In one embodiment, binary synapses are implemented using replaceable 1-bit static random-access memory (SRAM) cells, and each neuron 111 can be an excitatory neuron or an inhibitory neuron (or both). Each learning rule for each neuron axon and dendrite is reconfigurable as described below. This assumes replaceable access to a crossbar memory array. Spiking neurons are selected one at a time and send spike events to corresponding axons that can be on-core or elsewhere in a larger system with multiple cores.

[0068] As used herein, the term electronic neuron refers to an architecture configured to simulate a biological neuron. An electronic neuron creates connections between processing elements that are substantially functionally equivalent to the neurons of a biological brain. Thus, neuromorphic and synaptic systems that include an electronic neuron according to an embodiment of the present invention may include various electronic circuits modeled after biological neurons. Further, neuromorphic and synaptic systems that include an electronic neuron according to an embodiment of the present invention may include various processing elements (including computer simulations) modeled after biological neurons. One exemplary embodiment of the present invention is described herein using an electronic neuron that includes an electronic circuit, but the present invention is not limited to electronic circuits. Neuromorphic and synaptic systems according to embodiments of the present invention may be implemented as neuromorphic and synaptic architectures that include circuitry, as well as computer simulations. In fact, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments that include both hardware and software elements.

[0069] FIG. 13 is a block diagram of the components of a computing system that includes a computing device and a neuromorphic chip according to one embodiment of the present invention.

[0070] FIG. 13 is a block diagram of the components of system 200 that includes computing device 205. It should be understood that FIG. 13 provides only an illustration of one implementation and does not imply any limitations regarding the environments in which various embodiments may be implemented. Many modifications may be made to the illustrated environment.

[0071] Computing device 205 includes a communication fabric 202 that provides communication between computer processor(s) 204, memory 206, persistent storage 208, communication unit 210, and input / output (I / O) interface(s) 212. The communication fabric 202 can be implemented by any architecture designed to pass data or control information or both between processors (such as microprocessors, communication and network processors), system memory, peripheral devices, and any other hardware components within the system. For example, the communication fabric 202 can be implemented by one or more buses.

[0072] Memory 206, cache memory 216, and persistent storage 208 are computer-readable storage media. In this embodiment, memory 206 includes random access memory (RAM) 214. This memory 214 can also be a phase change memory of an exemplary embodiment of the present invention. In general, memory 206 can include any suitable volatile or non-volatile computer-readable storage media.

[0073] In some embodiments of the present invention, a deep learning program 225 is included as a component of the computing device 205 and is operated by the neuromorphic chip 222. In other embodiments, the deep learning program 225 is stored in the persistent storage 208 for execution via one or more memories of the memory 206 by the neuromorphic chip 222 in conjunction with one or more of the respective computer processors 204. In this embodiment, the persistent storage 208 includes a magnetic hard disk drive. Alternatively, or in addition to the magnetic hard disk drive, the persistent storage 208 can include a solid state hard drive, a semiconductor memory device, a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, or any other computer-readable storage medium capable of storing program instructions or digital information.

[0074] The medium used by the persistent storage 208 may be removable. For example, a removable hard drive may be used for the persistent storage 208. Other examples include optical disks and magnetic disks, thumb drives (R), and smart cards that are inserted into a drive for transfer to another computer-readable storage medium that is also part of the persistent storage 208.

[0075] In some embodiments of the present invention, a neuromorphic chip 222 is included in a computing device 205 and is connected to a communication fabric 202. The neuromorphic chip 222 includes electronic logic for providing a stacked restricted Boltzmann machine and a feedforward neural network, which is trainable and includes deep learning algorithm components for performing machine learning. In other embodiments, the operation of the logistic and algorithm components is performed by a dedicated data structure included within the computing device 205 that performs the deep learning functions of the stacked restricted Boltzmann machine and the feedforward neural network.

[0076] In these examples, the communication unit 210 provides communication with other data processing systems or devices, including resources of a distributed data processing environment. In these examples, the communication unit 210 includes one or more network interface cards. The communication unit 210 can provide communication through the use of either or both physical and wireless communication links. A deep learning program 225 can be downloaded to the persistent storage 208 through the communication unit 210.

[0077] The I / O interface(s) 212 enables the input and output of data by other devices that can be connected to the computing system 200. For example, the I / O interface 212 can provide a connection to an external device 218 such as a keyboard, keypad, touch screen, or some other suitable input device or combination thereof. The external device 218 can also include portable computer-readable storage media such as, for example, a thumb drive(R), a portable optical disk or magnetic disk, and a memory card.

[0078] The display 220 provides a mechanism for displaying data to a user and can be, for example, a computer monitor.

[0079] With respect to FIGS. 1 - 11, deposition is any process of growing, coating, or otherwise transferring material onto a wafer. Available techniques include, but are not limited to, thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently atomic layer deposition (ALD). As used herein, "deposition" can include, for example, chemical vapor deposition (CVD), low - pressure CVD (LPCVD), plasma - enhanced CVD (PECVD), semi - atmosphere CVD (SACVD), high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra - high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metal - organic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser - assisted deposition, thermal oxidation, thermal nitridation, spin - on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation, and can include any known or later - developed technique appropriate for the material being deposited, without limitation thereto.

[0080] The present invention is described from the perspective of a given exemplary architecture, but it should be understood that other architectures, structures, substrate materials, and process features as well as steps / blocks can vary within the scope of the present invention.

[0081] Also, when an element such as a layer, region, or substrate is said to be "on" or "upon" another element, it will be understood that it is either directly on the other element or intervening elements may be present. In contrast, when an element is said to be "directly on" or "directly upon" another element, no intervening elements are present. Also, when an element is said to be "connected" or "coupled" to another element, it will be understood that it is either directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is said to be "directly connected" or "directly coupled" to another element, no intervening elements are present.

[0082] This embodiment may include the design of an integrated circuit chip created in a graphical computer programming language and storable on a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive within a storage access network, etc.). If the designer does not fabricate the chip or the photolithography mask used to fabricate the chip, the designer can transmit the design result directly or indirectly to such an entity physically (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., via the Internet). Next, the stored design is converted to an appropriate format (such as GDSII) for the fabrication of a photolithography mask that includes a plurality of copies of the corresponding chip design to be formed on the wafer. Using the photolithography mask, the areas of the wafer where etching or other processing is to be performed are defined.

[0083] The methods described herein can be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of an unprocessed wafer (i.e., as a single wafer having a plurality of unpackaged chips), as bare dies, or in a packaged form. In the latter case, the chips can be mounted within a single-chip package (such as a plastic carrier with leads attached to a motherboard, or other higher-level carriers) or within a multi-chip package (such as a ceramic carrier having either or both surface interconnects or embedded interconnects). In any case, the chips are then integrated, as (a) an intermediate product such as a motherboard or (b) part of a final product, with other chips, discrete circuit elements, or other signal processing devices or combinations thereof. The final product can be any product that includes integrated circuit chips, ranging from toys and other low-performance applications to display, keyboard or other input devices, and high-end computer products having a central processor.

[0084] It should also be understood that material compounds, such as SiGe, are described with respect to the recited elements. These compounds include, for example, SiGe where Si x Ge 1-x and where x is less than or equal to 1, and include various ratios of the elements in the compound. In addition, other elements are included in the compound and can still function in accordance with embodiments of the present invention. Compounds that include additional elements are referred to herein as alloys. References herein to "one embodiment" or "an embodiment" of the present invention, as well as other variations thereof, mean that the specific features, structures, characteristics, etc. described in connection with that embodiment are included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" and any other variations thereof that occur throughout this specification are not necessarily all referring to the same embodiment.

[0085] For example, in the cases of "A / B", "A or B or both", and "at least one of A and B", the use of any of " / ", "~ or ··· or both", and "at least one of ~" is intended to include the selection of only the first-listed option (A), or only the second-listed option (B), or the selection of both options (A and B). As a further example, in the cases of "A, B or C or combinations thereof" and "at least one of A, B and C", such phrases are intended to include the selection of only the first-listed option (A), or only the second-listed option (B), or only the third-listed option (C), or the selection of only the first and second-listed options (A and B), or the selection of only the first and third-listed options (A and C), or the selection of only the second and third-listed options (B and C), or the selection of all three options (A and B and C). This can be extended to any number of items listed, as will be readily apparent to those of ordinary skill in the art of this and related arts.

[0086] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. The terms "comprises", "comprising", "includes", or "including" or combinations thereof as used in the specification specify the presence of the stated feature, integer, step, operation, element, or component or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components or groups thereof or combinations thereof.

[0087] Terms such as "directly below", "below", "lower", "above", "upper" etc. may be used in this specification to facilitate description of the relationship of one element or feature shown in the figures to another element(s) or feature(s). The terms expressing spatial relationships are intended to encompass different orientations of the device during use or operation in addition to the orientation shown in the figures. For example, if the device in the figure is inverted, the element described as "below" or "directly below" another element or feature will be in the "above" orientation of the other element or feature. Thus, the exemplary term "below" may encompass both upward and downward orientations. The device can be oriented in another direction (rotated 90 degrees or in another orientation), and the descriptive terms expressing spatial relationships used in this specification can be interpreted accordingly. In addition, when a layer is said to be between two layers, it will be understood that it can be the only layer between the two layers or one or more intervening layers can also exist.

[0088] Although terms such as first, second, etc. may be used in this specification to describe various elements, it will be understood that these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, the first element discussed below could also be termed the second element without departing from the scope of the concept of the present invention.

[0089] A preferred embodiment of a PCM cell using a plurality of stacks of GST materials with different crystallization temperatures or resistivity or both to improve the linearity of the device is described (these are for illustrative purposes and not limiting), and it should be noted that modifications and variations can be made by those skilled in the art in light of the above teachings. Thus, it must be understood that within the scope of the present invention as set forth in the appended claims, changes can be made in the specific embodiments described. Although the aspects of the present invention are described with the detail and particularity required by patent law, the content claimed and desired to be protected by the patent certificate is set forth in the appended claims.

Claims

1. A method for improving the linearity of a phase change memory (PCM) cell structure, comprising: forming a bottom electrode on a substrate; forming a heating element in contact with an upper surface of the bottom electrode; forming a flat resistive liner such that only the upper surface of the heating element is in contact therewith; constructing a PCM stack including a plurality of PCM layers having different crystallization temperatures on the flat surface of the resistive liner; forming an upper electrode on the PCM stack; wherein one of the crystallization temperatures varies in ascending order from the bottom electrode to the upper electrode, and the crystallization temperature in the central region of the PCM stack is at a lower point, and the crystallization temperatures in the uppermost and lowermost regions of the PCM stack are at higher points; a method.

2. The method according to claim 1, wherein each of the plurality of PCM layers comprises a Ge-Sb-Te (germanium-antimony-tellurium or "GST") alloy.

3. The method according to claim 1, wherein the crystallization temperature varies in ascending order from the bottom electrode to the upper electrode, and the plurality of PCM layers comprises four layers.

4. The method according to claim 3, wherein the first layer comprises a germanium (Ge) content of less than 20%, the second layer comprises a Ge content between 20% and 40%, the third layer comprises a Ge content between 40% and 70%, and the fourth layer comprises a Ge content of more than 60%.

5. The method according to claim 1, wherein the heating element is smaller than the bottom electrode.

6. The method according to claim 5, wherein the resistive liner is used for resistive drift correction.

7. The method according to claim 1, wherein the different crystallization temperatures are achieved by doping or different material contents or both.

8. The method according to claim 1, wherein the crystallization temperature in the central region of the PCM stack is at a lower point, the crystallization temperatures in the uppermost and lowermost regions of the PCM stack are at higher points, and the plurality of PCM layers comprises seven layers.

9. The method according to claim 8, wherein the first layer comprises a germanium (Ge) content of more than 60%, the second layer comprises a Ge content between 40% and 70%, the third layer comprises a Ge content between 20% and 40%, the fourth layer comprises a Ge content of less than 20%, the fifth layer comprises a Ge content between 20% and 40%, the sixth layer comprises a Ge content between 40% and 70%, and the seventh layer comprises a Ge content of more than 60%.

10. The crystallization temperature in the central region of the PCM stack is at a low point, the crystallization temperatures in the uppermost and lowermost regions of the PCM stack are at high points, and a resistance liner is disposed adjacent to the sidewall of the PCM stack. The method according to claim 1.

11. The crystallization temperature in the central region of the PCM stack is at a low point, the crystallization temperatures in the uppermost and lowermost regions of the PCM stack are at high points, and the crystallization temperature varies in ascending order in a portion of the PCM stack. The method according to claim 1.

12. The crystallization temperature in the central region of the PCM stack is at a low point, the crystallization temperatures in the uppermost and lowermost regions of the PCM stack are at high points, and the crystallization temperature varies in descending order in a portion of the PCM stack. The method according to claim 1.

13. A bottom electrode disposed on a substrate, A heating element disposed in contact with an upper surface of the bottom electrode, A flat resistance liner having a flat surface disposed in contact with only the upper surface of the heating element, A PCM stack including a plurality of PCM layers having different crystallization temperatures disposed on the flat surface of the resistance liner, An upper electrode disposed on the PCM stack and wherein the crystallization temperature varies in descending order in a part or the whole of the PCM stack, the crystallization temperature varies in ascending order from the bottom electrode to the upper electrode, and the crystallization temperature in the central region of the PCM stack is at a low point, and the crystallization temperatures in the uppermost and lowermost regions of the PCM stack are at high points, and is one of them. A semiconductor structure.

14. Each of the plurality of PCM layers includes a Ge-Sb-Te (germanium-antimony-tellurium or "GST") alloy. The semiconductor structure according to claim 13.

15. The different crystallization temperatures are achieved by doping or different material contents or both. The semiconductor structure according to claim 14.

16. The crystallization temperature varies in descending order in a part or the whole of the PCM stack. The first layer of the PCM stack includes a germanium (Ge) content of less than 20%, the second layer of the PCM stack includes a Ge content between 20% and 40%, the third layer of the PCM stack includes a Ge content between 40% and 70%, and the fourth layer of the PCM stack includes a Ge content exceeding 60%. The semiconductor structure according to claim 13.

17. The crystallization temperature varies in descending order within a part or the whole of the PCM stack, and the descending order is from the upper electrode to the bottom electrode. The semiconductor structure according to claim 13.

18. The crystallization temperature in the central region of the PCM stack is at a low point, and the crystallization temperature in the uppermost and lowermost regions of the PCM stack is at a high point. The plurality of PCM layers includes seven layers. The first layer includes a germanium (Ge) content exceeding 60%, the second layer includes a Ge content between 40% and 70%, the third layer includes a Ge content between 20% and 40%, the fourth layer includes a Ge content of less than 20%, the fifth layer includes a Ge content between 20% and 40%, the sixth layer includes a Ge content between 40% and 70%, and the seventh layer includes a Ge content exceeding 60%. The semiconductor structure according to claim 13.

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