Transmission and reception circuit

Abstract

To provide a transceiver circuit having a simple circuit configuration.SOLUTION: A transceiver circuit disclosed herein includes: a first circuit capable of transmitting and receiving signals; a second circuit capable of transmitting and receiving signals; and an insulation element that electrically insulates the first circuit and the second circuit, and is capable of transmitting a signal received from one of the first and second circuits to the other. The first circuit has a first terminal to which a first clock signal is input, increases a frequency of the first clock signal to generate a second clock signal, and transmits the second clock signal. The insulation element transmits the second clock signal obtained from the first circuit to the second circuit as a third clock signal. The second circuit receives the third clock signal from the insulation element and transmits a first data signal in response to the received third clock signal. The insulation element transmits the first data signal obtained from the second circuit as a second data signal, and the first circuit receives the second data signal from the insulation element.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a transceiver circuit.

Background Art

[0002] There is known a transceiver circuit capable of bidirectionally transmitting signals between two circuits connected via an insulating element such as a transformer or a current transformer. Usually, in such a transceiver circuit, two insulating elements are used: an insulating element for transmission from one circuit to the other circuit and an insulating element for transmission from the other circuit to one circuit.

[0003] Patent Document 1 describes a transceiver circuit capable of bidirectional transmission by a single insulating element. However, in Patent Document 1, instead of realizing bidirectional transmission by a single insulating element, an additional circuit such as a reception timing circuit is required. As a result, the overall transceiver circuit does not necessarily have a simple circuit configuration.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The present disclosure is for solving the above problems and aims to provide a transceiver circuit with a simple circuit configuration.

Means for Solving the Problems

[0006] To solve the above problems, the transmission and reception circuit according to the present disclosure includes a first circuit capable of transmitting and receiving signals, a second circuit capable of transmitting and receiving signals, and an insulating element that electrically insulates the first circuit and the second circuit and is capable of transmitting a signal transmitted from one of the first circuit and the second circuit to the other. The first circuit includes a first terminal to which a first clock signal is input, generates a second clock signal by high-frequencyizing the first clock signal, and transmits the second clock signal to the second circuit via the insulating element. The second circuit receives a third clock signal in which the second clock signal is delayed via the insulating element, and transmits a first data signal to the first circuit via the insulating element in response to the third clock signal. The first circuit receives a second data signal in which the first data signal is delayed via the insulating element.

Brief Description of the Drawings

[0007]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Modes for Carrying Out the Invention

[0008] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The same or corresponding elements in the drawings are denoted by the same reference numerals, and detailed descriptions thereof are omitted as appropriate.

[0009] (Embodiment 1) FIG. 1 is a diagram showing the configuration of a transmission / reception circuit 100 according to Embodiment 1 of the present disclosure. The transmission / reception circuit 100 includes a first circuit 10 capable of transmitting and receiving signals, a second circuit 20 capable of transmitting and receiving signals, an insulating element 30 composed of a single transformer or current transformer, and a signal processing circuit 40. The first circuit 10 is arranged in a first region R1, and the second circuit 20 is arranged in a second region R2. The first circuit 10 and the second circuit 20 are connected via the insulating element 30. Since the first circuit 10 and the second circuit 20 are electrically insulated but magnetically coupled, a signal transmitted from one circuit is transmitted to the other circuit via the insulating element 30.

[0010] The first circuit 10 includes a first transmission circuit 11, a first reception circuit 12, and a first control circuit 13 that controls the operations of these two circuits. The first circuit 10 also includes a first terminal 10a to which a first clock signal CLK1 is periodically input from outside the transmission / reception circuit 100. The first clock signal CLK1 is periodically input to the first transmission circuit 11 via the first terminal 10a. As will be described later, the first clock signal CLK1 is used, for example, to switch the operation mode of the first circuit 10. The outputs 11a and 11b of the first transmission circuit 11 are connected to the primary side 31 of the insulating element 30. The inputs 12a and 12b of the first reception circuit 12 are also connected to the primary side 31 of the insulating element 30.

[0011] When the first clock signal CLK1 is input to the first terminal 10a of the first circuit 10, the first circuit 10 generates and transmits a second clock signal by converting the first clock signal CLK1 to a higher frequency. The insulating element 30 transmits the second clock signal CLK2 from the first circuit 10 as a third clock signal CLK3 with a slight time delay. The second circuit 20 receives the third clock signal CLK3 from the insulating element 30.

[0012] The first circuit 10 has two operating modes: a first transmission mode and a first reception mode. In the first transmission mode, the first transmission circuit 11 enters an operating state in which operating power is supplied to the circuit portion responsible for transmitting signals included in the first transmission circuit 11, resulting in power consumption, and the first reception circuit 12 enters a stopped state in which operating power is not supplied to the circuit portion responsible for receiving signals included in the first reception circuit 12 and no power consumption occurs. On the other hand, in the first reception mode, the first transmission circuit 11 enters a stopped state in which operating power is not supplied to the circuit portion responsible for transmitting signals included in the first transmission circuit 11 and no power consumption occurs, and the first reception circuit 12 enters an operating state in which operating power is supplied to the circuit portion responsible for receiving signals included in the first reception circuit 12, resulting in power consumption. Note that, in either the operating state or the stopped state, operating power is always supplied to the circuit portion of the first transmission circuit 11 and the first reception circuit 12 that is responsible for receiving control signals from the control circuit 13.

[0013] The second circuit 20 includes a second transmission circuit 21, a second reception circuit 22, and a second control circuit 23 that controls the operation of these two circuits. A data signal DATA is input from the signal processing circuit 40 to the second transmission circuit 21. The third clock signal CLK3 received by the second reception circuit 22 is frequency-reduced to become the fourth clock signal CLK4 and is input to the clock terminal 41 of the signal processing circuit 40. While the first clock signal CLK1 described above is a clock signal input from outside the transceiver circuit 100, the second clock signal CLK2 and the third clock signal CLK3 are clock signals used inside the transceiver circuit 100. The third clock signal CLK3 is used, for example, for outputting the data signal DATA by the second circuit 20. The outputs 21a and 21b of the second transmission circuit 21 are connected to the secondary side 32 of the insulating element 30. The inputs 22a and 22b of the second reception circuit 22 are also connected to the secondary side 32 of the insulating element 30.

[0014] The second circuit 20 has two operating modes, namely a second transmission mode and a second reception mode. In the second transmission mode, the second transmission circuit 21 enters an operating state in which operating power is supplied to the circuit portion responsible for transmitting signals included in the second transmission circuit 21, resulting in power consumption, and the second reception circuit 22 enters a stopped state in which operating power is not supplied to the circuit portion responsible for receiving signals included in the second reception circuit 22 and no power consumption occurs. On the other hand, in the second reception mode, the second transmission circuit 21 enters a stopped state in which operating power is not supplied to the circuit portion responsible for transmitting signals included in the second transmission circuit 21 and no power consumption occurs, and the second reception circuit 22 enters an operating state in which operating power is supplied to the circuit portion responsible for receiving signals included in the second reception circuit 22, resulting in power consumption. Note that, in either the operating state or the stopped state, operating power is always supplied to the circuit portion of the second transmission circuit 21 and the second reception circuit 22 that is responsible for receiving control signals from the control circuit 23.

[0015] Each time a fourth clock signal CLK4 is input to the clock terminal 41 of the signal processing circuit 40, the signal processing circuit 40 outputs a 1-bit data signal DATA having a value of 0 or 1 from the output terminal 42. Specifically, the signal processing circuit 40 includes an analog / digital (A / D) converter 43 and a parallel / serial (P / S) converter 44. The A / D converter 43 converts an analog signal input from the outside into a multi-bit digital signal and outputs it. The P / S converter 44 converts the multi-bit digital signal output from the A / D converter 43, that is, the parallel bit signal, into a serial bit signal and outputs it. The serial bit signal output from the P / S converter 44 is output one bit at a time as the data signal DATA from the output terminal 42 each time the fourth clock signal CLK4 is input to the clock terminal 41.

[0016] The type of the analog signal input to the signal processing circuit 40 is not particularly limited. As an example, it may be a sensor signal output from a current sensor or a voltage sensor. In this case, the transmission and reception circuit 100 functions as a voltage measurement circuit or a current measurement circuit that transmits the voltage value or current value of the measurement target from the first circuit 10 to the second circuit 20 via the insulating element 30. Also, the specific configuration of the A / D converter 43 is not particularly limited. As an example, the A / D converter 43 can be configured by a ΔΣ modulator.

[0017] The data signal DATA output from the output terminal 42 of the signal processing circuit 40 is made into a high frequency by the second circuit 20 and transmitted as the first data signal DATA1. The insulating element 30 transmits the first data signal DATA1 from the second circuit 20 as the second data signal CLK2 with a slight time delay. The first circuit 10 receives the second data signal DATA2 from the insulating element 30. The first circuit 10 demodulates the received second data signal DATA2 to restore the original data signal DATA.

[0018] Next, an outline of the operation of the transmission and reception circuit 100 according to the first embodiment will be described with reference to the timing chart of FIG. 2. In the initial state of FIG. 2, that is, at the left end of the timing chart, the first circuit 10 is in the first reception mode and the second circuit 20 is in the second reception mode.

[0019] At time t1, when the first clock signal CLK1 is input, the first circuit 10 switches from the first reception mode to the first transmission mode and transmits the second clock signal CLK2 (S1). Thereafter, the first circuit 10 switches from the first transmission mode to the first reception mode at time t5. The insulating element 30 transmits the second clock signal CLK2 from the first circuit 10 as the third clock signal CLK3 with a slight time delay.

[0020] When the second circuit 20 receives the third clock signal CLK3 from the insulating element 30 (S2), it switches from the second reception mode to the second transmission mode and transmits the first data signal DATA1 (S3). Thereafter, the second circuit 20 switches from the second transmission mode to the second reception mode at time t10. The insulating element 30 transmits the first data signal DATA1 from the second circuit 20 as the second data signal DATA2 with a slight time delay.

[0021] The first circuit 10 receives the second data signal DATA2 from the insulating element 30 (S4). Thereafter, when the first clock signal CLK1 is input again at time t11, the first circuit 10 switches again from the first reception mode to the first transmission mode, and thereafter, each time the first clock signal CLK1 is input, the above operation is repeated.

[0022] Regarding the operation of the timing chart in FIG. 2, when the operations of the first transmission circuit 11 and the first reception circuit 12 included in the first circuit 10, and the second transmission circuit 21 and the second reception circuit 22 included in the second circuit 20 are shown in detail, it becomes as shown in FIG. 3. Hereinafter, the details of the operation of the transmission / reception circuit 100 according to the first embodiment will be described with reference to the timing chart of FIG. 3.

[0023] First, in the first embodiment, each of the first to fourth clock signals CLK1 to 4, the data signal DATA, and the first to second data signals DATA1 to 2 is a voltage pulse or a current pulse. Also, the reception determination of the first clock signal CLK1 and the third clock signal CLK3 is performed by detecting the positive edge (rise) of the pulse.

[0024] In the initial state of FIG. 3, that is, at the left end of the timing chart, the first circuit 10 is in the first reception mode. Therefore, the first transmission circuit 11 is in a stopped state, and the first reception circuit 12 is in an operating state. Also, the second circuit 20 is in the second reception mode. Therefore, the second transmission circuit 21 is in a stopped state, and the second reception circuit 22 is in an operating state.

[0025] At time t1, when the first clock signal CLK1 is input, the first circuit 10 switches from the first reception mode to the first transmission mode. Specifically, the first control circuit 13 starts supplying operating power to the circuit portion responsible for signal transmission included in the first transmission circuit 11, thereby putting the first transmission circuit 11 into an operating state, and stops supplying operating power to the circuit portion responsible for signal reception included in the first reception circuit 12, thereby putting the first reception circuit 12 into a stopped state. In this state, the first transmission circuit 11 transmits the second clock signal CLK2 (S1).

[0026] When the transmission of the second clock signal CLK2 is completed at time t3, the first circuit 10 switches from the first transmission mode to the first reception mode. Specifically, the first control circuit 13 stops supplying operating power to the circuit portion responsible for signal transmission included in the first transmission circuit 11, thereby putting the first transmission circuit 11 into a stopped state, and starts supplying operating power to the circuit portion responsible for signal reception included in the first reception circuit 12, thereby putting the first reception circuit 12 into an operating state. However, in order to wait for the residual transmission signal of the first transmission circuit 11 to attenuate and disappear, a certain amount of time is required for the switching. In FIG. 3, the period of "switching" from time t3 to t5 corresponds to this. The switching time is determined in advance as a design value.

[0027] On the other hand, from time t2 to t4, the second receiving circuit 22 of the second circuit 20 receives the third clock signal CLK3 from the insulating element 30 (S2). The received third clock signal CLK3 is frequency-reduced to become a fourth clock signal CLK4 and is input to the clock terminal 41 of the signal processing circuit 40. As a result, a 1-bit data signal DATA having a value of 0 or 1 is output from the output terminal 42 of the signal processing circuit 40, and the data signal DATA is input to the second transmitting circuit 21. Note that the data signal DATA output from the signal processing circuit 40 continues to hold the same value until the fourth clock signal CLK4 is next input. Also, in FIG. 3, the time difference between time t1 and time t2 and the time difference between time t3 and time t4 represent the delay that occurs in the process of transmitting the second clock signal CLK2 through the insulating element 30.

[0028] When the reception of the third clock signal CLK3 is completed at time t4, the second receiving circuit 22 waits for a certain period of time to wait for the residual transmission signal of the first transmitting circuit 11 of the first circuit 10 described above to attenuate and disappear. In FIG. 3, the period from time t4 to t6 corresponds to this waiting time. The waiting time is determined in advance as a design value.

[0029] At time t6, the second circuit 20 switches from the second receiving mode to the second transmitting mode. Specifically, the second control circuit 23 starts supplying operating power to the circuit portion responsible for transmitting signals included in the second transmitting circuit 21, thereby putting the second transmitting circuit 21 into an operating state, and stops supplying operating power to the circuit portion responsible for receiving signals included in the second receiving circuit 22, thereby putting the second receiving circuit 22 into a stopped state. In this state, the second transmitting circuit 21 transmits the first data signal DATA1 (S3). This first data signal DATA1 is obtained by frequency-increasing the data signal DATA output from the output terminal 42 of the signal processing circuit 40 when the fourth clock signal CLK4 was previously input to the clock terminal 41 of the signal processing circuit 40.

[0030] When the transmission of the first data signal DATA1 is completed at time t8, the second circuit 20 switches from the second transmission mode to the second reception mode. Specifically, the second control circuit 23 stops supplying operating power to the circuit portion responsible for transmitting signals included in the second transmission circuit 21, thereby stopping the second transmission circuit 21, and starts supplying operating power to the circuit portion responsible for transmitting signals included in the second transmission circuit 22, thereby putting the second reception circuit 22 into an operating state. Here too, in order to wait for the residual transmission signal of the second transmission circuit 21 to attenuate and disappear, a certain amount of time is required for the switching. In FIG. 3, the period of "switching" from time t8 to t10 corresponds to this. This switching time is also determined in advance as a design value. However, this switching needs to be completed before the next third clock signal CLK3 is received.

[0031] On the other hand, from time t7 to t9, the first reception circuit 12 of the first circuit 10 receives the second data signal DATA2 from the insulating element 30 (S4). The received second data signal DATA2 is frequency-reduced and restored to the data signal DATA, and then output outside the transceiver circuit 100 and used variously according to the purpose. As an example, the analog signal input to the signal processing circuit 40 is a sensor signal output from a voltage sensor or a current sensor, and when the transceiver circuit 100 functions as a voltage measurement circuit or a current measurement circuit, the data signal DATA constitutes part of the digital representation of the voltage value or current value of the measurement target. Even after the reception of the second data signal DATA2 is completed, the first circuit 10 continues the first reception mode in order to wait for the first clock signal CLK1 to be input again.

[0032] At time t11, when the first clock signal CLK1 is input again, the first circuit 10 switches back from the first reception mode to the first transmission mode, and thereafter, every time the first clock signal CLK1 is input, the above operation is repeated. As a result, every time the first clock signal CLK1 is input, the first circuit 10 can repeatedly receive the high-frequency second data signal DATA corresponding to the 1-bit data signal DATA from the second circuit 20 via the insulating element 30.

[0033] As described above, in the transceiver circuit 100 according to the first embodiment, the first circuit 10 includes a first terminal 10a to which the first clock signal CLK1 is input, and the first clock signal CLK1 is frequency-converted to generate and transmit a second clock signal CLK2 (S1). The insulating element 30 transmits the second clock signal CLK2 from the first circuit 10 as a third clock signal CLK3. The second circuit 20 receives the third clock signal CLK3 from the insulating element 30 (S2), and transmits a first data signal DATA1 according to the third clock signal CLK3 (S3). The insulating element 30 transmits the first data signal DATA1 from the second circuit 20 as a second data signal DATA2. The first circuit 10 receives the second data signal DATA2 from the insulating element 30 (S4).

[0034] Due to the above characteristics, in the transceiver circuit 100 according to the first embodiment, bidirectional transmission can be realized with a simple circuit configuration.

[0035] Further, the first circuit 10 has two operating modes, namely, a first transmission mode and a first reception mode. In the first transmission mode, only the first transmission circuit 11 is in an operating state, and operating power is supplied to the circuit portion responsible for transmitting signals included in the first transmission circuit 11, resulting in power consumption. However, the first reception circuit 12 is in a stopped state, and no operating power is supplied to the circuit portion responsible for receiving signals included in the first reception circuit 12, so no power consumption occurs. On the other hand, in the first reception mode, the first reception circuit 12 is in an operating state, and operating power is supplied to the circuit portion responsible for receiving signals included in the first reception circuit 12, resulting in power consumption. However, the first transmission circuit 11 is in a stopped state, and no operating power is supplied to the circuit portion responsible for transmitting signals included in the first transmission circuit 11, so no power consumption occurs.

[0036] Similarly, the second circuit 20 has two operating modes, namely, a second transmission mode and a second reception mode. In the second transmission mode, only the second transmission circuit 21 is in an operating state, and operating power is supplied to the circuit portion responsible for transmitting signals included in the second transmission circuit 21, resulting in power consumption. However, the second reception circuit 22 is in a stopped state, and no operating power is supplied to the circuit portion responsible for receiving signals included in the second reception circuit 22, so no power consumption occurs. On the other hand, in the second reception mode, only the second reception circuit 22 is in an operating state, and operating power is supplied to the circuit portion responsible for receiving signals included in the second reception circuit 22, resulting in power consumption. However, the second transmission circuit 21 is in a stopped state, and no operating power is supplied to the circuit portion responsible for transmitting signals included in the second transmission circuit 21, so no power consumption occurs.

[0037] Due to the above characteristics, bidirectional transmission between the first circuit 10 and the second circuit 20, specifically the transmission of the second clock signal CLK2 and the first data signal DATA1, can be performed by a single insulating element 30. As a result, the number of components can be reduced compared to a transceiver circuit using two conventional insulating elements. Also, during the operation of the first transmission circuit 11, the first reception circuit 12 is in a stopped state, and during the operation of the first reception circuit 12, the first transmission circuit 11 is in a stopped state. Therefore, the first circuit 10 has low power consumption. Similarly, during the operation of the second transmission circuit 21, the second reception circuit 22 is in a stopped state, and during the operation of the second reception circuit 22, the second transmission circuit 21 is in a stopped state. Therefore, the second circuit 20 also has low power consumption.

[0038] Also, in the first transmission mode, the first circuit 10 switches to the first reception mode after a predetermined switching time (the time from time t3 to t5 in FIG. 3) has elapsed after the transmission of the second clock signal CLK2 is completed. Similarly, in the second reception mode, the second circuit 20 switches to the second transmission mode after a predetermined waiting time (the time from time t4 to t6 in FIG. 3) has elapsed after the reception of the third clock signal CLK3 is completed. Due to such characteristics, the transmission of the first data signal DATA1 can be performed without being affected by the residual transmission signal of the first transmission circuit 11.

[0039] (Embodiment 2) In the above-described Embodiment 1, the first circuit 10 had two operating modes, namely the first transmission mode and the first reception mode. In contrast, the first circuit 10 according to the present Embodiment 2 has, in addition to the first transmission mode and the first reception mode, a first standby mode. In the first standby mode, both the first transmission circuit 11 and the first reception circuit 12 are in a stopped state.

[0040] In the initial state of FIG. 4, that is, at the left end of the timing chart, the first circuit 10 is in the first standby mode. Therefore, both the first transmission circuit 11 and the first reception circuit 12 are in a stopped state.

[0041] When the first clock signal CLK1 is input at time t1, the first circuit 10 switches from the first standby mode to the first transmission mode. Specifically, the first control circuit 13 activates the first transmission circuit 11 and keeps the first reception circuit 12 in a stopped state. Thereafter, the operations until time t9 are the same as those in the first embodiment.

[0042] When the reception of the second data signal DATA2 is completed at time t9, the first circuit 10 switches from the first reception mode to the first standby mode. Specifically, the first control circuit 13 stops both the first transmission circuit 11 and the first reception circuit 12.

[0043] When the first clock signal CLK1 is input again at time t11, the first circuit 10 switches again from the first standby mode to the first transmission mode, and thereafter, the above operations are repeated each time the first clock signal CLK1 is input.

[0044] As described above, in the transceiver circuit 100 according to the second embodiment, the first circuit 10 has a first standby mode in addition to the first transmission mode and the first reception mode. In the first standby mode, both the first transmission circuit 11 and the first reception circuit 12 are in a stopped state.

[0045] In the above-described first embodiment, in FIG. 3, the periods from the initial state at the left end to time t1 and from time t9 to t11 were the first reception mode. Therefore, although the first transmission circuit 11 is stopped, the first reception circuit is in an operating state, and power is consumed by the first reception circuit 12. In contrast, in the second embodiment, in FIG. 4, the periods from the initial state at the left end to time t1 and from time t9 to t11 are the first standby mode. Therefore, both the first transmission circuit 11 and the first reception circuit 12 are stopped, and the power consumption of the first circuit 10 is even lower than that in the first embodiment. As a result, the transceiver circuit 100 according to the second embodiment has even lower power consumption than the first embodiment.

[0046] (Embodiment 3) In the above-described Embodiment 1, when the transmission of the first data signal DATA1 is completed at time t8, the second circuit 20 switches from the second transmission mode to the second reception mode. However, if some error occurs and the mode switch fails, the second circuit 20 will remain fixed in the second transmission mode. In that case, the next third clock CLK3 cannot be received, and as a result, the transmission of the first data signal DATA1 from the second circuit 20 to the first circuit 10 stops. As a safety measure against such an event, in the transceiver circuit 100 according to Embodiment 3, when the second transmission mode continues for a predetermined time, the second circuit 20 switches to the second reception mode. Specifically, when the second control circuit 23 detects that a predetermined timeout time has elapsed by the built-in timer circuit, the second transmission circuit 21 is stopped, and the second reception circuit 22 is put into an operating state.

[0047] In the example of FIG. 5, the second control circuit 23 starts the built-in timer at the timing when it switches to the second transmission mode at time t6, and when it detects that the predetermined timeout time ΔT has elapsed by the built-in timer, at time t30, the second transmission circuit 21 is stopped, and the second reception circuit 22 is put into an operating state. Here, the predetermined timeout time ΔT is determined in advance as a value obtained by adding a desired margin to the time normally required for the transmission of the first data signal DATA1.

[0048] As described above, in the transceiver circuit 100 according to Embodiment 3, when the second transmission mode continues for a predetermined time, the second circuit 20 switches to the second reception mode. This prevents the second circuit 20 from remaining fixed in the second transmission mode. In the example of FIG. 5, the second circuit 20 cannot return the first data signal DATA1 in response to the second and third third clock signals CLK3 received from the first circuit 10, but returns to a state where the first data signal DATA1 can be returned normally from the fourth third clock signal CLK3.

[0049] (Modification example) In the above-described first to third embodiments, a configuration in which bidirectional transmission is performed by a single insulating element 30 is shown. However, it is not impossible to use a plurality of insulating elements. As an example, as shown in FIG. 6, instead of the single insulating element 30, a first insulating element 230A and a second insulating element 230B are provided, and the second clock signal CLK2 is transmitted through the first insulating element 230A, and the first data signal DATA1 may be transmitted through the second insulating element 230B. Thereby, it becomes possible to separately operate the paths of the first transmission circuit 11 and the second reception circuit 22 and the paths of the second transmission circuit 21 and the first reception circuit 12. Further, as the single insulating element 30, an electric field coupling capacitor as shown in FIG. 7 may be used instead of the magnetic coupling transformer or current transformer as shown in FIG.

[0050] Also, in the above-described first to third embodiments, the reception determination of the first clock signal CLK1 and the third clock signal CLK3 has been performed by detecting the positive edge of the voltage pulse or current pulse. Instead of this, the reception determination of each clock signal may be performed by detecting the negative edge (fall) of the voltage pulse or current pulse, or both the positive edge and the negative edge.

[0051] Although several embodiments of the present disclosure have been described, these embodiments are presented as examples and are not intended to limit the scope of the disclosure. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the disclosure. These embodiments and their modifications are included in the scope and gist of the disclosure, and are also included in the disclosure described in the claims and the equivalent scope thereof.

Explanation of reference numerals

[0052] 10 First circuit 10a First terminal 11 First transmission circuit 11a Output 11b output 12 First receiving circuit 12a Input 12b Input 20 Second circuit 21 Second transmitting circuit 21a Output 21b Output 22 Second receiving circuit 22a Input 22b Input 30 Insulating element 31 Primary side 32 Secondary side 40 Signal processing circuit 41 Clock terminal 42 Output terminal 43 A / D converter 44 P / S converter 100 Transceiver circuit 200 Transceiver circuit 230A First insulating element 230B Second insulating element 300 Transceiver circuit 330 Insulating element 331 Primary side 332 Secondary side CLK1 First clock signal CLK2 Second clock signal CLK3 Third clock signal CLK4 Fourth clock signal DATA Data signal DATA1 First data signal DATA2 Second data signal R1 First region R2 Second region

Claims

1. a first circuit capable of transmitting and receiving signals; a second circuit capable of transmitting and receiving signals; an insulating element that electrically insulates the first circuit and the second circuit and is capable of transmitting a signal transmitted from one of the first circuit or the second circuit to the other; and comprising the first circuit includes a first terminal to which a first clock signal that repeats a first level and a second level at a constant period is input from the outside, generates a second clock signal by high-frequencyizing the first clock signal, and transmits the second clock signal; the insulating element transmits the second clock signal from the first circuit to the second circuit as a third clock signal; the second circuit transmits a first data signal according to the third clock signal from the insulating element; the insulating element transmits the first data signal from the second circuit as a second data signal; the first circuit receives the second data signal from the insulating element; the first circuit has a first transmission mode and a first reception mode; when the first clock signal input from the outside reaches the first level, the first circuit switches to the first transmission mode and transmits the second clock signal, and when the transmission of the second clock signal is completed, before the level of the first clock signal transitions to the second level, it switches to the first reception mode and receives the second data signal from the insulating element; a transceiver circuit.

2. the first circuit includes a first transmission circuit and a first reception circuit; in the first transmission mode, the first transmission circuit is in an operating state in which operating power is supplied to a circuit portion responsible for transmitting signals included in the first transmission circuit, and the first reception circuit is in a stopped state in which operating power is not supplied to a circuit portion responsible for receiving signals included in the first reception circuit; The transceiver circuit according to claim 1, wherein in the first reception mode, the first transmission circuit is in a stopped state and the first reception circuit is in an operating state.

3. The transceiver circuit according to claim 2, wherein the first circuit switches to the first reception mode after a predetermined switching time has elapsed since the transmission of the second clock signal has been completed.

4. In the first reception mode, when the first circuit receives the second data signal from the insulating element, it switches to the first standby mode. The transceiver circuit according to claim 2 or 3, wherein in the first standby mode, both the first transmission circuit and the first reception circuit are in a stopped state.

5. The second circuit has a second transmission mode and a second reception mode. In the second reception mode, when the second circuit receives the third clock signal from the insulating element, it switches to the second transmission mode. The transceiver circuit according to any one of claims 1 to 4, wherein in the second transmission mode, the second circuit transmits the first data signal and switches to the second reception mode when the transmission of the first data signal is completed.

6. The second circuit includes a second transmission circuit and a second reception circuit. In the second transmission mode, the second transmission circuit is in an operating state in which operating power is supplied to a circuit portion responsible for transmitting signals included in the second transmission circuit, and the second reception circuit is in a stopped state in which operating power is not supplied to a circuit portion responsible for receiving signals included in the second reception circuit. The transceiver circuit according to claim 5, wherein in the second reception mode, the second transmission circuit is in a stopped state and the second reception circuit is in an operating state.

7. The transmission and reception circuit according to claim 6, wherein the second circuit switches to the second transmission mode after a predetermined standby time has elapsed since the reception of the third clock signal was completed.

8. The transmission and reception circuit according to any one of claims 5 to 7, wherein the second circuit switches to the second reception mode when the second transmission mode continues for a predetermined time.

9. The transmission and reception circuit according to claim 8, wherein the second circuit further includes a timer circuit that counts time in response to the switching to the second transmission mode, and when it is detected by the timer circuit that the predetermined time has elapsed, switches to the second reception mode.

10. The transmission and reception circuit according to any one of claims 1 to 9, wherein the insulating element is a single insulating element, and both the second clock signal and the first data signal are transmitted by the single insulating element.

11. The insulating element includes a first insulating element and a second insulating element, The transmission and reception circuit according to any one of claims 1 to 9, wherein the second clock signal is transmitted by the first insulating element, and the first data signal is transmitted by the second insulating element.

12. The transmission and reception circuit according to any one of claims 1 to 11, wherein the insulating element is constituted by a transformer, a current transformer, or a capacitor.

13. The transmission and reception circuit according to any one of claims 1 to 12, wherein the second clock signal, the third clock signal, the first data signal, and the second data signal are voltage pulses or current pulses.

14. The first circuit determines the reception of the first clock signal by detecting a positive edge, a negative edge, or both a positive edge and a negative edge of the first clock signal. The second circuit according to any one of claims 1 to 13, which determines reception of the third clock signal by detecting a positive edge, a negative edge, or both a positive edge and a negative edge of the third clock signal.

15. The second circuit further includes a signal processing circuit that supplies a data signal to the second circuit. The second circuit generates a fourth clock signal by down-converting the third clock signal, and inputs the fourth clock signal to the signal processing circuit. The signal processing circuit supplies the data signal in synchronization with the fourth clock signal input from the second circuit. The second circuit according to any one of claims 1 to 14, which generates the first data signal by up-converting the data signal supplied from the signal processing circuit.

16. The signal processing circuit according to claim 15, which includes an A / D converter.

17. The A / D converter according to claim 16, which is constituted by a ΔΣ modulator.

Images