Interconnection for modular die design

Abstract

Interconnects for modular die designs are disclosed. In one aspect, dies that are chiplets are designed and tested for compatibility. After approval of the chiplet design, multiple dies or chiplets can be bonded together in a multi-die package to form a package with a desired computing capability. After assembly, each chiplet is provided with a unique identifier, such as by setting fuses. Based on the unique identifier, each chiplet will know how its interface to other chiplets is configured so that signals can be routed appropriately. Using modular chiplets in this manner increases flexibility of design options while reducing test requirements and non-recurring costs.

Description

Claim of Priority

[0001] Priority Application

[0001] This application claims priority to U.S. Patent Application No. 17 / 655,823, filed on March 22, 2022, entitled "INTERCONNECTIONS FOR MODULAR DIE DESIGNS," which is hereby incorporated by reference in its entirety.

Technical Field

[0002] I. Field of Disclosure

[0002] The technology of this disclosure generally relates to interconnections for modular integrated circuit (IC) die designs.

Background Art

[0003] II. Background

[0003] The abundant computing devices in modern society provide numerous functions for different requirements. With the improvement of functional possibilities, an improvement in computing requirements (e.g., further processing power) has been demanded. In the past, such improved computing requirements could be met by increasing the number of transistors in an integrated circuit (IC) die or by increasing the size of the die. Since the size of transistors is approaching some theoretical limits at the low nanometer scale, it has become more difficult to add transistors within a given space. Similarly, the size of the die is reaching some practical limits due to current manufacturing processes. That is, as the size of the die increases, the yield for a given manufacturing run is likely to decrease, and there may be process variations across the entire die, which can lead to problems in managing internal latency and bias requirements. Therefore, there is still a need for a better method for designing a die that allows flexibility in meeting various computing requirements.

Summary of the Invention

[0004]

[0004] The aspects disclosed in the detailed description include interconnections for modular die design. In particular, dies that are chiplets are designed and tested for compatibility. After approval of the chiplet design, multiple dies or chiplets can be coupled together within a multi-die package to form a package with the desired computing capabilities. After assembly, each chiplet is provided with a unique identifier, such as by setting fuses. Based on the unique identifier, each chiplet becomes aware of how the interface to other chiplets is configured so that signals can be properly routed. Using modular chiplets in this way reduces test requirements and recurring costs while improving the flexibility of design options.

[0005]

[0005] In one aspect in this regard, a method of forming a package is disclosed. The method includes placing a plurality of chiplets on a substrate. The method also includes setting a unique identifier for each chiplet. The method also includes forming a look-up table (LUT) for each chiplet to route communication between the chiplets based on the unique identifier. The method also includes configuring ports to route communication between the chiplets based on the unique identifier.

[0006]

[0006] In another aspect, a method of communication between chiplets within a package is disclosed. The method includes generating a signal in a logic block within a first chiplet within the package. The method also includes comparing the address of the signal to an LUT to determine a physical address. The method also includes transmitting the signal to a port selected based on the LUT.

[0007]

[0007] In another aspect, a package is disclosed. The package includes a substrate. The package also includes a plurality of chiplets mounted on the substrate and interconnected with each other. Each chiplet of the plurality of chiplets includes a unique identifier. Each chiplet also includes a plurality of ports. Each chiplet also includes a LUT. Each chiplet also includes a control circuit configured to distinguish, based on the LUT, whether a signal generated within the chiplet is local or directed to a different chiplet.

[0008]

[0008] In another aspect, a package is disclosed. The package includes a substrate. The package also includes a plurality of chiplets mounted on the substrate and interconnected with each other. Each chiplet of the plurality of chiplets includes a unique identifier. Each chiplet also includes a plurality of ports. Each chiplet also includes a control circuit configured to route a signal generated within the chiplet to a local address or to a different chiplet within the plurality of chiplets based on the chiplet identifier within the signal.

[0009]

[0009] In another aspect, a package is disclosed. The package includes a substrate. The package also includes a plurality of chiplets mounted on the substrate and interconnected with each other. Each chiplet of the plurality of chiplets includes a unique identifier. Each chiplet also includes a plurality of ports. Each chiplet also includes a control circuit configured to route a signal generated within the chiplet to a local address or to a transmission port based on the chiplet identifier.

Brief Description of the Drawings

[0010]

Figure 1

[0010] It is a stylized diagram of an exemplary chiplet incorporated in a multi-chiplet package.

Figure 2

[0011] Block diagram of an exemplary chiplet having ports for interconnecting with other chiplets, according to an exemplary aspect of the present disclosure.

Figure 3

[0012] Block diagram of an exemplary package using four homogeneous chiplets having interconnects therebetween, according to an exemplary aspect of the present disclosure.

Figure 4

[0013] Table showing how addressing can function for interconnected chiplets within a die.

Figure 5

[0014] Table showing how memory mapping can function for interconnected chiplets within a die.

Figure 6

[0015] Flowchart showing an exemplary process for manufacturing a die from chiplets and creating interconnects, according to the present disclosure.

Figure 7

[0016] Block diagram of an exemplary processor-based system that can include a die formed from a chiplet having an interconnect, according to the present disclosure.

Figure 8

[0017] Block diagram of an exemplary transceiver circuit that can be present within a processor-based system including a formed die, according to the present disclosure.

DETAILED DESCRIPTION

[0011]

[0018] Here, some exemplary aspects of the present disclosure will be described with reference to the drawings. The term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other aspects.

[0012]

[0019] Aspects disclosed in the detailed description include interconnections for modular die design. In particular, dies that are chiplets are designed and tested for compatibility. After approval of the chiplet design, multiple dies or chiplets can be joined together within a multi-die package to form a package having the desired computing capabilities. After assembly, each chiplet is provided with a unique identifier, such as by setting fuses. Based on the unique identifier, each chiplet becomes aware of how the interface to other chiplets is configured so that signals can be properly routed. Using modular chiplets in this way reduces test requirements and recurring costs while improving the flexibility of design options.

[0013]

[0020] In this regard, FIG. 1 is a stylized diagram of a package 100 formed from a plurality of like chiplets 102(1)-102(4). Chiplets 102(1)-102(4) can be mounted on a substrate 104, such as a laminate (e.g., a printed circuit board (PCB)) having an internal metallization layer (not shown). The metallization layer can include vias and conductors for interconnecting pins on chiplets 102(1)-102(4). Package 100 can include a molded overcover (not shown), among other things.

[0014]

[0021] It should be further noted that although four chiplets 102(1)-102(4) are shown within package 100, the exemplary aspects of the present disclosure are not limited to only four. For example, the package can be formed using 2-10 (or more) chiplets 102. When the chiplets 102 are of the same type, it may be reasonable geometrically to use an even number of chiplets 102, and more logically, a power of two number of chiplets 102 (e.g., 2, 4, 8, etc.).

[0015]

[0022] Although all of the chiplets 102(1) to 102(4) are formed from general-purpose chiplets 102, it should be understood that the package 100 may be formed from heterogeneous chiplets (not shown). As yet another possibility, a plurality of chiplets 102 may be such that one or more heterogeneous chiplets on the same package are of the same type (e.g., three identical chiplets and one different chiplet, two sets of two different chiplets, etc.). The advantage of using homogeneous chiplets 102(1) to 102(4) is that only a single design and test cycle is required. Each additional chiplet design would add additional design and test cycles, which can increase overhead costs, increase the average unit cost, and / or delay the time to market.

[0016]

[0023] FIG. 2 provides further details regarding an exemplary chiplet 200 that may correspond to the chiplet 102 of FIG. 1. The chiplet 200 may include various logic blocks 202(1) to 202(N) coupled to an internal interconnect 204. The internal interconnect 204 may be associated with and / or controlled by a control circuit 206 that may control the routing of communications based in part on the contents of a look-up table (LUT) 208. A plurality of input / output (I / O) ports 210(0) to 210(M) may be coupled to the internal interconnect 204 to enable communication from the logic blocks 202(1) to 202(N) to external elements such as logic blocks within another chiplet 102. Fuses 212 may be externally accessible and may be used to help specify a unique identifier for the chiplet 200, as will be described in more detail below.

[0017]

[0024] When a number of chiplets 102 or 200 are assembled into a package, there may be a need for logical blocks within one chiplet to communicate with logical blocks within another chiplet. Where there are a number of identical chiplets, it may be necessary to distinguish between them for chiplet-to-chiplet communication. Exemplary aspects of the present disclosure contemplate using fuses 212 to solve this communication problem. In particular, the fuses 212 may be used to set a unique identifier (e.g., a unique sequence of bits) for the chiplet 200, as will be better described with reference to FIGS. 3-5.

[0018]

[0025] In this regard, FIG. 3 shows a package 300 similar to the package 100 of FIG. 1. The package 300 includes four chiplets 200(0) to 200(3). Each of the fuses 212(0) to 212(3) can be set to indicate a specific die identifier (Die_ID) during integration into the package 300. As shown, the chiplet 200(0) has a die_ID of 00, the chiplet 200(1) has a die_ID of 01, the chiplet 200(2) has a die_ID of 10 (2 in binary), and the chiplet 200(3) has a die_ID of 11 (3 in binary). Each of the control circuits 206(0) to 206(3) can read the fuses 212(0) to 212(3) and configure the port 302 based on the contents of the respective LUTs 208(0) to 208(3). Specifically, each of the chiplets 200(0) to 200(3) has three ports 3020(0) to 3020(2) - 3023(0) to 3023(2) (corresponding to the ports 210(0) to 210(M) of FIG. 2). Before the fuses 212(0) to 212(3) are set, the ports 3020(0) to 3020(2) - 3023(0) to 3023(2) appear the same to the respective internal interconnects 204(0) to 204(3). By setting the fuses 212(0) to 212(3) to provide unique die_IDs, the control circuits 206(0) to 206(3) here handle the ports 3020(0) to 3020(2) - 3023(0) to 3023(2) differently based on the die_ID. Thus, for the chiplet 200(0), the control circuit 206(0) knows that the port 3020(0) is coupled to the chiplet 200(1), the port 3020(1) is coupled to the chiplet 200(2), and the port 3020(2) is coupled to the chiplet 200(3). Thus, when communication from the logic blocks 2020(1) to 2020(N) within the chiplet 200(0) is addressed to the logic block 2022(3) within the chiplet 200(2), the control circuit 206(0) routes the communication to the port 3020(1) via the internal interconnect 204(0).

[0019]

[0026] For completeness, for die 200(1), control circuit 206(1) knows that port 3021(0) is coupled to die 200(0), port 3021(1) is coupled to die 200(3), and port 3021(2) is coupled to die 200(2). For die 200(2), control circuit 206(2) knows that port 3022(0) is coupled to die 200(3), port 3022(1) is coupled to die 200(0), and port 3022(2) is coupled to die 200(1). For die 200(3), control circuit 206(3) knows that port 3023(0) is coupled to die 200(2), port 3023(1) is coupled to die 200(1), and port 3023(2) is coupled to die 200(0). It should be understood that these connections can, in most cases, be a function of the positioning of dies 200(0) - 200(3) such that dies 200(0) - 200(3) are mirrored about different axes. For example, die 200(3) is mirrored about the y-axis with respect to die 200(0), and die 200(1) is mirrored about the x-axis with respect to die 200(0). Due to this mirroring, ports 3020(0) - 3020(2) - 3023(0) - 3023(2) are aligned as shown. If dies 200(0) - 200(3) are rotated or are not of the same type, ports 3020(0) - 3020(2) - 3023(0) - 3023(2) will be aligned differently and may have different die-to-die connections. Although not essential, a common goal is to minimize the distance of such die-to-die connections in order to reduce latency and potentially reduce the possibility of crosstalk or other forms of electromagnetic interference.

[0020]

[0027] It should be understood that if there are fewer or more chiplets than four, fewer or more bits may be required in fuse 212. Similarly, fewer or more ports 302 having corresponding entries within LUT 208 may be required.

[0021]

[0028] FIGS. 4 and 5 illustrate further nuances of routing. For purposes of example, assume that each chiplet 200 has sixty-four gigabytes (64 GB) of memory within logic block 202. Referring to FIG. 4 and table 400 therein, control circuits 206(0)-206(3) can prepend a chiplet identifier 402 to the physical address 404 used by logic block 202, and the chiplet identifier 402 can include a number of bits equal to one plus the number of bits necessary to uniquely identify the chiplet. Thus, for four chiplets 200(0)-200(3), the chiplet identifier 402 can be 3 bits (one plus 2 bits for identifying four chiplets). If there are additional chiplets, the chiplet identifier 402 can be more than 3 bits. The first bit can be a local or remote identifier. That is, for example, a first bit of 0 can indicate that the communication is local. Thus, as shown by row 404, a chiplet identifier of 000 refers to a memory element of the local chiplet. Other chiplet identifiers 402 that begin with 0 can be reserved for future use. If the first bit is 1, this usage can indicate that the subsequent bits identify which chiplet (and corresponding port) the communication is addressed to. Note that the chiplet identifier may begin with 1 but still be for a local address (generally indicated at 406).

[0022]

[0029] FIG. 5 extends the concept of the table 400 of FIG. 4 and shows how the default configuration memory map 500(0) stored for the chiplet 200(0) and the modified configuration can exist as shown by the memory maps 500(1)-500(3) after setting the fuses 212(0)-212(3).

[0023]

[0030] While fuses are specifically contemplated as a way to configure the control circuit, it should be understood that there may be other ways to achieve the same result. For example, software can reside within firmware that provides a logic-physical address mapping function. Optionally, other hardware mechanisms (e.g., jumpers, short circuits, or open circuits, etc.) can also be used.

[0024]

[0031] FIG. 6 shows a flowchart of a process 600 related to the design and manufacture of a package having a number of modular dies with interconnects in accordance with the present disclosure. Specifically, process 600 begins with the design of the chiplet 200 (block 602). The chiplet 200 is tested and verified (block 604). Next, computing requirements are identified and a package is designed using the chiplet 200 (block 606). Next, the designer can confirm whether the package can function as intended with the existing chiplet 200 (block 608). That is, the first designed chiplet 200 is optimized for a neural processor or a graphics processor, but perhaps not optimized for both. If a package cannot be constructed using the existing chiplet 200, additional chiplets 200 are designed, tested, and verified (block 610), and the designer determines whether a package can be constructed using the existing chiplet 200. In this way, the package can be of the same type of chiplet 200, or a combination of different types of chiplets 200.

[0025]

[0032] Once the designer is satisfied with the package design, the package is formed by assembling the chiplets 200 on the substrate 104 (block 612). As part of this step, each chiplet 200 can be assigned and a unique identifier can be set (block 612A). The setting of the unique identifier can be done by setting the fuse 212, grounding a specific connection, setting a jumper, via software, etc. The ports on the chiplet 200 are interconnected (block 612B). That is, the chiplet 200 can be soldered to the contacts in the metallization layer of the substrate 104 such that the conductors and vias in the metallization layer interconnect the pins of the ports of the chiplet 200. Note that it is possible to form the interconnections before setting the unique identifier by reversing blocks 612A and 612B in time.

[0026]

[0033] Once the unique identifier is set, the control circuit can configure the ports using the unique identifier (block 614). That is, the control circuit 206 can use the LUT 208 to determine which ports are connected to which other chiplets. The control circuit 206 can also form an address table (e.g., table 400 of FIG. 5 or memory mapping) including local and global addresses based on the unique identifier (block 616).

[0027]

[0034] The interconnects and packages assembled therefrom for modular die design according to the aspects disclosed herein can be provided within or integrated into any processor-based device. Examples include, but are not limited to, set-top boxes, entertainment units, navigation devices, communication devices, stationary data units, mobile data units, global positioning system (GPS) devices, mobile phones, cellular phones, smartphones, session initiation protocol (SIP) phones, tablets, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, eyewear, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multicopters.

[0028]

[0035] As described above, the modular die design of the present disclosure can be incorporated into a processor-based system. In this regard, FIG. 7 shows an example of a processor-based system 700 that can employ a package 300 as shown in FIG. 3. In this example, the processor-based system 700 includes one or more central processing units (CPUs) 702, each of which includes one or more processors 704. The processor(s) 704 can include the package 300. The CPU(s) 702 can have a cache memory 706 coupled to the processor(s) 704 to provide rapid access to temporarily stored data. The CPU(s) 702 are coupled to a system bus 708 and can interconnect master and slave devices included in the processor-based system 700. As is well known, the CPU(s) 702 communicate with these other devices by exchanging address information, control information, and data information via the system bus 708. For example, the CPU(s) 702 can communicate a burst transaction request to a memory controller 710 as an example of a slave device. Although not shown in FIG. 7, a number of system buses 708 may be provided.

[0029]

[0036] As shown in FIG. 7, these devices can include, by way of example, a memory system 712, one or more input devices 716, one or more output devices 718, one or more network interface devices 720, and one or more display controllers 722. The input device(s) 716 can include any type of input device including, but not limited to, input keys, switches, voice processors, etc. The output device(s) 718 can include any type of output device including, but not limited to, audio, video, other visual indicators, etc. The network interface device(s) 720 can be any device configured to enable the exchange of data with a network 724. The network 724 can be any type of network including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH (trademark) network, and the Internet. The network interface device(s) # can be configured to support any desired type of communication protocol. The memory system 712 can include one or more memory units 714(0 to N).

[0030]

[0037] The CPU(s) 702 may also be configured to access a display controller(s) 722 via a system bus 708 to control information sent to one or more displays 726. The display controller(s) 722 sends information to be displayed on the display(s) 726 via one or more video processors 728, and the video processor 728 processes the information to be displayed into a format suitable for the display(s) 726. The display(s) 726 can include any type of display including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc.

[0031]

[0038] FIG. 8 shows an exemplary wireless communication device 800 that includes radio frequency (RF) components formed from one or more ICs 802, and any one of the ICs 802 can be a package that includes a number of modular dies according to the present disclosure, or can include such a package. The wireless communication device 800 may, by way of example, include any of the devices described above or be provided therein. As shown in FIG. 8, the wireless communication device 800 includes a transceiver 804 and a data processor 806. The data processor 806 may include memory for storing data and program code. The transceiver 804 includes a transmitter 808 and a receiver 810 that support two-way communication. In general, the wireless communication device 800 may include any number of transmitters 808 and / or receivers 810 for any number of communication systems and frequency bands. All or part of the transceiver 804 may be implemented in one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc.

[0032]

[0039] The transmitter 808 or the receiver 810 can be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal is frequency-converted between RF and baseband in multiple stages, for example, from RF to an intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct conversion architecture, the signal is frequency-converted between RF and baseband in one stage. The superheterodyne architecture and the direct conversion architecture may use different circuit blocks and / or have different requirements. In the wireless communication device 800 of FIG. 8, the transmitter 808 and the receiver 810 are implemented using a direct conversion architecture.

[0033]

[0040] In the transmission path, the data processor 806 processes the data to be transmitted and provides an I analog output signal and a Q analog output signal to the transmitter 808. In the exemplary wireless communication device 800, the data processor 806 includes digital-to-analog converters (DACs) 812(1), 812(2) for converting the digital signal generated by the data processor 806 into an I analog output signal and a Q analog output signal, for example, an I output current and a Q output current, for further processing.

[0034]

[0041] Inside the transmitter 808, the low-pass filters 814(1) and 814(2) filter the I analog output signal and the Q analog output signal respectively to remove the unwanted signals generated by the previous digital-to-analog conversion. The amplifiers (AMPs) 816(1) and 816(2) amplify the signals from the low-pass filters 814(1) and 814(2) respectively to provide the I baseband signal and the Q baseband signal. The upconverter 818 upconverts the I baseband signal and the Q baseband signal using the I and Q transmit (TX) local oscillator (LO) signals from the transmit (TX) local oscillator (LO) signal generator 622 via the mixers 820(1) and 820(2) to provide the upconverted signal 824. The filter 826 filters the upconverted signal 824 to remove the unwanted signals generated by the frequency upconversion and the noise within the received frequency band. The power amplifier (PA) 828 amplifies the upconverted signal 824 from the filter 826 to obtain the desired output power level and provides the transmitted RF signal. The transmitted RF signal is routed via the duplexer or switch 830 and transmitted via the antenna 832.

[0035]

[0042] In the receiving path, antenna 832 receives the signal transmitted by the base station, provides a received RF signal, and this received RF signal is routed through duplexer or switch 830 and provided to low noise amplifier (LNA) 834. Duplexer or switch 830 is designed to operate using a specific RX-to-TX duplexer frequency separation so that the received (RX) signal is separated from the TX signal. The received RF signal is amplified by LNA 834 and filtered by filter 836 to obtain a desired RF input signal. Downconversion mixers 838(1), 838(2) mix the output of filter 836 with the I RX LO signal and Q RX LO signal (i.e., LO_I and LO_Q) from RX LO signal generator 840 to generate an I baseband signal and a Q baseband signal. The I baseband signal and the Q baseband signal are amplified by AMPs 842(1), 842(2) and further filtered by low pass filters 844(1), 844(2) to obtain an I analog input signal and a Q analog input signal provided to data processor 806. In this embodiment, data processor 806 includes analog-to-digital converters (ADCs) 846(1), 846(2) for converting the analog input signal into a digital signal to be further processed by data processor 806.

[0036]

[0043] In the wireless communication device 800 of FIG. Y, the TX LO signal generator 822 generates an I TX LO signal and a Q TX LO signal that are used for frequency upconversion, while the RX LO signal generator 840 generates an I RX LO signal and a Q RX LO signal that are used for frequency downconversion. Each LO signal is a periodic signal having a specific fundamental frequency. The TX phase-locked loop (PLL) circuit 848 receives timing information from the data processor 806 and generates a control signal that is used to adjust the frequency and / or phase of the TX LO signal from the TX LO signal generator 822. Similarly, the RX PLL circuit 850 receives timing information from the data processor 806 and generates a control signal that is used to adjust the frequency and / or phase of the RX LO signal from the RX LO signal generator 840.

[0037]

[0044] Those skilled in the art will further understand that the various exemplary logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium as instructions executed by a processor or other processing device, or implemented as a combination of both. The master device and slave device described herein can be used, for example, in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be any type and size of memory and can be configured to store any type of information desired. To clearly illustrate this interchangeability, the various exemplary components, blocks, modules, circuits, and steps have been generally described above in terms of their functionality. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in various ways for each particular application, but such implementation decisions should not be construed as departing from the scope of the present disclosure.

[0038]

[0045] Various exemplary logical blocks, modules, and circuits described in connection with the aspects disclosed herein can be implemented or executed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate logic or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. The processor can be a microprocessor, but alternatively, the processor can be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration).

[0039]

[0046] Aspects disclosed herein can be embodied in hardware or in instructions stored within hardware and can reside, for example, in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, hard disk, a removable disk, CD-ROM, or any other form of computer-readable medium known in the art. Exemplary memory media is coupled to the processor such that the processor can read information from, and write information to, the memory media. In alternative, the memory media may be integral to the processor. The processor and the memory media can reside in an ASIC. The ASIC can reside in a remote station. In alternative, the processor and the memory media can reside as discrete components in a remote station, base station, or server.

[0040]

[0047] Also, note that the operation steps described in any of the exemplary embodiments of this specification are also noted for the points explained to provide examples and considerations. The described operations can also be executed in many different sequences other than the illustrated sequence. Furthermore, the operations described in a single operation step can actually also be executed in several different steps. In addition, one or more operation steps considered in the exemplary embodiments can also be combined. Understand that various modifications can be made to the operation steps shown in the flowchart diagrams that will be readily apparent to those skilled in the art. Those skilled in the art will also understand that any of a variety of techniques and methods can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips, which may be referred to throughout the above description, can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0041]

[0048] The above description of the present disclosure is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be readily apparent to those skilled in the art, and the general principles defined herein can also be applied to other variations. Therefore, the present disclosure is not intended to be limited to the embodiments and designs described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

[0042]

[0049] In the following numbered clauses, implementation examples will be described. 1. A method of forming a package, comprising: placing a plurality of chiplets on a substrate; setting a unique identifier for each chiplet; forming a look-up table (LUT) for each chiplet to route communication between the chiplets based on the unique identifier; A method comprising configuring ports to route communication between chiplets based on a unique identifier. 2. The method according to clause 1, wherein the plurality of chiplets are of the same type. 3. The method according to clause 1, wherein the plurality of chiplets are of different types. 4. The method according to any one of clauses 1 to 3, wherein setting the unique identifier includes setting at least one fuse. 5. The method according to any one of clauses 1 to 3, wherein setting the unique identifier includes grounding a circuit. 6. The method according to any one of clauses 1 to 3, wherein setting the unique identifier includes using software to set the unique identifier. 7. The method according to any one of the preceding clauses, wherein arranging a plurality of chiplets on a substrate includes forming interconnects between the plurality of chiplets using vias and conductors in a metallization layer within the substrate. 8. The method according to any one of the preceding clauses, further comprising assigning a unique identifier to each chiplet prior to the setting. 9. The method according to any one of the preceding clauses, further comprising loading global address information versus local address information into a look-up table (LUT) based on the unique identifier. 10. The method according to any one of the preceding clauses, wherein arranging a plurality of chiplets on a substrate includes coupling a first port of a first chiplet to a first port of a second chiplet. 11. A method for communication between chiplets within a package, comprising: generating a signal in a logic block within a first chiplet within the package; comparing the address of the signal with a look-up table (LUT) to determine a physical address; transmitting the signal to a port selected based on the LUT. 12. A package comprising: a substrate; Comprising a plurality of chiplets mounted on a substrate and interconnected with each other, each of the plurality of chiplets, a unique identifier, a plurality of ports, a look-up table (LUT), and a control circuit configured to distinguish, based on the LUT, whether a signal generated within the chiplet is local or directed to a different chiplet, a package. 13. The package according to clause 12, wherein the plurality of chiplets are of the same type. 14. The package according to clause 12, wherein the plurality of chiplets are of different types. 15. The package according to any one of clauses 12 to 14, wherein the substrate comprises a metallization layer including conductors and vias, and the plurality of chiplets are interconnected using the conductors and vias. 16. A package, a substrate, comprising a plurality of chiplets mounted on the substrate and interconnected with each other, each of the plurality of chiplets, a unique identifier, a plurality of ports, and a control circuit configured to route a signal generated within the chiplet to a local address or to a different chiplet within the plurality of chiplets based on a chiplet identifier within the signal, a package. 17. The package according to clause 16, wherein the chiplet identifier is prepended to an address within the signal. 18. The package according to clause 16 or 17, wherein the chiplet identifier includes a number of bits equal to 1 plus the number of bits necessary to uniquely identify the plurality of chiplets. 19. A package, a substrate, comprising a plurality of chiplets mounted on the substrate and interconnected with each other, each of the plurality of chiplets, A unique identifier, a plurality of ports, and a control circuit configured to route signals generated within the chiplet to a local address or to an output port based on the chiplet identifier. A package comprising: The invention described in the claims of the present application at the time of filing is appended below. [C1] A method of forming a package, comprising: placing a plurality of chiplets on a substrate; setting a unique identifier for each chiplet; forming a look-up table (LUT) for each chiplet to route communication between the chiplets based on the unique identifier; configuring ports to route communication between the chiplets based on the unique identifier. [C2] The method according to C1, wherein the plurality of chiplets are of the same type. [C3] The method according to C1, wherein the plurality of chiplets are of different types. [C4] The method according to C1, wherein setting the unique identifier includes setting at least one fuse. [C5] The method according to C1, wherein setting the unique identifier includes grounding a circuit. [C6] The method according to C1, wherein setting the unique identifier includes using software to set the unique identifier. [C7] The method according to C1, wherein placing the plurality of chiplets on the substrate includes forming interconnects between the plurality of chiplets using vias and conductors in a metallization layer within the substrate. [C8] The method according to C1, further comprising assigning the unique identifier to each chiplet before the setting. [C9] The method according to C1, further comprising loading global address information versus local address information into the look-up table (LUT) based on the unique identifier. [C10] The method according to C1, wherein placing the plurality of chiplets on the substrate includes coupling a first port of a first chiplet to a first port of a second chiplet. [C11] A method of communication between chiplets within a package, comprising: generating a signal in a logic block within a first chiplet within the package; comparing the address of the signal with a look-up table (LUT) to determine a physical address; transmitting the signal to a port selected based on the LUT. [C12] A package, comprising: a substrate; a plurality of chiplets mounted on the substrate and interconnected with each other, wherein each chiplet of the plurality of chiplets has a unique identifier; a plurality of ports; A look-up table (LUT), and a control circuit configured to distinguish, based on the LUT, whether a signal generated within the chiplet is local or is directed to a different chiplet, a package comprising the same. [C13] The package according to C12, wherein the plurality of chiplets are of the same type. [C14] The package according to C12, wherein the plurality of chiplets are of different types. [C15] The package according to C12, wherein the substrate comprises a metallization layer including conductors and vias, and the plurality of chiplets are interconnected using the conductors and the vias. [C16] A package, comprising: a substrate; and a plurality of chiplets mounted on the substrate and interconnected with each other, each chiplet of the plurality of chiplets comprising: a unique identifier; a plurality of ports; and a control circuit configured to route a signal generated within the chiplet to a local address or to a different chiplet within the plurality of chiplets based on a chiplet identifier within the signal, a package comprising the same. [C17] The package according to C16, wherein the chiplet identifier is prepended to an address within the signal. [C18] The package according to C16, wherein the chiplet identifier comprises a number of bits equal to 1 plus the number of bits necessary to uniquely identify the plurality of chiplets. [C19] A package, comprising: a substrate; and a plurality of chiplets mounted on the substrate and interconnected with each other, each chiplet of the plurality of chiplets comprising: a unique identifier; a plurality of ports; and a control circuit configured to route a signal generated within the chiplet to a local address or to a transmit port based on a chiplet identifier, a package comprising the same.

Claims

1. A method of forming a package, comprising: placing a plurality of chiplets on a substrate; setting at least one fuse to set a unique identifier for each chiplet; forming a look-up table (LUT) for each chiplet to route communication between the chiplets based on the unique identifier; configuring ports to route communication between the chiplets based on the unique identifier.

2. The method according to claim 1, wherein the plurality of chiplets are of the same type.

3. The method according to claim 1, wherein the plurality of chiplets are of different types.

4. The method according to claim 1, wherein setting the unique identifier includes grounding a circuit.

5. The method according to claim 1, wherein setting the unique identifier includes using software to set the unique identifier.

6. The method according to claim 1, wherein placing the plurality of chiplets on the substrate includes forming interconnects between the plurality of chiplets using vias and conductors in a metallization layer within the substrate.

7. The method according to claim 1, further comprising assigning the unique identifier to each chiplet prior to setting.

8. The method according to claim 1, further comprising forming the look-up table (LUT) including a global address and a local address based on the unique identifier.

9. The method according to claim 1, wherein arranging the plurality of chiplets on the substrate includes coupling a first port of a first chiplet to a first port of a second chiplet. **Claim 10** A method for communication between chiplets within a package, comprising: generating a signal in a logic block within a first chiplet within the package; comparing an address of the signal to a look-up table (LUT) to determine a physical address, wherein each chiplet of the chiplets has a unique identifier defined by at least one fuse, and the LUT routes communication between the chiplets based on the unique identifier; transmitting the signal to a port selected based on the LUT. **Claim 11** A package, comprising: a substrate; a plurality of chiplets mounted on the substrate and interconnected with each other; wherein each chiplet of the plurality of chiplets comprises: a unique identifier; a plurality of ports; a look-up table (LUT); a control circuit configured to distinguish, based on the LUT, whether a signal generated within the chiplet is local or directed to a different chiplet. **Claim 12** The package according to claim 11, wherein the plurality of chiplets are of the same type. **Claim 13** The package according to claim 11, wherein the plurality of chiplets are of different types. **Claim 14** The package according to claim 11, wherein the substrate comprises a metallization layer including conductors and vias, and the plurality of chiplets are interconnected using the conductors and the vias.

15. A package, comprising: a substrate; a plurality of chiplets mounted on the substrate and interconnected with each other; each chiplet of the plurality of chiplets comprising: a unique identifier; a plurality of ports; a look-up table (LUT); and a control circuit configured to route signals generated within the chiplet to a local address or to a different chiplet within the plurality of chiplets based on the chiplet identifier in the signal using the LUT.

16. The package according to claim 15, wherein the chiplet identifier is prepended to the address in the signal.

17. The package according to claim 15, wherein the chiplet identifier includes a number of bits equal to 1 plus the number of bits necessary to uniquely identify the plurality of chiplets.

18. A package, comprising: a substrate; a plurality of chiplets mounted on the substrate and interconnected with each other; each chiplet of the plurality of chiplets comprising: a unique identifier; a plurality of ports; a look-up table (LUT); and a control circuit configured to route signals generated within the chiplet to a local address or to a transmission port based on the chiplet identifier using the LUT.

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