Semiconductor device

Abstract

To provide a semiconductor device in which the connection reliability of each electrode is improved even when the gap between opposing electrodes fluctuates and the gap between arranged electrodes is narrow.SOLUTION: In a semiconductor device including a plurality of first electrode portions formed on a substrate surface of a first electronic component, and a plurality of second electrode portions which are formed on the surface of a second electronic component and face the respective first electrode portions, an opposing surface of the first electrode portion and an opposing surface of the second electrode portion that are opposed to each other and paired with each other being electrically connected to each other via solder 5, at least one of the paired first electrode portion and the second electrode portion includes pillar electrodes 14 and 24 protruding from the surface of the electronic component. In the paired first and second electrode portions, a first tip surface 24a which is a surface portion closest to the second electrode portion side of the opposing surface of the first electrode portion, and a second tip surface 14a which is a surface portion closest to the first electrode portion side of the opposing surface of the second electrode portion are different in area from each other.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a semiconductor device in which a plurality of electronic components having electrodes arranged at narrow intervals with respect to an electrode formation surface are electrically connected by solder.

Background Art

[0002] Semiconductor elements tend to have an increasing number of terminals (electrodes) with the progress of the times and the increase in integration and multifunctionality. Along with this, as a method of mounting a semiconductor element, which is an electronic component, on a wiring board, which is also an electronic component, from solder bonding using a lead frame, a plurality of electrodes (pins) are arranged in a grid pattern on the mounting surface (surface) of the semiconductor element, and this is connected to the wiring board by solder, a method called BGA (Ball Grid Array) has been adopted. As a result, the connection parts between electronic components tend to have a large number of pins.

[0003] In recent years, further high integration has advanced. Therefore, there is a desire to further increase the number of terminals (the number of electrodes to be arranged) by making the cross-section of the electrodes smaller and the interval between the electrodes narrower. However, due to the narrowing of the interval between the arranged electrodes, it has become necessary to consider the volume of the solder for connecting between the opposing electrodes. This is because in the conventional solder connection (BGA method), the solder sandwiched between the opposing electrodes on the substrate side and the electrodes on the electronic component side spreads horizontally (see Fig. 8(a)), and there is a concern that the spread solder may contact the adjacent electrodes and cause a short circuit between the electrodes.

[0004] Therefore, in order to suppress the lateral spread of solder, conventionally, electrodes that were previously under an insulating layer or non-conductive layer such as solder resist have been made into pillar electrodes that protrude from the surface of electronic components, and a mounting method has been adopted in which opposing pillar electrodes (between opposing electrodes) are connected with a small amount of solder (see Fig. 8(b)). This mounting method can suppress the lateral spread of solder by reducing the amount of solder. On the other hand, when all the solder is alloyed, the mechanical properties of the solder change significantly, or the allowable tolerance for warping (such as warping of the substrate) of the electronic component on which the electrode is formed becomes small, resulting in a so-called cold joint (disconnection defect) where a semiconductor element (chip) cannot be mounted on the wiring board.

[0005] As a technique for solving the above problems, for example, there is the method described in Patent Document 1. Patent Document 1 describes that by forming a solder layer by plating, the variation in solder height due to the conventional solder printing method can be improved, and a solder with a uniform thickness can be obtained while having sufficient solder.

[0006] However, in the method described in Patent Document 1, in a place where the interval between the electrodes to be arranged becomes narrow, the solder does not spread laterally and electrode short-circuit does not occur.

[0007] Also, as described above, an actual substrate has some warping. For this reason, the gap between opposing electrodes is narrow between some opposing electrodes and wide between some opposing electrodes. Therefore, considering ensuring electrical connection even in a wide gap between opposing electrodes, it is necessary to define the amount of solder interposed between each pair of opposing electrodes. For this reason, in the opposing electrode portion where the distance between opposing electrodes is relatively narrow, since the opposing distance is closer, the solder interposed between the opposing electrodes does not fit between the opposing electrodes and protrudes laterally.

Prior Art Documents

Patent Documents

[0008]

Patent Document 1

SUMMARY OF THE INVENTION

PROBLEMS TO BE SOLVED BY THE INVENTION

[0009] The present invention has been made paying attention to the above points, and an object thereof is to provide a semiconductor device in which there is a variation in the gap between opposing electrodes and the connection reliability of each electrode is improved even when the distance between the arranged electrodes is narrow.

MEANS FOR SOLVING THE PROBLEMS

[0010] To solve the problems, one aspect of the present invention includes a plurality of first electrode portions formed on the surface of a substrate of a first electronic component, and a plurality of second electrode portions formed on the surface of a second electronic component and facing each of the first electrode portions. A semiconductor device in which the opposing surfaces of the first electrode portion and the second electrode portion that face each other are electrically connected via solder, and at least one of the first electrode portion and the second electrode portion that form a pair is a pillar electrode protruding from the surface of the electronic component. The gist is that the area of a first tip surface, which is the surface portion closest to the second electrode portion side among the opposing surfaces of the first electrode portion, and a second tip surface, which is the surface portion closest to the first electrode portion side among the opposing surfaces of the second electrode portion, in the first electrode portion and the second electrode portion that form a pair, are different.

EFFECTS OF THE INVENTION

[0011] According to an aspect of the present invention, it is possible to provide a semiconductor device in which the connection reliability of each electrode is improved even when there is a variation in the gap between opposing electrodes and the distance between the arranged electrodes is narrow. That is, even if there is a variation in the gap between opposing electrodes due to warping of the substrate or the like as described above, according to an aspect of the present invention, soldering can be performed more reliably without extremely reducing the amount of solder interposed between each pair of opposing electrodes. Even when the distance between the arranged electrodes is narrow, a predetermined or higher reliability can be ensured for the connection of the opposing electrodes.

[0012] As a result, for example, all the solder interposed between the opposing electrodes does not alloy, preventing a decrease in mechanical performance, preventing the occurrence of cold joints, and enabling reliable mounting.

Brief Description of the Drawings

[0013]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7A

Figure 7B

Figure 8

Embodiments for Carrying Out the Invention

[0014] Next, embodiments of the present invention will be described with reference to the drawings. (Configuration) As shown in FIG. 1, the semiconductor device of the present embodiment is an example of a semiconductor package substrate 100 on which a semiconductor element 1, which is a second electronic component, is mounted on a connection surface (electrode formation surface) of a wiring substrate 2, which is a first electronic component. The wiring substrate is, for example, an interposer substrate. The semiconductor element 1 is, for example, a semiconductor integrated circuit.

[0015] On the opposing connection surfaces of the semiconductor element and the wiring substrate 2, a plurality of electrodes are arranged in a grid pattern, and in order to increase the number of electrodes, the interval between adjacent electrodes is narrowed. That is, a plurality of first electrode portions are formed in a grid pattern on the connection surface of the substrate surface of the wiring substrate 2. Further, a plurality of second electrode portions are arranged in a grid pattern at positions on the connection surface of the semiconductor element 1 that can face each first electrode portion.

[0016] FIG. 2 is an enlarged view illustrating a connection structure between a pair of opposing electrodes 14 and 24 in the substrate connection portion of the semiconductor element 1 and the wiring substrate 2 in FIG. 1. In FIG. 2, insulation layers, wiring layers, etc. other than the portions related to mounting in the semiconductor element 1 and the wiring substrate 2 are not shown.

[0017] The connection surfaces formed on the surfaces of the semiconductor element 1 and the wiring substrate 2 are composed of wiring layers 11 and 21 as shown in the enlarged view of FIG. 2, and insulation layers 12 and 22 are formed on the wiring layers 11 and 21. Note that the insulation layers 12 and 22 are composed of a material that repels solder 5. Then, the positions for providing electrodes in the insulation layers 12 and 22 are respectively opened to expose the wiring layers 11 and 21, and the exposed portions become the electrodes 13 and 23.

[0018] In this embodiment, pillar electrodes 14 and 24 are respectively formed on the exposed electrodes 13 and 23 of the semiconductor element 1 and the wiring substrate 2. That is, both the first electrode portion and the second electrode portion have pillar electrodes. That is, each of the pillar electrodes 14 and 24 is formed so as to protrude from the surface (electrodes 13 and 23) of the exposed wiring layers 11 and 21 toward the counterpart member. In this embodiment, the cross-sectional shape of the pillar electrodes 14 and 24 is a circular shape. However, in the present invention, the cross-sectional shape of the pillar electrodes 14 and 24 does not have to be a circular shape, as long as it protrudes. Note that the maximum diameter of each of the pillar electrodes 14 and 24 is less than, for example, 100 μm.

[0019] In this embodiment, both the pillar electrode 24 on the wiring substrate 2 side and the pillar electrode 14 on the semiconductor element 1 side are composed of a column shape, but the cross-sectional area S2 of the pillar electrode 24 on the wiring substrate 2 side is different from the cross-sectional area S1 of the pillar electrode 14 on the semiconductor element 1 side. That is, in this embodiment, the area S2 (S21) of the opposing surface constituting the tip surface 24a of the pillar electrode 24 on the wiring substrate 2 side is different from the area S1 (S11) of the opposing surface constituting the tip surface 14a of the pillar electrode 14 on the semiconductor element 1 side. In this example, the opposing surface itself of the pillar electrode 24 on the wiring substrate 2 side constitutes the first tip surface 24a. Also, the opposing surface itself of the pillar electrode 14 on the semiconductor element 1 side constitutes the second tip surface 14a. The tip surfaces 14a and 24a refer to the surface portions of the opposing surfaces that are closest to the counterpart member. When the opposing surfaces of the pair of electrodes are brought into contact, the contact surface portion and the planar portion continuous with the contact surface portion constitute the tip surfaces 14a and 24a.

[0020] Also, the pillar electrode 24 on the wiring substrate 2 side constitutes the first electrode portion. The pillar electrode 14 on the semiconductor element 1 side constitutes the second electrode portion. Then, the pillar electrode 24 on the wiring board 2 side and the pillar electrode 14 on the semiconductor element 1 side are coaxially arranged, such that the opposing surfaces of the pillar electrode 24 on the wiring board 2 side and the pillar electrode 14 on the semiconductor element 1 side face each other, and solder 5 is interposed between the opposing surfaces. That is, the pillar electrode 24 on the wiring board 2 side and the pillar electrode 14 on the semiconductor element 1 side are electrically connected via the solder 5.

[0021] The solder 5 is placed on one or both of the electrodes, and the solder 5 interposed therebetween is heated while the opposing tip surfaces 14a, 24a of the paired electrodes are brought into contact. As a result, the solder 5 melts and integrates, thereby electrically connecting the opposing electrodes 14 and 24. At this time, by bringing the opposing tip surfaces 14a, 24a of the paired electrodes into contact, the solder 5 at the contact position bulges out laterally, but the bulging solder 5 moves to the outer peripheral position of the portion where the tip surface 14a (opposing surface) of the pillar electrode 14 with the smaller tip surface 14a (opposing surface) faces the opposing surface of the pillar electrode 24 with the larger opposing surface 24a, forming a solder pool. Specifically, the solder pool lies on the outer peripheral position of the opposing surface of the pillar electrode 24 and is formed between the outer peripheral position thereon and the outer peripheral position (in this example, the side surface of the pillar electrode 14) of the tip surface 14a of the pillar electrode 14. In this example, the pillar electrode 24 becomes the large surface electrode portion and the pillar electrode 14 becomes the small surface electrode portion.

[0022] Here, the wiring layers 11, 21 and the pillar electrodes 14, 24 may be formed, for example, by electrolytic copper plating made of copper or a copper alloy. Further, the solder 5 is a conductive substance and may be composed of a material having a melting point lower than that of the wiring layers 11, 21 and the pillar electrodes 14, 24, for example, a metal or alloy containing at least tin.

[0023] (Operation and Others) FIG. 8 is a diagram showing a mounting example using a conventional solder 5. Fig. 8(a) shows an example in which the exposed electrodes 13 and 23 of the semiconductor element 1 and the wiring board 2 adopting the BGA method are connected only by the solder 5. In this example, as can be seen from Fig. 8(a), among the solder 5 interposed between the opposing electrodes 13 and 23, the excess solder 5 significantly spreads horizontally more than the diameter of the electrodes 13 and 23. For this reason, it is difficult to narrow the interval between the electrodes arranged in a plane.

[0024] On the other hand, Fig. 8(b) is a conventional example in the case where pillar electrodes 14 and 24 are provided on the exposed electrodes 13 and 23, respectively. In the joining example shown in Fig. 8(b), compared with Fig. 8(a), the amount of solder used can be reduced, so that the interval between the electrodes to be arranged can be narrowed accordingly.

[0025] However, in the joining method shown in Fig. 8(b), since the amount of solder is small, all the tin constituting the solder 5 is alloyed and the mechanical properties are deteriorated, or since the amount of solder 5 is small, there is a possibility that the electrodes cannot be sufficiently approached and connected due to the warpage of the components (cold joint). Further, in order to cope with the variation in the gap between the opposing electrodes 14 and 24 due to the warpage of electronic components such as the substrate, if the amount of solder attached to the tip portions of the electrodes 14 and 24 is increased, in the portion where the gap between the opposing electrodes 14 and 24 is narrow, the amount of the solder 5 protruding in the lateral direction increases, and accordingly, the interval between the electrodes to be arranged cannot be narrowed. That is, since the opposing surfaces of the paired pillar electrodes 14 and 24 are the same size, when the opposing surfaces of the paired pillar electrodes 14 and 24 come into contact, the solder 5 interposed therebetween protrudes outside the opposing surfaces of the pillar electrodes 14 and 24. Further, when the central axes of some of the paired pillar electrodes 14 and 24 are eccentric due to the warpage of the substrate or the like, the joining area of the electrodes changes and becomes small.

[0026] On the contrary, in the present embodiment, as shown in Fig. 2, the opposing electrodes are constituted by paired pillar electrodes 14 and 24, and the areas S1, S2 (S11, S21) of the opposing surfaces (tip surfaces 14a, 24a) formed at the tip portions of the pillar electrodes 14 and 24 are configured to be different.

[0027] Therefore, in this embodiment, when solder 5 is attached to the tip surfaces 24a (synonymous with the opposing surfaces in this example) of the respective pillar electrodes 14 and 24, and the paired pillar electrodes 14 and 24 are connected via the solder 5, the opposing surface 14a of the pillar electrode 14 with a small cross-sectional area and the central portion of the opposing surface 24a of the pillar electrode 24 opposing the opposing surface 14a come into contact (connected in a state where the gap between the electrodes 14 and 24 is minimized). At the same time, the solder 5 protruding from the contacted gap contacts the side surface of the pillar electrode 14 with a small cross-sectional area at the surface position on the outer peripheral side of the opposing surface 24a of the pillar electrode 24 with a large cross-sectional area, and the pillar electrode 14 is covered with solder. That is, a solder pool is formed around the pillar electrode 14 with a small cross-sectional area, which is the surface position on the outer peripheral side of the opposing surface 24a of the pillar electrode 24 with a large cross-sectional area, and the solder 5 can be suppressed from spreading laterally outward beyond the pillar electrode 24 with a large cross-section.

[0028] That is, in order to cope with variations in the gap between the opposing electrodes 14 and 24 due to warping of electronic components such as substrates, even if the amount of solder attached to the tip portions of the electrodes is increased, the solder 5 can be suppressed from spreading outward (laterally) from the pillar electrode 24 at narrow portions of the gap between the opposing electrodes 14 and 24. As a result, solder mounting can be performed more reliably without extremely reducing the amount of solder interposed between each pair of opposing electrodes 14 and 24, and even when the interval between the electrodes to be arranged is narrow, a predetermined or higher reliability can be ensured for the connection of the opposing electrodes. In the case of this embodiment, the side surface portion of the pillar electrode 14 with a small cross-sectional area also serves as a connection portion of the electrodes. From this perspective, it is preferable to set the height of the pillar electrode 14 side with a relatively small cross-sectional area higher than the height of the other pillar electrode 24.

[0029] Also, even if the central axis between the opposing electrodes 14 and 24 is eccentric due to warping of components or the like, the entire opposing surface 14a of the pillar electrode 14 with a small cross-sectional area can be surely accommodated within the opposing surface 24a of the pillar electrode 24. That is, changes in the bonding area are suppressed, and the connection reliability of the electrodes can be ensured from this point as well.

[0030] Here, the relationship between the area S1 of the opposing surface 14a of the pillar electrode 14 with a smaller cross-sectional area relative to the area S2 of the opposing surface 24a of the pillar electrode 24 may be set based on the amount of solder to be interposed and the volume of the solder pool formed on the outer peripheral surface of the opposing surface of the pillar electrode 24 around the outer periphery of the pillar electrode 14 with a smaller cross-sectional area.

[0031] For example, the relationship between the area S11 of the opposing surface of the pillar electrode 14 with a smaller cross-sectional area relative to the area S21 of the opposing surface of the pillar electrode 24 is as follows. That is, the area S11 is at least less than the area S21, preferably 0.75 times or less of the area S21, and more preferably 0.5 times or less.

[0032] (Modification example) Next, another modification example in which the area S21 of the first tip surface 24a and the area S11 of the second tip surface 14a of the opposing electrodes are made different will be described.

[0033] (1) The first modification example is shown in FIG. 3. Regarding the paired and opposing pillar electrodes 14 and 24, the shapes of the respective opposing surfaces (14a, 14b) (24a, 24b) are changed so that the areas S11 and S21 of the first tip surface 24a and the second tip surface 14a are different. In the example of FIG. 3, regarding the opposing pillar electrodes 14 and 24, the cross-sections on the wiring layer 11, 21 sides have the same shape and areas S1 and S2, and the outer peripheral edges 14b and 24b of the opposing surfaces of the respective pillar electrodes 14 and 24 are chamfered. In this case, by changing the radius of the chamfer, the areas S11 and S21 of the first tip surface 24a and the second tip surface 14a are made different.

[0034] In this case, the opposing surface of the pillar electrode 14 is composed of the second tip surface 14a and the rounded portion 14b on its outer periphery. The opposing surface of the pillar electrode 24 is composed of the first tip surface 24a and the rounded portion 24b on its outer periphery. Then, by forming the area of the rounded portion 14b to be larger than that of the rounded portion 24b, the area S11 of the second tip surface 14a is made smaller than the area S21 of the first tip surface 24a.

[0035] Also in this example, when solder 5 is attached to the tip surfaces 14a and 24a of each of the pillar electrodes 14 and 24, respectively, and the paired pillar electrodes 14 and 24 are connected via the solder 5, the second tip surface 14a of the pillar electrode 14 with a small cross-sectional area and the central portion of the tip surface 24a of the pillar electrode 24 facing the tip surface 14a come into contact (connected in a state where the gap between the electrodes 14 and 24 is minimized), and the solder 5 protruding from the minimum gap accumulates in the space between the rounded portion 14b of the opposing surface of the pillar electrode 14 with a small cross-sectional area and the opposing surface of the pillar electrode 24, and the space forms a solder accumulation, thereby suppressing the solder 5 from spreading outward (laterally) of the pillar electrodes 14 and 24.

[0036] That is, in order to cope with the variation in the gap between the opposing electrodes 14 and 24 due to the warping of electronic components such as a substrate, even if the amount of solder attached to the tip portions of the electrodes is increased, the solder 5 can be suppressed from spreading outward (laterally) of the pillar electrodes 14 and 24 even at a location where the gap between the opposing electrodes 14 and 24 is narrow. As a result, solder mounting can be more reliably performed without extremely reducing the amount of solder interposed between each pair of opposing electrodes 14 and 24, and even when the interval between the arranged electrodes is narrow, a predetermined or higher reliability can be ensured for the connection of the opposing electrodes 14 and 24. In the case of this embodiment, the solder 5 also adheres to the rounded portion 14b constituting the opposing surface of the pillar electrode 14 with a small cross-sectional area and the rounded portion 24b constituting the opposing surface of the pillar electrode 24, and serves as the connection portion of the electrodes.

[0037] Further, even if the central axes between the opposing electrodes 14 and 24 are eccentric due to warping of components or the like, the entire tip surface 14a of the pillar electrode 14 with a small cross-sectional area can be accommodated within the tip surface 24a of the pillar electrode 24. As a result, the bonding area does not change, and the connection reliability of the electrodes can be ensured also from this point.

[0038] Here, the relationship between the area S11 of the tip surface 14a of the pillar electrode 14, which has a smaller cross-sectional area than the area S21 of the tip surface 24a of the pillar electrode 24, may be set based on the amount of solder to be interposed and the volume of the space for forming the solder pool.

[0039] For example, the relationship between the area S11 of the tip surface 14a of the pillar electrode 14, which has a smaller cross-sectional area than the area S21 of the tip surface 24a of the pillar electrode 24, is as follows. That is, the area S11 is at least less than the area S21, preferably 0.75 times or less of the area S21, and more preferably 0.5 times or less. In this embodiment, in order to increase the solder pool, a rounded portion 24b is also formed on the pillar electrode 24, which is a large surface electrode portion, but it is not necessary to form a rounded portion at the tip of the pillar electrode 24. Also, it may be set such that the cross-sectional area of the pillar electrode 24 on the wiring layer 21 side is larger than the cross-sectional area of the pillar electrode 14 on the wiring layer 21 side.

[0040] Here, as in the structure shown in FIG. 2, when the cross-section of the pillar electrode 14 becomes small, if there is instability in the strength of the pillar electrode 14 corresponding to the reduction in its cross-section, as shown in FIG. 3, by setting only the tip portion of the pillar electrode 14 to have a cross-section that becomes smaller toward the tip, there is an advantage that the strength of the entire pillar electrode 14 can be maintained while providing a solder pool.

[0041] (2) A second modification is shown in FIG. 4. In the second modification, the shape of the tip portion of the pillar electrode 14 is a frustum shape (a cross-sectional trapezoid shape), and the area S11 of the tip surface 14a of the pillar electrode 14 is configured to be smaller than the area S21 of the tip surface 24a of the pillar electrode 24. The operation and effect of the second modification are the same as those of the first modification. In the second modification, by increasing the height of the frustum shape formed at the tip portion, it becomes possible to increase the solder pool.

[0042] (3) A third modification is shown in FIG. 5. In the third modification, the tip of the pillar electrode 14 is a small-diameter column portion, increasing the solder accumulation, and has the same operational effects as the structures in FIGS. 2 and 4.

[0043] (4) Fig. 6 shows the fourth embodiment. In the fourth modification, based on the configuration of Fig. 2, the pillar electrode 14 is provided only on the semiconductor element 1 side, and on the wiring substrate 2 side, the electrode surface 23 is formed by the exposed portion of the wiring layer 21. In this case, the portion of the opposing surface of the electrode 23 on the wiring substrate 2 side is the exposed portion itself. Also, the opposing surface itself becomes the tip surface. In this example, the area S1 of the opposing surface (tip surface 14a) of the tip of the pillar electrode is set to be smaller than the area S2 of the electrode 23 on the wiring substrate 2 side.

[0044] The fourth modification has the same operational effects as the structure in Fig. 2. Note that as the pillar electrode 14, the configurations of the first to third modifications may be appropriately combined and adopted. Also, in the above description, the case where the area S21 of the tip surface 24a on the wiring substrate 2 side is larger than the area S11 of the tip surface 14a on the semiconductor element 1 side is illustrated, but the area S11 of the tip surface 14a on the semiconductor element 1 side may be larger. However, it is preferable that the area S21 of the tip surface 24a on the wiring substrate 2 side is large.

[0045] Also, for each pair of opposing electrodes, the electrode structure of the above structure may be individually adopted, but it is simpler in manufacturing to make all of them the same structure.

[0046] (Example of manufacturing method) Next, an example of the bonding structure between the electrodes 14 and 24 forming a pair described above will be explained. Here, an example on the wiring substrate 2 side is mainly shown, but the same process can be taken for the semiconductor element 1 side. Also, the manufacturing method is not limited to this example, and the manufacturing method can be freely selected as long as the same shape can be obtained. Also, although only one electrode is illustrated, the processing may be performed simultaneously on one or more electrodes.

[0047] FIG. 7A(a) shows a state where an insulating layer 22 is formed on the wiring layer 21 on the outermost surface of the wiring board 2. As for the manufacturing method up to this point, a known method may be adopted. On the insulating layer 22, a seed layer (not shown) for electrolytic plating in the next process is formed by electroless plating or sputtering, and then only the portion where the plating resist 6 is pasted and the pillar electrode 24 is formed is opened by photolithography to expose the electrode 23 portion.

[0048] Next, a copper pillar electrode 24 is formed in the portion without the plating resist 6 by electrolytic copper plating. At this time, by adjusting the additive in the electrolytic copper plating solution, it becomes possible to finish the electrode in a convex shape with a cross-sectional area that widens from the tip toward the substrate side (see FIG. 7A(b)). After the electrolytic plating process is completed, the plating resist 6 is peeled off, and the seed layer on the insulating layer 22 is removed by an etching process (see FIG. 7A(c)). Also, as shown in FIG. 7A(d), a pillar electrode 14 to be opposed is also formed on the semiconductor element 1 side.

[0049] Next, solder 5 is placed on the tip surfaces 14a and 24a of the pillar electrodes 14 and 24. As methods for placing the solder 5, there are methods such as printing paste, mounting spherical solder 5 on the pillar electrodes 14 and 24, and plating methods, but it is not limited to these. In any method, after mounting the solder 5, it can be heated to melt the solder 5 and connect it to the pillar electrodes 14 and 24 (see FIG. 7B(e)).

[0050] Next, the semiconductor element 1 provided with the pillar electrode 14 and the wiring board 2 are arranged so that the electrodes face each other, and are fixed so that the solders 5 on the tip surfaces 14a and 24a of the electrodes come into contact with each other (see FIG. 7B(f)).

[0051] Next, solder 5 is heated and melted to join pillar electrodes 14 and 24. At this time, the solder 5 can accumulate in the portion with a larger area of the pillar electrodes 14 and 24, and even if the amount of solder is large, it is possible to narrow the distance between the electrodes 14 and 24 without spreading laterally. Finally, by performing underfill 7 between the semiconductor element 1 and the wiring board 2, the board is completely fixed (see Fig. 7B(g)).

[0052] (Others) The present disclosure can also adopt the following configurations. (1) A semiconductor device including a plurality of first electrode portions formed on the surface of a substrate of a first electronic component and a plurality of second electrode portions formed on the surface of a second electronic component and facing each of the first electrode portions, wherein the opposing surfaces of the first electrode portions and the second electrode portions that face each other are electrically connected via solder 5, and at least one of the electrode portions of the pair of the first electrode portion and the second electrode portion is composed of pillar electrodes 14 and 24 protruding from the surface of the electronic component. Among the opposing surfaces of the pair of the first electrode portion and the second electrode portion, a first tip surface 24a, which is the surface portion closest to the second electrode portion side among the opposing surfaces of the first electrode portion, and a second tip surface 14a, which is the surface portion closest to the first electrode portion side among the opposing surfaces of the second electrode portion, have different areas. (2) When the electrode portion having a relatively larger area tip surface 14a, 24a among the first tip surface 24a and the second tip surface 14a is described as a large surface electrode portion, and the electrode portion having a smaller area tip surface 14a, 24a is described as a small surface electrode portion, a solder pool is formed at the outer peripheral position of the portion of the opposing surface of the large surface electrode portion that faces the tip surfaces 14a, 24a of the small surface electrode portion. (3) Both the pair of the first electrode portion and the second electrode portion have pillar electrodes 14 and 24. (4) Regarding the pair of the first electrode portion and the second electrode portion, one electrode portion has the pillar electrodes 14 and 24, and the other electrode portion does not have the pillar electrodes 14 and 24 formed, and the surface of the electronic component forms the opposing surface of the electrode. The area S21 of the tip surface 24a of the pillar electrodes 14 and 24 is smaller than the area of the opposing surface, which is the tip surfaces 14a, 24a of the other electrode portion. (5) Among the pillar electrodes 14 and 24, at least the pillar electrodes 14 and 24 that form the tip surface 14a or 24a with the smaller area among the first tip surface 24a and the second tip surface 14a have a continuously or stepwise decreasing cross-sectional area from the surface side of the electronic component toward the tip surface 24a side of the pillar electrodes 14 and 24. (6) The solder 5 is a conductive substance and is composed of a metal or alloy containing at least tin. The semiconductor device according to any one of claims 1 to 5 is characterized by this. (7) The electrode portion is made of electrolytic copper plating made of copper or a copper alloy. (8) The first electronic component is the wiring board 2, and the second electronic component is the semiconductor element 1.

Explanation of Reference Numerals

[0053] 1 Semiconductor element 2 Wiring board 5 Solder 11, 21 Wiring layer 12, 22 Insulating layer 13, 23 Electrodes formed on the connection surface 14, 24 Pillar electrodes 14a Second tip surface (opposing surface) 14b Rounded portion (outer peripheral edge) (opposing surface) 24a First tip surface (opposing surface) 24b Rounded portion (outer peripheral edge) (opposing surface) 55 Solder 100 Semiconductor package substrate

Claims

1. A semiconductor device comprising a plurality of first electrode portions formed on a substrate surface of a first electronic component and a plurality of second electrode portions formed on a surface of a second electronic component and facing each of the first electrode portions, wherein facing surfaces of the first electrode portions and the second electrode portions facing each other are electrically connected via solder, at least one of the first electrode portion and the second electrode portion forming a pair is a pillar electrode protruding from the surface of the electronic component, a first tip surface, which is a surface portion closest to the second electrode portion side among the facing surfaces of the first electrode portion, and a second tip surface, which is a surface portion closest to the first electrode portion side among the facing surfaces of the second electrode portion, in the first electrode portion and the second electrode portion forming a pair, have different areas, the facing surface of the pillar electrode is composed of the tip surface and a rounded portion on the outer periphery of the tip surface, characterized in that it is a semiconductor device.

2. When an electrode portion having a relatively larger area tip surface among the first tip surface and the second tip surface is described as a large surface electrode portion and an electrode portion having a relatively smaller area tip surface is described as a small surface electrode portion, a solder pool is formed at an outer peripheral position of a portion of the facing surface of the large surface electrode portion that faces the tip surface of the small surface electrode portion, characterized in that it is the semiconductor device according to claim 1.

3. both the first electrode portion and the second electrode portion forming a pair have pillar electrodes, characterized in that it is the semiconductor device according to claim 1 or claim 2.

4. Regarding the first electrode portion and the second electrode portion forming a pair, one electrode portion has the pillar electrode, and the other electrode portion forms a facing surface of the electrode with the surface of the electronic component without forming the pillar electrode, the area of the tip surface of the pillar electrode is smaller than the area of the facing surface that is the tip surface of the other electrode portion, characterized in that it is the semiconductor device according to claim 1 or claim 2.

5. Among the pillar electrodes, at least the pillar electrode forming the tip surface with a smaller area among the first tip surface and the second tip surface has a continuously or stepwise decreasing cross-sectional area from the surface side of the electronic component toward the tip surface side of the pillar electrode, characterized in that it is the semiconductor device according to claim 3 or claim 4.

6. the solder is a conductive substance and is composed of a metal or alloy containing at least tin, characterized in that it is the semiconductor device according to any one of claims 1 to 5.

7. The above electrode part is made of electrolytic copper plating made of copper or a copper alloy. The semiconductor device according to any one of claims 1 to 6, characterized in that.

8. The first electronic component is a wiring board, and the second electronic component is a semiconductor element. The semiconductor device according to any one of claims 1 to 7, characterized in that.

9. The paired first electrode part and second electrode part both have pillar electrodes. The opposing surface of the first electrode part is composed of the first tip surface and the rounded part on the outer periphery of the first tip surface. The opposing surface of the second electrode part is composed of the second tip surface and the rounded part on the outer periphery of the second tip surface. The semiconductor device according to any one of claims 1 to 8, characterized in that.

10. The area of the rounded part constituting the opposing surface of the second electrode part is larger than the area of the rounded part constituting the opposing surface of the first electrode part. The semiconductor device according to claim 9, characterized in that.

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