Semiconductor device, method of manufacturing semiconductor device, and electronic device

Abstract

To stably achieve a semiconductor device including a low-resistance semiconductor region connected to an electrode.SOLUTION: A semiconductor device 1 includes a semiconductor layer 10 including an active region AR1 and an inactive region AR2 adjacent to the active region, n-type semiconductor regions 21 and 22 provided in the active region AR1, and n-type semiconductor regions 61 and 62 provided in the inactive region AR2. A source electrode 40 and a drain electrode 50 are respectively connected to an n-type semiconductor region 21 and an n-type semiconductor region 22 of the active region AR1. Providing the n-type semiconductor regions 61 and 62 in the inactive region AR2 makes it possible to suppress speed-up of a growth rates of the n-type semiconductor regions 21 and 22 of the active region AR1 regrown together with them. This speed-up decreases an uptake quantity of dopant, thereby suppressing an increase in resistance. This stably achieves the semiconductor device 1 including sufficiently low-resistance n-type semiconductor regions 21 and 22 in the active region AR1.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present invention relates to a semiconductor device, a method of manufacturing a semiconductor device, and an electronic device.

Background Art

[0002] Regarding nitride semiconductor devices such as high electron mobility transistors (HEMTs), in order to obtain a low resistance value between a substrate and an electrode formed thereon, a main electrode region where the electrode is formed is formed as an additional active layer portion on the active layer main body portion of the substrate and protruded. A technique is known. Regarding this technique, an opening of a planned main electrode region formation region and a dummy opening are opened in a mask layer formed on the active layer main body portion, and a method of growing an additional active layer portion in the opening of the planned main electrode region formation region by utilizing the local loading effect has been proposed. In this method, it is said that film growth does not occur in the dummy opening due to the local loading effect.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Regarding a semiconductor device, as a method for reducing the resistance between a semiconductor layer in an active region where a transistor element is provided and an electrode that is ohmically connected to the semiconductor layer, there is a method of providing a semiconductor region doped with a dopant of a predetermined conductivity type between the semiconductor layer and the electrode to reduce the resistance. Such a semiconductor region is formed, for example, by providing a mask having an opening on the semiconductor layer and growing (regrowing) a semiconductor crystal in the opening using a Metal Organic Chemical Vapor Deposition (MOCVD) method. An electrode for ohmic connection is connected to the semiconductor region formed on the semiconductor layer.

[0005] In the formation of a semiconductor region using the MOCVD method, in addition to the semiconductor layer on the opening of the mask, atoms of the main raw material of the semiconductor region to be formed are also supplied onto the mask outside the opening. The atoms of the main raw material supplied onto the mask can diffuse on the mask. When the atoms of the main raw material diffusing on the mask move to the opening, they can be consumed in the growth of the semiconductor region on the semiconductor layer. When the atoms of the main raw material diffusing on the mask move to the opening and are consumed in the growth of the semiconductor region, the growth rate of the semiconductor region grown in the opening becomes faster compared to the case where the atoms of the main raw material diffusing on the mask do not move to the opening. When the growth rate of the semiconductor region becomes faster, the amount of dopant raw material atoms incorporated may decrease, and the resistance of the formed semiconductor region may increase. Thus, if the dopant amount varies due to the difference in the growth rate of the semiconductor region caused by the influence of the atoms of the main raw material diffusing on the mask, there is a risk that a semiconductor device in which the semiconductor region connected to the electrode is sufficiently low in resistance cannot be stably realized.

[0006] In one aspect, an object of the present invention is to stably realize a semiconductor device having a low-resistance semiconductor region connected to an electrode.

Means for Solving the Problem

[0007] In one aspect, including an electron supply layer and an electron transport layerA semiconductor layer, an active region provided in the semiconductor layer, an inactive region provided in the semiconductor layer and adjacent to the active region, and the semiconductor layer in the active region on the side of the electron supply layer provided on the first surface side n-type a first semiconductor region, provided on the first surface side of the semiconductor layer in the inactive region n-type, located away from the active region and provided at a position within 500 μm from the first semiconductor region a second semiconductor region, and a semiconductor device including a first electrode provided on the first surface side of the semiconductor layer and connected to the first semiconductor region is provided.

[0008] In another aspect, a method for manufacturing a semiconductor device as described above and an electronic device including the semiconductor device as described above are provided.

Advantages of the Invention

[0009] On one side, it becomes possible to stably realize a semiconductor device having a low-resistance semiconductor region connected to an electrode.

Brief Description of the Drawings

[0010]

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Embodiments for Carrying Out the Invention

[0011] As a technique for reducing the resistance between a semiconductor layer and an electrode to realize an ohmic connection, a so-called selective regrowth ohmic contact technique is known. In this technique, a low-resistance semiconductor region containing a dopant of a predetermined conductivity type is selectively grown (regrown) at a predetermined site of the semiconductor layer, and an electrode is connected on the semiconductor region to realize an ohmic connection between the electrode and the semiconductor layer. The semiconductor region provided between the semiconductor layer and the electrode is also referred to as a regrowth region, a regrowth layer, etc.

[0012] By the way, as one type of semiconductor device, those using nitride semiconductors are known. Semiconductor devices using nitride semiconductors utilize features such as high saturation electron velocity and wide bandgap, and are being developed as high-voltage-resistant and high-output devices. As semiconductor devices using nitride semiconductors, numerous reports have been made on field effect transistors (FETs), for example, HEMTs. As one type of HEMT, a HEMT using an AlGaN (aluminum gallium nitride) layer as an electron supply layer (also referred to as a "barrier layer") and a GaN (gallium nitride) layer as an electron traveling layer (also referred to as a "channel layer") is known. In such a HEMT, due to the spontaneous polarization of the AlGaN layer and the piezoelectric polarization generated in the AlGaN layer due to the strain caused by the lattice constant difference with the GaN layer, a high-concentration two-dimensional electron gas (2DEG) is generated in the GaN layer near the junction interface with the AlGaN layer, and a high-output device is realized. Therefore, HEMTs using GaN-based nitride semiconductors are expected to be applied to high-output amplifiers for communication and the like.

[0013] FIG. 1 is a diagram for explaining an example of a semiconductor device. FIG. 1(A) schematically shows a cross-sectional view of the main part of a first example of a semiconductor device. FIG. 1(B) schematically shows a cross-sectional view of the main part of a second example of a semiconductor device.

[0014] The semiconductor device 100A shown in FIG. 1(A) is an example of a HEMT. The semiconductor device 100A includes a semiconductor layer 110, and a gate electrode 120, a source electrode 130, and a drain electrode 140 provided thereon.

[0015] The semiconductor layer 110 includes an electron transport layer 111 and an electron supply layer 112. For example, GaN is used for the electron transport layer 111 and AlGaN is used for the electron supply layer 112. A 2DEG 1a is generated near the junction interface of the electron transport layer 111 with the electron supply layer 112. The 2DEG 1a is generated in an active region 160 defined by an inactive region 150 provided in the semiconductor layer 110. The inactive region 150 is a region formed as an element isolation region by ion implantation of Ar (argon) into the semiconductor layer 110 or the like. The active region 160 is a region formed as an element region defined by such an element isolation region.

[0016] The gate electrode 120 is provided on the electron supply layer 112 of the semiconductor layer 110 in the active region 160. The gate electrode 120 is provided on the electron supply layer 112 so as to function as a Schottky electrode. The source electrode 130 and the drain electrode 140 are provided on the electron supply layer 112 of the semiconductor layer 110 in the active region 160 so as to sandwich the gate electrode 120. The source electrode 130 and the drain electrode 140 are formed on the electron supply layer 112 so as to function as ohmic electrodes.

[0017] During the operation of the semiconductor device 100A, a predetermined voltage is supplied between the source electrode 130 and the drain electrode 140, and a predetermined gate voltage is supplied to the gate electrode 120. A channel for transporting carrier electrons is formed in the electron transport layer 111 between the source electrode 130 and the drain electrode 140, and the transistor function of the semiconductor device 100A is realized.

[0018] In the semiconductor device 100A, an electron supply layer 112 is interposed between a channel, i.e., a 2DEG 1a generated in an electron traveling layer 111 near the junction interface with the electron supply layer 112, and a source electrode 130 and a drain electrode 140 provided on the electron supply layer 112. In the semiconductor device 100A, the resistance R1 between the 2DEG 1a and the source electrode 130 and the drain electrode 140 becomes relatively high. Therefore, in the semiconductor device 100A, the on-resistance between the source electrode 130 and the drain electrode 140 of the transistor element included therein via the channel becomes relatively high. When the on-resistance increases, the large current flow between the source electrode 130 and the drain electrode 140 of the semiconductor device 100A is suppressed, and the high output of the semiconductor device 100A is suppressed.

[0019] Therefore, the above-described selective regrowth ohmic contact technology is adopted for the connection between the source electrode 130 and the drain electrode 140 and the semiconductor layer 110. The semiconductor device 100B shown in FIG. 1(B) is an example of a HEMT that employs the selective regrowth ohmic contact technology. The semiconductor device 100B has a configuration in which an n-type semiconductor region 181 and an n-type semiconductor region 182 (regrowth regions) are provided in recesses 171 and 172 provided in the semiconductor layer 110, and the source electrode 130 and the drain electrode 140 are connected thereto, respectively. The semiconductor device 100B is different from the above-described semiconductor device 100A in that it has such a configuration.

[0020] In the semiconductor device 100B, the recesses 171 and 172 are provided so as to penetrate the electron supply layer 112 and reach the electron traveling layer 111, and the bottom surfaces of the recesses 171 and 172 are deeper than the 2DEG 1a generated in the electron traveling layer 111. In such recesses 171 and 172, an n-type semiconductor region 181 and an n-type semiconductor region 182 are grown (regrown) and formed, respectively, using, for example, the MOCVD method. For example, n-type GaN is used for the n-type semiconductor region 181 and the n-type semiconductor region 182. The source electrode 130 and the drain electrode 140 are connected to the formed n-type semiconductor region 181 and n-type semiconductor region 182, respectively.

[0021] In the semiconductor device 100B, the 2DEG 1a of the channel generated in the electron traveling layer 111 is connected to the relatively low-resistance n-type semiconductor regions 181 and 182, and the resistance R2 between the 2DEG 1a and the n-type semiconductor regions 181 and 182 becomes relatively low. Then, the source electrode 130 and the drain electrode 140 are connected to the relatively low-resistance n-type semiconductor regions 181 and 182, respectively. As a result, the resistance between the 2DEG 1a and the source electrode 130 and the drain electrode 140 becomes relatively low. Therefore, in the semiconductor device 100B, the on-resistance between the source electrode 130 and the drain electrode 140 of the transistor element included therein becomes relatively low. By reducing the on-resistance, a large current can flow between the source electrode 130 and the drain electrode 140 of the semiconductor device 100B, and the semiconductor device 100B can be made to have a high output.

[0022] Here, an example of a method for forming a regrowth region such as the n-type semiconductor regions 181 and 182 will be described with reference to FIG. 2. FIG. 2 is a diagram for explaining an example of a method for forming a regrowth region. FIGS. 2(A) to 2(D) schematically show cross-sectional views of main parts of each step of forming the regrowth region.

[0023] First, as shown in FIG. 2(A), a semiconductor layer 110 in which an electron supply layer 112 is provided on an electron traveling layer 111 is prepared, and a mask 190 having an opening 190a is formed on the electron supply layer 112.

[0024] The semiconductor layer 110 is prepared, for example, by growing an electron supply layer 112 such as AlGaN on an electron traveling layer 111 such as GaN grown on a lower base substrate (not shown) using the MOCVD method. An inactive region 150 is formed in the semiconductor layer 110 by ion implantation of Ar or the like, and an active region 160 defined by the inactive region 150 is formed. The mask 190 is formed on such a semiconductor layer 110.

[0025] For the mask 190, an insulating film such as SiN (silicon nitride) is used. For example, using a plasma CVD method or the like, a mask 190 such as SiN is formed on the electron supply layer 112. An opening 190a is formed in the mask 190 corresponding to the site of the semiconductor layer 110 where the regrowth region is to be formed by photolithography technology and dry etching technology such as RIE (Reactive Ion Etching) using an F (fluorine)-based gas. The opening 190a is formed at the site of the semiconductor layer 110 in the active region 160.

[0026] Next, as shown in FIG. 2(B), the site of the semiconductor layer 110 exposed from the opening 190a of the mask 190 is removed by dry etching technology such as RIE using a Cl (chlorine)-based gas, and a recess 170 (corresponding to the recess 171 or recess 172 in FIG. 1(B) above) is formed. The recess 170 is formed, for example, to penetrate the electron supply layer 112 of the semiconductor layer 110 and reach the electron traveling layer 111, and the bottom surface of the recess 170 is formed at a position deeper than the 2DEG1a generated in the electron traveling layer 111.

[0027] Next, as shown in FIG. 2(C), an n-type semiconductor region 180 such as n-type GaN (corresponding to the n-type semiconductor region 181 or n-type semiconductor region 182 in FIG. 1(B) above) is regrown and formed as a regrowth region in the recess 170 formed in the semiconductor layer 110, for example, using the MOCVD method. For example, when regrowing n-type GaN as the n-type semiconductor region 180, in the MOCVD method, trimethylgallium (TMGa) and NH3 (ammonia) are used as main raw materials, and SiH4 (silane) and GeH4 (germanium) are used as n-type dopant raw materials.

[0028] Thereafter, as shown in FIG. 2(D), the mask 190 on the semiconductor layer 110 is removed by wet etching technology using HF (hydrogen fluoride) or the like. Thereby, a structure in which an n-type semiconductor region 180 is formed as a regrowth region in the recess 170 formed in the semiconductor layer 110 of the active region 160 is obtained.

[0029] However, when forming such a regrowth region, the growth rate of the n-type semiconductor region 180 may vary depending on the arrangement of the opening 190a of the mask 190 or the recess 170 formed therein. This will be described with reference to FIG. 3.

[0030] FIG. 3 is a diagram for explaining the difference in the growth rate of the regrowth region. FIG. 3 schematically shows a main part plan view of a semiconductor layer on which a mask is formed. For example, consider a case as shown in FIG. 3, that is, a case where the mask 190 formed on the semiconductor layer 110 includes a region 191 where the groups of openings 190a are relatively dense and a region 192 where they are relatively sparse. In the semiconductor layer 110 in the region 191 where the groups of openings 190a of the mask 190 are relatively dense, groups of recesses 170 are formed relatively densely. On the other hand, in the semiconductor layer 110 in the region 192 where the groups of openings 190a of the mask 190 are relatively sparse, groups of recesses 170 are formed relatively sparsely. For the semiconductor layer 110 on which the mask 190 including such regions 191 and 192 is formed and the recesses 170 are formed in the groups of its openings 190a, as described above, an n-type semiconductor region 180 such as n-type GaN is formed using the MOCVD method.

[0031] At this time, atoms 183 of the main raw material of the n-type semiconductor region 180, for example, Ga (gallium) atoms, are supplied not only on the semiconductor layer 110 of the opening 190a of the mask 190 but also on the mask 190 outside the opening 190a. The atoms 183 of the main raw material supplied on the mask 190 can diffuse on the mask 190. When the atoms 183 of the main raw material diffusing on the mask 190 move to the opening 190a, they can be consumed for the regrowth of the n-type semiconductor region 180 formed in the recess 170 of the semiconductor layer 110. When the atoms 183 of the main raw material diffusing on the mask 190 move to the opening 190a and are consumed for the regrowth of the n-type semiconductor region 180, the growth rate of the n-type semiconductor region 180 regrown in the opening 190a becomes faster than when the atoms 183 do not move to the opening 190a.

[0032] In region 192 where the group of openings 190a of mask 190 is relatively sparse, since mask 190 exists in a relatively large area around the group of openings 190a, the amount of atoms 183 of the main raw material diffusing on mask 190 and moving to the group of openings 190a tends to be relatively large. And in region 192 where the group of openings 190a is relatively sparse, since the number of the group of openings 190a per unit area is small, the amount of atoms 183 of the main raw material reaching each opening 190a also tends to be large. As a result, in region 192 where the group of openings 190a is relatively sparse, the growth rate of the n-type semiconductor region 180 regrown in the recess 170 is likely to be faster than that in region 191 where the group of openings 190a is relatively dense.

[0033] When the growth rate of the n-type semiconductor region 180 increases, the amount of incorporation of dopant raw material atoms, such as Si (silicon) atoms and Ge (germanium) atoms, decreases, and the resistance of the obtained n-type semiconductor region 180 tends to be high. That is, the n-type semiconductor region 180 regrown in region 192 where the group of openings 190a of mask 190 is relatively sparse is more likely to be regrown at a fast growth rate and is more likely to have a high resistance than the n-type semiconductor region 180 regrown in region 191 where the group of openings 190a is relatively dense.

[0034] In addition, when regrowing the n-type semiconductor region 180 using the MOCVD method, in addition to atoms 183 of the main raw material such as Ga atoms, atoms of dopant raw materials such as Si atoms and Ge atoms can also be supplied onto mask 190. However, the atoms of the dopant raw material have a shorter residence (adsorption) time and a shorter diffusion distance on mask 190 than the atoms 183 of the main raw material. Therefore, the probability that the atoms of the dopant raw material supplied onto mask 190 reach the opening 190a and are consumed in the regrowth there is relatively low. As a result, in the n-type semiconductor region 180 where the growth rate is increased by the movement of the atoms 183 of the main raw material supplied onto mask 190 and diffusing to the opening 190a, the amount of incorporation of the atoms of the dopant raw material decreases, and the resistance tends to be high.

[0035] FIG. 4 is a diagram showing an example of the relationship between the growth rate of the regrowth region and the on-resistance of the transistor element. In FIG. 4, the horizontal axis represents the growth rate [nm / min] of the n-type semiconductor region (regrowth region) provided in the active region and connected to the electrode (ohmic electrode) of the transistor element, and the vertical axis represents the on-resistance [Ω·mm] of the transistor element. As shown in FIG. 4, as the growth rate of the n-type semiconductor region increases, the on-resistance of the transistor element tends to increase.

[0036] As described above, when forming the regrowth region using the MOCVD method, due to the influence of the atoms of the main raw material diffusing on the mask, a difference may occur in the growth rate of the n-type semiconductor region formed as the regrowth region in the semiconductor layer at the opening of the mask. Note that such a difference in the growth rate of the n-type semiconductor region can occur not only between different n-type semiconductor regions formed in one semiconductor layer, but also between n-type semiconductor regions formed in different semiconductor layers respectively. When a difference occurs in the growth rate of the n-type semiconductor region, the amount of the n-type dopant incorporated fluctuates, and a difference occurs in the resistance of the formed n-type semiconductor region. As a result, it may occur that a semiconductor device having a sufficiently low-resistance n-type semiconductor region connected to an electrode such as a source electrode or a drain electrode cannot be stably realized.

[0037] In view of the above points, here, a method as shown in the following embodiments is used to suppress the occurrence of a difference in the growth rate of the semiconductor region regrown in the semiconductor layer for electrode connection, and stably realize a semiconductor device having a low-resistance semiconductor region connected to the electrode.

[0038] [First Embodiment] FIG. 5 is a diagram for explaining an example of a semiconductor device according to the first embodiment. FIG. 5 schematically shows a cross-sectional view of a main part of an example of a semiconductor device according to the first embodiment.

[0039] The semiconductor device 1 shown in FIG. 5 is an example of a HEMT. The semiconductor device 1 includes a semiconductor layer 10, an n-type semiconductor region 21 and an n-type semiconductor region 22 provided in its active region AR1, and a gate electrode 30, a source electrode 40, and a drain electrode 50. The semiconductor device 1 further includes an n-type semiconductor region 61 and an n-type semiconductor region 62 provided in the inactive region AR2 of the semiconductor layer 10.

[0040] The semiconductor layer 10 includes an electron traveling layer 11 and an electron supply layer 12. For example, GaN is used for the electron traveling layer 11, and AlGaN is used for the electron supply layer 12. A 2DEG1a is generated near the junction interface of the electron traveling layer 11 with the electron supply layer 12. The 2DEG1a is generated in the active region AR1 defined by the inactive region AR2 provided in the semiconductor layer 10. The inactive region AR2 is a region formed as an element isolation region by ion implantation of Ar into the semiconductor layer 10 or the like. The active region AR1 is a region formed as an element region defined by such an element isolation region.

[0041] The n-type semiconductor region 21 and the n-type semiconductor region 22 are respectively provided in recesses 71 and 72 provided on one surface (the surface on the electron supply layer 12 side) 10a of the semiconductor layer 10 in the active region AR1. The recesses 71 and 72 penetrate the electron supply layer 12 and reach the electron traveling layer 11, and are provided such that the bottom surfaces of the recesses 71 and 72 are at positions deeper than the 2DEG1a generated in the electron traveling layer 11. In such recesses 71 and 72, the n-type semiconductor region 21 and the n-type semiconductor region 22 are respectively regrown and formed using, for example, the MOCVD method. For the n-type semiconductor region 21 and the n-type semiconductor region 22, n-type GaN is used, for example. Note that the n-type semiconductor region 21 and the n-type semiconductor region 22 provided in the active region AR1 are also referred to as a regrown region, a regrown layer, or the like.

[0042] The gate electrode 30 is provided on the surface 10a side of the semiconductor layer 10 in the active region AR1. In the example of FIG. 5, the gate electrode 30 is provided on the surface 10a (electron supply layer 12) of the semiconductor layer 10. The gate electrode 30 is positioned between the n-type semiconductor regions 21 and 22 provided in the active region AR1 and is provided so as not to be connected to the n-type semiconductor regions 21 and 22 (and the source electrode 40 and drain electrode 50 provided thereon). Metals such as Ni (nickel) and Au (gold) are used for the gate electrode 30. The gate electrode 30 is provided so as to function as a Schottky electrode.

[0043] The source electrode 40 and the drain electrode 50 are provided on the surface 10a side of the semiconductor layer 10 so as to sandwich the gate electrode 30. The source electrode 40 is positioned on the n-type semiconductor region 21 provided in the recess 71 of the semiconductor layer 10 and is provided so as to be connected to the n-type semiconductor region 21. The drain electrode 50 is positioned on the n-type semiconductor region 22 provided in the recess 72 of the semiconductor layer 10 and is provided so as to be connected to the n-type semiconductor region 22. Metals such as Ti (titanium) and Al (aluminum) are used for the source electrode 40 and the drain electrode 50. The source electrode 40 and the drain electrode 50 are provided so as to function as ohmic electrodes.

[0044] During the operation of the semiconductor device 1, a predetermined voltage is supplied between the source electrode 40 and the drain electrode 50, and a predetermined gate voltage is supplied to the gate electrode 30. A channel for transporting carrier electrons is formed in the electron traveling layer 11 between the source electrode 40 and the drain electrode 50, and the transistor function of the semiconductor device 1 is realized.

[0045] In the semiconductor device 1, the 2DEG 1a of the channel generated in the electron traveling layer 11 is connected to the relatively low-resistance n-type semiconductor regions 21 and 22, and the resistance between the 2DEG 1a and the n-type semiconductor regions 21 and 22 is reduced. Then, a source electrode 40 and a drain electrode 50 are connected to the relatively low-resistance n-type semiconductor regions 21 and 22, respectively. As a result, the resistance between the 2DEG 1a and the source electrode 40 and the drain electrode 50 becomes relatively low. Therefore, in the semiconductor device 1, the on-resistance between the source electrode 40 and the drain electrode 50 of the element (transistor element) having the transistor function through the channel becomes relatively low. By reducing the on-resistance, a large current can flow between the source electrode 40 and the drain electrode 50 of the semiconductor device 1, and the semiconductor device 1 can be made to have a high output.

[0046] In the semiconductor device 1, an n-type semiconductor region 61 and an n-type semiconductor region 62 are provided in an inactive region AR2 that is adjacent to the active region AR1 where the transistor element is formed and that defines the active region AR1. For the n-type semiconductor region 61 and the n-type semiconductor region 62 provided in the inactive region AR2, for example, n-type GaN is used in the same manner as the n-type semiconductor regions 21 and 22 provided in the active region AR1. Note that the n-type semiconductor region 61 and the n-type semiconductor region 62 provided in the inactive region AR2 are also referred to as a dummy regrowth region, a dummy regrowth layer, or the like.

[0047] The n-type semiconductor regions 61 and 62 are respectively provided in the recesses 81 and 82 provided on the surface 10a side of the semiconductor layer 10 in the inactive region AR2. The recesses 81 and 82 are provided intermittently or continuously, for example, so as to surround the active region AR1. The recesses 81 and 82 are provided, for example, at the same or equivalent depth as the recesses 71 and 72 in which the n-type semiconductor regions 21 and 22 are respectively provided. In such recesses 81 and 82, the n-type semiconductor regions 61 and 62 are regrown and formed respectively, for example, using the MOCVD method. At this time, the n-type semiconductor regions 61 and 62 are formed simultaneously with the n-type semiconductor regions 21 and 22. As will be described later, with respect to the surface 10a of the semiconductor layer 10, the end faces 61a and 62a on the surface 10a side of the n-type semiconductor regions 61 and 62 are at a higher position than the end faces 21a and 22a on the surface 10a side of the n-type semiconductor regions 21 and 22.

[0048] The n-type semiconductor regions 61 and 62 provided in the inactive region AR2 are provided so as to be spaced apart from the active region AR1. That is, the n-type semiconductor regions 61 and 62 are provided so as not to contact the active region AR1 (and the n-type semiconductor regions 21 and 22 provided therein) in the semiconductor layer 10. The n-type semiconductor regions 61 and 62 (recesses 81 and 82) are preferably provided at a position where the distance D1 from the active region AR1 in the inactive region AR2 adjacent to the active region AR1 is 50 μm or more. This is because if the n-type semiconductor regions 61 and 62 are located in a range where the distance D1 from the active region AR1 is less than 50 μm, there is a risk as follows. That is, due to the electrical action (capacitance coupling, etc.) between the n-type semiconductor regions 61 and 62 and the n-type semiconductor regions 21 and 22 and 2DEG1a in the active region AR1 in the semiconductor layer 10, the operation of the transistor element may be affected. However, as will be described later, the n-type semiconductor regions 61 and 62 are preferably provided at a position where the distance from the n-type semiconductor regions 21 and 22 (recesses 71 and 72) provided in the active region AR1, that is, the distance D1 from the active region AR1 in the example of FIG. 5, is within 500 μm.

[0049] When regrowing the n-type semiconductor regions 21 and 22 and the n-type semiconductor regions 61 and 62 of the semiconductor device 1 having the above configuration by using the MOCVD method, a mask having an opening group is formed on the surface 10a of the semiconductor layer 10 at the site where they are regrown. Recesses 71 and 72 and recesses 81 and 82 are formed in the opening group of this mask, and the n-type semiconductor regions 21 and 22 and the n-type semiconductor regions 61 and 62 are regrown therein, respectively. Atoms of the main raw material (such as Ga atoms) of the n-type semiconductor regions 21 and 22 and the n-type semiconductor regions 61 and 62 are supplied not only to the recesses 71 and 72 and the recesses 81 and 82 but also onto the mask. The atoms of the main raw material supplied onto the mask can diffuse on the mask.

[0050] Furthermore, since the atoms of the dopant raw material stay on the mask for a shorter time and have a shorter diffusion distance than the atoms of the main raw material, diffusion on the mask like that of the atoms of the main raw material does not occur. The atoms of the main raw material diffusing on the mask corresponding to the inactive region AR2 move to the group of openings in the mask corresponding to the recesses 81 and 82 provided in the inactive region AR2, and are likely to be consumed for the regrowth of the n-type semiconductor regions 61 and 62. As a result, the atoms of the main raw material diffusing on the mask corresponding to the inactive region AR2 are suppressed from moving to the group of openings in the mask corresponding to the recesses 71 and 72 provided in the active region AR1, and are suppressed from being consumed for the regrowth of the n-type semiconductor regions 21 and 22. Therefore, the growth rates of the n-type semiconductor regions 21 and 22 provided in the active region AR1 are suppressed from increasing rapidly due to the influence of the atoms of the main raw material diffusing on the mask corresponding to the inactive region AR2, and are stabilized.

[0051] In order to make the atoms of the main raw material diffusing on the mask corresponding to the inactive region AR2 likely to be consumed for the regrowth of the n-type semiconductor regions 61 and 62 and difficult to be consumed for the regrowth of the n-type semiconductor regions 21 and 22, the arrangement of the group of openings in the mask is adjusted. Thereby, the arrangement of the recesses 71 and 72 and the recesses 81 and 82 formed in the semiconductor layer 10 is adjusted. The recesses 81 and 82 (n-type semiconductor regions 61 and 62) are preferably provided at positions where the distance from the recesses 71 and 72 (n-type semiconductor regions 21 and 22) is within 500 μm. This is because when the distance between the recesses 81 and 82 and the recesses 71 and 72 exceeds 500 μm, the following is likely to occur. That is, the atoms of the main raw material diffusing on the mask corresponding to the inactive region AR2 move to the group of openings in the mask corresponding to the recesses 71 and 72, and are consumed for the regrowth of the n-type semiconductor regions 21 and 22, and their growth rates are likely to increase.

[0052] Furthermore, the atoms of the main raw material diffusing over the mask corresponding to the inactive region AR2 are more likely to be consumed for the regrowth of the n-type semiconductor regions 61 and 62, and less likely to be consumed for the regrowth of the n-type semiconductor regions 21 and 22. Therefore, the growth rates of the n-type semiconductor regions 61 and 62 provided in the inactive region AR2 become relatively faster than the growth rates of the n-type semiconductor regions 21 and 22 provided in the active region AR1. As a result, with respect to the surface 10a of the semiconductor layer 10, the end faces 61a and 62a on the surface 10a side of the n-type semiconductor regions 61 and 62 are at higher positions than the end faces 21a and 22a on the surface 10a side of the n-type semiconductor regions 21 and 22.

[0053] As described above, the growth rates of the n-type semiconductor regions 21 and 22 provided in the active region AR1 are suppressed from increasing and are stabilized. As a result, the amount of dopant incorporated into the n-type semiconductor regions 21 and 22 is suppressed from decreasing, and the resistance thereof is suppressed from increasing. Thereby, the semiconductor device 1 having the n-type semiconductor regions 21 and 22 with sufficiently low resistance connected to the source electrode 40 and the drain electrode 50 is stably realized.

[0054] Furthermore, the n-type semiconductor regions 61 and 62 in the inactive region AR2, which have a faster growth rate than the n-type semiconductor regions 21 and 22 provided in the active region AR1, have a smaller amount of dopant incorporated than the n-type semiconductor regions 21 and 22.

[0055] As described above, the method of providing an n-type semiconductor region (dummy regrowth region) in the inactive region and suppressing the growth rate of the n-type semiconductor region (regrowth region) provided in the active region is effective when the arrangement of the n-type semiconductor regions provided in the active region is sparse (when the growth rate tends to be high). However, this method is equally applicable even when the arrangement of the n-type semiconductor regions provided in the active region is dense. By providing an n-type semiconductor region in the inactive region, it becomes possible to suppress and stabilize the growth rate of the n-type semiconductor region provided in the active region not only when the arrangement of the n-type semiconductor regions provided in the active region is sparse but also when it is dense.

[0056] Also, by providing an n-type semiconductor region (dummy regrowth region) in the inactive region, it becomes possible to stabilize the growth rates of the plurality of n-type semiconductor regions (regrowth regions) provided in the active region and suppress the difference in growth rates that occurs between different n-type semiconductor regions provided in the active region. Furthermore, it becomes possible to suppress the difference in growth rates that occurs not only between n-type semiconductor regions provided in the active region of one semiconductor layer but also between n-type semiconductor regions provided in the active regions of different semiconductor layers.

[0057] [Second Embodiment] FIGS. 6 and 7 are diagrams for explaining an example of a semiconductor device according to the second embodiment. FIG. 6 schematically shows a plan view of a main part of the semiconductor device according to the second embodiment. FIG. 7 schematically shows a cross-sectional view of a main part of the semiconductor device according to the second embodiment. FIG. 7 is a schematic cross-sectional view taken along line VII-VII of FIG. 6.

[0058] The semiconductor device 1A shown in FIGS. 6 and 7 is an example of a HEMT. As shown in FIGS. 6 and 7, the semiconductor device 1A includes a semiconductor layer 10A, n-type semiconductor regions 21 and 22 (regrowth regions) provided in its active region AR1, and a gate electrode 30, a source electrode 40, and a drain electrode 50. The semiconductor device 1A further includes n-type semiconductor regions 61 and 62 (dummy regrowth regions) provided in the inactive region AR2 of the semiconductor layer 10A.

[0059] As shown in FIG. 7, the semiconductor layer 10A of the semiconductor device 1A includes a substrate 13, an initial layer 14, an electron traveling layer 11, a spacer layer 15, and an electron supply layer 12. Here, as the substrate 13, substrates such as SiC (silicon carbide), Si, sapphire, GaN, AlN (aluminum nitride), and diamond are used. The substrate 13 may have a single-layer structure of one type of substrate or a laminated structure of two or more types of substrates.

[0060] The initial layer 14 is provided on one surface 13a of the substrate 13. As the initial layer 14, nitride semiconductors such as AlN, GaN, and AlGaN are used. The initial layer 14 may have a single-layer structure of one type of nitride semiconductor or a laminated structure of two or more types of nitride semiconductors.

[0061] The electron traveling layer 11 is provided on a surface 14a of the initial layer 14, which is opposite to the substrate 13 side. As the electron traveling layer 11, nitride semiconductors such as GaN and AlGaN are used. The electron traveling layer 11 may have a single-layer structure of one type of nitride semiconductor or a laminated structure of two or more types of nitride semiconductors. For example, i-type GaN is used for the electron traveling layer 11.

[0062] The spacer layer 15 is provided on a surface 11a of the electron traveling layer 11, which is opposite to the initial layer 14 side. As the spacer layer 15, nitride semiconductors such as AlN and AlGaN are used. The spacer layer 15 may have a single-layer structure of one type of nitride semiconductor or a laminated structure of two or more types of nitride semiconductors.

[0063] The electron supply layer 12 is provided on a surface 15a of the spacer layer 15, which is opposite to the electron traveling layer 11 side. As the electron supply layer 12, nitride semiconductors such as AlGaN, InAlN (indium aluminum nitride), InAlGaN (indium aluminum gallium nitride), AlN, and ScAlN (scandium aluminum nitride) are used. The electron supply layer 12 may have a single-layer structure of one type of nitride semiconductor or a laminated structure of two or more types of nitride semiconductors.

[0064] In the semiconductor device 1A, a 2DEG 1a is generated near the bonding interface of the electron traveling layer 11 with the spacer layer 15. The 2DEG 1a is generated in the active region AR1 defined by the inactive region AR2 provided in the semiconductor layer 10A. The inactive region AR2 is a region formed as an element isolation region by ion implantation of Ar into the semiconductor layer 10A or the like. The active region AR1 is a region formed as an element region defined by such an element isolation region. The inactive region AR2 is provided adjacent to the active region AR1 so as to surround the active region AR1. A transistor element having a transistor function is formed in the active region AR1 where the 2DEG 1a is generated.

[0065] The semiconductor layer 10A is formed, for example, by growing an initial layer 14 on the surface 13a of the substrate 13 using the MOCVD method, growing an electron traveling layer 11 on the surface 14a, growing a spacer layer 15 on the surface 11a, and growing an electron supply layer 12 on the surface 15a.

[0066] Although not shown here, the semiconductor layer 10A may further include other layers such as a cap layer using a nitride semiconductor such as GaN provided on the surface 12a of the electron supply layer 12 on the side opposite to the spacer layer 15 side.

[0067] An n-type semiconductor region 21 and an n-type semiconductor region 22 are provided on the surface 10a of the semiconductor layer 10A (the surface 12a of the electron supply layer 12 in this example) side in the active region AR1. The n-type semiconductor region 21 and the n-type semiconductor region 22 are respectively provided in the recesses 71 and 72 provided on the surface 10a side of the semiconductor layer 10A in the active region AR1. The recesses 71 and 72 penetrate through the electron supply layer 12 and the spacer layer 15 and reach the electron traveling layer 11, for example, as shown in FIG. 7, and are provided so that the bottom surfaces of the recesses 71 and 72 are at positions deeper than the 2DEG 1a generated in the electron traveling layer 11. In such recesses 71 and 72, an n-type semiconductor region 21 and an n-type semiconductor region 22 are regrown and formed respectively using, for example, the MOCVD method. For the n-type semiconductor region 21 and the n-type semiconductor region 22, n-type GaN is used, for example.

[0068] The gate electrode 30 is provided on the surface 10a side of the semiconductor layer 10A. In the examples of FIGS. 6 and 7, the gate electrode 30 is provided on the surface 10a (electron supply layer 12) of the semiconductor layer 10A in the active region AR1 and the inactive region AR2. A part of the gate electrode 30 is located between the n-type semiconductor region 21 and the n-type semiconductor region 22 provided in the active region AR1, and is provided so as not to be connected to the n-type semiconductor region 21 and the n-type semiconductor region 22 (and the source electrode 40 and the drain electrode 50 provided thereon). A metal such as Ni or Au is used for the gate electrode 30. The gate electrode 30 is provided so as to function as a Schottky electrode. Note that a gate insulating film (not shown) using an oxide, a nitride, an oxynitride, or the like may be interposed between the gate electrode 30 and the surface 10a of the semiconductor layer 10A.

[0069] The source electrode 40 and the drain electrode 50 are provided on the surface 10a side of the semiconductor layer 10A so as to sandwich the gate electrode 30. A part of the source electrode 40 is located on the n-type semiconductor region 21 provided in the recess 71 of the semiconductor layer 10A, and is provided so as to be connected to the n-type semiconductor region 21. A part of the drain electrode 50 is located on the n-type semiconductor region 22 provided in the recess 72 of the semiconductor layer 10A, and is provided so as to be connected to the n-type semiconductor region 22. A metal such as Ti or Al is used for the source electrode 40 and the drain electrode 50. The source electrode 40 and the drain electrode 50 are provided so as to function as ohmic electrodes.

[0070] During the operation of the semiconductor device 1A, a predetermined voltage is supplied between the source electrode 40 and the drain electrode 50, and a predetermined gate voltage is supplied to the gate electrode 30. A channel for transporting electrons of carriers is formed in the electron traveling layer 11 between the source electrode 40 and the drain electrode 50, and the transistor function of the semiconductor device 1A is realized.

[0071] In the semiconductor device 1A, the 2DEG 1a of the channel generated in the electron traveling layer 11 is connected to the relatively low-resistance n-type semiconductor regions 21 and 22, and the resistance between the 2DEG 1a and the n-type semiconductor regions 21 and 22 is reduced. As a result, in the semiconductor device 1A, the resistance between the 2DEG 1a and the source electrode 40 and the drain electrode 50 connected via the n-type semiconductor regions 21 and 22 is reduced, and the on-resistance of the transistor element is reduced. In the semiconductor device 1A, the n-type semiconductor regions 21 and 22 are provided so as to penetrate the electron supply layer 12 and further penetrate the spacer layer 15 and be connected to the 2DEG 1a of the electron traveling layer 11. Even if the spacer layer 15 is further interposed between the 2DEG 1a and the surface 10a of the semiconductor layer 10A in addition to the electron supply layer 12, the resistance between the 2DEG 1a and the source electrode 40 and the drain electrode 50 is effectively reduced by the n-type semiconductor regions 21 and 22.

[0072] In the semiconductor device 1, n-type semiconductor regions 61 and 62 are provided in an inactive region AR2 that is adjacent to the active region AR1 where the transistor element is formed and that defines the active region AR1. For the n-type semiconductor regions 61 and 62 provided in the inactive region AR2, for example, n-type GaN is used in the same manner as the n-type semiconductor regions 21 and 22 provided in the active region AR1.

[0073] The n-type semiconductor regions 61 and 62 are respectively provided in recesses 81 and 82 provided on the surface 10a side of the semiconductor layer 10A in the inactive region AR2. The recesses 81 and 82 are provided, for example, so as to surround the active region AR1. In the examples of FIGS. 6 and 7, U-shaped recesses 81 and 82 are provided on both sides of the inactive region AR2 sandwiching the active region AR1 in plan view. The recesses 81 and 82 are provided, for example, at the same or equivalent depth as the recesses 71 and 72 in which the n-type semiconductor regions 21 and 22 are respectively provided, as shown in FIG. 7.

[0074] For such recesses 81 and 82, an n-type semiconductor region 61 and an n-type semiconductor region 62 are regrown and formed respectively, for example, using the MOCVD method. At this time, the n-type semiconductor region 61 and the n-type semiconductor region 62 are formed simultaneously with the n-type semiconductor region 21 and the n-type semiconductor region 22. With respect to the surface 10a of the semiconductor layer 10A, the end faces 61a and 62a on the surface 10a side of the n-type semiconductor region 61 and the n-type semiconductor region 62 are at a higher position than the end faces 21a and 22a on the surface 10a side of the n-type semiconductor region 21 and the n-type semiconductor region 22.

[0075] The n-type semiconductor region 61 and the n-type semiconductor region 62 provided in the inactive region AR2 are provided so as to be spaced apart from the active region AR1. The n-type semiconductor region 61 and the n-type semiconductor region 62 (recesses 81 and 82) are preferably provided at a position more than 50 μm away from the active region AR1 in the inactive region AR2 adjacent to the active region AR1. This is to suppress the electrical action (such as capacitive coupling) between the n-type semiconductor region 61 and the n-type semiconductor region 62 and the n-type semiconductor region 21, the n-type semiconductor region 22, and 2DEG1a in the active region AR1 in the semiconductor layer 10A, and to suppress the influence on the operation of the transistor element due to the electrical action. However, as will be described later, the n-type semiconductor region 61 and the n-type semiconductor region 62 (recesses 81 and 82) are preferably provided at a position within 500 μm from the n-type semiconductor region 21 and the n-type semiconductor region 22 (recesses 71 and 72) provided in the active region AR1.

[0076] In addition, the n-type semiconductor region 61 and the n-type semiconductor region 62 are provided in the inactive region AR2 so as not to contact the gate electrode 30. Thereby, the influence on the gate electrode 30 of the n-type semiconductor region 61 and the n-type semiconductor region 62 is suppressed, and the influence on the operation of the transistor element due to the influence on the gate electrode 30 is suppressed.

[0077] In the semiconductor device 1A having the above-described configuration, an n-type semiconductor region 21 and an n-type semiconductor region 22 connected to the source electrode 40 and the drain electrode 50 are provided in the active region AR1, and an n-type semiconductor region 61 and an n-type semiconductor region 62 are provided in the inactive region AR2. By providing the n-type semiconductor region 61 and the n-type semiconductor region 62 in the inactive region AR2, it is possible to suppress an increase in the growth rate during regrowth of the n-type semiconductor region 21 and the n-type semiconductor region 22 provided in the active region AR1 together with them. Note that the details of regrowth will be described later. By suppressing an increase in the growth rate during regrowth, it is possible to suppress a decrease in the amount of dopant incorporated into the n-type semiconductor region 21 and the n-type semiconductor region 22, and to suppress an increase in their resistance. As a result, a semiconductor device 1A having n-type semiconductor regions 21 and 22 with sufficiently low resistance connected to the source electrode 40 and the drain electrode 50 can be stably realized.

[0078] Subsequently, a method for forming the semiconductor device 1A having the above-described configuration will be described. FIGS. 8 to 15 are diagrams for explaining an example of a method for forming a semiconductor device according to the second embodiment. Hereinafter, an example of each step of forming a semiconductor device will be described in order with reference to FIGS. 8 to 15.

[0079] FIG. 8 is a diagram showing an example of a step of preparing a semiconductor layer. FIG. 8(A) schematically shows a plan view of a main part of an example of a step of preparing a semiconductor layer. FIG. 8(B) schematically shows a cross-sectional view of a main part of an example of a step of preparing a semiconductor layer. FIG. 8(B) is a cross-sectional schematic view taken along line VIII-VIII of FIG. 8(A).

[0080] For example, a semiconductor layer 10A as shown in FIGS. 8(A) and 8(B) is prepared. For example, using the MOCVD method, an initial layer 14 is grown on the surface 13a of the substrate 13, an electron traveling layer 11 is grown on the surface 14a thereof, a spacer layer 15 is grown on the surface 11a thereof, and an electron supply layer 12 is grown on the surface 15a thereof. A 2DEG 1a is generated in the vicinity of the bonding interface between the electron traveling layer 11 and the spacer layer 15.

[0081] FIG. 9 is a diagram showing an example of a process for forming an inactive region and an active region. FIG. 9(A) schematically shows a plan view of a main part of an example of a process for forming an inactive region and an active region. FIG. 9(B) schematically shows a cross-sectional view of a main part of an example of a process for forming an inactive region and an active region. FIG. 9(B) is a schematic cross-sectional view taken along line IX-IX of FIG. 9(A).

[0082] After preparing the semiconductor layer 10A, for example, as shown in FIGS. 9(A) and 9(B), an inactive region AR2 is formed, and thereby, an active region AR1 defined by the formed inactive region AR2 is formed.

[0083] For example, on the surface 10a of the semiconductor layer 10A, a resist pattern (not shown) having an opening at a site of the semiconductor layer 10A where the inactive region AR2 is to be formed is formed by photolithography technology. Then, ion implantation of Ar is performed on the site of the semiconductor layer 10A exposed from the opening of the resist pattern. An inactive region AR2 is formed at the site of the semiconductor layer 10A where ion implantation of Ar is performed. The ion implantation of Ar is performed so as to extend to a position deeper than the 2DEG1a generated in the electron traveling layer 11. An active region AR1 defined by the inactive region AR2 is formed at the site of the semiconductor layer 10A where ion implantation of Ar is not performed. After the ion implantation of Ar, the resist pattern is removed using an organic solvent or the like.

[0084] Note that instead of the ion implantation of Ar, an inactive region can also be formed by dry-etching and removing the site of the semiconductor layer 10A exposed from the opening of the resist pattern by RIE or the like using a Cl-based gas.

[0085] FIG. 10 is a diagram showing an example of a process for forming a mask. FIG. 10(A) schematically shows a plan view of a main part of an example of a process for forming a mask. FIG. 10(B) schematically shows a cross-sectional view of a main part of an example of a process for forming a mask. FIG. 10(B) is a schematic cross-sectional view taken along line X-X of FIG. 10(A).

[0086] After the formation of the inactive region AR2 and the active region AR1, for example, as shown in FIGS. 10(A) and 10(B), a mask 90 having a group of openings 90a at a predetermined site of the semiconductor layer 10A is formed on the surface 10a of the semiconductor layer 10A. The group of openings 90a of the mask 90 is provided at sites of the semiconductor layer 10A where the n-type semiconductor regions 21 and 22 (or recesses 71 and 72) provided in the active region AR1 are to be formed. The group of openings 90a of the mask 90 is further provided at sites of the semiconductor layer 10A where the n-type semiconductor regions 61 and 62 (or recesses 81 and 82) provided in the inactive region AR2 are to be formed.

[0087] An insulating film such as SiN is used for the mask 90. For example, an insulating film such as SiN is formed on the surface 10a of the semiconductor layer 10A by using the plasma CVD method. Next, a resist pattern (not shown) having a group of openings corresponding to the sites where the n-type semiconductor regions 21 and 22 of the semiconductor layer 10A and the sites where the n-type semiconductor regions 61 and 62 are to be formed is formed on the insulating film by photolithography technology. Then, the insulating film exposed from the group of openings of the resist pattern is dry-etched and removed by RIE using an F-based gas or the like. Thereby, the group of openings 90a of the mask 90 as shown in FIGS. 10(A) and 10(B) is formed.

[0088] Incidentally, although not shown here, the resist pattern used at the time of forming the group of openings 90a may remain on the mask 90 after the formation of the group of openings 90a. FIG. 11 is a diagram showing an example of a recess formation process. FIG. 11(A) schematically shows a plan view of a main part of an example of a recess formation process. FIG. 11(B) schematically shows a cross-sectional view of a main part of an example of a recess formation process. FIG. 11(B) is a cross-sectional schematic view taken along line XI-XI of FIG. 11(A).

[0089] After forming the mask 90 having the opening portions 90a group, as shown in FIGS. 11(A) and 11(B), the portions of the semiconductor layer 10A exposed from the opening portions 90a group are dry-etched and removed by RIE or the like using a Cl-based gas. As a result, recesses 71 and 72 communicating with the opening portions 90a of the mask 90 are formed on the surface 10a side of the semiconductor layer 10A in the active region AR1. Recesses 81 and 82 communicating with the opening portions 90a of the mask 90 are formed on the surface 10a side of the semiconductor layer 10A in the inactive region AR2.

[0090] The recesses 71 and 72 in the active region AR1 penetrate the electron supply layer 12 and the spacer layer 15 of the semiconductor layer 10A and reach the electron traveling layer 11, and are formed such that the bottom surfaces of the recesses 71 and 72 are at positions deeper than the 2DEG1a generated in the electron traveling layer 11. As an example, the recesses 71 and 72 are formed such that their bottom surfaces are located at a depth within 60 nm from the surface 11a of the electron traveling layer 11 toward the initial layer 14 side. The recesses 81 and 82 in the inactive region AR2 are formed at the same or equivalent depth as the recesses 71 and 72 in the active region AR1 simultaneously, and penetrate the electron supply layer 12 and the spacer layer 15 of the semiconductor layer 10A in the inactive region AR2 to reach the electron traveling layer 11.

[0091] After forming the recesses 71 and 72 and the recesses 81 and 82, if the resist pattern used at the time of forming the opening portions 90a group remains on the mask 90, the resist pattern is removed using an organic solvent or the like.

[0092] FIG. 12 is a diagram showing an example of a formation process of an n-type semiconductor region. FIG. 12(A) schematically shows a main part plan view of an example of a formation process of an n-type semiconductor region. FIG. 12(B) schematically shows a main part cross-sectional view of an example of a formation process of an n-type semiconductor region. FIG. 12(B) is a cross-sectional schematic view taken along line XII-XII of FIG. 12(A).

[0093] After the formation of the recesses 71 and 72 and the recesses 81 and 82, as shown in FIGS. 12(A) and 12(B), an n-type semiconductor region 21 and an n-type semiconductor region 22, and an n-type semiconductor region 61 and an n-type semiconductor region 62 are formed in them, respectively.

[0094] For example, using the MOCVD method, an n-type semiconductor region 21 and an n-type semiconductor region 22, and an n-type semiconductor region 61 and an n-type semiconductor region 62 are regrown in the recesses 71 and 72 and the recesses 81 and 82 that are exposed from the aperture groups 90a of the mask 90, respectively. As the n-type semiconductor region 21 and the n-type semiconductor region 22, and the n-type semiconductor region 61 and the n-type semiconductor region 62, for example, n-type GaN is regrown. The n-type semiconductor region 21 and the n-type semiconductor region 22, and the n-type semiconductor region 61 and the n-type semiconductor region 62 are regrown in the recesses 71 and 72 and the recesses 81 and 82, respectively, in the same regrowth process using the MOCVD method.

[0095] When the n-type semiconductor region 21 and the n-type semiconductor region 22, and the n-type semiconductor region 61 and the n-type semiconductor region 62 are regrown using the MOCVD method, the atoms of their main raw materials are supplied not only to the recesses 71 and 72 and the recesses 81 and 82 but also onto the mask 90.

[0096] In addition, since the atoms of the dopant raw material have a shorter residence time and a shorter diffusion distance on the mask than the atoms of the main raw material, diffusion on the mask as much as that of the atoms of the main raw material does not occur. Atoms of the main raw material that are supplied onto the mask 90 corresponding to the inactive region AR2 and diffuse thereon move to the group of openings 90a of the mask 90 corresponding to the recesses 81 and 82 of the inactive region AR2, and are easily consumed for the regrowth of the n-type semiconductor regions 61 and 62. As a result, the atoms of the main raw material that diffuse on the mask 90 corresponding to the inactive region AR2 are suppressed from moving to the group of openings 90a of the mask 90 corresponding to the recesses 71 and 72 of the active region AR1 and being consumed for the regrowth of the n-type semiconductor regions 21 and 22. Therefore, the growth rates of the n-type semiconductor regions 21 and 22 provided in the active region AR1 are suppressed from increasing due to the influence of the atoms of the main raw material that diffuse on the mask 90 corresponding to the inactive region AR2.

[0097] In order to make the atoms of the main raw material that diffuse on the mask 90 corresponding to the inactive region AR2 easily consumed for the regrowth of the n-type semiconductor regions 61 and 62 and difficult to be consumed for the regrowth of the n-type semiconductor regions 21 and 22, the arrangement of the group of openings 90a is adjusted (FIG. 10). Thereby, the arrangements of the recesses 71 and 72 and the recesses 81 and 82 are adjusted (FIG. 11). The recesses 81 and 82 (n-type semiconductor regions 61 and 62) are preferably provided at positions within a distance of 500 μm from the recesses 71 and 72 (n-type semiconductor regions 21 and 22). This is because when the distance between the recesses 81 and 82 and the recesses 71 and 72 exceeds 500 μm, the following is likely to occur. That is, the atoms of the main raw material that diffuse on the mask 90 corresponding to the inactive region AR2 move to the group of openings 90a corresponding to the recesses 71 and 72 and are consumed for the regrowth of the n-type semiconductor regions 21 and 22, and their growth rates are likely to increase.

[0098] From this perspective, the arrangement of the apertures 90a of the mask 90 is adjusted, and the arrangements of the recesses 71 and 72 and the recesses 81 and 82 are adjusted. The n-type semiconductor regions 21 and 22 and the n-type semiconductor regions 61 and 62 are regrown in the same regrowth process using the MOCVD method in the adjusted recesses 71 and 72 and the recesses 81 and 82, respectively. Thereby, the growth rates of the n-type semiconductor regions 21 and 22 provided in the active region AR1 are suppressed from increasing due to the influence of the atoms of the main raw material diffusing on the mask 90 corresponding to the inactive region AR2, and are stabilized.

[0099] In addition, the atoms of the main raw material diffusing on the mask 90 corresponding to the inactive region AR2 are more likely to be consumed in the regrowth of the n-type semiconductor regions 61 and 62, and are less likely to be consumed in the regrowth of the n-type semiconductor regions 21 and 22. Therefore, the growth rates of the n-type semiconductor regions 61 and 62 provided in the inactive region AR2 become relatively faster than the growth rates of the n-type semiconductor regions 21 and 22 provided in the active region AR1. As a result, with respect to the surface 10a of the semiconductor layer 10A, the end faces 61a and 62a on the surface 10a side of the n-type semiconductor regions 61 and 62 are at a higher position than the end faces 21a and 22a on the surface 10a side of the n-type semiconductor regions 21 and 22.

[0100] As described above, since the growth rates of the n-type semiconductor regions 21 and 22 provided in the active region AR1 are suppressed from increasing and are stabilized, the amount of dopant incorporated into the n-type semiconductor regions 21 and 22 is suppressed from decreasing. Since the amount of dopant incorporated is suppressed from decreasing, the resistance of the n-type semiconductor regions 21 and 22 is suppressed from increasing. Thereby, sufficiently low-resistance n-type semiconductor regions 21 and 22 are stably formed.

[0101] The n-type semiconductor regions 61 and 62 of the inactive region AR2, which have a faster growth rate than the n-type semiconductor regions 21 and 22 provided in the active region AR1, have a smaller amount of dopant incorporated than the n-type semiconductor regions 21 and 22.

[0102] FIG. 13 is a diagram showing an example of a mask removal process. FIG. 13(A) schematically shows a plan view of a main part of an example of the mask removal process. FIG. 13(B) schematically shows a cross-sectional view of a main part of an example of the mask removal process. FIG. 13(B) is a cross-sectional schematic view taken along XIII-XIII of FIG. 13(A).

[0103] After the formation of the n-type semiconductor regions 21 and 22 and the n-type semiconductor regions 61 and 62, as shown in FIGS. 13(A) and 13(B), the mask 90 is removed. For example, the mask 90 is removed by wet etching using HF or the like.

[0104] FIG. 14 is a diagram showing an example of a source electrode and drain electrode formation process. FIG. 14(A) schematically shows a plan view of a main part of an example of the source electrode and drain electrode formation process. FIG. 14(B) schematically shows a cross-sectional view of a main part of an example of the source electrode and drain electrode formation process. FIG. 14(B) is a cross-sectional schematic view taken along XIV-XIV of FIG. 14(A).

[0105] After the removal of the mask 90, as shown in FIGS. 14(A) and 14(B), the source electrode 40 and the drain electrode 50 are formed. For example, first, a resist pattern (not shown) having openings is formed at the sites where the source electrode 40 and the drain electrode 50 are to be formed by photolithography technology. The openings of this resist pattern are provided so as to communicate with the n-type semiconductor regions 21 and 22 regrown in the recesses 71 and 72 of the semiconductor layer 10A in the active region AR1, respectively. After the formation of the resist pattern, a metal is deposited on the resist pattern and within its openings by vacuum evaporation. As an example, Ti with a thickness of 2 nm to 50 nm is deposited, and Al with a thickness of 100 nm to 300 nm is deposited thereon. After the deposition of the metal, the resist pattern is removed together with the metal deposited thereon by lift-off technology. Thereby, the source electrode 40 and the drain electrode 50 connected to the n-type semiconductor regions 21 and 22, respectively, are formed. Thereafter, heat treatment (alloying treatment) is performed at 500°C to 900°C in a nitrogen atmosphere, thereby establishing ohmic connections in the source electrode 40 and the drain electrode 50.

[0106] In addition, as long as a part of each of the source electrode 40 and the drain electrode 50 is connected to the n-type semiconductor regions 21 and 22 in the active region AR1, the other part may be located in the inactive region AR2.

[0107] FIG. 15 is a diagram showing an example of the gate electrode formation process. FIG. 15(A) schematically shows a plan view of a main part of an example of the gate electrode formation process. FIG. 15(B) schematically shows a cross-sectional view of a main part of an example of the gate electrode formation process. FIG. 15(B) is a cross-sectional schematic view taken along line XV-XV of FIG. 15(A).

[0108] After the source electrode 40 and the drain electrode 50 are formed, as shown in FIGS. 15(A) and 15(B), the gate electrode 30 is formed. For example, first, a resist pattern (not shown) having an opening is formed at a site where the gate electrode 30 is to be formed by photolithography. The opening of this resist pattern is provided so as to communicate with the semiconductor layer 10A of the active region AR1 (or the gate insulating film if the gate insulating film is formed) between the source electrode 40 and the drain electrode 50. After the resist pattern is formed, a metal is vapor-deposited on the resist pattern and within its opening by vacuum evaporation. As an example, Ni with a thickness of 5 nm to 30 nm is vapor-deposited, and Au with a thickness of 100 nm to 300 nm is vapor-deposited thereon. After the metal is vapor-deposited, the resist pattern is removed together with the metal vapor-deposited thereon by a lift-off technique. Thereby, the gate electrode 30 is formed. Heat treatment may be performed after the gate electrode 30 is formed.

[0109] Note that the gate electrode 30 is not limited to being within the active region AR1, and may extend outward from the active region AR1 and a part thereof may be provided in the inactive region AR2. Also, when a gate insulating film is interposed between the gate electrode 30 and the semiconductor layer 10A, the gate insulating film is formed before the gate electrode 30 is formed.

[0110] Through the above steps, a semiconductor device 1A having a configuration as shown in FIGS. 15(A) and 15(B) is formed. In the semiconductor device 1A, the growth rates of the n-type semiconductor regions 21 and 22 provided in the active region AR1 are suppressed from increasing (FIG. 12). As a result, the amount of dopant incorporated into the n-type semiconductor regions 21 and 22 is suppressed from decreasing, and the increase in their resistance due to the decrease in the incorporation amount is suppressed. Thereby, the n-type semiconductor regions 21 and 22 having sufficiently low resistance are stably formed. The source electrode 40 and the drain electrode 50 are respectively connected to the n-type semiconductor regions 21 and 22 having sufficiently low resistance, and the resistance between them and the 2DEG1a is reduced. Thereby, the large current and high output of the semiconductor device 1A are realized. According to the above method, the semiconductor device 1A having the n-type semiconductor regions 21 and 22 with sufficiently low resistance connected to the source electrode 40 and the drain electrode 50 is stably realized.

[0111] FIG. 16 is a diagram showing an example of the relationship between the growth rate of the regrowth region according to the second embodiment and the on-resistance of the transistor element. In FIG. 16, the horizontal axis represents the growth rate [nm / min] of the n-type semiconductor region (regrowth region) provided in the active region and connected to the electrode (ohmic electrode) of the transistor element, and the vertical axis represents the on-resistance [Ω·mm] of the transistor element. In the P part of FIG. 16, an example of the relationship between the growth rate of the n-type semiconductor region (regrowth region) in the active region and the on-resistance of the transistor element when an n-type semiconductor region (dummy regrowth region) is provided in the inactive region is shown. For comparison, in the Q part of FIG. 16, an example of the relationship between the growth rate of the n-type semiconductor region in the active region and the on-resistance of the transistor element when no n-type semiconductor region is provided in the inactive region is shown.

[0112] As shown in FIG. 16, when providing an n-type semiconductor region in the inactive region together with the n-type semiconductor region in the active region (P portion), the growth rate of the n-type semiconductor region in the active region is reduced compared to the case where it is not provided (Q portion), and the on-resistance of the transistor element is stabilized at a low value. According to the above method, it is possible to suppress an increase in the growth rate of the n-type semiconductor region in the active region, suppress an increase in its resistance due to an increase in the growth rate, and stably realize a semiconductor device including a transistor element with a low on-resistance.

[0113] Subsequently, a modified example will be described. FIGS. 17 to 19 are diagrams for explaining a modified example of a semiconductor device according to the second embodiment. FIGS. 17(A) and 17(B) schematically show a plan view of a main part of an example of a semiconductor device according to the modified example, and FIGS. 18(A), 18(B), and 19 schematically show a cross-sectional view of a main part of an example of a semiconductor device according to the modified example.

[0114] The semiconductor device 1Aa shown in FIG. 17(A) is different from the above semiconductor device 1A (FIG. 6, etc.) in that the n-type semiconductor region 61 provided in the inactive region AR2 is divided into a plurality of segments 61b, and the n-type semiconductor region 62 is divided into a plurality of segments 62b. The segment 61b group and the segment 62b group in the inactive region AR2 are formed by adjusting the arrangement of the opening 90a group of the mask 90 in accordance with them in the process of FIG. 10, and thereafter, the processes according to the examples of the processes of FIGS. 11 to 13 are performed. After forming the segment 61b group and the segment 62b group, the source electrode 40, the drain electrode 50, and the gate electrode 30 are formed according to the examples of the processes of FIGS. 14 and 15. For example, the semiconductor device 1Aa is obtained in this way.

[0115] In the semiconductor device 1Aa, in the regrowth process using the MOCVD method, an n-type semiconductor region (dummy regrowth region) is formed in the segment 61b group and the segment 62b group of the inactive region AR2 together with the n-type semiconductor region 21 and the n-type semiconductor region 22 of the active region AR1. By forming an n-type semiconductor region in the segment 61b group and the segment 62b group of the inactive region AR2, the growth rate of the n-type semiconductor region 21 and the n-type semiconductor region 22 of the active region AR1 regrown together with them can be suppressed from increasing, and the increase in their resistance can be suppressed.

[0116] In the semiconductor device 1Aa, like this, the inactive region AR2 may be provided with an n-type semiconductor region 61 in which a group of segments 61b divided into a plurality are intermittently arranged, or an n-type semiconductor region 62 in which a group of segments 62b divided into a plurality are intermittently arranged.

[0117] Further, the semiconductor device 1Ab shown in FIG. 17(B) is different from the above semiconductor device 1A (FIG. 6, etc.) in that a continuous n-type semiconductor region 63 that surrounds the active region AR1 without interruption is provided in the inactive region AR2. The n-type semiconductor region 63 of the inactive region AR2 is formed by adjusting the arrangement of the opening 90a of the mask 90 accordingly in the process of FIG. 10, and thereafter performing the process according to the example of the processes of FIGS. 11 to 13. After the formation of the n-type semiconductor region 63, the source electrode 40, the drain electrode 50, and the gate electrode 30 are formed according to the example of the processes of FIGS. 14 and 15. For example, the semiconductor device 1Ab is obtained in this way.

[0118] In the semiconductor device 1Ab, in the regrowth process using the MOCVD method, a continuous n-type semiconductor region 63 (dummy regrowth region) of the inactive region AR2 is formed together with the n-type semiconductor region 21 and the n-type semiconductor region 22 of the active region AR1. By forming the n-type semiconductor region 63 in the inactive region AR2, the growth rate of the n-type semiconductor region 21 and the n-type semiconductor region 22 of the active region AR1 regrown together with it can be suppressed from increasing, and the increase in their resistance can be suppressed.

[0119] In the semiconductor device 1Ab in which a continuous n-type semiconductor region 63 surrounding the active region AR1 is provided in the inactive region AR2, for example, as shown in FIG. 17(B), it may be necessary to intersect the gate electrode 30 with the n-type semiconductor region 63 in a plan view in terms of layout. In such a case, an insulating layer may be provided at least at the intersection portion with the gate electrode 30 on the n-type semiconductor region 63 so that an insulating layer is interposed between the n-type semiconductor region 63 and the gate electrode 30. Thereby, the contact between the n-type semiconductor region 63 and the gate electrode 30 is avoided. By avoiding the contact between the n-type semiconductor region 63 and the gate electrode 30, the influence of the n-type semiconductor region 63 on the gate electrode 30 is suppressed, and the influence on the operation of the transistor element due to the influence on the gate electrode 30 is suppressed.

[0120] Note that the same applies to the source electrode 40 and the drain electrode 50. That is, in terms of layout, when it is necessary to intersect the source electrode 40 and the drain electrode 50 with the n-type semiconductor region 63 while avoiding contact in a plan view, an insulating layer may be interposed between the source electrode 40 and the drain electrode 50 and the n-type semiconductor region 63. Thereby, the influence of the n-type semiconductor region 63 on the source electrode 40 and the drain electrode 50 is suppressed.

[0121] In addition, the semiconductor device 1Ac shown in Fig. 18(A) has a structure in which a trench 64 is provided between the n-type semiconductor region 21 in the active region AR1 and the n-type semiconductor region 61 in the inactive region AR2. Further, the semiconductor device 1Ac has a structure in which a trench 65 is provided between the n-type semiconductor region 22 in the active region AR1 and the n-type semiconductor region 62 in the inactive region AR2. Fig. 18(A) shows an example in which the trench 64 and the trench 65 are provided so as to divide the inactive region AR2. The semiconductor device 1Ac is different from the above-described semiconductor device 1A (Fig. 7, etc.) in that it has such a structure. The trench 64 and the trench 65 can be formed after any one of the steps shown in Figs. 8 to 15 above. For example, after forming the inactive region AR2 in the step of Fig. 9 above, a predetermined portion of the inactive region AR2 is dry-etched and removed by RIE or the like using a Cl-based gas to form the trench 64 and the trench 65. For example, the semiconductor device 1Ac can be obtained in this way.

[0122] In the semiconductor device 1Ac, in the regrowth process using the MOCVD method, the n-type semiconductor regions 61 and 62 in the inactive region AR2 are formed together with the n-type semiconductor regions 21 and 22 in the active region AR1. By forming the n-type semiconductor regions 61 and 62 in the inactive region AR2, it is possible to suppress an increase in the growth rate of the n-type semiconductor regions 21 and 22 in the active region AR1 that are regrown together with them, and to suppress an increase in their resistance.

[0123] In the semiconductor device 1Ac, a trench 64 is provided between the n-type semiconductor region 21 and the n-type semiconductor region 61, and a trench 65 is provided between the n-type semiconductor region 22 and the n-type semiconductor region 62. Thereby, the electrical action (capacitive coupling, etc.) between the n-type semiconductor regions 61 and 62 in the inactive region AR2 and the n-type semiconductor regions 21 and 22 or 2DEG1a in the active region AR1 can be effectively suppressed.

[0124] Further, the semiconductor device 1Ad shown in Fig. 18(B) is different from the above semiconductor device 1A (Fig. 7, etc.) in that a recess 66 surrounding the active region AR1 is formed in the inactive region AR2, and an n-type semiconductor region 61 and an n-type semiconductor region 62 are provided at the bottom of the recess 66. The recess 66 is formed, for example, by dry-etching and removing a portion of the semiconductor layer 10A exposed from the opening of a resist pattern (not shown) by RIE or the like using a Cl-based gas, instead of ion implantation of Ar, in the process of Fig. 9 above. The recess 66 is formed so that the bottom is at a position deeper than the 2DEG1a generated in the electron traveling layer 11.

[0125] For the semiconductor layer 10A in which the recess 66 is formed, the processes according to the examples of the processes in Figs. 10 to 15 above are performed. That is, the formation of the mask 90, the formation of the recesses 71 and 72 of the active region AR1 and the recesses 81 and 82 of the recess 66 of the inactive region AR2, and the formation of the n-type semiconductor region 21, the n-type semiconductor region 22, the n-type semiconductor region 61, and the n-type semiconductor region 62 are performed. Then, the removal of the mask 90, the formation of the source electrode 40 and the drain electrode 50, and the formation of the gate electrode 30 are performed, and the semiconductor device 1Ad is obtained.

[0126] In the semiconductor device 1Ad, in the regrowth process using the MOCVD method, the n-type semiconductor region 61 and the n-type semiconductor region 62 of the recess 66 in the inactive region AR2 are formed together with the n-type semiconductor region 21 and the n-type semiconductor region 22 of the active region AR1. By forming the n-type semiconductor region 61 and the n-type semiconductor region 62 in the inactive region AR2, it is possible to suppress the increase in the growth rate of the n-type semiconductor region 21 and the n-type semiconductor region 22 of the active region AR1 regrown together with them, and to suppress the increase in their resistance.

[0127] In the semiconductor device 1Ad, an n-type semiconductor region 61 and an n-type semiconductor region 62 are provided in the recess 66 of the inactive region AR2. Therefore, in the semiconductor device 1Ad, the facing of the side surfaces of the n-type semiconductor region 61 and the n-type semiconductor region 62 in the inactive region AR2 and the n-type semiconductor region 21 and the n-type semiconductor region 22 in the active region AR1, and the facing of the side surfaces of the two with a large area are suppressed. Thereby, the electrical action (capacitance coupling, etc.) between the n-type semiconductor region 61 and the n-type semiconductor region 62 in the inactive region AR2 and the n-type semiconductor region 21, the n-type semiconductor region 22, and 2DEG1a in the active region AR1 is effectively suppressed.

[0128] Further, the semiconductor device 1Ae shown in FIG. 19 has a configuration in which an n-type semiconductor region 21, an n-type semiconductor region 22, an n-type semiconductor region 61, and an n-type semiconductor region 62 are provided on the surface 10a of the semiconductor layer 10A. In the semiconductor device 1Ae, the recesses 71 and 72 and the recesses 81 and 82 as described above are not provided in the semiconductor layer 10A. The semiconductor device 1Ae is different from the above semiconductor device 1A (FIG. 7, etc.) in that it has such a configuration.

[0129] For example, after the mask 90 is formed according to the example of the process in FIG. 10 above, without forming the recesses 71 and 72 and the recesses 81 and 82 shown in the process of FIG. 11 above, regrowth using the MOCVD method is performed according to the example of the process in FIG. 12 above. That is, using the MOCVD method, an n-type semiconductor region 21, an n-type semiconductor region 22, an n-type semiconductor region 61, and an n-type semiconductor region 62 are regrown on the surface 10a of the semiconductor layer 10A. Then, for the semiconductor layer 10A regrown on the surface 10a in this way, according to the example of the processes in FIGS. 13 to 15 above, the mask 90 is removed, the source electrode 40 and the drain electrode 50 are formed, and the gate electrode 30 is formed, and the semiconductor device 1Ae is obtained.

[0130] In the semiconductor device 1Ae, in the regrowth process using the MOCVD method, an n-type semiconductor region 21 and an n-type semiconductor region 22 are formed on the surface 10a of the semiconductor layer 10A in the active region AR1. Together with them, an n-type semiconductor region 61 and an n-type semiconductor region 62 are formed on the surface 10a of the semiconductor layer 10A in the inactive region AR2. By forming the n-type semiconductor region 61 and the n-type semiconductor region 62 in the inactive region AR2, it is possible to suppress an increase in the growth rate of the n-type semiconductor region 21 and the n-type semiconductor region 22 in the active region AR1 regrown together with them, and to suppress an increase in their resistance.

[0131] Like the semiconductor device 1Ae, the n-type semiconductor region 21, the n-type semiconductor region 22, the n-type semiconductor region 61, and the n-type semiconductor region 62 do not necessarily have to be provided in the recesses 71, the recesses 72, the recesses 81, and the recesses 82. If the source electrode 40 and the drain electrode 50 respectively connected to the n-type semiconductor region 21 and the n-type semiconductor region 22 provided on the surface 10a of the semiconductor layer 10A are connected to the 2DEG1a with sufficiently low resistance, a configuration like that of the semiconductor device 1Ae may be adopted.

[0132] [Third Embodiment] FIGS. 20 and 21 are diagrams for explaining an example of a semiconductor device according to the third embodiment. FIG. 20 schematically shows a plan view of a main part of the semiconductor device according to the third embodiment. FIG. 21 schematically shows a cross-sectional view of a main part of the semiconductor device according to the third embodiment. FIG. 21 is a cross-sectional schematic view taken along XXII-XXII of FIG. 20.

[0133] The semiconductor device 1B shown in FIGS. 20 and 21 is an example of a HEMT. The semiconductor device 1B has a configuration in which a source electrode 40 connected to an n-type semiconductor region 21 provided in an active region AR1 extends into an inactive region AR2 and is connected to an n-type semiconductor region 61 provided in the inactive region AR2. As an example, the source electrode 40 is provided so as to cover the n-type semiconductor region 61 and a part of the source electrode 40 overlaps the n-type semiconductor region 61 in plan view. Similarly, the semiconductor device 1B has a configuration in which a drain electrode 50 connected to an n-type semiconductor region 22 provided in the active region AR1 extends into the inactive region AR2 and is connected to an n-type semiconductor region 62 provided in the inactive region AR2. As an example, the drain electrode 50 is provided so as to cover the n-type semiconductor region 62 and a part of the drain electrode 50 overlaps the n-type semiconductor region 62 in plan view. The semiconductor device 1B is different from the semiconductor device 1A (FIGS. 6 and 7, etc.) described in the second embodiment in that it has such a configuration.

[0134] In the formation of the semiconductor device 1B, in the process of FIG. 14 described in the second embodiment, the source electrode 40 is formed so as to be connected to both the n-type semiconductor region 21 in the active region AR1 and the n-type semiconductor region 61 in the inactive region AR2. The drain electrode 50 is formed so as to be connected to both the n-type semiconductor region 22 in the active region AR1 and the n-type semiconductor region 62 in the inactive region AR2. Other processes are performed according to the examples of the processes of FIGS. 8 to 13 and FIG. 15 described in the second embodiment. By such a method, a semiconductor device 1B as shown in FIGS. 20 and 21 is obtained.

[0135] Note that, with respect to the surface 10a of the semiconductor layer 10A, the end faces 61a and 62a of the n-type semiconductor regions 61 and 62 are at a higher position than the end faces 21a and 22a of the n-type semiconductor regions 21 and 22.

[0136] FIG. 20 shows, as an example, a semiconductor device 1B having a layout in which the source electrode 40 covers the entire n-type semiconductor region 61 of the inactive region AR2 in plan view, and the drain electrode 50 covers the entire n-type semiconductor region 62 of the inactive region AR2 in plan view. In addition, the source electrode 40 may have a layout that covers a part of the n-type semiconductor region 61 of the inactive region AR2 in plan view, and the drain electrode 50 may have a layout that covers a part of the n-type semiconductor region 62 of the inactive region AR2 in plan view.

[0137] In the semiconductor device 1B, in the regrowth process using the MOCVD method, similar to that described in the second embodiment, the n-type semiconductor regions 61 and 62 of the inactive region AR2 are formed together with the n-type semiconductor regions 21 and 22 of the active region AR1. By forming the n-type semiconductor regions 61 and 62 in the inactive region AR2, an increase in the growth rate of the n-type semiconductor regions 21 and 22 of the active region AR1 regrown together with them can be suppressed, and an increase in their resistance can be suppressed.

[0138] Furthermore, in the semiconductor device 1B, the source electrode 40 covers the entire or a part of the n-type semiconductor region 61 of the inactive region AR2 and is connected to the n-type semiconductor region 61. The drain electrode 50 covers the entire or a part of the n-type semiconductor region 62 of the inactive region AR2 and is connected to the n-type semiconductor region 62.

[0139] Here, the n-type semiconductor regions 61 and 62 of the inactive region AR2 are provided at positions spaced apart from the active region AR1, for example, positions spaced apart by 50 μm or more. Therefore, the n-type semiconductor region 61 of the inactive region AR2 connected to the source electrode 40 is suppressed from affecting the operation of the transistor element in the active region AR1 due to the electrical action with the n-type semiconductor regions 21 and 2DEG1a in the active region AR1 within the semiconductor layer 10A. Similarly, the n-type semiconductor region 62 of the inactive region AR2 connected to the drain electrode 50 is suppressed from affecting the operation of the transistor element in the active region AR1 due to the electrical action with the n-type semiconductor regions 22 and 2DEG1a in the active region AR1 within the semiconductor layer 10A. In the semiconductor device 1B, by suppressing such electrical action, the source electrode 40 can be arranged to cover all or part of the n-type semiconductor region 61, and the drain electrode 50 can be arranged to cover all or part of the n-type semiconductor region 62. By adopting a configuration such as that of the semiconductor device 1B, it becomes possible to increase the degree of freedom in the layout of the source electrode 40 and the drain electrode 50 and the degree of freedom in pattern design.

[0140] Note that the n-type semiconductor regions 61 and 62 are provided in the inactive region AR2 so as not to contact the gate electrode 30. Thereby, the influence on the gate electrode 30 of the n-type semiconductor regions 61 and 62 is suppressed, and the influence on the operation of the transistor element due to the influence on the gate electrode 30 is suppressed.

[0141] [Fourth Embodiment] FIGS. 22 and 23 are diagrams for explaining an example of a semiconductor device according to the fourth embodiment. FIG. 22 schematically shows a plan view of a main part of the semiconductor device according to the fourth embodiment. FIG. 23 schematically shows a cross-sectional view of a main part of the semiconductor device according to the fourth embodiment. FIG. 23 is a cross-sectional schematic view taken along XXIII-XXIII of FIG. 22.

[0142] The semiconductor device 1C shown in FIGS. 22 and 23 is an example of a HEMT. The semiconductor device 1C includes a pair of source electrode groups 40, a drain electrode 50 provided between the source electrode groups 40, and a gate electrode 30 having gate finger portions 31 respectively provided between the drain electrode 50 and each source electrode 40. A part of each of the source electrode groups 40, a part of the drain electrode 50, and a part of the gate finger portion 31 (FIG. 22) are provided in the active region AR1. Each of the source electrode groups 40 is connected to an n-type semiconductor region 21 and an n-type semiconductor region 22 provided in the active region AR1, and further extends to an inactive region AR2 and is connected to an n-type semiconductor region 61 and an n-type semiconductor region 62 provided in the inactive region AR2. As an example, each of the source electrode groups 40 covers the n-type semiconductor region 61 and the n-type semiconductor region 62, and is provided such that a part of each of the source electrode groups 40 overlaps the n-type semiconductor region 61 and the n-type semiconductor region 62 in plan view. Further, the drain electrode 50 is connected to an n-type semiconductor region 23 provided in the active region AR1, and is provided so as to extend to the inactive region AR2 (FIG. 22). The semiconductor device 1C is different from the semiconductor device 1A (FIGS. 6 and 7, etc.) described in the second embodiment in that it has such a configuration.

[0143] In the formation of the semiconductor device 1C, in the steps of FIGS. 10 to 13 described in the second embodiment, an n-type semiconductor region 21, an n-type semiconductor region 22, and an n-type semiconductor region 23 are formed in the active region AR1, and an n-type semiconductor region 61 and an n-type semiconductor region 62 are formed in the inactive region AR2. That is, a mask 90 having a group of openings 90a corresponding thereto is formed, recesses 71, 72, and 73 in the active region AR1, and recesses 81 and 82 in the inactive region AR2 are formed, and a regrowth process using the MOCVD method is performed. Thereafter, the mask 90 is removed. Next, according to the example of the steps of FIGS. 14 and 15 described in the second embodiment, the source electrode groups 40 and the drain electrode 50 are formed so as to have a pattern as shown in FIGS. 22 and 23, and further, a gate electrode 30 having gate finger portions 31 is formed. By such a method, a semiconductor device 1C as shown in FIGS. 22 and 23 is obtained.

[0144] Further, with respect to the surface 10a of the semiconductor layer 10A, the end surfaces 61a and 62a of the n-type semiconductor region 61 and the n-type semiconductor region 62 are at a higher position than the end surfaces 21a, 22a, and 23a of the n-type semiconductor region 21, the n-type semiconductor region 22, and the n-type semiconductor region 23.

[0145] Also, one of the source electrode 40 groups may be arranged to cover a part of the n-type semiconductor region 61 of the inactive region AR2 in a plan view, and the other of the source electrode 40 groups may similarly be arranged to cover a part of the n-type semiconductor region 62. This increases the degree of freedom in layout and pattern design, making it possible to provide the source electrode 40 groups.

[0146] In the semiconductor device 1C, in the regrowth process using the MOCVD method, the n-type semiconductor region 61 and the n-type semiconductor region 62 of the inactive region AR2 are formed together with the n-type semiconductor region 21, the n-type semiconductor region 22, and the n-type semiconductor region 23 of the active region AR1. By forming the n-type semiconductor region 61 and the n-type semiconductor region 62 in the inactive region AR2, it is possible to suppress an increase in the growth rate of the n-type semiconductor region 21, the n-type semiconductor region 22, and the n-type semiconductor region 23 of the active region AR1 that are regrown together with them, and to suppress an increase in their resistance.

[0147] The semiconductor device 1C is applicable to a source-grounded transistor in which a group of source electrodes 40 is grounded (GND), a discrete device, a monolithic microwave integrated circuit (MMIC), and the like. The n-type semiconductor regions 61 and 62 in the inactive region AR2 are provided at positions separated from the gate electrode 30 and the drain electrode 50 used as signal transmission lines and separated from the gate electrode 30 and the drain electrode 50. The n-type semiconductor regions 61 and 62 are provided in the inactive region AR2 directly below the group of source electrodes 40 used as GND or in a part of the inactive region AR2 where other passive elements and the like are not provided. The n-type semiconductor regions 61 and 62 in the inactive region AR2 are provided at positions separated from the active region AR1, for example, at positions separated by 50 μm or more, and the electrical interaction with the n-type semiconductor regions 21 and 2DEG1a in the active region AR1 in the semiconductor layer 10A is suppressed. Thereby, the influence on the operation and signal transmission of the transistor element is suppressed by providing the n-type semiconductor regions 61 and 62 that suppress the growth rate of the n-type semiconductor regions 21, 22, and 23 in the active region AR1 from increasing.

[0148] The first to fourth embodiments have been described above. Semiconductor devices 1, 1A, 1B, 1C, etc. having the configurations described in the first to fourth embodiments above can be applied to various electronic devices. As an example, the case of applying a semiconductor device having the above configuration to a semiconductor package, a power factor improvement circuit, a power supply device, and an amplifier will be described below.

[0149] [Fifth Embodiment] Here, an application example of a semiconductor device having the above configuration to a semiconductor package will be described as the fifth embodiment.

[0150] FIG. 24 is a diagram for explaining an example of a semiconductor package according to the fifth embodiment. FIG. 24 schematically shows a plan view of a main part of an example of a semiconductor package according to the fifth embodiment.

[0151] The semiconductor package 200 shown in FIG. 24 is an example of a discrete package. The semiconductor package 200 includes the semiconductor device 1A described in the second embodiment above, a lead frame 210 on which the semiconductor device 1A is mounted, and a resin 220 that seals them.

[0152] The semiconductor device 1A is mounted, for example, on the die pad 210a of the lead frame 210 using a die attach material or the like (not shown). The semiconductor device 1A is provided with a pad 30a connected to the gate electrode 30, a pad 40a connected to the source electrode 40, and a pad 50a connected to the drain electrode 50. The pad 30a, the pad 40a, and the pad 50a are respectively connected to the gate lead 211, the source lead 212, and the drain lead 213 of the lead frame 210 using wires 230 such as Au and Al. The lead frame 210, the semiconductor device 1A mounted thereon, and the wires 230 connecting them are sealed with the resin 220 so that a part of each of the gate lead 211, the source lead 212, and the drain lead 213 is exposed.

[0153] An external connection electrode connected to the source electrode 40 may be provided on the surface of the semiconductor device 1A opposite to the surface on which the pad 30a connected to the gate electrode 30 and the pad 50a connected to the drain electrode 50 are provided. The external connection electrode may be connected to the die pad 210a connected to the source lead 212 using a conductive bonding material such as solder.

[0154] For example, the semiconductor device 1A described in the second embodiment above is used, and a semiconductor package 200 having such a configuration is obtained. As described above, in the semiconductor device 1A (Figs. 6 and 7, etc.), an n-type semiconductor region (regrowth region) connected to an electrode (source electrode 40 or drain electrode 50) is provided in the active region, and further, an n-type semiconductor region (dummy regrowth region) is provided in the inactive region. By providing an n-type semiconductor region in the inactive region, it is possible to suppress an increase in the growth rate of the n-type semiconductor region provided in the active region together therewith. As a result, it is possible to suppress a decrease in the amount of dopant incorporated into the n-type semiconductor region provided in the active region, and it is possible to suppress an increase in the resistance due to a decrease in the amount of dopant incorporated, and a sufficiently low-resistance n-type semiconductor region is stably formed in the active region. Thereby, a semiconductor device 1A having a sufficiently low-resistance n-type semiconductor region connected to an electrode in the active region is stably realized. Such a semiconductor device 1A is used, and a high-performance semiconductor package 200 is realized.

[0155] Here, the semiconductor device 1A has been taken as an example, but it is possible to obtain a semiconductor package in the same manner using other semiconductor devices 1, 1B, 1C, etc. [Sixth Embodiment] Here, an application example of a semiconductor device having the above-described configuration to a power factor improvement circuit will be described as a sixth embodiment.

[0156] FIG. 25 is a diagram for explaining an example of a power factor improvement circuit according to the sixth embodiment. FIG. 25 shows an equivalent circuit diagram of an example of a power factor improvement circuit according to the sixth embodiment. The power factor correction (PFC) circuit 300 shown in FIG. 25 includes a switch element 310, a diode 320, a choke coil 330, a capacitor 340, a capacitor 350, a diode bridge 360, and an AC power supply 370 (AC).

[0157] In the PFC circuit 300, the drain electrode of the switching element 310 is connected to the anode terminal of the diode 320 and one terminal of the choke coil 330. The source electrode of the switching element 310 is connected to one terminal of the capacitor 340 and one terminal of the capacitor 350. The other terminal of the capacitor 340 is connected to the other terminal of the choke coil 330. The other terminal of the capacitor 350 is connected to the cathode terminal of the diode 320. Also, a gate driver is connected to the gate electrode of the switching element 310. An AC power supply 370 is connected between both terminals of the capacitor 340 via a diode bridge 360, and a DC power supply (DC) is taken out from between both terminals of the capacitor 350.

[0158] For example, the semiconductor devices 1, 1A, 1B, 1C, etc. are used for the switching element 310 of the PFC circuit 300 having such a configuration. As described above, in the semiconductor devices 1, 1A, 1B, 1C, etc., an n-type semiconductor region (regrowth region) connected to an electrode is provided in the active region, and further, an n-type semiconductor region (dummy regrowth region) is provided in the inactive region. By providing the n-type semiconductor region in the inactive region, it is possible to suppress the growth rate of the n-type semiconductor region provided in the active region together with it from increasing. As a result, it is possible to suppress a decrease in the amount of dopant incorporated in the n-type semiconductor region provided in the active region, and it is possible to suppress an increase in its resistance due to a decrease in the amount of dopant incorporated, and a sufficiently low-resistance n-type semiconductor region is stably formed in the active region. Thereby, the semiconductor devices 1, 1A, 1B, 1C, etc. having a sufficiently low-resistance n-type semiconductor region connected to an electrode in the active region are stably realized. By using such semiconductor devices 1, 1A, 1B, 1C, etc., a high-performance PFC circuit 300 is realized.

[0159] [Seventh Embodiment] Here, an application example of the semiconductor device having the above configuration to a power supply device will be described as the seventh embodiment.

[0160] FIG. 26 is a diagram for explaining an example of a power supply device according to the seventh embodiment. FIG. 26 shows an equivalent circuit diagram of an example of a power supply device according to the seventh embodiment. The power supply device 400 shown in FIG. 26 includes a primary-side circuit 410, a secondary-side circuit 420, and a transformer 430 provided between the primary-side circuit 410 and the secondary-side circuit 420.

[0161] The primary-side circuit 410 includes a PFC circuit 300 as described in the third embodiment, and an inverter circuit, for example, a full-bridge inverter circuit 440 connected between both terminals of the capacitor 350 of the PFC circuit 300. The full-bridge inverter circuit 440 includes a plurality of, here as an example, four switch elements 441, switch element 442, switch element 443, and switch element 444.

[0162] The secondary-side circuit 420 includes a plurality of, here as an example, three switch elements 421, switch element 422, and switch element 423. For example, the semiconductor devices 1, 1A, 1B, 1C, etc. are used for the switch element 310 of the PFC circuit 300 included in the primary-side circuit 410 and the switch elements 441 to 444 of the full-bridge inverter circuit 440 of the power supply device 400 having such a configuration. For example, for the switch elements 421 to 423 of the secondary-side circuit 420 of the power supply device 400, a normal MIS (Metal Insulator Semiconductor) type FET using silicon is used.

[0163] As described above, in semiconductor devices 1, 1A, 1B, 1C, etc., an n-type semiconductor region (regrowth region) connected to an electrode is provided in the active region, and further, an n-type semiconductor region (dummy regrowth region) is provided in the inactive region. By providing the n-type semiconductor region in the inactive region, it is possible to suppress the growth rate of the n-type semiconductor region provided in the active region together with it from increasing. As a result, it is possible to suppress a decrease in the amount of dopant incorporated in the n-type semiconductor region provided in the active region, and it is possible to suppress an increase in its resistance due to a decrease in the amount of dopant incorporated, and a sufficiently low-resistance n-type semiconductor region is stably formed in the active region. Thereby, semiconductor devices 1, 1A, 1B, 1C, etc. having a sufficiently low-resistance n-type semiconductor region connected to an electrode in the active region are stably realized. Such semiconductor devices 1, 1A, 1B, 1C, etc. are used, and a high-performance power supply device 400 is realized.

[0164] [Eighth Embodiment] Here, an application example of a semiconductor device having the above-described configuration to an amplifier will be described as the eighth embodiment.

[0165] FIG. 27 is a diagram for explaining an example of an amplifier according to the eighth embodiment. FIG. 27 shows an equivalent circuit diagram of an example of an amplifier according to the eighth embodiment. The amplifier 500 shown in FIG. 27 includes a digital predistortion circuit 510, a mixer 520, a mixer 530, and a power amplifier 540.

[0166] The digital predistortion circuit 510 compensates for the non-linear distortion of the input signal. The mixer 520 mixes the input signal SI with the non-linear distortion compensated and an AC signal. The power amplifier 540 amplifies the signal obtained by mixing the input signal SI with the AC signal. In the amplifier 500, for example, by switching the switch, the output signal SO can be mixed with the AC signal by the mixer 530 and sent to the digital predistortion circuit 510. The amplifier 500 can be used as a high-frequency amplifier or a high-output amplifier.

[0167] The semiconductor devices 1, 1A, 1B, 1C, etc. are used in the power amplifier 540 of the amplifier 500 having such a configuration. As described above, in the semiconductor devices 1, 1A, 1B, 1C, etc., an n-type semiconductor region (regrown region) connected to an electrode is provided in the active region, and further, an n-type semiconductor region (dummy regrown region) is provided in the inactive region. By providing the n-type semiconductor region in the inactive region, it is possible to suppress the growth rate of the n-type semiconductor region provided in the active region together with it from increasing. As a result, it is possible to suppress a decrease in the amount of dopant incorporated in the n-type semiconductor region provided in the active region, and it is possible to suppress an increase in its resistance due to a decrease in the amount of dopant incorporated, and a sufficiently low-resistance n-type semiconductor region is stably formed in the active region. Thereby, the semiconductor devices 1, 1A, 1B, 1C, etc. having a sufficiently low-resistance n-type semiconductor region connected to an electrode in the active region are stably realized. Such semiconductor devices 1, 1A, 1B, 1C, etc. are used, and a high-performance amplifier 500 is realized.

[0168] The various electronic devices (the semiconductor package 200, the PFC circuit 300, the power supply device 400, the amplifier 500, etc. described in the above fifth to eighth embodiments) to which the semiconductor devices 1, 1A, 1B, 1C, etc. are applied can be mounted on various electronic devices or electronic apparatuses. For example, it can be mounted on various electronic devices or electronic apparatuses such as a computer (personal computer, supercomputer, server, etc.), a smartphone, a mobile phone, a tablet terminal, a sensor, a camera, an audio device, a measuring device, an inspection device, a manufacturing device, a transmitter, a receiver, and a radar device.

[0169] Regarding the embodiments described above, the following additional remarks are further disclosed. (Supplementary Note 1) A semiconductor layer, an active region provided in the semiconductor layer, an inactive region provided in the semiconductor layer and adjacent to the active region, a first semiconductor region provided on the first surface side of the semiconductor layer in the active region, A second semiconductor region provided on the first surface side of the semiconductor layer in the inactive region, A first electrode provided on the first surface side of the semiconductor layer and connected to the first semiconductor region A semiconductor device, characterized by comprising the same.

[0170] (Appendix 2) The first semiconductor region is provided in a first recess provided on the first surface side of the semiconductor layer in the active region, The semiconductor device according to Appendix 1, wherein the second semiconductor region is provided in a second recess provided on the first surface side of the semiconductor layer in the inactive region.

[0171] (Appendix 3) The semiconductor layer An electron supply layer provided on the first surface side, An electron transport layer provided on the side opposite to the first surface side of the electron supply layer And includes The semiconductor device according to Appendix 1 or 2, wherein the first semiconductor region and the second semiconductor region penetrate the electron supply layer and reach the electron transport layer.

[0172] (Appendix 4) The semiconductor device according to any one of Appendices 1 to 3, wherein the second semiconductor region is located at a distance from the active region. (Appendix 5) The semiconductor device according to any one of Appendices 1 to 4, wherein the second semiconductor region is provided at a position where the distance from the active region is 50 μm or more.

[0173] (Appendix 6) The semiconductor device according to any one of Appendices 1 to 5, wherein the second semiconductor region is provided at a position where the distance from the first semiconductor region is within 500 μm. (Appendix 7) With respect to the first surface of the semiconductor layer, the first end surface on the first surface side of the semiconductor layer of the first semiconductor region is at a lower position than the second end surface on the first surface side of the semiconductor layer of the second semiconductor region. The semiconductor device according to any one of Appendices 1 to 6, characterized in that.

[0174] (Supplementary Note 8) The semiconductor device according to any one of Supplementary Notes 1 to 7, wherein the first electrode is connected to the first semiconductor region and the second semiconductor region. (Supplementary Note 9) The semiconductor device according to any one of Supplementary Notes 1 to 8, further comprising a second electrode provided on the first surface side of the semiconductor layer, at least a part of which is located in the active region and is separated from the first semiconductor region and the second semiconductor region.

[0175] (Supplementary Note 10) A method of manufacturing a semiconductor device, comprising: forming an active region and an inactive region adjacent to the active region in a semiconductor layer; forming a first semiconductor region on the first surface side of the semiconductor layer in the active region; forming a second semiconductor region on the first surface side of the semiconductor layer in the inactive region; forming a first electrode connected to the first semiconductor region on the first surface side of the semiconductor layer; and a method of manufacturing a semiconductor device, characterized by including the steps.

[0176] (Supplementary Note 11) In the step of forming the first semiconductor region and the step of forming the second semiconductor region, a mask having a first opening communicating with the active region and a second opening communicating with the inactive region is formed on the first surface side of the semiconductor layer; using metalorganic chemical vapor deposition, the first semiconductor region and the second semiconductor region are grown in the first opening and the second opening of the mask, respectively. The method of manufacturing a semiconductor device according to Supplementary Note 10, characterized by the above steps.

[0177] (Supplementary Note 12) After forming the mask, the semiconductor layer in the first opening and the second opening is partially removed, and a first recess communicating with the first opening and a second recess communicating with the second opening are formed in the semiconductor layer. When growing the first semiconductor region and the second semiconductor region in the first opening and the second opening respectively, grow the first semiconductor region and the second semiconductor region in the first recess communicating with the first opening and the second recess communicating with the second opening respectively. The manufacturing method of the semiconductor device according to appended claim 11, characterized in that.

[0178] (Appended claim 13) A semiconductor layer, An active region provided in the semiconductor layer, An inactive region provided in the semiconductor layer and adjacent to the active region, A first semiconductor region provided on the first surface side of the semiconductor layer in the active region, A second semiconductor region provided on the first surface side of the semiconductor layer in the inactive region, A first electrode provided on the first surface side of the semiconductor layer and connected to the first semiconductor region An electronic device comprising a semiconductor device including.

Explanation of symbols

[0179] 1, 1A, 1Aa, 1Ab, 1Ac, 1Ad, 1Ae, 1B, 1C, 100A, 100B Semiconductor device 1a 2DEG 10, 10A, 110 Semiconductor layer 10a, 11a, 12a, 13a, 14a, 15a Surface 11, 111 Electron traveling layer 12, 112 Electron supply layer 13 Substrate 14 Initial layer 15 Spacer layer 21, 22, 23, 61, 62, 63, 180, 181, 182 n-type semiconductor region 21a, 22a, 23a, 61a, 62a End face 30, 120 Gate electrode 30a, 40a, 50a Pad 31 Gate finger part 40, 130 Source electrode 50, 140 Drain electrode 61b, 62b segments 64, 65 trenches 66 recess 71, 72, 73, 81, 82, 170, 171, 172 recesses 90, 190 masks 90a, 190a openings 150, AR2 inactive regions 160, AR1 active regions 183 atom 191, 192 regions 200 semiconductor package 210 lead frame 210a die pad 211 gate lead 212 source lead 213 drain lead 220 resin 230 wire 300 PFC circuit 310, 421, 422, 423, 441, 442, 443, 444 switching elements 320 diode 330 choke coil 340, 350 capacitors 360 diode bridge 370 AC power supply 400 power supply device 410 primary side circuit 420 secondary side circuit 430 transformer 440 full bridge inverter circuit 500 amplifier 510 digital predistortion circuit 520, 530 mixers 540 power amplifier R1, R2 resistors

Claims

1. A semiconductor layer including an electron supply layer and an electron transport layer, an active region provided in the semiconductor layer, an inactive region provided in the semiconductor layer and adjacent to the active region, an n-type first semiconductor region provided on a first surface side of the semiconductor layer in the electron supply layer side of the active region, an n-type second semiconductor region provided on the first surface side of the semiconductor layer in the inactive region, located at a distance from the active region, and provided at a position within 500 μm from the first semiconductor region, and a first electrode provided on the first surface side of the semiconductor layer and connected to the first semiconductor region A semiconductor device characterized by comprising the above.

2. The semiconductor device according to claim 1, wherein the first semiconductor region and the second semiconductor region penetrate the electron supply layer and reach the electron transport layer.

3. The semiconductor device according to claim 1 or 2, wherein the second semiconductor region is provided at a position where the distance from the active region is 50 μm or more.

4. The semiconductor device according to any one of claims 1 to 3, wherein, with respect to the first surface of the semiconductor layer, a first end face of the first semiconductor region on the first surface side of the semiconductor layer is at a lower position than a second end face of the second semiconductor region on the first surface side of the semiconductor layer.

5. The semiconductor device according to any one of claims 1 to 4, wherein the first electrode is connected to the first semiconductor region and the second semiconductor region.

6. A step of forming an active region and an inactive region adjacent to the active region in a semiconductor layer including an electron supply layer and an electron transport layer, a step of forming an n-type first semiconductor region on a first surface side of the semiconductor layer in the electron supply layer side of the active region, a step of forming an n-type second semiconductor region provided on the first surface side of the semiconductor layer in the inactive region, located at a distance from the active region, and provided at a position within 500 μm from the first semiconductor region, and a step of forming a first electrode connected to the first semiconductor region on the first surface side of the semiconductor layer A method for manufacturing a semiconductor device characterized by comprising the above.

7. In the step of forming the first semiconductor region and the step of forming the second semiconductor region, a mask having a first opening leading to the active region and a second opening leading to the inactive region is formed on the first surface side of the semiconductor layer, The method of manufacturing a semiconductor device according to claim 6, wherein the first semiconductor region and the second semiconductor region are grown in the first opening and the second opening of the mask, respectively, by using a metalorganic chemical vapor deposition method.

8. A semiconductor layer including an electron supply layer and an electron transport layer, an active region provided in the semiconductor layer, an inactive region provided in the semiconductor layer and adjacent to the active region, an n-type first semiconductor region provided on the first surface side of the electron supply layer side of the semiconductor layer in the active region, an n-type second semiconductor region provided on the first surface side of the semiconductor layer in the inactive region, located apart from the active region, and provided at a position within 500 μm from the first semiconductor region, a first electrode provided on the first surface side of the semiconductor layer and connected to the first semiconductor region An electronic device comprising a semiconductor device.

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