Manufacture of silicon carbide and nitride structures on a carrier substrate

Abstract

To provide a method for forming silicon carbide and group III nitrides having a desired quality.SOLUTION: In a method for forming a semiconductor structure, a first oxide layer located on a set of group III nitride layers formed on a silicon carbide substrate is bonded to a first oxide layer located on a carrier substrate to form an oxide layer located between the carrier substrate and the set of group III nitride layers. The silicon carbide substrate has a doped layer. The silicon carbide substrate having the doped layer is etched using a photo-electrochemical etching process. A doping level of the doped layer is such that the doped layer is removed and a silicon carbide layer in the silicon carbide substrate remains unetched. The semiconductor structure is formed using the silicon carbide layer and the set of group III nitride layers.SELECTED DRAWING: Figure 25

Description

Technical Field

[0001] The present disclosure generally relates to semiconductors, and more specifically, to a method of forming a semiconductor structure, and more specifically, to forming a silicon carbide and a nitride structure on a carrier substrate.

Background Art

[0002] Silicon carbide and group III nitrides such as gallium nitride are semiconductors desirable for signal processing and quantum applications. These materials have a wide bandgap greater than 3 eV and a larger nonlinear optical coefficient compared to other materials such as silicon, silica, and silicon nitride materials currently used for low-loss photonics and on-chip nonlinear optics.

[0003] Silicon carbide (SiC) is a semiconductor material containing silicon and carbon. Silicon carbide can be used in devices for quantum information processing and other purposes. For example, the color centers of a silicon carbide structure can be used to provide optical readouts indicative of their electron spin states. Each color center is a qubit for quantum computing. The state of a qubit can be a logical value "0", a logical value "1", or a superposition of the two states. For example, the color centers can be incorporated into photonic devices such as microcavities for waveguide elements.

[0004] Fabricating devices on a silicon carbide structure can be difficult. For example, devices formed using thin films having silicon carbide and group III nitrides can be more difficult to fabricate than expected compared to other materials such as silicon. A thin film device includes one or more thin film layers where one thin film layer can be from a few nanometers to a few micrometers thick.

[0005] The quality of thin film devices using silicon carbide and group III nitrides formed on a wafer may not be as high as desired compared to materials such as silicon. Therefore, it would be desirable to have methods and devices that take into account at least some of the above problems and other possible problems. For example, it would be desirable to have methods and apparatuses that overcome the technical problems associated with forming silicon carbide and group III nitrides having the desired quality. SUMMARY OF THE INVENTION

[0006] Embodiments of the present disclosure provide a method for forming a semiconductor structure. A set of group III nitride layers is formed on a silicon carbide substrate. The silicon carbide substrate includes a doped layer. The doped layer has a doping level such that the doped layer is etched using a photoelectrochemical etching process and other portions of the silicon carbide substrate remain unetched. A first oxide layer is formed on the set of group III nitride layers. The set of group III nitride layers is disposed between the first oxide layer and the silicon carbide substrate. The first oxide layer is bonded to a second oxide layer on a carrier substrate to form an oxide layer disposed between the carrier substrate and the set of group III nitride layers. The silicon carbide substrate is polished. The polishing is stopped when it reaches and exposes a portion of the doped layer of the silicon carbide substrate. The silicon carbide substrate is etched using photoelectrochemical etching such that when a portion of the doped layer of the silicon carbide substrate is exposed, the doped layer is removed and the silicon carbide layer of the silicon carbide substrate remains. The semiconductor structure is formed using the silicon carbide layer and the group III nitride layer.

[0007] Another embodiment of the present disclosure provides a method for forming a semiconductor structure. A first oxide layer disposed on a set of group III nitride layers formed on a silicon carbide substrate is bonded to a second oxide layer disposed on a carrier substrate to form an oxide layer disposed between the carrier substrate and the set of group III nitride layers. The silicon carbide substrate has a doped layer. The silicon carbide substrate having the doped layer is etched using a photoelectrochemical etching process, and the doping level of the doped layer is at a level where the doped layer is removed and the silicon carbide layer of the silicon carbide substrate remains unetched. The semiconductor structure is formed using the silicon carbide layer and the group III nitride layer.

[0008] Yet another embodiment of the present disclosure provides a product management system including a manufacturing apparatus and a control system. The control system controls the manufacturing apparatus to bond a first oxide layer disposed on a set of group III nitride layers formed on a silicon carbide substrate to a second oxide layer disposed on a carrier substrate to form an oxide layer disposed between the carrier substrate and the set of group III nitride layers. The silicon carbide substrate has a doped layer. The silicon carbide substrate having the doped layer is etched using a photoelectrochemical etching process. The doping level of the doped layer is at a level where the doped layer is removed and the silicon carbide layer of the silicon carbide substrate remains unetched. The semiconductor structure is formed using the silicon carbide layer and the group III nitride layer.

[0009] These features and functions can be realized independently in various embodiments of the present disclosure or can be combined in still other embodiments that can be understood in further detail by referring to the following description and drawings.

[0010] The novel features believed to be characteristic of the exemplary embodiments are set forth in the appended claims. However, the exemplary embodiments, preferred modes of use, and further objects and features thereof will be best understood from the following detailed description of the exemplary embodiments of the present disclosure when read in conjunction with the accompanying drawings.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0012] Exemplary embodiments recognize and consider one or more different considerations. For example, exemplary embodiments recognize and consider that currently used techniques can produce non-uniform polycrystalline silicon carbide films across a wafer. Further, exemplary embodiments recognize and consider that when current techniques for ensuring a desired thickness for thin film devices are used, material damage can occur within the silicon carbide film, resulting in undesirable light absorption or scattering.

[0013] Furthermore, exemplary embodiments recognize and consider that current techniques for manufacturing silicon carbide (SiC) nanophotonics are mainly limited to 3C-SiC (cubic crystal structure) epitaxially grown on silicon (Si). Exemplary embodiments recognize and consider that while 3C-SiC can be easily trimmed on Si or silicon dioxide (SiO2) due to the selectivity of chemical etching between SiC and Si / SiO2, 3C-SiC devices can suffer from undesirable optical losses due to dislocations, residual doping, high film strain, and interface defects at the Si-SiC growth interface.

[0014] Exemplary embodiments recognize and consider that, to reduce interface defects, 3C-SiC can be transferred to another substrate and the preceding interface can be removed by etching. However, exemplary embodiments recognize and consider that 3C-SiC contains high inhomogeneous strain due to lattice mismatch with the Si substrate. In contrast to 3C-SiC films grown on Si substrates, exemplary embodiments recognize and consider that single-crystalline bulk and homoepitaxially grown 4H-SiC and 6H-SiC (hexagonal crystal structures) involve low crystal strain and low residual doping due to growth. Thus, exemplary embodiments recognize and consider that the 4H-SiC platform has great potential in photonics and other related fields. Exemplary embodiments recognize and consider that the homoepitaxial growth of 4H-SiC on a silicon carbide substrate produces few lattice defects, and thus the hexagonal SiC crystal polymorph of silicon carbide (e.g., 4H-) is sought for photonics. Exemplarily, embodiments recognize and consider that existing methods for separating thin films of 4H-SiC are limited such that chemical etching of the currently utilized base substrate is not possible, assuming that the material is grown on a bulk 4H-SiC substrate.

[0015] Exemplary embodiments recognize and consider that while thin films of hexagonal silicon carbide are suitable for photonics applications, flexible pattern design and stacked layers are possible. Accordingly, exemplary embodiments provide methods, apparatuses, and systems for forming structures using nitrides such as silicon carbide and group III nitrides, having a desired level of uniformity in film thickness and reducing damage or defects. In one exemplary embodiment, the method forms a semiconductor structure. A first oxide layer disposed on a set of group II nitride layers formed on a silicon carbide substrate is bonded to a second oxide layer disposed on a carrier substrate, forming an oxide layer disposed between the carrier substrate and the set of group III nitride layers. The silicon carbide substrate has a doped layer. The silicon carbide substrate having the doped layer is etched using a photoelectrochemical etching process, and the doping level of the doped layer is at a level such that the doped layer is removed and the silicon carbide layer of the silicon carbide substrate remains unetched. The semiconductor structure can be formed using a set of silicon carbide layers and group III nitride layers.

[0016] One or more exemplary embodiments enable the fabrication of semiconductor structures using silicon carbide as a platform for providing photonic functionality. The semiconductor structure includes at least one of an optical waveguide and an optical resonator. The functionality of these structures includes splitters, directional couplers, diffraction grating couplers, microrings for filters, microdisks for filters, nonlinear optical frequency converters, light emitters, and other types of functionality. Exemplary embodiments enable the fabrication of these or other types of structures while keeping optical losses low using wafer-scale thin films of silicon carbide.

[0017] In this book, the expression "at least one of" used with the listed items means that one or more various combinations of the listed items can be used, and only one of each of the listed items may be required. In other words, "at least one of" means that any combination of items and any number of items can be used from the list, but it does not mean that all of the listed items are required. An item can be a specific object, article, or category.

[0018] For example, without limitation, "at least one of item A, item B, and item C" may include "item A", "item A and item B", or "item B". This example can also include "item A, item B, and item C", or "item B and item C". Any combination of these items can, of course, exist. In one exemplary embodiment, "at least one of" can be, by way of example and not limitation, "2 item As, 1 item B, and 10 item Cs", "4 item Bs and 7 item Cs", or other suitable combinations.

[0019] Detailed embodiments of the claimed structures and methods are disclosed herein, but it should be understood that the disclosed embodiments are only examples of the claimed structures and methods that can be embodied in various forms. In addition, each example presented in connection with the various embodiments is intended to be illustrative and not limiting.

[0020] Furthermore, some features may be exaggerated to show details of a particular component, and the drawings are not necessarily to scale. Accordingly, the specific structures and function details disclosed herein should not be construed as limiting, but are merely representative principles for teaching those skilled in the art to utilize the methods and structures of the present disclosure in various ways.

[0021] For the following description, terms such as "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom", and derivatives thereof relate to the exemplary embodiments of the present disclosure as oriented in the drawings. The term "positioned on" means that a first component, such as a first structure, is present above a second component, such as a second structure, and that intervening components, such as an interface structure (e.g., an interface layer), may be present between the first and second components.

[0022] In the present disclosure, when a component, such as a layer, region, or substrate, is described as being "on" or "over" another component, the component is either directly above the other component or intervening components may also be present. In contrast, when a component is described as being "directly on", "directly over", or "on and in direct contact with" another component, no intervening components are present and the component is in contact with the other component.

[0023] The processes, steps, and structures described below do not form a complete process flow for manufacturing an integrated circuit. The present disclosure may be practiced in conjunction with currently used integrated circuit manufacturing techniques in the art, and most of the commonly practiced process steps are included as necessary for an understanding of the different embodiments of the present disclosure. The drawings represent a cross-section of a portion of an integrated circuit during manufacture, but are not drawn to an exact scale and are drawn to show various exemplary features of the present disclosure.

[0024] In an exemplary embodiment, the process for manufacturing a semiconductor structure can utilize two or more silicon carbide layers having different doping types. The silicon carbide layers, in the exemplary embodiment, epitaxially grow in the form of wafers on a base silicon carbide substrate. One or more silicon carbide layers can be doped by implantation. The silicon carbide layers with the base silicon carbide substrate can be collectively referred to as a silicon carbide substrate. Further, an epitaxial layer of a group-III nitride can grow above the uppermost silicon carbide layer of the silicon carbide substrate.

[0025] Further, an optional epitaxial layer of one or more group-III nitride layers can be present on or grow on the first group-III nitride layer. Examples of group-III nitride layers that can be used include, for example, aluminum nitride (AlN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), and other group-III nitrides.

[0026] In an exemplary embodiment, the feature can be at least one of patterning and etching the group-III nitride layer or can be deposited on the group-III nitride layer. The top of this structure can be coated with a low refractive index insulator such as an oxide layer formed from silicon dioxide. The oxide layer is a layer of silicon dioxide that can also be deposited in the form of a wafer on a carrier substrate. In an exemplary embodiment, both wafers are bonded together.

[0027] In an exemplary embodiment, the first base silicon carbide substrate can be at least partially removed by grinding. In these illustrated embodiments, the grinding can be at least one of mechanical grinding, polishing, or chemical mechanical polishing (CMP). Mechanical grinding of the silicon carbide substrate can result in a silicon carbide layer having a non-uniform thickness. The non-uniformity can be reduced when the grinding is performed at a distance measured in centimeters.

[0028] Thereafter, to selectively remove the exposed non-uniform silicon carbide layer, photoelectrochemical (PEC) etching can be performed until the etching stop silicon carbide layer is reached. In this example, the photoelectrochemical etching can be performed from either the carbon or silicon surface of the silicon carbide substrate. Silicon carbide is a crystalline material and can have a silicon or carbon surface depending on the orientation. This silicon carbide layer functions as an etching stop and can be semi-insulating or have at least one of different doping polarities compared to the silicon carbide material removed using photoelectrochemical (PEC) etching.

[0029] In an exemplary embodiment, the resulting set of silicon carbide layers on the set of group III nitride layers can be less than 1 μm thick. In some cases, using the techniques of the exemplary embodiment, it can be less than 50 nm thick.

[0030] In an exemplary embodiment, an additional planarization step can be used. For example, mechanical polishing or chemical mechanical polishing can be performed after at least one of the material growth or photochemical (PEC) etching of the silicon carbide layer substrate. These processes can be performed to reduce roughness at various interfaces.

[0031] Referring now to FIGS. 1-8, cross-sectional views of the process for forming a semiconductor structure according to an exemplary embodiment are shown. In FIG. 1, a cross-sectional view of a silicon carbide substrate according to an exemplary embodiment is shown. As shown, the silicon carbide (SiC) substrate 100 can be in the shape of a wafer. For example, the silicon carbide substrate 100 can be a hexagonal silicon carbide wafer. The silicon carbide material is, for example, 4H or 6H crystal polymorphs in this example. As shown, in this example, the silicon carbide material has a non-centrosymmetric and polar crystal structure. As shown, the wafer has, for example, an area of 25 square centimeters or more.

[0032] In this exemplary embodiment, the silicon carbide substrate 100 has a bonding surface 102 and an etching surface 104. More specifically, the etching surface 104 can be either the carbon surface or the silicon surface of the silicon carbide substrate 100. In this embodiment, the bonding surface 102 is the surface on which additional materials of the semiconductor structure are formed.

[0033] In addition, the silicon carbide substrate 100 has a doped layer 106. Doping to form the doped layer 106 can be performed using any available doping technology currently available, including at least one of diffusion or ion implantation. The doped layer 106 can be a layer with a thickness ranging from about 50 nanometers to several tens of micrometers.

[0034] In this exemplary embodiment, the doped layer 106 can be a p-type layer or an n-type silicon carbide layer. The doping concentration is such that the doped layer 106 can be etched using a photoelectrochemical etching process. In this exemplary embodiment, doping is such that the doped layer 106 is etched by a photoelectrochemical etching process, while the other part of the silicon carbide substrate 100 that is under the doped layer 106 and in direct contact with the doped layer 106 remains unetched.

[0035] Next, referring to FIG. 2, a cross-sectional view of a set of group III nitride layers on a silicon carbide substrate according to an exemplary embodiment is shown. In an exemplary embodiment, the same reference numbers can be used in multiple figures. When reference numbers are repeatedly used in different figures, they represent the same elements in different figures.

[0036] As shown, in this embodiment, a set of group III nitride layers 200 is growing on the bonding surface 102 of the silicon carbide substrate 100. The set of group III nitride layers 200 can be grown using techniques currently available for the formation of nitride layers.

[0037] As used herein, "a set of" when used in connection with items means one or more items. For example, "a set of group III nitride layers 200" is one or more group III nitride layers 200. As shown, the set of group III nitride layers 200 may be thin film layers each having a thickness of from several nanometers to several micrometers. For example, the thin film layer may be less than 1 micrometer.

[0038] In this exemplary embodiment, the set of group III nitride layers 200 includes at least one of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium aluminum gallium nitride (InAlGaN), or other suitable group III nitrides. In this embodiment, the set of group III nitride layers 200 includes an AlN layer having a thickness of at least 10 nanometers. Additionally, AlN, GaN, or Al x Ga 1-x GaN layers can optionally be grown on top of this layer. These additional layers can be, for example, from nanometers to hundreds of microns thick. The numerical value "x" represents the ratio of Al:Ga to the stoichiometry of the material, and in this embodiment, "x" has a value between 0 and 1.

[0039] Referring now to Figure 3, a cross-sectional view of a structure formed using a set of group III nitride layers is shown according to an exemplary embodiment. As shown, a first metal 300 and a second metal 302 are formed on the group III nitride layers 200. The first metal 300 and the second metal 302 can be formed using currently known techniques including industry standard lithography and deposition techniques.

[0040] In addition, the set of group III nitride layers 200 can be patterned and etched using currently known techniques such as hard mask definition, etching of group III nitride materials, hard mask removal, etc. In this embodiment, patterning in the etching forms a first opening 304 and a second opening 306 in the set of group III nitride layers 200 to expose the bonding surface 102.

[0041] Referring now to FIG. 4, a cross-sectional view of silicon dioxide deposited on a silicon carbide substrate coating structure formed on a bonding surface of a silicon carbide substrate is shown according to an exemplary embodiment. In this exemplary embodiment, the first oxide layer 400 is silicon dioxide deposited on the first metal 300, the second metal 302, the set of group III nitride layers 200, and the bonding surface 102 exposed in the first opening 304 and the second opening 306 of the set of group III nitride layers 200. The deposition of silicon dioxide to form the first oxide layer 400 can be carried out using known techniques such as plasma-enhanced chemical vapor deposition, sputtering, or other suitable known techniques for forming the first oxide layer 400.

[0042] As shown, the first oxide layer 400 has a first surface 402. In this embodiment, the first surface 402 can be processed using chemical mechanical polishing (CMP) to improve planarity and reduce surface roughness. Further, the first surface 402 of the first oxide layer 400 can be processed and activated to be a hydrophilic surface.

[0043] Referring now to FIG. 5, a cross-sectional view of a carrier substrate according to an exemplary embodiment is shown. In this exemplary embodiment, the carrier substrate 500 can take a number of different forms. For example, the carrier substrate 500 can be one of a silicon carbide substrate, a silicon substrate, an aluminum oxide substrate, a gallium oxide substrate, a silica substrate, an aluminum nitride substrate, a gallium nitride substrate, and other suitable substrates.

[0044] As shown, the carrier substrate 500 has a second oxide layer 502 with a second surface 504. In this embodiment, the second oxide layer 502 contains silicon dioxide. The second surface 504 can be chemically mechanically polished and processed or activated to be a hydrophilic surface.

[0045] In an exemplary embodiment, the silicon carbide substrate 100 of FIG. 4 and the carrier substrate 500 of FIG. 5 can be coupled to each other. In this exemplary embodiment, the carrier substrate 500 is a substrate for a semiconductor structure. On the other hand, the silicon carbide substrate 100 includes a silicon carbide material that makes up a set of silicon carbide device layers used to form a semiconductor structure.

[0046] As shown, the first surface 402 of the first oxide layer 400 on the bonding surface 102 of the silicon carbide substrate 100 of FIG. 4 can be arranged to contact the second surface 504 of the second oxide layer 502 of FIG. 5. The bonding by van der Waals forces occurs due to the contact between the first surface 402 of the first oxide layer 400 and the second surface 504 of the second oxide layer 502. These substrates bonded to each other by the oxide layers can be annealed. To strengthen the bond formed between the oxide layers of these two substrates, annealing can be performed at at least 150 °C.

[0047] Referring now to FIG. 6, a cross-sectional view of a silicon carbide substrate coupled to a carrier substrate is shown according to an exemplary embodiment. In this exemplary embodiment, the mutual coupling between the silicon carbide substrate 100 and the carrier substrate 500 forms an oxide layer 600. The carrier substrate 500 is a substrate for the semiconductor structure to be formed. The oxide layer 600 is a dielectric layer for the semiconductor structure. In other exemplary embodiments, in addition to or instead of the oxide layer 600, other dielectrics may be used to form a dielectric layer.

[0048] Referring now to FIG. 7, a cross-sectional view showing the removal of a portion of a silicon carbide substrate is shown according to an exemplary embodiment. As shown, the silicon carbide substrate 100 is thinned. This thinning can occur within the stage. For example, the silicon carbide substrate 100 can be ground starting from the etching surface 104 until it reaches the doped layer 106 of the silicon carbide substrate 100. In the illustrated embodiment, the grinding is mechanical grinding that removes most of the silicon carbide substrate 100 up to the doped layer 106. In this exemplary embodiment, the grinding can stop at the doped layer 106 or extend into the doped layer 106.

[0049] Referring now to FIG. 8, a cross-sectional view of a silicon carbide device layer is shown according to an exemplary embodiment. Once the doped layer 106 is reached, additional thinning can be performed using a photoelectrochemical (PEC) etching process. As shown, the photoelectrochemical (PEC) etching is performed on the side of the silicon carbide substrate 100 having the etching surface 104, but this is not being performed using currently available technology.

[0050] This process can be used to remove the doped layer 106. The doping is selected such that other portions of the silicon carbide substrate 100 below the doped layer 106 are removed by the photoelectrochemical etching process. Thus, the doped layer 106 of the silicon carbide substrate 100 functions as a sacrificial layer.

[0051] The portion of the silicon carbide substrate 100 below the doped layer 106 remains as the silicon carbide device layer 800. The silicon carbide device layer 800 is an example of a set of silicon carbide layers. In other exemplary embodiments, there may be multiple silicon carbide layers for use in forming a semiconductor structure. These additional semiconductor carbide layers can have different doping levels to distinguish the layers.

[0052] In this exemplary embodiment, the silicon carbide device layer 800 is a thin film layer. In this exemplary embodiment, the silicon carbide device layer 800 has a thickness ranging from about 10 nanometers to several micrometers. In some exemplary embodiments, the silicon carbide device layer 800 is between about 50 nanometers and about 500 nanometers. Further, the process can be performed to fabricate one or more semiconductor structures using a workpiece including the silicon carbide device layer 800, a stack of group III nitride layers 200, and an oxide layer 600 on a carrier substrate 500.

[0053] With the use of the doped layer 106 and the photoelectrochemical etching process, the silicon carbide device layer 800 can have a higher quality level compared to other currently utilized techniques. For example, the silicon carbide device layer 800 can be a polycrystalline film having a desired uniformity across the wafer. Further, the silicon carbide device layer 800 can reduce mismatches and defects, and as a result, reduce unwanted light absorption or scattering. Further, the process of the exemplary embodiment can result in an epitaxial growth of a desired quality in addition to a desired level of uniformity in film thickness. For example, using the steps of the exemplary embodiment, thickness variations of less than 50 nm can occur across a 100 mm wafer.

[0054] The illustrations of the process for forming the semiconductor structures of FIGS. 1 - 8 are examples of one manner in which the exemplary embodiments can be implemented. The embodiments shown in these figures are not intended to limit the manner in which other exemplary embodiments can be implemented. For example, in another exemplary embodiment, at least one of the stack of group III nitride layers 200, the first metal 300, or the second metal 302 can be excluded.

[0055] Referring now to FIGS. 9 - 12, cross-sections of a process for forming a semiconductor structure are shown in accordance with an exemplary embodiment. First, referring to FIG. 9, a cross-sectional view of a substrate is shown in accordance with an exemplary embodiment. As shown, the silicon carbide substrate 900 includes a base substrate 902, a doped layer 904, and a silicon carbide device layer 906.

[0056] As shown, base substrate 902 is a bulk 4H-SiC wafer having a wafer normal miscut that deviates 4 degrees or other small angle off-axis from the (0001) crystal direction. Doped layer 904 is a first layer grown as an epitaxial layer of 4H-SiC that is doped and becomes a sacrificial portion of silicon carbide substrate 900. In this embodiment, 4H-SiC is deposited with a thickness and doping of a desired specification to form silicon carbide device layer 906 on silicon carbide substrate 900.

[0057] Furthermore, a group III nitride layer stack, aluminum nitride (AlN) layer 908 and gallium nitride (GaN) layer 910, grows on silicon carbide device layer 906. In this embodiment, aluminum nitride layer 908 is an epitaxially grown undoped AlN buffer layer. Gallium nitride layer 910 can be formed to desired specifications using, for example, metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). The doping of gallium nitride layer 910 can be selected at the growth stage depending on the application.

[0058] As shown, first oxide layer 912 is deposited on gallium nitride layer 910. In this embodiment, silicon dioxide (SiO2) can be deposited using a process such as plasma enhanced chemical vapor deposition (PECVD), sputtering, or atomic layer deposition to form first oxide layer 912. In this exemplary embodiment, the growth of the various layers is in the direction of arrow 914. These various layers form workpiece 916.

[0059] Referring now to FIG. 10, a cross-sectional view of the bonding of a workpiece to a carrier substrate is shown according to an exemplary embodiment. As shown, the workpiece 916 is upside down with respect to the display of the workpiece 916 in FIG. 9. Next, the workpiece 916 can be bonded to a carrier substrate 1000 having a second oxide layer 1002. In this example, a bonding surface 1001 and an etching surface 1003 are shown. As shown, the etching surface 1003 can be the silicon surface or the carbon surface of the silicon carbide substrate 900.

[0060] In this exemplary embodiment, the carrier substrate 1000 can be made of silicon carbide, silicon, silica, aluminum oxide, or other suitable materials. As shown, the second oxide layer 1002 is formed using thermal oxidation, plasma enhanced chemical vapor deposition (PEVCD), sputtering, atomic layer deposition, or other suitable processes.

[0061] In this exemplary embodiment, the bonding can be performed by contact between the oxide layers. In this example, the contact is performed after annealing at a temperature of about 200°C.

[0062] In FIG. 11, a cross-sectional view of the removal of silicon carbide material from a silicon carbide substrate is shown according to an exemplary embodiment. In this figure, the mutual bonding of the first oxide layer 912 and the second oxide layer 1002 forms an oxide layer 1100.

[0063] As shown, the silicon carbide substrate 900 is thinned by mechanical grinding and can be polished by chemical mechanical polishing (CMP) as shown in section 1102. Section 1102 shows the removed silicon carbide material. As shown, in this example, the removal reaches into the doped layer 904.

[0064] In this embodiment, mechanical polishing is used to remove a portion rather than all of the doped layer 904. Mechanical grinding and polishing may, in some cases, be suitable over length scales ranging from micrometers to millimeters. However, due to the existence of larger length scales, the thickness of the thin film is desired across the entire wafer, and furthermore, the forces and stresses due to the removal of this type of material can introduce unwanted inconsistencies such as lattice defects, dislocations, and crystal strain.

[0065] In this exemplary embodiment, mechanical grinding stops when the grinding reaches into the doped layer 904. For example, mechanical grinding can stop when the doped layer 904 is approximately a few micrometers thick.

[0066] Referring to FIG. 12, a cross-sectional view of the silicon carbide material reaching the silicon carbide device layer is shown according to an exemplary embodiment. As shown, in this cross-sectional view, an optoelectrochemical etching process is used to remove the remaining portion of the doped layer 904 as shown in section 1200. This etching exposes the silicon carbide device layer 906 without removing material from the silicon carbide device layer 906. The dopant and doping level in the doped layer 904 are selected such that the doped layer 904 is etchable without removing material from the silicon carbide device layer 906.

[0067] Etching with the selected dopant type by optoelectrochemical etching can be performed to remove the doped layer 904 and expose the silicon carbide device layer 906. In this exemplary embodiment, the silicon carbide device layer 906 can have desired properties such as a clean crystal surface with a low level of defect density compared to the use of mechanical grinding.

[0068] In this exemplary embodiment, the optoelectrochemical etching process can be performed while the doped layer 904 is in contact with a solution such as a diluted aqueous potassium hydroxide solution or a hydrofluoric acid aqueous solution.

[0069] Furthermore, the illumination of the carrier substrate 1000 having different layers can be carried out using illumination having a wavelength of light corresponding to a photon energy exceeding the bandgap of silicon carbide. In the illustrated embodiment, since the bandgap of 4H-SiC is about 3.2 eV, the light source includes wavelengths shorter than 390 nm. The voltage bias can be applied between one of the contact points of the doped layer of the sample and the platinum electrode in the aqueous solution. The etching selectivity of p-type, n-type, and intrinsic materials can be adjusted and optimized by controlling the magnitude and direction of the DC voltage bias. Photoelectrochemical etching is related to wet chemistry and can be selected according to the doping type, so the final results of the silicon carbide and group III nitride thin films have the desired level of uniformity and planarity across the wafer. This result is in contrast to currently available techniques such as smart cut that use ion implantation to create an amorphous layer to a specified depth. The photoelectrochemical etching of the exemplary embodiment avoids the introduction of point defects or dopants into the silicon carbide and group III nitride thin films.

[0070] Next, FIGS. 13 to 15 are cross-sectional views of a workpiece etched using photoelectrochemical etching according to an exemplary embodiment. Referring now to FIG. 13, a cross-sectional view of a workpiece according to an exemplary embodiment is shown. As shown, workpiece 1300 results from the bonding of a silicon carbide substrate to a carrier substrate, with the bond formed between the oxide layers on the two substrates.

[0071] In this exemplary embodiment, the workpiece 1300 comprises a silicon substrate 1301 including a doped layer 1302, a doped silicon carbide device layer 1304, a silicon carbide device layer 1306, an aluminum nitride (AlN) layer 1308, a gallium nitride (GaN) layer 1310, an oxide layer 1312, and a carrier substrate 1314. In this embodiment, the doped layer 1302 is the topmost layer and is not disposed on other layers of the silicon substrate 1301 as illustrated in other preceding embodiments. The workpiece 1300 has a bonding surface 1305 and an etching surface 1303. As illustrated, the etching surface 1303 can be a silicon surface or a carbon surface.

[0072] As illustrated, the doped layer 1302 is an n-type layer. In other exemplary embodiments, the doped layer 1302 can be a p-type layer. The doping difference is selected to avoid etching of the doped silicon carbide device layer 1304. In other words, the doping level and doping type are selectable with respect to the doped silicon carbide device layer 1304, such that this layer functions as an etch stop for the photoelectrochemical etching process.

[0073] In this illustrated embodiment, the doped layer 1302 is a sacrificial layer that can be etched using a photoelectrochemical etching process. The doping level of the doped layer 1302 is sufficiently different in doping type, density, or both, from the doped silicon carbide device layer 1304 having a doping type and level that define the etch stop. In this embodiment, the etching selectivity can be maximized when the doped layer 1302 is doped at a concentration exceeding 1x10 18 cm -3 and the doped silicon carbide device layer 1304 has a doping concentration of at least 1x10 18 cm -3 and is of a dopant type opposite to that of the doped layer 1302.

[0074] In this exemplary embodiment, the type of dopant for the doped layer 1302 is n-type, while the type of dopant for the doped silicon carbide device layer 1304 is p-type. If a different type of dopant is desired for the doped silicon carbide device layer 1304, for example, in the case of a p-type dopant, the type of dopant used for the doped layer 1302 can be changed to an n-type dopant.

[0075] In another exemplary embodiment, the sacrificial layer, the doped layer 1302, and the etching stop layer, the doped silicon carbide device layer 1304 are doped to a concentration of about 1x10 17 cm -3 or higher. At a doping level of 1x10 17 cm -3 or higher, the etching rate of silicon carbide can depend on the voltage bias present during photoelectrochemical etching. The etching rate begins to change more significantly with the doping concentration and is a factor that gives photoelectrochemical etching selectivity based on the doping type.

[0076] Furthermore, the doped silicon carbide device layer 1304 can have a thickness of, for example, about 100 nanometers or more. The silicon device layer below the doped silicon carbide device layer 1304 can have any desired thickness formed by growth. For example, the thickness of these layers can be from about 50 nanometers to 200 microns at customizable doping concentrations. Each of the nitride layers such as the AlN layer and the GaN layer can have a thickness suitable for a specific semiconductor device.

[0077] In this exemplary embodiment, the voltage bias can be applied to the surface of the doped layer 1302 through an ohmic contact. Furthermore, the surface of the silicon carbide layer is in contact with an aqueous potassium hydroxide solution and is exposed to light with an energy exceeding the bandgap energy. In this embodiment, the light can have a wavelength of less than 390 nanometers.

[0078] Referring to FIG. 14, a cross-sectional view of the removal of the silicon carbide material is shown according to an exemplary embodiment. In this exemplary embodiment, substrate thinning is performed by grinding and polishing to remove the silicon carbide material from the doped layer 1302, as shown by section 1400 representing the removed silicon carbide material. This polishing can be mechanical polishing, chemical mechanical polishing, or a combination of the two. As can be seen from this embodiment, a portion of the doped layer 1302 remains after grinding and chemical mechanical polishing.

[0079] In FIG. 15, a cross-sectional view of the doped layer within the silicon carbide device layer is shown according to an exemplary embodiment. In this exemplary embodiment, the doped layer 1302 is etched using a photoelectrochemical etching process to reach the doped silicon carbide device layer 1304, which is an etching stop layer in this embodiment. Section 1500 shows the removed silicon carbide material.

[0080] Accordingly, the processes shown in FIGS. 1 - 15 enable the formation of silicon carbide layers for use in devices having desired characteristics. For example, the silicon carbide device layer can be formed on the wafer size scale to have a desired level of uniformity in layer thickness. Additionally, the silicon carbide device layer can be formed with a low level of material damage so that unwanted light absorption or scattering can be avoided. These processes enable obtaining the desired quality for the silicon carbide layer with a device at a larger size compared to current technologies.

[0081] Next, referring to FIG. 16, a diagram of a waveguide coupled to an optical resonator is shown according to an exemplary embodiment. As shown, the waveguide coupled to the optical resonator and filter 1600 is a semiconductor device formed on a carrier substrate 1602 having an oxide layer 1604, an aluminum nitride layer 1606, and a silicon carbide layer 1608. The carrier substrate 1602 having the oxide layer 1604, the aluminum nitride layer 1606, and the silicon carbide layer 1608 can be formed using the processes shown in FIGS. 1 - 8, FIGS. 9 - 12, and FIGS. 13 - 15.

[0082] In this exemplary embodiment, aluminum nitride layer 1606 is in direct contact with silicon carbide layer 1608. In other embodiments, one or more other layers may be disposed between aluminum nitride layer 1606 and silicon carbide layer 1608.

[0083] In this embodiment, the waveguide coupled to optical resonator and filter 1600 has three components. As shown, the waveguide coupled to optical resonator and filter 1600 includes linear waveguide 1601, linear waveguide 1603, and ring waveguide 1605. In this embodiment, the waveguide coupled to optical resonator and filter 1600 filters light of a selected wavelength. For example, light traveling through linear waveguide 1601 can pass through ring waveguide 1605. Ring waveguide 1605 can pass light of one or more selected wavelengths to linear waveguide 1603 and functions as a filter for which light to pass from linear waveguide 1601 to linear waveguide 1603.

[0084] Referring to FIG. 17, a cross-sectional view of a waveguide coupled to an optical resonator and filter is shown according to an exemplary embodiment. In this figure, a cross-sectional view of the waveguide coupled to optical resonator and filter 1600 taken along line 17-17 of FIG. 16 is shown. In this embodiment, the oxide layers are bonded to form oxide layer 1604. Thus, aluminum nitride layer 1606 and silicon carbide layer 1608 are etchable to form a structure that forms linear waveguide 1601, linear waveguide 1603, and ring waveguide 1605.

[0085] Referring to FIG. 18, an integrated optical waveguide including a quantum memory is shown according to an exemplary embodiment. As shown, the quantum memory device 1800 is a semiconductor device formed on a carrier substrate 1802 having an oxide layer 1804, an aluminum nitride region 1806, and a silicon carbide region 1808. In this example, the carrier substrate 1802 having the oxide layer 1804, the aluminum nitride region 1806, and the silicon carbide region 1808 can be formed using the processes shown in FIGS. 1-8, FIGS. 9-12, and FIGS. 13-15.

[0086] As shown, the aluminum nitride region 1806 has side surfaces 1801 and 1803. The silicon carbide region 1808 has side surfaces 1805 and 1807.

[0087] In this example, the quantum memory device 1800 includes a quantum memory 1810 and an integrated optical waveguide 1811. The quantum memory 1810 is coupled to the integrated optical waveguide 1811. The quantum memory 1810 can be formed from defects in the silicon carbide material within the silicon carbide region 1808. The defects can be point defects selected, for example, from complex vacancies, single silicon atom vacancies, other vacancy complexes, transition metal ions, or rare earth element ions within the silicon carbide region 1808. The quantum memory 1810 can emit a photon 1812 in response to a defect or color center and an electron spin associated with the entanglement of the state of the photon with the electron spin state. The photon 1812 emitted from the quantum memory 1810 can move into the integrated optical waveguide 1811.

[0088] Referring to FIG. 19, a cross-sectional view of an integrated optical waveguide including a quantum memory is shown according to an exemplary embodiment. In this figure, a cross-sectional view of the quantum memory device 1800 taken along line 19-19 of FIG. 18 is shown.

[0089] Referring to FIGS. 20 to 23, a fabricated waveguide structure is shown according to one or more exemplary embodiments. These shown waveguide structures can be formed using the processes shown in FIGS. 1 to 8, FIGS. 9 to 12, and FIGS. 13 to 15. These waveguides can also be used in place of the optical waveguide structures depicted in FIGS. 16 and 18, and their cross-sections are shown in FIGS. 17 and 19.

[0090] Referring to FIG. 20, a cross-sectional view of a waveguide according to an exemplary embodiment is shown. As illustrated, waveguide 2000 is an example of a strip waveguide that can be formed in an exemplary embodiment.

[0091] In this illustrated example, waveguide 2000 is formed on carrier substrate 2002. Oxide layer 2004 is disposed on carrier substrate 2002. Aluminum nitride layer 2006 is on oxide layer 2004, and silicon carbide region 2008 is disposed on aluminum nitride layer 2006. As shown in this figure, silicon carbide region 2008 is patterned and etched to form waveguide 2000.

[0092] As used herein, a region is a layer and does not extend infinitely. In this example, the region has defined sides. As illustrated, silicon carbide region 2008 has sides 2001 and 2003.

[0093] Coating 2010 covers silicon carbide region 2008 and aluminum nitride layer 2006. In this example, coating 2010 is in direct contact with silicon carbide region 2008 and aluminum nitride layer 2006. Coating 2010 can include a material selected from at least one of air, vacuum, resistance, polymer, silicon nitride, silicon dioxide, or other materials. In other words, coating 2010 can include two or more types of materials in some exemplary embodiments. In this example, coating 2010 has a refractive index lower than that of silicon carbide region 2008.

[0094] In this exemplary embodiment, the carrier substrate 2002 has a thickness starting from about 100 μm. In this embodiment, the oxide layer 2004 has a thickness of about 3.0 μm. The aluminum nitride layer 2006 has a thickness of about 200 nm, and the silicon carbide region 2008 has a thickness of about 300 nm and a width of about 1.0 μm. The coating material 2010 has a thickness ranging from about 500 nm to about 5.0 μm.

[0095] In this exemplary embodiment, the silicon carbide layer is etchable to form the silicon carbide region 2008, while the aluminum nitride layer 2006 is not etched. This etching can be performed after bonding.

[0096] The cross-section of the structure depicted with respect to the waveguide 2000 in FIG. 20 can be used to form the components of the structure. For example, the silicon carbide region 2008 can be replicated to generate four regions. The two outer regions can each be part of a linear waveguide, and the two inner regions can be for a ring waveguide.

[0097] Referring now to FIG. 21, another cross-sectional view of a waveguide is shown according to an exemplary embodiment. As shown, the waveguide 2100 is an example of a waveguide that can be formed in an exemplary embodiment.

[0098] In this exemplary embodiment, the waveguide 2100 is formed on a manufacturing environment 2102. The oxide layer 2104 is disposed on the carrier substrate 2102. The aluminum nitride layer 2106 is on the oxide layer 2104, and the silicon carbide layer 2108 is disposed on the aluminum nitride layer 2106. Further, the rib region 2110 is a region of silicon carbide extending from the silicon carbide layer 2108. As shown in this figure, the silicon carbide layer 2108 is patterned and etched to form the waveguide 2100 in the form of a rib waveguide having the rib region 2110.

[0099] The waveguide 2100 also has a coating material 2112 that covers the silicon carbide layer 2108 and the rib region 2110. In this embodiment, the coating material 2112 is in direct contact with these components. The coating material 2112 has a refractive index lower than that of the silicon carbide layer 2108 and the rib region 2110.

[0100] In this exemplary embodiment, the carrier substrate 2102 has a thickness starting from about 100 μm. In this embodiment, the oxide layer 2004 has a thickness of about 3.0 μm.

[0101] The aluminum nitride layer 2106 has a thickness of about 200 nm. The silicon carbide layer 2108 has a thickness of about 100 nm. The rib region 2110 extending from the silicon carbide layer 2008 has a thickness of about 200 nm and a width of about 1.0 μm. The coating material 2112 has a thickness from about 500 nm to about 5.0 μm.

[0102] In FIG. 22, a cross-sectional view of a waveguide is shown according to an exemplary embodiment. As shown, the waveguide 2200 is an example of an embedded ridge waveguide structure.

[0103] In this illustrated embodiment, the waveguide 2200 is formed on a carrier substrate 2202. The oxide layer 2204 is disposed on the carrier substrate 2202. The gallium nitride region 2212 is disposed on the oxide layer 2204 of the cavity 2208 within the oxide layer 2204. The aluminum nitride region 2210 is disposed on the gallium nitride region 2212 of the cavity 2208 within the oxide layer 2204. The aluminum nitride region 2210 and the gallium nitride region 2212 are examples of a pair of group III nitride regions that can be embedded within the cavity 2208.

[0104] A region is a layer having defined sides and can be disposed within a range of another material. In this embodiment, the gallium nitride region 2212 has sides 2201 and 2203 to the cavity 2208 within the oxide layer 2204. The aluminum nitride region 2210 has sides 2205 and 2207 to the cavity 2208 within the oxide layer 2204.

[0105] In this embodiment, the silicon carbide layer 2214 is disposed over the oxide layer 2204 and the aluminum nitride region 2210. As shown in this figure, the gallium nitride region 2212 within the cavity 2208 of the silicon carbide layer 2214, the aluminum nitride region 2210, and the oxide layer 2204 form a waveguide 2200. The aluminum nitride region 2210 and the gallium nitride region 2212 form a ridge 2220 embedded in the oxide layer 2204. The refractive index in at least one of the aluminum nitride region 2210 or the gallium nitride region 2212 is greater than the refractive index of the oxide layer 2204.

[0106] As shown, the waveguide 2200 has a cladding 2222 covering the silicon carbide layer 2214. In this exemplary embodiment, the cladding 2222 is in direct contact with the silicon carbide layer 2214. The cladding 2222 has a refractive index smaller than the refractive index of the silicon carbide layer 2214.

[0107] In this exemplary embodiment, the carrier substrate 2202 has a thickness of about 100 μm. The oxide layer 2204 has a thickness of about 3.3 μm in this embodiment. The aluminum nitride layer 2210 has a thickness of about 100 nm, and the gallium nitride layer 2212 has a thickness of about 200 nm. These two layers within the cavity 2208 have a width of about 1.0 μm. As shown, the silicon carbide layer 2214 has a thickness of about 200 nm. The cladding 2222 has a thickness ranging from about 500 nm to about 5.0 μm.

[0108] In this embodiment, the aluminum nitride layer and the gallium nitride region are etched to form the aluminum nitride region 2210 and the gallium nitride region 2212. The first oxide layer is formed to embed the aluminum nitride region 2210 and the gallium nitride region 2212. This first oxide layer is then bonded to a second oxide layer on the carrier substrate 2202. The first oxide layer and the second oxide layer are then bonded to form the oxide layer 2204.

[0109] In this exemplary embodiment, the semiconductor structure depicted in FIG. 22 can be manufactured using the processes shown in the exemplary embodiment. For example, the group III nitride layer can be patterned and etched before oxide deposition and wafer bonding. The waveguide structure can be integrated with a lateral (horizontal) diode, and doping can be performed on the active electronics and depletion layer of the silicon carbide layer 2214. The doped regions can be manufactured by mask implantation followed by annealing, or by in-growth substrate (SiC and GaN) doping followed by patterning and etching, or by a combination thereof. To adjust the resonance frequency of the optical resonator or the light emission frequency of the embedded single photon emitter, it is possible to apply an electric field across these materials or between metal contacts.

[0110] Referring now to FIG. 23, another cross-sectional view of a waveguide is shown according to an exemplary embodiment. As shown, the waveguide 2300 is another embodiment of an embedded optical waveguide structure.

[0111] In this illustrated embodiment, the waveguide 2300 is formed on a carrier substrate 2302. An oxide layer 2304 is disposed on the carrier substrate 2302. A gallium nitride region 2312 is disposed on the oxide layer 2304 of the cavity 2308 within the oxide layer 2304. An aluminum nitride region 2310 is disposed on the gallium nitride region 2312 of the cavity 2308 within the oxide layer 2304. The aluminum nitride region 2310 has side surfaces 2301 and 2303. The gallium nitride region 2312 has side surfaces 2305 and 2307. As shown, the aluminum nitride region 2310 and the gallium nitride region 2312 form a ridge 2317 embedded in the cavity 2308 within the oxide layer 2304.

[0112] In this embodiment, the silicon carbide layer 2314 is disposed over the oxide layer 2304 and the aluminum nitride region 2310. Further, the rib region 2316 extends from the silicon carbide layer 2314. As shown in this figure, the rib region 2316 is a portion of silicon carbide extending from the silicon carbide layer 2314 and is also referred to as a silicon carbide region. As shown, the silicon carbide layer 2314, the rib region 2316, the aluminum nitride region 2310, and the gallium nitride region 2312 within the cavity 2308 of the oxide layer 2304 form the waveguide 2300.

[0113] As shown, the waveguide 2300 has a cladding 2322 that covers the silicon carbide layer 2314 and the rib region 2316. As shown, the cladding 2222 is in direct contact with the silicon carbide layer 2214 and the rib region 2316. The cladding 2222 has a lower refractive index than the silicon carbide layer 2214 and the rib region 2316.

[0114] In this exemplary embodiment, the carrier substrate 2302 has a thickness of from about 100 μm. The oxide layer 2304 has a thickness of about 3.3 μm in this embodiment. The aluminum nitride region 2310 has a thickness of about 100 nm, and the gallium nitride region 2312 has a thickness of about 200 nm. These two regions within the cavity 2308 have a width of about 1.0 μm. As shown, the silicon carbide layer 2214 has a thickness of about 100 nm. The rib region 2316 has a width of about 1.0 μm and a thickness of about 200 nm. The cladding 2322 has a thickness of from about 500 nm to about 5.0 μm.

[0115] The illustrations of the waveguide structures of FIGS. 20-23 are provided as one type of example of a semiconductor structure that can be fabricated in accordance with one or more exemplary embodiments. These illustrations are not intended to limit the manner in which other exemplary embodiments may be implemented.

[0116] For example, the thicknesses shown for these layers and regions are examples of thicknesses that are usable for thin film implementation. These thicknesses are not intended to limit the thicknesses usable in other exemplary embodiments.

[0117] Furthermore, the number and type of group III nitride layers and regions may be different from those shown in FIGS. 20-23. For example, indium nitride (InN) layers and indium aluminum gallium nitride (InAlGaN) layers can be used in addition to or instead of the illustrated aluminum nitride (AlN) and gallium nitride (GaN) layers.

[0118] As another example, in addition to or instead of the waveguide structure, other types of semiconductor structures can be fabricated. For example, the semiconductor structure can include at least one of a superconducting single photon detector, a light emitter, a quantum memory utilizing point defects within a silicon carbide device layer, or other suitable types of components of a semiconductor structure.

[0119] Additional embodiments of semiconductor structures having one or more silicon carbide device layers and one or more group III nitride layers that can be fabricated using the steps of one or more exemplary embodiments include microelectromechanical systems and photonic components including waveguide-coupled 4-port or 2-port ring resonators or filters. In yet another exemplary embodiment, in addition to photonic components, electrical components, and mechanical components, superconducting materials can be deposited in a manner that enables the operation of superconducting nanowire single photon detectors and logic components at cryogenic temperatures.

[0120] As another example, a slot waveguide can be used to select optical modes with respect to a low refractive index cladding or vacuum outside the substrate by etching two ridges disposed at a narrow interval. The spacing can be, for example, less than a few hundred nanometers. As another example, suspended waveguides can be fabricated from a material stack similar to that depicted in these figures by performing lithographic patterning within a selected region and then chemically etching away the oxide (SiO2). This can result in an optical spatial mode that extends air or alternatively a vacuum within the oxide layer.

[0121] Referring now to FIG. 24, another example of a silicon carbide substrate with a group III nitride stack is shown according to an exemplary embodiment. In this exemplary embodiment, workpiece 2400 is an example of a layer that can be formed and bonded to a carrier substrate such as carrier substrate 500 of FIG. 5.

[0122] In this example, the silicon carbide substrate 2402 of workpiece 2400 includes a base substrate 2404, a p-type silicon carbide layer 2406, an n-type silicon carbide layer 2408, an undoped silicon carbide layer 2410, and a p-type silicon carbide layer 2412. As shown, the p-type silicon carbide layer 2406 is a sacrificial layer for performing photoelectrochemical etching. The other silicon carbide layers are examples of silicon carbide device layers that can be used to form a semiconductor structure. In this example, in addition to being a device layer, the n-type silicon carbide layer 2408 can function as an etch stop.

[0123] In this exemplary embodiment, the base substrate 2404 has a thickness of about 350 μm. As shown, the sacrificial layer, the p-type silicon carbide layer 2406, has a thickness of about 5 μm. In this example, the n-type silicon carbide layer 2408 has a thickness of about 0.1 μm, the undoped silicon carbide layer 2410 has a thickness of about 0.2 μm, and the p-type silicon carbide layer 2412 has a thickness of about 0.1 μm.

[0124] As shown, the group-III nitride layer grows on the p-type silicon carbide layer 2412 of the silicon carbide substrate 2402. These group-III nitride layers include an undoped aluminum nitride layer 2414 and an undoped gallium nitride layer 2416. In this exemplary embodiment, the undoped aluminum nitride layer 2414 has a thickness of about 0.1 μm, and the undoped gallium nitride layer 2416 has a thickness of about 0.4 μm.

[0125] In this illustrated embodiment, the oxide layer 2418 is deposited on the undoped gallium nitride layer 2416. The oxide layer 2418 has a thickness of about 0.2 μm in this embodiment.

[0126] By the workpiece 2400, thin films of silicon carbide and group-III nitrides can be stacked on top of a material having a low refractive index (n) such as SiO2. n is about 1.4 for SiO2, 2.1 / 2.3 for single-crystal AlN / GaN, and 2.6 for 4H-SiC. As a result, the optical mode of the photonic device can remain within at least one of the silicon carbide or group-III nitride layers without emitting or losing optical energy to the underlying bulk substrate material.

[0127] Furthermore, the silicon carbide layer within the group-III nitride layers depicted within the workpiece 2400 can be used to create a p-i-n junction within the silicon carbide material. In this embodiment, the use of the undoped aluminum nitride layer 2414 can be beneficial, causing fewer non-passivated interface states (especially at very low temperatures) compared to the exposed surface of the SiC or the direct interface between silicon carbide and the oxide. The use of one or more additional group-III nitride layers is optional in the exemplary embodiment.

[0128] The illustration of the workpiece 2400 is provided as an example of one embodiment in which a silicon carbide substrate having a set of group-III nitride layers can be implemented. This illustration is not intended to limit the manner in which other exemplary embodiments may be implemented.

[0129] For example, other exemplary embodiments may have other numbers of layers with the silicon carbide substrate. In some exemplary embodiments, the layer adjacent to the sacrificial layer may not be a layer having a doping type opposite to that of the sacrificial layer, but rather an undoped layer. In yet another exemplary embodiment, three, five, or some other number of group III nitride layers may be employed. Further, exemplary thicknesses of the layers are provided as examples of thicknesses that may be used with thin film layers. In other embodiments, other thicknesses may be used.

[0130] Referring now to FIG. 25, a flow diagram of a process for forming a semiconductor structure is shown in accordance with an exemplary embodiment. The process begins by bonding a first oxide layer disposed on a set of group III nitride layers formed on a silicon carbide substrate to a second oxide layer disposed on a carrier substrate to form an oxide layer disposed between the carrier substrate and the group III nitride layers (step 2500). The silicon carbide substrate has a doped layer.

[0131] The process etches the silicon carbide substrate having the doped layer using a photoelectrochemical etching process (step 2502). The doping level of the doped layer is a level at which the doped layer is removed and the silicon carbide device layer of the silicon carbide substrate remains unetched. In step 2502, the doped layer is a sacrificial layer that enables the formation of a silicon carbide device layer on the substrate, such as a wafer having at least one of a desired uniformity of the thickness of the silicon carbide device layer or a desired level of optical performance. In step 2502, the photoelectrochemical etching is performed on an etching surface that can be a silicon face, which in this example is the carbon face of the silicon carbide material. The photoelectrochemical etching can also be performed on an etching surface that is the silicon face of the silicon carbide material.

[0132] The process forms a semiconductor structure using a combination of a silicon carbide device layer and a group III nitride layer (step 2504). The process then ends. In this example, the silicon carbide device layer and the group III nitride layer can be thin film layers. The semiconductor structure is selected from at least one of an optical waveguide, a slot waveguide, a ridge waveguide, a rib waveguide, a buried optical waveguide, a suspended waveguide, an optical resonator, a photonic emission quantum memory utilizing point defects in the silicon carbide device layer, or other suitable structures. The semiconductor structure can include a plurality of components. For example, the semiconductor structure can include a plurality of waveguides of the same type or different types. As another example, the semiconductor structure can include one or more waveguides and a quantum memory. These components or other components can be selected to provide one or more desired functions to the semiconductor structure.

[0133] Referring next to FIG. 26, a flow diagram of a process for forming a semiconductor structure is shown according to an exemplary embodiment. The process begins by forming a group III nitride layer combination on a silicon carbide substrate (step 2600). The silicon carbide substrate includes a doped layer. The doped layer has a doping level such that the doped layer is etched using a photoelectrochemical etching process while other portions of the silicon carbide substrate remain unetched. In other exemplary embodiments, forming the group III nitride layer combination can include etching the group III nitride layer combination to form a structure.

[0134] The process forms a first oxide layer on the group III nitride layer combination, and the group III nitride layer combination is disposed between the first oxide layer and the silicon carbide substrate (step 2602). The process bonds the first oxide layer to a second oxide layer on a carrier substrate to form an oxide layer disposed between the carrier substrate and the group III nitride layer combination (step 2604).

[0135] The process grinds the silicon carbide substrate (step 2606). When a portion of the doped layer of the silicon carbide substrate is exposed, the process stops grinding (step 2608). In step 2608, the portion of the doped exposed layer may be the uppermost portion of the doped layer or a portion within the doped layer.

[0136] When the doped layer is removed and a portion of the doped layer of the silicon carbide substrate is exposed, the process etches the silicon carbide substrate using photoelectrochemical etching (step 2610) so that the silicon carbide device layer of the silicon carbide substrate remains.

[0137] The process forms a semiconductor structure using a combination of the silicon carbide device layer and the group III nitride layer (step 2612). The process then ends.

[0138] Next, referring to FIG. 27, a diagram of a bonding component according to an exemplary embodiment is shown. The flowchart of FIG. 27 is an example of the implementation of step 2500 of FIG. 25 and step 2604 of FIG. 26.

[0139] The process is initiated by bringing the first surface of the first oxide layer into contact with the second surface of the second oxide layer (step 2700). In step 2700, intermolecular interactions occur between the first oxide layer and the second oxide layer. These intermolecular interactions include, for example, van der Waals forces, hydrogen bonds, or strong covalent bonds.

[0140] The process anneals the first oxide layer and the second oxide layer, while the first surface is in direct contact with the second surface to form an oxide layer disposed between the carrier substrate and the combination of the group III nitride layer (step 2702). In this example, the annealing in step 2702 is optional. The process then ends.

[0141] Referring to FIG. 28, a flowchart of a process for forming a semiconductor structure is shown according to an exemplary embodiment. The process begins by bonding a first oxide layer disposed on a silicon carbide substrate to a second oxide layer disposed on a carrier substrate to form an oxide layer disposed between the carrier substrate and the silicon carbide substrate (step 2800).

[0142] In step 2800, the silicon carbide substrate has a doped layer. Further, in an exemplary embodiment, the first oxide layer is in direct contact with the silicon carbide substrate. In another exemplary embodiment, a set of intervening layers, such as a set of group III nitride layers, is disposed between the first silicon layer and the silicon carbide substrate.

[0143] The process etches the silicon carbide substrate having the doped layer using a photoelectrochemical etching process (step 2802). In step 2802, the doping level of the doped layer is at a level where the doped layer is removed and the silicon carbide device layer of the silicon carbide substrate remains unetched.

[0144] The process forms a semiconductor structure using the silicon carbide device layer (step 2804). In step 2804, other materials may also be utilized to form the semiconductor structure. For example, a set of group III layers or regions may be formed in this step. Also, a coating material, a metal layer, or a metal region may be formed in step 2804 to form the semiconductor structure.

[0145] The flowcharts and block diagrams in the various illustrated embodiments illustrate the structure, functionality, and operation of some possible implementations of the apparatus and methods of the exemplary embodiments. In this regard, each block in the flowchart or block diagram can represent at least one of a module, segment, function, or part of a process or step. For example, to control manufacturing equipment for manufacturing a semiconductor structure, one or more blocks can be implemented as program code, hardware, or a combination of program code and hardware. When implemented in hardware, the hardware can take the form of, for example, an integrated circuit manufactured or configured to perform one or more processes of the flowchart or block diagram. When implemented as a combination of program code and hardware, this implementation can take the form of firmware. Each block of the flowchart or block diagram can be implemented using special-purpose hardware for performing various processes to operate manufacturing equipment for manufacturing a semiconductor structure, or a combination of special-purpose hardware and program code executed by the special-purpose hardware.

[0146] In some alternative implementations of the exemplary embodiments, one or more of the functions described in the blocks may be performed out of the order shown in the figures. For example, in some cases, two blocks shown in succession may be performed substantially simultaneously, or depending on the functions involved, the blocks may be performed in reverse order. Also, other blocks may be added in addition to those depicted in the flowchart or block diagram.

[0147] For example, the bonding performed in step 2604 is shown to be performed prior to the etching of the silicon carbide substrate in step 2610. In other exemplary embodiments, the bonding in step 2604 may be performed after the etching that occurs in step 2610. As another example, other dielectrics having desired properties such as a desired dielectric constant can be used instead of or in addition to the silicon dioxide shown and described in the figures.

[0148] Referring to FIG. 29 here, a block diagram of a product management system is shown according to an exemplary embodiment. The product management system 2900 is a physical hardware system. In this exemplary embodiment, the product management system 2900 includes at least one of a manufacturing system 2902 or a maintenance system 2904.

[0149] The manufacturing system 2902 is configured to manufacture products. As shown, the manufacturing system 2902 includes manufacturing equipment 2906. The manufacturing equipment 2906 includes at least one of fabrication equipment 2908 or assembly equipment 2910.

[0150] The fabrication equipment 2908 is equipment used to fabricate components for parts used to form products. Using the fabrication equipment 2908, at least one of metal parts, composite parts, semiconductors, circuits, fasteners, ribs, outer panel, spars, antennas, or other suitable types of parts can be fabricated.

[0151] For example, the fabrication equipment 2908 may include machines and tools. These machines and tools may be at least one of a drill, a hydraulic press, a combustion chamber, a mold, a composite tape laying machine, a vacuum system, a lathe, or other suitable types of equipment.

[0152] Regarding the fabrication of semiconductor components, the fabrication equipment 2908 may include at least one of an epitaxial reactor, an oxidation system, a diffusion system, an etching machine, a cleaning machine, a bonding machine, a dicing machine, a wafer saw, an ion implantation machine, a physical vapor deposition system, a chemical vapor deposition system, a photolithography system, an electron beam lithography system, a plasma etcher, a die attachment machine, a wire bonder, a die overcoat system, a molding device, a hermetic sealer, an electrical tester, a burn-in oven, a holding bake oven, a UV eraser machine, or other suitable types of equipment that can be used in the manufacture of semiconductor structures.

[0153] The assembly equipment 2910 is equipment used to assemble parts to form products such as chips, integrated circuits, computers, aircraft, or other products. The assembly equipment 2910 may also include machines and tools. Such machines and tools may be at least one of a robotic arm, a crawler, a fastener installation system, a rail-based drill system, or a robot.

[0154] In this exemplary embodiment, the maintenance system 2904 includes maintenance equipment 2912. The maintenance equipment 2912 may include any equipment necessary for performing maintenance on the product. The maintenance equipment 2912 may include tools for performing various processes on the parts on the product. These processes may include at least one of disassembly of parts, repair of parts, inspection of parts, reworking of parts, manufacture of replacement parts, or other processes for performing maintenance on the product. These processes may be regular maintenance, inspection, updating, repair, or other types of maintenance processes.

[0155] In this exemplary embodiment, the maintenance equipment 2912 may include an ultrasonic inspection device, an X-ray imaging system, a vision system, a drill, a crawler, and other suitable devices. In some cases, the maintenance equipment 2912 may include the manufacturing equipment 2908, the assembly equipment 2910, or both for producing and assembling the parts required for maintenance.

[0156] The product management system 2900 also includes a control system 2914. The control system 2914 is a hardware system and may further include software or other types of components. The control system 2914 is configured to control at least one process of the manufacturing system 2902 or the maintenance system 2904. Specifically, the control system 2914 may control at least one process of the manufacturing equipment 2908, the assembly equipment 2910, or the maintenance equipment 2912.

[0157] The hardware within control system 2914 can be implemented using hardware that can include computers, circuits, networks, and other types of devices. The control can take the form of direct control of manufacturing equipment 2906. For example, robots, computer-controlled machines, and other devices can be controlled by control system 2914. In other exemplary embodiments, control system 2914 can manage the processes performed by personnel 2916 in the execution of product manufacturing or maintenance. For example, control system 2914 can assign tasks, give instructions, display models, or perform other processes for managing the processes performed by personnel 2916. In these exemplary embodiments, the various steps described and illustrated for fabricating semiconductor structures using silicon carbide and group III nitride layers can be implemented using control system 2914.

[0158] In various exemplary embodiments, personnel 2916 can operate or interact with at least one of manufacturing equipment 2906, maintenance equipment 2912, or control system 2914. This interaction occurs when manufacturing semiconductor devices or components for use in semiconductor structures and other components of products, such as products for use in aircraft, spacecraft, communication systems, microelectromechanical systems, photonic devices, or superconducting single-photon detectors.

[0159] Accordingly, exemplary embodiments provide a method, apparatus, and system for manufacturing a semiconductor structure. In one exemplary embodiment, the method forms a semiconductor structure. A first oxide layer disposed on a set of III-nitride layers formed on a silicon carbide substrate is bonded to a second oxide layer disposed on a carrier substrate, forming an oxide layer disposed between the carrier substrate and the set of III-nitride layers. The silicon carbide substrate has a doped layer. The silicon carbide substrate having the doped layer is etched using a photoelectrochemical etching process, and the doping level of the doped layer is at a level where the doped layer is removed and the silicon carbide layer of the silicon carbide substrate remains unetched. The semiconductor structure is formed using the silicon carbide layer and the III-nitride layer.

[0160] Furthermore, the processes in the exemplary embodiments are suitable for processing large-area wafers, such as wafers with an area of 10 cm 2 or more. The exemplary embodiments are compatible with the processes currently used for these types of wafers to fabricate silicon carbide and III-nitride based crystal structures with low refractive index insulators, low loss, and high thickness uniformity thereon. This enables the fabrication of active and passive integrated photonics and electronics in silicon carbide and III-nitride.

[0161] For example, the exemplary embodiments may include wafer bonding and subsequent grinding / polishing or chemical mechanical polishing for thinning the silicon carbide substrate and then for photoelectrochemical etching from the carbon face of the silicon carbide substrate. The photoelectrochemical etching used in the described embodiments utilizes its material-selective etching characteristics to planarize the silicon carbide layer to a clean crystal interface, resulting in a uniform silicon carbide film thickness.

[0162] To promote photoelectrochemical etching, the electrode can be attached to another doped layer of a silicon carbide layer disposed under the surface to be etched, or to the doped layer to be etched, and the second electrode can be disposed in the etching solution. Applying photoelectrochemical etching in this way provides a different process for forming silicon carbide on an insulator film as compared to currently utilized techniques. Further, the steps of the exemplary embodiments can be used to form sub-micron thick films of silicon carbide and group III nitrides in a manner that maintains a doped layer (e.g., a p-i-n junction) and structure under the exposed silicon carbide surface.

[0163] In an exemplary embodiment, the resulting reconstruction can take many different forms. For example, but not limited to, the semiconductor structure can be selected from at least one of an optical waveguide, a slot waveguide, a ridge waveguide, a rib waveguide, a buried optical waveguide, a suspended waveguide, an optical resonator, and a photonic emission quantum memory utilizing point defects within a silicon carbide device layer. In other words, the semiconductor structure can include one or more of these devices and can include multiple devices of the same type.

[0164] The description of various exemplary embodiments is presented for purposes of illustration and description and is not intended to be exhaustive or to limit the embodiments to the disclosed forms. Components that perform operations or steps are described by various examples. In an exemplary embodiment, a component can be configured to perform the described operations or steps. For example, the component can have a structure configuration or design that provides the component with the ability to perform the operations or steps described as being performed by the component in the exemplary embodiments. Further, although the terms "includes", "including", "has", "contains", or variations thereof are used herein, such terms are intended to be inclusive in the same manner as the term "comprises" as an open transition word that does not exclude any additional or other components.

[0165] Furthermore, the present disclosure includes embodiments according to the following clauses.

[0166] Clause 1. A method for forming a semiconductor structure, comprising: forming a group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) on a silicon carbide substrate (100, 1003), wherein the silicon carbide substrate (100, 1003) includes a doped layer (106, 904, 1302), and the doped layer (106, 904, 1302) has a doping level such that the doped layer (106, 904, 1302) is etched using a photoelectrochemical etching process while other portions of the silicon carbide substrate (100, 1003) remain unetched, and forming a group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312); Forming (2602) a first oxide layer (402, 912) on the group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312), wherein the group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) is disposed between the first oxide layer (402, 912) and the silicon carbide substrate (100, 1003), and forming (2602) a first oxide layer (402, 912), Bonding the first oxide layer (402, 912) to a first oxide layer (504, 1002) on a carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form (2604) an oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) disposed between the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312), Grinding (2606) the silicon carbide substrate (100, 1003), Stopping (2608) the grinding when reaching a portion of the doped layer (106, 904, 1302) of the silicon carbide substrate (100, 1003), Etching (2610) the silicon carbide substrate (100, 1003) using the photoelectrochemical etching process such that when the doped layer (106, 904, 1302) is removed and the portion of the doped layer (106, 904, 1302) of the silicon carbide substrate (100, 1003) is exposed, the silicon carbide device layer (100, 906) of the silicon carbide substrate (100, 1003) remains, Forming the semiconductor structure (2612) using the silicon carbide device layer (100, 906) and the group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312); A method comprising.

[0167] Clause 2. The method according to clause 1, wherein bonding the first oxide layer (402, 912) to the first oxide layer (504, 1002) on the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form the oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) disposed between the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) is performed after etching of the silicon carbide substrate (100, 1003).

[0168] Clause 3. The method according to clause 1 or 2, wherein the first oxide layer (402, 912) is bonded to the first oxide layer (504, 1002) on the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form the oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) disposed between the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312), and the formation is performed after etching of one group III nitride layer of the group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312).

[0169] Clause 4. The method according to any one of clauses 1 to 3, wherein the first oxide layer (402, 912) is bonded to the first oxide layer (504, 1002) on the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form the oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) disposed between the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312), and the formation is performed before etching of the silicon carbide substrate (100, 1003).

[0170] Clause 5. Bonding the first oxide layer (402, 912) to the first oxide layer (504, 1002) on the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form the oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) disposed between the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) is contacting (2700) a first surface of the first oxide layer (402, 912) with a second surface of the first oxide layer (504, 1002), such that an intermolecular interaction occurs between the first oxide layer (402, 912) and the first oxide layer (504, 1002), annealing (2702) the first oxide layer (402, 912) and the first oxide layer (504, 1002) while the first surface is in direct contact with the second surface to form the oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) disposed between the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312); and The method according to any one of clauses 1 to 4, comprising

[0171] Clause 6. When the doped layer (106, 904, 1302) is removed and the portion of the doped layer (106, 904, 1302) of the silicon carbide substrate (100, 1003) is exposed, etching the silicon carbide substrate (100, 1003) using the photoelectrochemical etching process such that the silicon carbide device layer (100, 906) of the silicon carbide substrate (100, 1003) remains, The method according to any one of clauses 1 to 5, comprising etching one of the silicon surface and the carbon surface of the silicon carbide substrate (100, 1003) using the photoelectrochemical etching process such that the silicon carbide device layer (100, 906) of the silicon carbide substrate (100, 1003) remains when the doped layer (106, 904, 1302) is removed and the portion of the doped layer (106, 904, 1302) of the silicon carbide substrate (100, 1003) is exposed.

[0172] Clause 7. The method according to any one of clauses 1 to 6, wherein the doped layer (106, 904, 1302) is a sacrificial layer that enables the formation of the silicon carbide device layer (100, 906) on a wafer having at least one of a desired uniformity in the thickness of the silicon carbide device layer (100, 906) or a desired optical performance level.

[0173] Clause 8. The method according to clause 1, wherein the semiconductor structure is selected from at least one of an optical waveguide, a slot waveguide, a ridge waveguide, a rib waveguide, a buried optical waveguide, a suspended waveguide, an optical resonator, or a photonic emission quantum memory utilizing point defects in the silicon carbide device layer (100, 906).

[0174] Clause 9. The method according to any one of clauses 1 to 8, wherein the silicon carbide device layer (100, 906) and the group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) are thin film layers.

[0175] Clause 10. The method according to Clause 1, wherein the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) is one of a silicon carbide substrate (100, 1003), a silicon substrate, an aluminum oxide substrate, a gallium oxide substrate, a silica substrate, an aluminum nitride substrate, and a gallium nitride substrate.

[0176] Clause 11. The method according to any one of Clauses 1 to 10, wherein the group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) includes at least one of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and indium aluminum gallium nitride (InAlGaN).

[0177] Clause 12. A method for forming a semiconductor structure, bonding (2800) a first oxide layer (402, 912) disposed on a group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) formed on a silicon carbide substrate (100, 1003) to a first oxide layer (504, 1002) disposed on a carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form an oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) disposed between the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312), wherein the silicon carbide substrate (100, 1003) has a doped layer (106, 904, 1302); and Etching the silicon carbide substrate (100, 1003) having the doped layer (106, 904, 1302) using photoelectrochemical etching (2082), wherein the doping level of the doped layer (106, 904, 1302) is such that the doped layer (106, 904, 1302) is removed and the silicon carbide device layer (100, 906) of the silicon carbide substrate (100, 1003) remains without being etched, etching (2082); Forming the semiconductor structure (2804) using the silicon carbide device layer (100, 906) and the group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312); A method comprising.

[0178] Clause 13. Grinding the silicon carbide substrate (100, 1003) (2606) before etching the silicon carbide substrate (100, 1003); Stopping the grinding of the silicon carbide substrate (100, 1003) (2608) when reaching a portion of the doped layer (106, 904, 1302) of the silicon carbide substrate (100, 1003) before etching the silicon carbide substrate (100, 1003); The method according to clause 12, further comprising.

[0179] Clause 14. Forming the group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) on the silicon carbide substrate (100, 1003) (2600); Forming the first oxide layer (402, 912) on the group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312), wherein the group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) is disposed between the first oxide layer (402, 912) and the silicon carbide substrate (100, 1003), and forming the first oxide layer (402, 912), The method according to claim 12 or 13, further comprising.

[0180] Clause 15. Bonding the first oxide layer (402, 912) disposed on the group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) formed on the silicon carbide substrate (100, 1003) to the first oxide layer (504, 1002) disposed on the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form the oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) disposed between the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) is performed after etching the silicon carbide substrate (100, 1003), the method according to any one of clauses 12 to 14.

[0181] Clause 16. Bonding the first oxide layer (402, 912) to the first oxide layer (504, 1002) on the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form the oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) disposed between the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) is performed after etching one group III nitride layer of the group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312), and is the method according to any one of Clauses 12 to 15.

[0182] Clause 17. Bonding the first oxide layer (402, 912) disposed on the group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) formed on the silicon carbide substrate (100, 1003) to the first oxide layer (504, 1002) disposed on the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form the oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) disposed between the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) is performed before etching the silicon carbide substrate (100, 1003), and is the method according to any one of Clauses 12 to 16.

[0183] Item 18. The first oxide layer (402, 912) disposed on the group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) formed on the silicon carbide substrate (100, 1003) is bonded to the first oxide layer (504, 1002) disposed on the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402), and the oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) disposed between the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) is formed, contacting (2700) the first surface of the first oxide layer (402, 912) with the second surface of the first oxide layer (504, 1002), such that an intermolecular interaction occurs between the first oxide layer (402, 912) and the first oxide layer (504, 1002), while the first surface is in direct contact with the second surface, annealing (2702) the first oxide layer (402, 912) and the first oxide layer (504, 1002) to form the oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) disposed between the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312); The method according to any one of Items 12 to 17, including.

[0184] Clause 19. The doping layer (106, 904, 1302) is a sacrificial layer that enables the formation of the silicon carbide device layer (100, 906) on a wafer having at least one of a desired uniformity in the thickness of the silicon carbide device layer (100, 906) or a desired optical performance level, according to any one of Clauses 12 to 18.

[0185] Clause 20. The semiconductor structure is selected from at least one of an optical waveguide, a slot waveguide, a ridge waveguide, a rib waveguide, an embedded optical waveguide, a suspended waveguide, an optical resonator, or a photonic emission quantum memory utilizing point defects in the silicon carbide device layer (100, 906), according to any one of Clauses 12 to 19.

[0186] Clause 21. The silicon carbide device layer (100, 906) and the group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) are thin film layers, according to any one of Clauses 12 to 20.

[0187] Clause 22. The carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) is one of a silicon carbide substrate (100, 1003), a silicon substrate, an aluminum oxide substrate, a gallium oxide substrate, a silica substrate, an aluminum nitride substrate, and a gallium nitride substrate, according to any one of Clauses 12 to 21.

[0188] Clause 23. The group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) includes at least one of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and indium aluminum gallium nitride (InAlGaN), according to any one of Clauses 12 to 22.

[0189] Clause 24. A method for forming a semiconductor structure, comprising: Bonding (2800) a first oxide layer (402, 912) disposed on a silicon carbide substrate (100, 1003) to a first oxide layer (504, 1002) disposed on a carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form an oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) disposed between the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the silicon carbide substrate (100, 1003), wherein the silicon carbide substrate (100, 1003) has a doped layer (106, 904, 1302); Etching (2802) the silicon carbide substrate (100, 1003) having the doped layer (106, 904, 1302) using a photoelectrochemical etching process, wherein the doping level of the doped layer (106, 904, 1302) is at a level such that the doped layer (106, 904, 1302) is removed and the silicon carbide device layer (100, 906) of the silicon carbide substrate (100, 1003) remains unetched; Forming (2804) the semiconductor structure using the silicon carbide device layer (100, 906); A method comprising the above steps.

[0190] Clause 25. The etching of the silicon carbide substrate (100, 1003) having the doped layer (106, 904, 1302) using the photoelectrochemical etching process comprises: Etching the carbon surface of the silicon carbide substrate (100, 1003) having the doped layer (106, 904, 1302) using photoelectrochemical etching, wherein the doping level of the doped layer (106, 904, 1302) is such that the doped layer (106, 904, 1302) is removed and the silicon carbide device layer (100, 906) of the silicon carbide substrate (100, 1003) remains without being etched. The method according to claim 24, comprising etching the carbon surface.

[0191] Claim 26. The method according to claim 24 or 25, wherein the first oxide layer (402, 912) is in direct contact with the silicon carbide substrate (100, 1003).

[0192] Claim 27. A group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) is disposed between the first oxide layer (402, 912) and the silicon carbide substrate (100, 1003). The method according to any one of claims 24 to 26.

[0193] Claim 28. A product management system (2900) comprising a manufacturing apparatus (2914) and a control system, wherein the control system causes the manufacturing apparatus (2914) to A first oxide layer (402, 912) disposed on a group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) formed on a silicon carbide substrate (100, 1003) is bonded to a first oxide layer (504, 1002) disposed on a carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form an oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) disposed between the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312), wherein the silicon carbide substrate (100, 1003) has a doped layer (106, 904, 1302), and forming; Etching the silicon carbide substrate (100, 1003) having the doped layer (106, 904, 1302) using photoelectrochemical etching (2082), wherein the doping level of the doped layer (106, 904, 1302) is such that the doped layer (106, 904, 1302) is removed and the silicon carbide device layer (100, 906) of the silicon carbide substrate (100, 1003) remains without being etched, and etching; Forming the semiconductor structure using the silicon carbide device layer (100, 906) and the group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312); A product management system (2900) for controlling to perform.

[0194] Clause 29. The control system further includes the manufacturing equipment (2914). Grinding the silicon carbide substrate (100, 1003) before etching the silicon carbide substrate (100, 1003); Before etching the silicon carbide substrate (100, 1003), when reaching the portion of the doped layer (106, 904, 1302) of the silicon carbide substrate (100, 1003), stopping the grinding of the silicon carbide substrate (100, 1003); The product management system (2900) according to clause 28, which is further controlled to include this.

[0195] Clause 30. The control system causes the manufacturing equipment (2914) to form the group of III-nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) on the silicon carbide substrate (100, 1003); form the first oxide layer (402, 912) on the group of III-nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312), wherein the group of III-nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) is disposed between the first oxide layer (402, 912) and the silicon carbide substrate (100, 1003), and form the first oxide layer (402, 912); The product management system (2900) according to clause 28 or 29, which is controlled to perform the above.

[0196] Clause 31. The semiconductor structure is selected from at least one of an optical waveguide, a slot waveguide, a ridge waveguide, a rib waveguide, a buried optical waveguide, a suspended waveguide, an optical resonator, or a photonic emission quantum memory using point defects in the silicon carbide device layer (100, 906), and the product management system (2900) according to any one of clauses 28 to 30.

[0197] Clause 32. The silicon carbide device layer (100, 906) and the group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) are the product management system (2900) according to any one of Clauses 28 to 31 which are thin film layers.

[0198] Clause 33. The carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) is one of a silicon carbide substrate (100, 1003), a silicon substrate, an aluminum oxide substrate, a gallium oxide substrate, a silica substrate, an aluminum nitride substrate, and a gallium nitride substrate, and is the product management system (2900) according to any one of Clauses 28 to 32.

[0199] Clause 34. The group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) includes at least one of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and indium aluminum gallium nitride (InAlGaN), and is the product management system (2900) according to any one of Clauses 28 to 33.

[0200] Clause 41. A substrate (500, 1000, 1314, 1602, 1802), an oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) on the substrate (500, 1000, 1314, 1602, 1802), a group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) on the oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304), a silicon carbide layer set (100, 906, 1306, 2008, 2108, 2214, 2314) on the group III nitride layer set (200), A semiconductor structure including

[0201] Clause 42. The set of group-III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) on the oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) is a set of group-III nitride regions (2210, 2212), the semiconductor structure according to Clause 41.

[0202] Clause 43. The set of group-III nitride regions (2210, 2212) is embedded in the cavity (2208) of the oxide layer (600), the semiconductor structure according to Clause 42.

[0203] Clause 44. The semiconductor structure according to Clause 43, further including a coating material (2222) on the set of silicon carbide layers (2214), the coating material (2222) having a refractive index smaller than that of the set of silicon carbide layers (2224).

[0204] Clause 45. The set of silicon carbide layers (100, 906, 1306) is a set of silicon carbide regions (2008, 2110, 2316), the semiconductor structure according to any one of Clauses 41 to 44.

[0205] Clause 46. The set of group-III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) on the oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) is a set of group-III nitride regions, the semiconductor structure according to Clause 45.

[0206] Clause 47. The semiconductor structure according to Clause 46, further including defects in the silicon carbide material of the set of silicon carbide layers (1808).

[0207] Clause 48. The defect is one of complex voids, single silicon atom voids, other void composites, transition metal ions, and rare earth element ions, and the semiconductor structure described in Clause 47.

[0208] Clause 49. The set of silicon carbide regions (2008, 2110, 2316) forms a waveguide, and the semiconductor structure described in Clause 45.

[0209] Clause 50. A coating material (2010, 2112, 2322) on the set of silicon carbide regions (2008, 2110, 2316), further including a coating material (2010, 2112, 2322) having a refractive index smaller than the refractive index of the set of silicon carbide regions (2008, 2110, 2316), and the semiconductor structure described in Clause 49.

[0210] Clause 51. The coating material (2010, 2112, 2322) includes a material selected from at least one of air, vacuum, resistance, polymer, silicon dioxide, or silicon nitride, and the semiconductor structure described in Clause 50.

[0211] Clause 52. The set of silicon carbide layers (100, 906, 1306) includes a silicon carbide layer (2108, 2314) and silicon carbide regions (2110, 2316) extending from the silicon carbide layer (2108), and the semiconductor structure described in Clause 51.

[0212] Clause 53. A coating material (2112, 2322) on the silicon carbide layer (2108) and the silicon carbide regions (2110, 2316), further including a coating material (2112, 2322) having a refractive index smaller than the refractive index of the silicon carbide layer (2108) and the silicon carbide regions (2008, 2316), and the semiconductor structure described in Clause 52.

[0213] Clause 54. The semiconductor structure according to Clause 51, wherein the group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) is in direct contact with the oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304).

[0214] Clause 55. The semiconductor structure according to Clause 51, wherein a set of silicon carbide layers is in direct contact with the group III nitride layer (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312).

[0215] Clause 56. The semiconductor structure according to Clause 51, wherein the substrate (500, 1000, 1314, 1602, 1802) is one of a silicon carbide substrate, a silicon substrate, an aluminum oxide substrate, a gallium oxide substrate, a silica substrate, an aluminum nitride substrate, and a gallium nitride substrate.

[0216] Clause 57. The semiconductor structure according to Clause 51, wherein the group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) includes at least one of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and indium aluminum gallium nitride (InAlGaN).

[0217] Clause 58. The semiconductor structure according to Clause 51, wherein the set of silicon carbide layers and the group III nitride layer set (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) are thin film layers.

[0218] Clause 59. The semiconductor structure according to Clause 51, wherein the semiconductor structure is selected from at least one of an optical waveguide, a slot waveguide, a ridge waveguide, a rib waveguide, a buried optical waveguide, a suspended waveguide, or an optical resonator.

[0219] Clause 60. A semiconductor structure comprising a substrate (500, 1000, 1314, 1602, 1802), an oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) on the substrate (500, 1000, 1314, 1602, 1802), and a set of silicon carbide layers (100, 906, 1306, 2008, 2108, 2214, 2314) on the substrate (500, 1000, 1314, 1602, 1802).

[0220] Clause 61. The semiconductor structure according to Clause 60, wherein the set of silicon carbide layers (100, 906, 1306, 2008, 2108, 2214, 2314) is in direct contact with the oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304).

[0221] Clause 62. The semiconductor structure according to Clause 60 or 61, further comprising a set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) on the oxide layer (600), wherein the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) is disposed between the oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) and the set of silicon carbide layers (100, 906, 1306, 2008, 2108, 2214, 2314).

[0222] Clause 63. The semiconductor structure according to any one of Clauses 60 to 62, wherein the set of silicon carbide layers (100, 906, 1306, 2008, 2108, 2214, 2314) is a set of silicon carbide regions (2008, 2110, 2316).

[0223] Clause 64. The set of silicon carbide layers (100, 906, 1306, 2008, 2108, 2214, 2314) includes a silicon carbide layer (2108, 2314) and a silicon carbide region (2110, 2316) extending from the silicon carbide layer, and is the semiconductor structure according to any one of Clauses 60 to 63.

[0224] Clause 65. The semiconductor structure according to Clause 64 further includes a coating material (2112, 2322) on the silicon carbide layer (2108) and the silicon carbide region (2110, 2316), and the coating material (2112, 2322) has a refractive index smaller than that of the silicon carbide layer (2108, 2314) and the silicon carbide region (2110, 2316).

[0225] Clause 66. The semiconductor structure according to Clause 65, wherein the coating material (2112, 2322) includes a material selected from at least one of air, vacuum, resistor, polymer, silicon dioxide, or silicon nitride.

[0226] Clause 67. The set of silicon carbide layers (100, 906, 1306, 2008, 2108, 2214, 2314) is a set of thin film layers, and is the semiconductor structure according to any one of Clauses 60 to 66.

[0227] Clause 68. The substrate (500, 1000, 1314, 1602, 1802) is one of a silicon carbide substrate, a silicon substrate, an aluminum oxide substrate, a gallium oxide substrate, a silica substrate, an aluminum nitride substrate, and a gallium nitride substrate, and is the semiconductor structure according to Clause 60.

[0228] Numerous modifications and variations will be apparent to those skilled in the art. Further, various exemplary embodiments may provide different features compared to other preferred embodiments. One or more selected embodiments are selected and described in order to best explain the principles of the embodiments, the practical applications, and to facilitate the understanding of various modifications suitable for the specific applications contemplated by those skilled in the art in view of the disclosure of the various embodiments.

Claims

1. A method for forming a semiconductor structure, comprising: forming a group III nitride layer stack on a silicon carbide substrate, wherein the silicon carbide substrate includes a doped layer having a doping level such that the doped layer is etched using a photoelectrochemical etching process while other portions of the silicon carbide substrate remain unetched, to form the group III nitride layer stack; forming a first oxide layer on the group III nitride layer stack, wherein the group III nitride layer stack is disposed between the first oxide layer and the silicon carbide substrate; bonding the first oxide layer to a second oxide layer on a carrier substrate to form an oxide layer disposed between the carrier substrate and the group III nitride layer stack; grinding the silicon carbide substrate; stopping the grinding when a portion of the doped layer of the silicon carbide substrate is reached; etching the silicon carbide substrate using the photoelectrochemical etching process such that when the portion of the doped layer of the silicon carbide substrate is exposed, the doped layer is removed and a silicon carbide device layer of the silicon carbide substrate remains; forming the semiconductor structure using the silicon carbide device layer and the group III nitride layer stack; A method comprising the above steps.

2. The method according to claim 1, wherein bonding the first oxide layer to the second oxide layer on the carrier substrate to form the oxide layer disposed between the carrier substrate and the group III nitride layer stack is performed after etching the silicon carbide substrate.

3. The method according to claim 1, wherein bonding the first oxide layer to the second oxide layer on the carrier substrate to form the oxide layer disposed between the carrier substrate and the group III nitride layer stack is performed after etching one of the group III nitride layers of the group III nitride layer stack.

4. The method according to claim 1, wherein bonding the first oxide layer to the second oxide layer on the carrier substrate to form the oxide layer disposed between the carrier substrate and the group III nitride layer stack is performed before etching the silicon carbide substrate.

5. Bonding the first oxide layer to the second oxide layer on the carrier substrate to form the oxide layer disposed between the carrier substrate and the group III nitride layer assembly comprises: Contacting a first surface of the first oxide layer with a second surface of the second oxide layer, the contacting of the first surfaces causing an intermolecular interaction between the first oxide layer and the second oxide layer; Annealing the first oxide layer and the second oxide layer while the first surface is in direct contact with the second surface to form the oxide layer disposed between the carrier substrate and the group III nitride layer assembly; The method according to any one of claims 1 to 4, comprising:

6. Etching the silicon carbide substrate using the photoelectrochemical etching process such that when a portion of the doped layer of the silicon carbide substrate is exposed, the doped layer is removed and the silicon carbide device layer of the silicon carbide substrate remains; The method according to any one of claims 1 to 5, comprising etching one of a silicon surface and a carbon surface of the silicon carbide substrate using the photoelectrochemical etching process such that when a portion of the doped layer of the silicon carbide substrate is exposed, the doped layer is removed and the silicon carbide device layer of the silicon carbide substrate remains;

7. The doped layer is a sacrificial layer that enables forming the silicon carbide device layer on a wafer with at least one of a desired uniformity of thickness of the silicon carbide device layer or a desired optical performance level, and / or The semiconductor structure is selected from at least one of an optical waveguide, a slot waveguide, a ridge waveguide, a rib waveguide, a buried optical waveguide, a suspended waveguide, an optical resonator, or a photon-emitting quantum memory utilizing point defects in the silicon carbide device layer; the method according to any one of claims 1 to 6.

8. The assembly of the silicon carbide device layer and the group III nitride layer is a thin film layer; The carrier substrate is one of a silicon carbide substrate, a silicon substrate, an aluminum oxide substrate, a gallium oxide substrate, a silica substrate, an aluminum nitride substrate, and a gallium nitride substrate, and / or The group-III nitride layer set of claim 1 to 7, wherein the group-III nitride layer set includes at least one of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and indium aluminum gallium nitride (InAlGaN).

9. A method for forming a semiconductor structure, comprising: bonding a first oxide layer disposed on a group-III nitride layer set formed on a silicon carbide substrate to a second oxide layer disposed on a carrier substrate to form an oxide layer disposed between the carrier substrate and the group-III nitride layer set, wherein the silicon carbide substrate has a doped layer, forming the oxide layer; using a photoelectrochemical etching process to etch the silicon carbide substrate having the doped layer, wherein the doping level of the doped layer is such that the doped layer is removed by the photoelectrochemical etching process and the silicon carbide device layer of the silicon carbide substrate remains unetched; forming the semiconductor structure using the silicon carbide device layer and the group-III nitride layer set; A method comprising the above steps.

10. grinding the silicon carbide substrate before etching the silicon carbide substrate; and stopping the grinding of the silicon carbide substrate when a portion of the doped layer of the silicon carbide substrate is reached before etching the silicon carbide substrate, and / or forming the group-III nitride layer set on the silicon carbide substrate; and forming the first oxide layer on the group-III nitride layer set, wherein the group-III nitride layer set is disposed between the first oxide layer and the silicon carbide substrate, forming the first oxide layer; The method according to claim 9, further comprising the above steps.

11. The step of bonding the first oxide layer disposed on the group-III nitride layer set formed on the silicon carbide substrate to the second oxide layer disposed on the carrier substrate to form the oxide layer disposed between the carrier substrate and the group-III nitride layer set is performed after etching the silicon carbide substrate, according to the method of claim 9 or 10.

12. Bonding the first oxide layer to the second oxide layer on the carrier substrate to form the oxide layer disposed between the carrier substrate and the group III nitride layer set is performed after etching of one of the group III nitride layers in the group III nitride layer set, according to the method of claim 9 or 10.

13. Bonding the first oxide layer disposed on the group III nitride layer set formed on the silicon carbide substrate to the second oxide layer disposed on the carrier substrate to form the oxide layer disposed between the carrier substrate and the group III nitride layer set is performed before etching of the silicon carbide substrate, according to the method of claim 9 or 10.

14. Bonding the first oxide layer disposed on the group III nitride layer set formed on the silicon carbide substrate to the second oxide layer disposed on the carrier substrate to form the oxide layer disposed between the carrier substrate and the group III nitride layer set is contacting a first surface of the first oxide layer with a second surface of the second oxide layer, such that an intermolecular interaction occurs between the first oxide layer and the second oxide layer, contacting the first surface; annealing the first oxide layer and the second oxide layer while the first surface is in direct contact with the second surface to form the oxide layer disposed between the carrier substrate and the group III nitride layer set; The method according to any one of claims 9 to 13, comprising.

15. The doped layer is a sacrificial layer that enables formation of the silicon carbide device layer on the wafer with at least one of a desired uniformity in thickness of the silicon carbide device layer or a desired optical performance level, The semiconductor structure is selected from at least one of an optical waveguide, a slot waveguide, a ridge waveguide, a rib waveguide, a buried optical waveguide, a suspended waveguide, an optical resonator, or a photon-emitting quantum memory that utilizes point defects in the silicon carbide device layer, The silicon carbide device layer and the group III nitride layer set are thin film layers, The carrier substrate is one of a silicon carbide substrate, a silicon substrate, an aluminum oxide substrate, a gallium oxide substrate, a silica substrate, an aluminum nitride substrate, and a gallium nitride substrate, and / or The group III nitride layer set includes at least one of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and indium aluminum gallium nitride (InAlGaN), according to the method of any one of claims 9 to 14.

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