Field Effect Transistor Device

Abstract

To provide a normally-off field effect transistor device with less variation in a threshold voltage or less number of electrodes required for operation.SOLUTION: A field effect transistor device includes a gate electrode structure consisting of a first insulating film 105, a charge storage gate electrode 306, a second insulating film 111, and a gate electrode 112, which are sequentially laminated on a semiconductor, and a first capacitance formed by capacitive coupling between the charge storage gate electrode 306 and a source electrode 308, a charge is accumulated in the charge storage gate electrode 306 by a first current flowing through the first capacitance, and a laminated film composed of a third insulating film 315 and a first semiconductor layer 316 is provided between the source electrode 308 and the charge storage gate electrode 306, and at least a part of the first current flows through the laminated film.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a semiconductor transistor device, and more particularly to a field effect transistor device that realizes so-called normally-off in which a conductive channel under a gate electrode is substantially in an off state without applying a voltage to the gate electrode in a field effect transistor.

Background Art

[0002] Semiconductors having a wide bandgap are useful for electronic devices that operate at high voltages. Among them, nitrides such as GaN, AlN, InN, ScN, and nitride semiconductors composed of these mixed crystals are suitable for high-voltage and high-output power electronic devices because they not only have a wide bandgap but also have high mobility of conductive electrons. In particular, a field effect transistor (FET, Field Effect Transistor) made using a nitride semiconductor, and an electron mobility transistor (HEMT, High Electron Mobility Transistor) that uses conductive electrons induced at a semiconductor hetero-junction interface such as AlGaN / GaN, which is a form thereof, as a conductive channel can operate with high voltage, large current, and low on-resistance, and is used as a power switch or a transistor for a high-frequency power amplifier.

[0003] However, a normal nitride semiconductor FET is a so-called normally-on type, and a conductive channel under the gate electrode is in an on state without applying a voltage to the gate electrode. That is, the gate voltage that blocks the current flowing between the source electrode and the drain electrode, that is, the so-called threshold voltage, is a negative value. For example, when a nitride semiconductor FET is used as a power switch in a power supply device or the like, the switch may turn on when the control voltage applied to the gate electrode is lost due to a malfunction or the like. This may lead to destruction of the entire device and is not preferable from the viewpoints of safety and the like.

[0004] Therefore, techniques for normally-off nitride semiconductor FETs, that is, techniques for setting the threshold voltage to a positive value, have been developed. One such method is known as providing a floating gate electrode for charge storage between the gate electrode and the conductive channel (see Patent Document 1). FIG. 10 shows the structure of a nitride semiconductor HEMT according to the prior art. A buffer layer 1002, a GaN layer 1003, and an AlGaN layer 1004 are sequentially deposited on a substrate 1001, and a conductive channel 1010 is formed on the GaN layer 1003 side at the interface between the GaN layer 1003 and the AlGaN layer 1004. Further, a gate electrode 1006 for charge storage is formed on the AlGaN layer 1004 with a first insulating film 1005 interposed therebetween, and a gate electrode 1012 is formed thereon with a second insulating film 1011 interposed therebetween. Further, source electrodes 1008 and drain electrodes 1009 are formed sandwiching the gate electrode 1006 for charge storage in the horizontal direction. The source electrodes 1008 and the drain electrodes 1009 are both electrically connected to the conductive channel 1010 within a region surrounded by the element isolation region 1014. The capacitance formed between the gate electrode 1012 and the gate electrode 1006 for charge storage with the second insulating film 1011 as a capacitive film is called the second capacitance. Further, the capacitance formed between the gate electrode 1006 for charge storage and the gate electrode portion conductive carrier 1013 existing below the gate electrode of the conductive channel 1010 with the first insulating film 1005 as a capacitive film is called the third capacitance. The voltage applied to the gate electrode 1012 is capacitively coupled to the gate electrode portion conductive carrier 1013 through the second capacitance and the third capacitance connected in series, and the number of carriers can be changed. Thereby, the current flowing between the source electrode 1008 and the drain electrode 1009 can be adjusted, and the operation as an FET can be obtained. In this conventional example, a charge injection electrode 1007 is further provided, and a first capacitance is formed between the charge injection electrode 1007 and the gate electrode 1006 for charge storage through a third insulating film 1015. FIG. 11A is a diagram schematically showing a part of the nitride semiconductor HEMT shown in FIG. 10. FIGS. 11B to 11F are diagrams showing the energies of the lower end of the conduction band (Ec) and the upper end of the valence band (Ev) along the cross section connecting the symbols shown in FIG. 11A, the inside A of the gate electrode 1012, the inside B of the gate electrode 1006 for charge storage, the inside C of the GaN layer 1003, and the inside D of the charge injection electrode 1007, respectively.A(1012), B(1006), and D(1007) indicate the Fermi levels of metals at their respective locations. Figure 11B is a diagram in a state without an externally applied voltage. Due to polarization, the energy of the lower end of the conductor and the upper end of the valence band in the AlGaN layer 1004 is inclined. As a result, the energy of the lower end of the conduction band in the GaN layer 1003 becomes lower than the Fermi level 1104 at the interface with the AlGaN layer 1004, and conductive carriers 1013 in the gate electrode part are generated. That is, the FET is normally on. Here, the electrode areas and the dielectric constants and thicknesses of the second insulating film 1011 and the third insulating film 1015 are selected so that the first capacitance is sufficiently smaller than the second capacitance. In this case, when a positive voltage 1101 indicated by an arrow in Figure 11C is applied to the gate electrode 1012 with respect to the charge injection electrode 1007, due to the strong capacitive coupling with the gate electrode 1012 by the second capacitance, the potential of the charge storage gate electrode 1006 also rises, and the potential energy of the conductive electrons in the charge storage gate electrode 1006 decreases. Then, the potential difference between the charge storage gate electrode 1006 and the charge injection electrode 1007 increases, a high electric field is applied to the third insulating film 1015, and a tunnel current 1102 of conductive electrons indicated by an arrow in Figure 11C flows through the first capacitance. As a result, negative charges 1103 are accumulated in the electric field storage gate electrode 1006. Depending on the type of the third insulating film 1015, there may be a case where conduction holes tunnel from the charge storage gate electrode 1006 through the third insulating film 1015 and become the current flowing through the first capacitance. In this case as well, negative charges are accumulated in the charge storage gate electrode 1006. Hereinafter, only the case where conductive electrons tunnel will be described in this specification. Figure 11D is a diagram showing the energy of the lower end of the conduction band and the upper end of the valence band in a state where the application of the positive voltage 1101 has been stopped after accumulating the negative charges 1103. Due to the negative charges 1103, the potential energy of the conductive electrons in the charge storage gate electrode 1006 increases. Along with this, the energy of the lower end of the conduction band and the upper end of the valence band in the AlGaN layer 1004 and the GaN layer 1003 is pulled up. Therefore, the energy of the lower end of the conduction band in the GaNs layer 1003 becomes higher than the Fermi level 1104, and the conductive carriers 1013 in the gate electrode part disappear. That is, the nitride semiconductor HEMT turns off.

Prior Art Documents

Patent Document

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] Describe the first problem to be solved by the present invention. In the nitride semiconductor FET shown in FIG. 10, assume that the charge injection electrode 1007 is also connected to an external terminal in the same manner as other electrodes and is always connected to an external circuit. It is difficult to completely insulate the potential of the external terminal connected to the charge injection electrode 1007, and usually a leakage circuit to the ground potential remains. FIG. 11E shows the case where the potentials of the charge injection electrode 1007 and the gate electrode 1012 are both zero. Since a negative charge 1103 is accumulated in the charge storage gate electrode 1006 to turn off the FET, a potential difference occurs between the charge storage gate electrode 1006 and the charge injection electrode 1007, and the energies of the lower end of the conduction band and the upper end of the valence band in the third insulating film 1015 are inclined, and an electric field in the opposite direction to that during charge injection is generated in the third insulating film 1015. That is, a potential difference with a sign opposite to that during negative charge accumulation occurs between the electrodes of the first capacitor. Further, for example, when the FET is used as a power switch, dynamic voltage fluctuations occur due to various reactance components of the FET and the switch drive circuit during the on / off operation, and a negative voltage 1104 indicated by an arrow in FIG. 11F may be applied to the gate electrode 1012 with respect to the charge injection electrode 1007. In that case, the potential of the charge storage gate electrode 1006 is further lowered by the strong capacitive coupling of the second capacitor, and the potential difference between the charge storage gate electrode 1006 and the charge injection electrode 1007 becomes larger. As a result, a tunnel current 1105 is generated by the strong electric field in the third insulating film 1015, and the accumulated negative charge 1103 flows back to the charge injection electrode 1007. As a result, the threshold voltage returns in the negative direction, and the time for maintaining the positive threshold voltage required for the normally-off operation becomes shorter. The first object of the present invention is to provide a new field effect transistor device that solves the above first problem.

[0007] Next, the second problem that the present invention aims to solve will be described. A normal FET is a three-terminal device and operates with a total of three electrodes: a source electrode, a drain electrode, and a gate electrode. However, in the above conventional example, the charge injection electrode 1007 is added, and the total number of electrodes is four. Therefore, when supplying a voltage from an external terminal, four terminals are required, and the external circuit for operating the FET becomes complicated. Also, the FET manufacturing process becomes complicated, and furthermore, the area occupied on the substrate of the FET increases. The second object of the present invention is to provide a new field-effect transistor device that solves the above second problem.

[0008] Next, the third problem that the present invention aims to solve will be described. In the conventional example shown in FIG. 10, if there are local defects in the first insulating film 1005, the second insulating film 1011, or the third insulating film 1015 that sandwich the charge storage gate electrode 1006, there is a risk that the negative charges accumulated in the charge storage gate electrode 1006 will flow out through the defects. Furthermore, if local electric field concentration occurs in a part of the charge storage gate electrode 1006, tunneling may occur in that part, and there is also a risk that the negative charges accumulated in the charge storage gate electrode 1006 will flow out. For this reason, the life as a normally-off FET becomes short. Also, if leakage of the stored charge occurs during operation and it instantaneously changes to normally-on, there is also a risk of causing damage to the device. The third object of the present invention is to provide a new field-effect transistor device that solves the above third problem.

Means for Solving the Problems

[0009] To achieve the first object of the present invention, a field effect transistor device according to the first invention of the present application includes a semiconductor, a conductive channel provided in or on the surface of the semiconductor, a first insulating film provided in proximity to the conductive channel, a charge storage gate electrode at least a part of which is provided on the opposite side of the first insulating film from the conductive channel, a second insulating film provided on the opposite side of the charge storage gate electrode from the first insulating film, a gate electrode at least a part of which is provided on the opposite side of the second insulating film from the charge storage gate electrode, a source electrode and a drain electrode provided on the semiconductor with the charge storage gate electrode therebetween and electrically connected to the conductive channel, a charge injection electrode that forms a first capacitance by capacitive coupling with the charge storage gate electrode, and a stacked film including a third insulating film and a first semiconductor layer provided between the charge injection electrode and the charge storage gate electrode, wherein charge is accumulated in the charge storage gate electrode by a first current flowing through the first capacitance, and at least a part of the first current flows through the stacked film.

[0010] In a preferred embodiment of the first invention of the present application, the third insulating film is provided on the side of the charge storage gate electrode, the first semiconductor layer is provided on the side of the charge injection electrode, and the first semiconductor layer contains n-type impurities.

[0011] In a preferred embodiment of the first invention of the present application, the third insulating film is provided on the side of the charge injection electrode, the first semiconductor layer is provided on the side of the charge storage gate electrode, and the first semiconductor layer contains p-type impurities.

[0012] To achieve the second object of the present invention, a field effect transistor device according to the second invention of the present application includes a semiconductor, a conductive channel provided in or on the surface of the semiconductor, a first insulating film provided adjacent to the conductive channel, a charge storage gate electrode at least a part of which is provided on the opposite side of the first insulating film from the conductive channel, a second insulating film provided on the opposite side of the first insulating film from the charge storage gate electrode, a gate electrode at least a part of which is provided on the opposite side of the second insulating film from the charge storage gate electrode, and a source electrode and a drain electrode provided on the semiconductor with the charge storage gate electrode therebetween and electrically connected to the conductive channel. The source electrode or the drain electrode forms a first capacitance by capacitive coupling with the charge storage gate electrode, and charges are stored in the charge storage gate electrode by a first current flowing through the first capacitance.

[0013] In a preferred embodiment of the second invention of the present application, a laminated film composed of a third insulating film and a first semiconductor layer is provided between the source electrode or the drain electrode forming the first capacitance and the charge storage gate electrode, and at least a part of the first current flows through the laminated film.

[0014] In a preferred embodiment of the second invention of the present application, the third insulating film is provided on the side of the charge storage gate electrode, the first semiconductor layer is provided on the side of the source electrode or the drain electrode forming the first capacitance, and the first semiconductor layer contains n-type impurities.

[0015] In a preferred embodiment of the second invention of the present application, the third insulating film is provided on the side of the source electrode or the drain electrode forming the first capacitance, the first semiconductor layer is provided on the side of the charge storage gate electrode, and the first semiconductor layer contains p-type impurities.

[0016] To achieve the third object of the present invention, a field effect transistor device according to the third invention of the present application includes a semiconductor, a conductive channel provided in or on the surface of the semiconductor, a first insulating film provided in proximity to the conductive channel, a charge storage gate electrode at least a part of which is provided on the side of the first insulating film opposite to the conductive channel, a second insulating film provided on the side of the charge storage gate electrode opposite to the first insulating film, a gate electrode at least a part of which is provided on the side of the second insulating film opposite to the charge storage gate electrode, and a source electrode and a drain electrode provided on the semiconductor with the charge storage gate electrode therebetween and electrically connected to the conductive channel. The charge storage gate electrode is composed of a plurality of separated electrodes.

[0017] In a preferred embodiment of the third invention of the present application, the plurality of electrodes of the charge storage gate electrode are all arranged so as to intersect the current direction of the conductive channel.

[0018] In a preferred embodiment of the third invention of the present application, the plurality of electrodes of the charge storage gate electrode are all arranged along the current direction of the conductive channel.

[0019] In a preferred embodiment of the third invention of the present application, it has a charge injection electrode that forms a first capacitance by capacitive coupling with the charge storage gate electrode, and charges are stored in the charge storage gate electrode by a first current flowing through the first capacitance.

[0020] In a preferred embodiment of the third invention of the present application, it has a charge injection electrode that forms a first capacitance by capacitive coupling with the charge storage gate electrode, and charges are stored in the charge storage gate electrode by a first current flowing through the first capacitance. It has a laminated film composed of a third insulating film and a first semiconductor layer provided between the charge injection electrode and the charge storage gate electrode, and at least a part of the first current flows through the laminated film.

[0021] In a preferred embodiment of the third invention of the present application, there is a charge injection electrode that forms a first capacitance by capacitive coupling with the charge storage gate electrode, and charges are stored in the charge storage gate electrode by a first current flowing through the first capacitance. There is a stacked film composed of a third insulating film and a first semiconductor layer provided between the charge injection electrode and the charge storage gate electrode, and at least a part of the first current flows through the stacked film. The third insulating film is provided on the side of the charge storage gate electrode, the first semiconductor layer is provided on the side of the charge injection electrode, and the first semiconductor layer contains n-type impurities.

[0022] In a preferred embodiment of the third invention of the present application, there is a charge injection electrode that forms a first capacitance by capacitive coupling with the charge storage gate electrode, and charges are stored in the charge storage gate electrode by a first current flowing through the first capacitance. There is a stacked film composed of a third insulating film and a first semiconductor layer provided between the charge injection electrode and the charge storage gate electrode, and at least a part of the first current flows through the stacked film. The third insulating film is provided on the side of the charge injection electrode, the first semiconductor layer is provided on the side of the charge storage gate electrode, and the first semiconductor layer contains p-type impurities.

[0023] In a preferred embodiment of the third invention of the present application, the source electrode or the drain electrode forms a first capacitance by capacitive coupling with the charge storage gate electrode, and charges are stored in the charge storage gate electrode by a first current flowing through the first capacitance.

[0024] In a preferred embodiment of the third invention of the present application, the source electrode or the drain electrode forms a first capacitance by capacitive coupling with the charge storage gate electrode, and charges are stored in the charge storage gate electrode by a first current flowing through the first capacitance. There is a stacked film composed of a third insulating film and a first semiconductor layer provided between the source electrode or the drain electrode that forms the first capacitance and the charge storage gate electrode, and at least a part of the first current flows through the stacked film.

[0025] In a preferred embodiment of the third invention of the present application, the source electrode or the drain electrode forms a first capacitance by capacitive coupling with the charge storage gate electrode, and charges are stored in the charge storage gate electrode by a first current flowing through the first capacitance. A laminated film composed of a third insulating film and a first semiconductor layer is provided between the source electrode or the drain electrode forming the first capacitance and the charge storage gate electrode, and at least a part of the first current flows through the laminated film. The third insulating film is provided on the side of the charge storage gate electrode, the first semiconductor layer is provided on the side of the source electrode or the drain electrode forming the first capacitance, and the first semiconductor layer contains n-type impurities.

[0026] In a preferred embodiment of the third invention of the present application, the source electrode or the drain electrode forms a first capacitance by capacitive coupling with the charge storage gate electrode, and charges are stored in the charge storage gate electrode by a first current flowing through the first capacitance. A laminated film composed of a third insulating film and a first semiconductor layer is provided between the source electrode or the drain electrode forming the first capacitance and the charge storage gate electrode, and at least a part of the first current flows through the laminated film. The third insulating film is provided on the side of the source electrode or the drain electrode forming the first capacitance, the first semiconductor layer is provided on the side of the charge storage gate electrode, and the first semiconductor layer contains p-type impurities.

Advantages of the Invention

[0027] According to the first invention of the present application, the magnitude of the current flowing through the first capacitor can be made asymmetric depending on whether the potential of the gate electrode for charge storage is lower or higher than the potential of the electrode for charge injection. For example, by making the potential of the gate electrode for charge storage higher than that of the electrode for charge injection, negative charges can be accumulated in the gate electrode for charge storage, but the outflow of negative charges when the reverse potential difference occurs can be suppressed. When an FET is used as a power switch and negative charges are accumulated in the gate electrode for charge storage for normally-off operation, dynamic voltage fluctuations occur due to various reactance components of the FET and the switch drive circuit, and the dynamic voltage of the gate electrode becomes negative. Due to the capacitive coupling with the gate electrode, the potential of the gate electrode for charge storage may become lower than that of the electrode for charge injection. However, the outflow of the negative charges accumulated in the gate electrode for charge storage to the electrode for charge injection at that time can be suppressed. As a result, the positive threshold voltage required for normally-off operation can be maintained for a long time.

[0028] The effects of the first invention of the present application will be further described in detail with reference to the drawings. FIG. 12A is a diagram schematically showing a part of the FET according to the first invention of the present application. The difference from the conventional FET shown in FIG. 11A is that a first semiconductor layer 1216 is provided between the third insulating film 1215 and the charge injection electrode 1207. Similar to the description of the conventional FET, the coupling capacitance between the charge injection electrode 1207 and the charge storage gate electrode 1006 is referred to as the first capacitance, the coupling capacitance between the gate electrode 1012 and the charge storage gate electrode 1006 is referred to as the second capacitance, and the coupling capacitance between the charge storage gate electrode 1006 and the gate electrode portion conductive carrier 1013 is referred to as the third capacitance. FIGS. 12B and 12C are diagrams showing the energies of the lower end (Ec) of the conduction band and the upper end (Ev) of the valence band of electrons along the cross section connecting the inside A of the gate electrode 1012, the inside B of the charge storage gate electrode 1006, and the inside D of the charge injection electrode 1207 indicated by symbols in FIG. 12A. FIG. 12B is a diagram when conduction electrons are injected from the charge injection electrode 1207 to the charge storage gate electrode 1006, and a positive voltage 1201 is applied to the gate electrode 1012 with respect to the charge injection electrode 1207. This corresponds to FIG. 11C in the case of the conventional FET. Here, the electrode areas and the dielectric constants and thicknesses of the second insulating film 1011 and the third insulating film 1215 are selected so that the first capacitance is sufficiently smaller than the second capacitance. Then, due to the strong capacitive coupling with the gate electrode 1012 by the second capacitance, the potential of the charge storage gate electrode 1006 also increases significantly. On the other hand, the first semiconductor layer 1216 is formed to have n-type conductivity, and the electrical contact with the charge injection electrode 1207 is formed to be ohmic or a low-resistance contact close to ohmic for conduction electrons. In this case, the energy of the lower end of the conduction band of the first semiconductor layer 1216 becomes substantially flat when the positive voltage 1201 is applied, and the potential of the conduction electrons at the interface with the third insulating film 1215 becomes substantially the same as that of the charge injection electrode 1207. As a result, the potential difference between the charge storage gate electrode 1006 and the first semiconductor layer 1216 increases, a high electric field is generated in the third insulating film 1215, and a tunnel current 1202 of conduction electrons indicated by an arrow in FIG. 12B flows. The tunneled conduction electrons are accumulated as negative charges 1203 in the electric field storage gate electrode 1006.FIG. 12C shows a case where a negative voltage 1204 indicated by an arrow in the figure is applied to the gate electrode 1012 with respect to the charge storage electrode 1007. This is caused by dynamic fluctuations in voltage during the on-off operation when the FET is used as a power switch. Due to the strong capacitive coupling by the second capacitor, the potential of the charge storage gate electrode 1006 significantly decreases. However, since the first semiconductor layer 1216 is of n-type, carrier depletion occurs, and a part of the potential difference between the charge storage gate electrode 1006 and the charge injection electrode 1207 is compensated by the potential difference generated within the first semiconductor layer 1216. For this reason, the electric field strength within the third insulating film becomes smaller than that of the conventional FET shown in FIG. 11F, and the generation of tunnel current is suppressed. By suppressing the outflow of the negative charge 1203, the threshold voltage becomes less likely to return in the negative direction, and the positive threshold voltage required for the normally-off operation is more easily maintained.

[0029] The effects of the first invention of the present application will be further described in detail based on the results of device simulations performed on the first capacitor. The simulations were performed on a parallel plate capacitor corresponding to the B-D cross-section of FIG. 12A. The third insulating film 1215 was made of silicon oxide (SiO2) with a thickness of 8 nm. The first semiconductor layer 1216 was made of silicon carbide (SiC) with a thickness of 40 nm, and the conductivity type was n-type with an impurity concentration of 1X10 17 cm -3 . FIG. 13 shows the simulation results of the current-voltage characteristics of the first capacitor. The inter-electrode voltage of the first capacitor shown on the horizontal axis corresponds to the voltage of the charge storage gate electrode 1206 with respect to the charge injection electrode 1207. The vertical axis shows the absolute value of the current in logarithmic scale. The current-voltage characteristics are asymmetric between negative and positive voltages, and the current is significantly lower in the negative voltage region compared to the positive voltage region. For example, at -12V compared to +12V, the current decrease 1301 indicated by an arrow in FIG. 13 is on the order of 9 digits. As a result, even when a voltage in the opposite direction to that during negative charge accumulation is applied to the first capacitor due to dynamic fluctuations in voltage during the on-off operation when the FET is used as a switch, almost no outflow of the stored charge occurs.

[0030] In the above method, the first semiconductor layer 1216 is provided on the side of the charge injection electrode 1207, and the third insulating film 1215 is provided on the side of the charge storage gate electrode 1006. Next, another method of the first invention of the present application will be described with reference to FIGS. 14A, 14B, and 14C. FIG. 14A is a diagram schematically showing a part of the FET according to the first invention of the present application, similar to FIG. 12A. In this method, the first semiconductor layer 1416 is provided on the side of the charge storage gate electrode 1006, and the third insulating film 1415 is provided on the side of the charge injection electrode 1407. Also, the conductivity type of the first semiconductor layer 1416 is p-type, and it is electrically in contact with the charge storage gate electrode 1006 with ohmic or near-ohmic low resistance to conduction holes. FIG. 14B is a diagram when a positive voltage 1401 is applied to the gate electrode 1012 with respect to the charge injection electrode 1407. The energies of the lower end (Ec) of the conduction band and the upper end (Ev) of the valence band of the p-type first semiconductor layer 1416 become substantially flat, and the potential of the conduction hole 1405 at the interface between the first semiconductor layer 1416 and the third insulating film 1415 becomes substantially the same as that of the charge storage gate electrode 1006. Therefore, the potential difference between the charge injection electrode 1407 and the first semiconductor layer 1416 increases, and a strong electric field is generated in the third insulating film 1415. As a result, a tunnel current 1402 of conduction electrons from the charge injection electrode 1407 to the first semiconductor layer 1416 is generated, and negative charges 1403 are accumulated in the charge storage gate electrode 1006. On the other hand, FIG. 14C is a diagram when a negative voltage 1404 is applied to the gate electrode 1012 with respect to the charge injection electrode 1407 due to dynamic fluctuations of the voltage during the switch operation or the like. In this case, since a part of the potential difference between the charge injection electrode 1407 and the charge storage gate electrode 1006 is covered by the p-type first semiconductor layer 1416, the voltage applied to the third insulating film 1415 decreases. Thereby, the generation of the tunnel current can be suppressed, and the backflow 1406 of negative charges to the charge injection electrode 1407 can be suppressed.

[0031] The above has described the case where SiC is used for the first semiconductor layer. SiC is known as a wide-bandgap semiconductor. Wide-bandgap semiconductors are less likely to undergo impact ionization or Zener breakdown and have a high breakdown electric field strength. Therefore, it is suitable for the first invention of the present application to suppress tunneling in the insulating film by causing a part of the voltage to be borne when a voltage opposite to the charge injection time is applied to the first capacitor. Further, in the example shown in FIG. 12A, in the case of a wide-bandgap semiconductor, the energy difference between the lower end of the conduction band between the third insulating film 1215 and the first semiconductor layer 1216 indicated by ΔEc in FIG. 12B becomes small, so that the tunnel current 1202 easily flows. On the other hand, since the leakage current when a reverse voltage is applied is determined by the energy of the lower end of the conduction band of the third insulating film 1215 measured from the Fermi level of the charge storage gate electrode 1006, as can be seen from FIG. 12C, it hardly depends on the bandgap of the first semiconductor layer 1216. Therefore, if a wide-bandgap semiconductor is used for the first semiconductor layer 1216, the current difference between the voltage at the time of negative charge injection and the voltage of the opposite sign can be increased, which is suitable for the first invention of the present application. As wide-bandgap semiconductors other than SiC, for example, nitride semiconductors such as AlGaN and AlN may be used. However, the material of the first semiconductor is not limited to wide-bandgap semiconductors, and for example, a semiconductor material with a relatively small bandgap such as Si may be used. If the thickness is made sufficiently thick, the electric field strength in the first semiconductor layer becomes small, and voltage breakdown can be suppressed. Si, especially polycrystalline Si, is easy to film and forms an interface with good electrical characteristics with few defects with an insulating film, especially silicon oxide. In the example shown in FIG. 12A, when negative charges are trapped at the defect levels at the interface, the Ec at the interface increases and the tunnel current 1202 at the time of negative charge injection shown in FIG. 12B becomes difficult to flow, but this problem can be avoided by using a semiconductor with excellent interface characteristics such as Si. The first semiconductor layer may be a laminated film of a plurality of different semiconductor materials. For example, a thin semiconductor layer with good interface characteristics such as Si may be inserted in the portion in contact with the third insulating film, and the other portions may be wide-bandgap semiconductors such as SiC. Thereby, both good interface characteristics and high breakdown electric field strength can be obtained.

[0032] Next, the effects of the second invention of the present application will be described. According to the second invention of the present application, since the first capacitor used for charge storage in the charge storage gate electrode is formed between the charge storage gate electrode and the source electrode or the drain electrode, an individual electrode for charge injection becomes unnecessary, and the four electrodes that were necessary for operating the FET in the prior art can be reduced to three. As a result, the external circuit for operating the FET can be simplified, the manufacturing process of the FET can be simplified, and further, the area occupied by the FET on the substrate can be reduced.

[0033] According to the third invention of the present application, even if the stored charge flows out from one of the plurality of separated charge storage gate electrodes, the partial threshold voltage of the remaining charge storage gate electrodes does not change, so it becomes easier to maintain normally-off. As a result, the life as a normally-off FET can be extended, and the failure of the device due to normal-on during use as a switch can be minimized.

Brief Description of the Drawings

[0034]

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Figure 11A

Figure 11B

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Figure 11D

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Figure 14A

Figure 14B

Figure 14C

Embodiments for Carrying Out the Invention

[0035] Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing the structure of a field effect transistor device which is an embodiment of the first invention of the present application. A buffer layer 102, a first nitride semiconductor layer 103, and a second nitride semiconductor layer 104 are sequentially deposited on a substrate 101. As the substrate, Si, GaN, sapphire, SiC, etc. are used. Further, at least a part of the bandgap of the second nitride semiconductor layer 104 is larger than at least a part of the bandgap of the first nitride semiconductor layer 103. Thereby, a conductive channel 110 is formed on the first nitride semiconductor layer 103 side of the interface between the first nitride semiconductor layer 103 and the second nitride semiconductor layer 104. For example, GaN is used for the first nitride semiconductor layer 103 and AlGaN is used for the second nitride semiconductor layer 104. Here, when the composition of AlGaN is described as AlxGa1-xN, x satisfies the relationship of 0 < x ≦ 1. As the nitride semiconductor material, in addition to this, InN, ScN, or a mixed crystal semiconductor of these nitride semiconductors may also be used. Further, a gate electrode 106 for charge storage is formed on the first nitride semiconductor layer 104 with a first insulating film 105 interposed therebetween. The coupling capacitance between the gate electrode lower conductive carrier 113 formed in the conductive channel 110 below the gate electrode 106 for charge storage and the gate electrode 106 for charge storage is called the third capacitance. Further, a gate electrode 112 is formed on the gate electrode 106 for charge storage with a second insulating film 111 interposed therebetween. The coupling capacitance between the gate electrode 112 and the gate electrode 106 for charge storage is called the second capacitance. Further, source electrodes 108 and drain electrodes 109 are formed while sandwiching the gate electrode 106 for charge storage in the horizontal direction. Both the source electrode 108 and the drain electrode 109 are electrically connected to the conductive channel 110 in the inner region surrounded by the element isolation region 114. The gate electrode 112 is capacitively coupled to the gate electrode part conductive carrier 113 via the second capacitance and the third capacitance connected in series. By changing the number of carriers of the gate electrode part conductive carrier 113 with the voltage applied to the gate electrode 112, the current flowing between the source electrode 108 and the drain electrode 109 can be adjusted, and the operation as a field effect transistor (FET) can be obtained.The charge storage gate electrode 106, gate electrode 112, source electrode 108, and drain electrode 109 shall all include all the metallically connected portions on the substrate 100. Therefore, these electrodes do not necessarily need to be formed in a single process, and they may be formed by making metal contact with films created in multiple processes. This is the same in other embodiments of the first invention of this application. Also, as the film material, a conventionally known single metal, alloy, compound metal, semiconductor with high-concentration doping of impurities such as polysilicon to reduce resistance, or a combination of these materials may be used. This is also the same in other embodiments of the first invention of this application. Here, a third insulating film 115, a first semiconductor layer 116, and a charge injection electrode 107 are sequentially formed on the charge storage gate electrode 106. This portion is the characteristic portion as the first invention of this application in this embodiment. The coupling capacitance between the charge injection electrode 107 and the charge storage gate electrode 106 is called the first capacitance. The peripheral portions of the first capacitance, the second capacitance, and the third capacitance are protected by a protective insulating film 117. The protective insulating film 117 may use the insulating films forming the first capacitance, the second capacitance, and the third capacitance, or another insulating film may be used. The first capacitance is used when accumulating charges in the charge storage gate electrode 106. The method is as follows.

[0036] This will be described below. Note that as the materials for the first insulating film 105, the second insulating film 111, and the third insulating film 115, conventionally known insulating film materials such as silicon oxide, silicon nitride, silicon oxynitride, alumina, hafnia, zirconia, or laminated films or mixed films of these materials may be used. Also, as the material for the first semiconductor layer 116, conventionally known semiconductor materials such as silicon, silicon carbide, nitride, or laminated films or mixed films thereof may be used. The semiconductor layer may be either single crystal or polycrystalline. As described in

[0031] , since silicon carbide has a large bandgap and a high breakdown electric field strength, it is suitable for the purpose of preventing the backflow of charges accumulated in the gate electrode 106 for charge storage. On the other hand, polycrystalline silicon is easy to form as a thin film, and is preferable in that a good interface with few trap levels can be obtained when silicon oxide is used for the third insulating film 115. Silicon has a small bandgap and a low breakdown electric field strength, but a desired withstand voltage can be obtained by making it thick enough. Alternatively, if thin silicon is used for the portion in contact with the insulating film 115 and other portions are made of a material with a large bandgap such as silicon carbide, a structure excellent in both interface characteristics and withstand voltage can be obtained. The conductivity type of the first semiconductor layer 116 is set to n-type and formed so as to obtain an ohmic or near-ohmic low-resistance electrical contact with respect to the charge injection electrode 107. Note that the concentration of n-type impurities in the first semiconductor layer 116 may be uniform, or may have a concentration gradient, with a low concentration on the side of the third insulating film 115 and a high concentration on the opposite side. When a gradient is provided, a low-resistance electrical contact can be obtained with the charge injection electrode 107 while ensuring the withstand voltage. Alternatively, when a material that generates polarization charges is used for the first semiconductor layer 116, a thin high-concentration impurity layer may be introduced for the purpose of canceling the polarization charges. Also, as the material for the charge injection electrode 107, a commonly known single metal, alloy, compound metal, or semiconductor in which impurities such as n-type polysilicon are doped at a high concentration, or a combination of these materials may be used. The materials for the third insulating film 115, the first semiconductor layer 116, and the charge injection electrode 107 are the same in other embodiments of the first invention of the present application.

[0036] The threshold voltage adjustment method in the embodiment of the first invention of the present application shown in FIG. 1 will be described. The following method assumes the normal-off state of the FET and is the case where the threshold voltage is shifted in the positive direction. A negative charge is accumulated in the charge storage gate electrode 106 by a minute current flowing through the first capacitor having the charge injection electrode 107 as one of its electrodes. The charge storage gate electrode 106 is a floating electrode, and the potential energy of electrons is raised by the stored negative charge, reducing the number of carriers in the gate electrode portion conductive carriers 113. Until the carriers in the gate electrode portion conductive carriers 113 substantially disappear at a positive value of the voltage of the gate electrode 112 measured with respect to the source electrode 108 being zero or more, by accumulating negative charges in the charge storage gate electrode 106, the threshold voltage becomes a positive value and the normal-off operation is realized. When accumulating negative charges in the charge storage gate electrode 106 using the first capacitor, a positive voltage may be applied to the gate electrode 112 with reference to the charge injection electrode 107. For example, the voltage of the charge injection electrode 107 is set to zero and the voltage of the gate electrode 112 is set to positive. Then, the potential of the charge storage gate electrode 106 also changes according to the voltage of the gate electrode 112 by capacitive coupling by the second capacitor and becomes higher than the potential of the charge injection electrode 107. In other words, the potential energy with respect to the conduction electrons becomes lower at the charge storage gate electrode 106 than at the charge injection electrode 107. As a result, conduction electrons tunnel through the third insulating film 115 and flow into the first semiconductor layer 116, reach the charge storage gate electrode 106, and negative charges are accumulated. The charge injection electrode 1207 in FIG. 12A for explaining the principle of the first invention of the present application corresponds to the charge injection electrode 107 in this embodiment, and the energies of the lower end of the conduction band and the upper end of the valence band are as shown in FIG. 12B. The current at the time of charge injection corresponds to the current in the positive voltage region of FIG. 13. Here, the areas of the gate electrode 112 and the charge injection electrode 107, and the dielectric constants and thicknesses of the second insulating film 111 and the third insulating film 115 are selected so that the first capacitor is sufficiently smaller than the second capacitor. Since the voltages applied to the two capacitors connected in series are distributed in inverse proportion to their respective capacitance values, a larger voltage can be applied to the first capacitor than to the second capacitor.As a result, tunneling in the third insulating film 115 becomes likely to occur, and negative charges can be efficiently injected into the charge storage gate electrode 106. On the other hand, when the FET is used as a power switch, the static voltage of the gate electrode 112 at the time of switch-off is zero volts, and furthermore, dynamic voltage fluctuations occur due to various reactance components of the FET and the switch drive circuit, and the dynamic voltage of the gate electrode 112 may become negative. When the charge injection electrode 107 is connected to the gate drive circuit through an external terminal, it is difficult to completely insulate the charge injection electrode 107, and a leakage path to the ground potential remains during the switch operation. Therefore, when the voltage of the gate electrode 112 becomes negative, the voltage of the charge storage gate electrode 106 also becomes negative due to capacitive coupling by the second capacitor, and a voltage opposite to that at the time of negative charge storage is applied to the first capacitor. For this reason, in a conventional FET, a reverse flow due to tunneling of the stored negative charges occurs, and there is a problem that the holding time of the positive threshold voltage required for the normally-off operation becomes short. However, in the present embodiment of the first invention of the present application, by inserting the first semiconductor layer 116 between the third insulating film and the charge injection electrode 107, the voltage is distributed between the third insulating film 115 and the first semiconductor layer 116 as in FIG. 12C, and the voltage applied to the third insulating film 115 becomes small. As shown in FIG. 13, since the current in the negative voltage region is smaller than that in the positive voltage region, the reverse flow of the negative charges stored in the charge storage gate electrode 106 can be suppressed. As a result, the holding time of the positive threshold voltage required for the normally-off operation can be lengthened.

[0037] In the embodiment shown in FIG. 1, in the portion constituting the first capacitor, the third insulating film 115 is provided on the side of the charge storage gate electrode 106, and the first semiconductor layer 116 is provided on the side of the charge injection electrode 107, and the first semiconductor layer 116 is of n-type. This is the same as the layer structure shown in FIG. 12A, but as in the structure shown in FIG. 15A, the third insulating film 115 may be provided on the side of the charge injection electrode 107, the first semiconductor layer 116 may be provided on the side of the charge storage gate electrode 106, and the first semiconductor layer 116 may be of p-type. As described in the explanations of FIGS. 15A, 15B, and 15C, the same effects as those in the case of the structure shown in FIG. 1 can be obtained in this case as well.

[0038] In the embodiment of the first invention of the present application described above, the nitride semiconductor layer is composed of a first nitride semiconductor layer 103 and a second nitride semiconductor layer 104, and the conductive channel 110 formed on the first nitride semiconductor layer 103 side of the interface between the first nitride semiconductor layer 103 and the second nitride semiconductor layer 104 serves as a path for the current flowing between the source electrode 108 and the drain electrode 109. In the FET of this embodiment, since conductive carriers are induced in the conductive channel 110 by utilizing the polarization charges generated due to the different compositions of the first nitride semiconductor layer 103 and the second nitride semiconductor layer 104, a large number of conductive carriers are spontaneously generated even in the absence of an externally applied voltage. Therefore, the FET becomes a normally-on FET having a very large negative threshold voltage. Thus, in order to turn the FET off, it is necessary to accumulate a very large amount of negative charges in the charge storage gate electrode 106, and the backflow of the accumulated negative charges to the charge injection electrode 107 also becomes a serious problem. In the first invention of the present application, this backflow can be suppressed, and it is particularly effective in a nitride semiconductor FET, that is, a HEMT, which uses the conductive channel 110 formed at the interface between the first nitride semiconductor layer 103 and the second nitride semiconductor layer 104. However, the first invention of the present application is not limited to HEMTs. For example, in this embodiment, when the second nitride semiconductor layer 114 is eliminated, the first insulating film 105 is formed directly on the first nitride semiconductor layer 103, and the conductive channel generated on the first nitride semiconductor layer 103 side of the interface between the first nitride semiconductor layer 103 and the first insulating film 105 is used as a path for the current flowing between the source electrode 108 and the drain electrode 109, the same effect can be obtained in the FET. The above points are the same for other embodiments of the present application.

[0039] FIG. 2 is a diagram showing another embodiment of the first invention of the present application. The difference between this embodiment and the embodiment shown in FIG. 1 is that the charge injection electrode 207 for forming the first capacitance is disposed closer to the substrate 101 side than the charge storage gate electrode 206. The third insulating film 215 is provided on the charge storage gate electrode 206 side, and the first semiconductor layer 216 is provided on the charge injection electrode 207 side, which is the same as the embodiment of FIG. 1. The conductivity type of the first semiconductor layer 216 is n-type. The structure of this embodiment can be obtained, for example, by first forming the charge injection electrode 207, sequentially forming the first semiconductor layer 216 and the third insulating film 215 thereon, and then forming the charge storage gate electrode 206. Similar to the embodiment shown in FIG. 1, when a negative voltage is applied to the gate electrode 112, the voltage applied between the charge storage gate electrode 206 and the charge injection electrode 207 is distributed between the third insulating film 215 and the first semiconductor layer 216, and the voltage applied to the third insulating film 215 becomes smaller. Therefore, the reverse flow of the negative charge accumulated in the charge storage gate electrode 206 is less likely to occur, and the holding time of the positive threshold voltage required for the normally-off operation can be extended. Also, in this embodiment, the first capacitance is formed to include the upper edge portion of the charge injection electrode 207. Since the electric field is concentrated at the edge portion, a tunnel current can be generated with a smaller potential difference, and the injection of negative charges into the charge storage gate electrode 206 becomes easier.

[0040] Also in the embodiment shown in FIG. 2, similar to the embodiment shown in FIG. 1, the third insulating film 216 may be provided on the charge injection electrode 207 side, the first semiconductor layer 216 may be provided on the charge storage gate electrode 206 side, and the first semiconductor layer 216 may be p-type. Also in this case, the same effects as the structure shown in FIG. 2 can be obtained.

[0041] FIG. 3 is a diagram showing the structure of a field effect transistor device which is an embodiment of the second invention of the present application. A buffer layer 102, a first nitride first semiconductor layer 103, and a second nitride semiconductor layer 104 are sequentially deposited on a substrate 101. As the substrate, Si, GaN, sapphire, SiC, etc. are used. Also, at least a part of the bandgap of the second nitride semiconductor layer 104 is larger than at least a part of the bandgap of the first nitride semiconductor layer 103. Thereby, a conductive channel 110 is formed on the first nitride semiconductor layer 103 side of the interface between the first nitride semiconductor layer 103 and the second nitride semiconductor layer 104. For example, GaN is used for the first nitride semiconductor layer 103 and AlGaN is used for the second nitride semiconductor layer 104. Here, when the composition of AlGaN is described as AlxGa1-xN, x satisfies the relationship 0 < x ≦ 1. In addition to this, InN, ScN, or a mixed crystal semiconductor of these nitride semiconductors may be used as the nitride semiconductor material. Further, a gate electrode 306 for charge storage is formed on the first nitride semiconductor layer 104 with a first insulating film 105 interposed therebetween. The coupling capacitance between the gate electrode lower conductive carrier 113 formed in the conductive channel 110 below the gate electrode 306 for charge storage and the gate electrode 306 for charge storage is called the third capacitance. Further, a gate electrode 112 is formed on the gate electrode 306 for charge storage with a second insulating film 111 interposed therebetween. The coupling capacitance between the gate electrode 112 and the gate electrode 306 for charge storage is called the second capacitance. Also, a source electrode 308 and a drain electrode 109 are formed while sandwiching the gate electrode 306 for charge storage in the horizontal direction. Both the source electrode 308 and the drain electrode 109 are electrically connected to the conductive channel 110 in an internal region surrounded by the element isolation region 114. The gate electrode 112 is capacitively coupled to the gate electrode part conductive carrier 113 via the second capacitance and the third capacitance connected in series. By changing the number of carriers of the gate electrode part conductive carrier 113 with the voltage applied to the gate electrode 112, the current flowing between the source electrode 308 and the drain electrode 109 can be adjusted, and the operation as a field effect transistor (FET) can be obtained. The gate electrode 306 for charge storage, the gate electrode 112, the source electrode 308, and the drain electrode 109 all include all the metallically connected portions on the substrate 100.Therefore, these electrodes do not necessarily need to be formed in a single process, and may be formed by making metal contact with films created in multiple processes. This also applies to other embodiments of the second invention of this application. Also, as the material of the film, a conventionally known single metal, alloy, compound metal, semiconductor with high-concentration doping of impurities such as polysilicon to reduce resistance, or a material combining these materials may be used. This also applies to other embodiments of the second invention of this application. Here, as an example of a method for forming a characteristic part of the second invention of this application, a part of the source electrode 308 extends so as to overlap the substrate 101 of the charge storage gate electrode 306 on the opposite side, and a first capacitance is formed by capacitive coupling with the charge storage gate electrode 306. Also, in this embodiment, a third insulating film 315 is provided on the charge storage gate electrode 306 side and a first semiconductor layer 316 is provided on the source electrode 308 side at the portion where the first capacitance is formed. The peripheral portions of the first capacitance, the second capacitance, and the third capacitance are protected by a protective insulating film 117. The protective insulating film 117 may use the insulating film for forming the first capacitance, the second capacitance, and the third capacitance, or another insulating film may be used. The first capacitance is used when accumulating charge in the charge storage gate electrode 306. The method is as follows.

[0042] This will be described below. Note that as the materials for the first insulating film 105, the second insulating film 111, and the third insulating film 315, conventionally known insulating film materials such as silicon oxide, silicon nitride, silicon oxynitride, alumina, hafnia, zirconia, or a laminated film or a mixed film of these materials may be used. Also, as the material for the first semiconductor layer 316, conventionally known semiconductor materials such as silicon, silicon carbide, nitride, or a laminated film or a mixed film of these may be used. The semiconductor may be either single crystal or polycrystalline. As described in

[0031] , since silicon carbide has a large bandgap and a high breakdown electric field strength, it is suitable for the purpose of preventing the backflow of the charges accumulated in the gate electrode 306 for charge storage. On the other hand, polycrystalline silicon is easy to form as a thin film, and it is preferable in that a good interface with few trap levels can be obtained when silicon oxide is used for the third insulating film 315. Silicon has a small bandgap and a low breakdown electric field strength, but a desired breakdown voltage can be obtained by making it thick enough. Alternatively, if thin silicon is used for the portion in contact with the insulating film 315 and a material with a large bandgap such as silicon carbide is used for the other portions, a structure excellent in both interface characteristics and breakdown voltage can be obtained. The conductivity type of the first semiconductor layer 316 is made n-type and formed so as to obtain an ohmic or nearly ohmic low-resistance electrical contact with respect to the source electrode 308. Note that the n-type impurity concentration of the first semiconductor layer 316 may be uniform, or the impurity concentration may be inclined such that it is low on the side of the third insulating film 315 and high on the opposite side. When inclined, a low-resistance electrical contact can be obtained with the source electrode 308 while ensuring the breakdown voltage. Alternatively, when a material that generates polarization charges is used for the first semiconductor layer 316, a thin high-concentration impurity layer may be introduced for the purpose of canceling the polarization charges. The materials for the third insulating film 315 and the first semiconductor layer 316 are the same in other embodiments of the second invention of the present application.

[0042] The threshold voltage adjustment method in the embodiment of the second invention of the present application shown in FIG. 3 will be described. The following method assumes the normal-off state of the FET and is the case where the threshold voltage is shifted in the positive direction. Negative charges are accumulated in the charge storage gate electrode 306 by a minute current flowing through the first capacitor having the source electrode 308 as one of its electrodes. The charge storage gate electrode 306 is a floating electrode, and the potential energy of electrons is raised by the accumulated negative charges, reducing the number of carriers in the gate electrode portion conductive carriers 113. Even when the voltage of the gate electrode 112 measured with respect to the source electrode 308 is zero or a positive value, negative charges are accumulated in the charge storage gate electrode 306 until the number of carriers in the gate electrode portion conductive carriers 113 substantially becomes zero, so that the threshold voltage becomes a positive value and the normal-off operation is realized. When accumulating negative charges in the charge storage gate electrode 306 using the first capacitor, a positive voltage may be applied to the gate electrode 112 compared to the source electrode 308. For example, the voltage of the source electrode 308 is set to zero and the voltage of the gate electrode 112 is set to positive. In this case, the potential of the charge storage gate electrode 306 also becomes higher than that of the source electrode 308 due to capacitive coupling by the second capacitor. In other words, the potential energy for electrons becomes lower at the charge storage gate electrode 306 than at the source electrode 308. As a result, conduction electrons tunnel through the third insulating film 315 and flow into the first semiconductor 316, reach the charge storage gate electrode 306, and negative charges are accumulated. In the conventional FET, an individual electrode was required for accumulating negative charges in the charge storage gate electrode 306. However, in the present embodiment of the second invention of the present application, the accumulation of negative charges in the charge storage gate electrode 306 is performed from the source electrode 308. Therefore, the four electrodes that were necessary to operate the FET in the prior art can be reduced to three. As a result, the external circuit for operating the FET can be simplified, the manufacturing process of the FET can be simplified, and further, the area occupied by the FET on the substrate can be reduced. Note that the area of the gate electrode 112, the area of the overlapping portion between the source electrode 308 and the charge storage gate electrode 306, and the dielectric constant and thickness of the second insulating film 111 and the third insulating film 315 are selected so that the first capacitor is sufficiently smaller than the second capacitor.Since the voltages applied to two capacitances connected in series are distributed in inverse proportion to their respective capacitance values, a larger voltage can be applied to the first capacitance than to the second capacitance. As a result, tunneling in the third insulating film 315 is likely to occur, and negative charges can be efficiently injected into the charge storage gate electrode 306.

[0043] In the embodiment of the second invention of the present application shown in FIG. 3, in the overlapping portion between the source electrode 308 forming the first capacitance and the charge storage gate electrode 306, a third insulating film 315 is provided on the charge storage gate electrode 306 side, and a first semiconductor layer 316 is provided on the source electrode 308 side. This structure is the same as that of the first capacitance in the first invention of the present application, and corresponds to the case where the charge injection electrode 1207 is replaced with the source electrode in FIGS. 12A, 12B, and 12C. The lower end of the conduction band and the upper end of the valence band during negative charge injection are the same as those in FIG. 12B. Since almost all of the voltage between the source electrode 308 and the charge storage gate electrode 306 is applied to the third insulating film 315, negative charges are accumulated by tunneling in the third insulating film 315. On the other hand, when the FET of this embodiment is used as a switch, the static voltage of the gate electrode 112 becomes almost zero with reference to the source electrode 308 when the switch is off. Furthermore, due to various reactance components of the FET and the switch drive circuit, dynamic voltage fluctuations may occur and the dynamic voltage of the gate electrode 112 may become negative. In this case, due to the capacitive coupling of the second capacitance between the gate electrode 112 and the charge storage gate electrode 306, the potential of the charge storage gate electrode 306 also becomes negative. In this case, since the electrode on the side opposite to the charge storage gate electrode 306 of the first capacitance is the source electrode 308, a voltage in the opposite direction to that during negative charge storage in the charge storage gate electrode 306 is applied to the first capacitance. However, in this embodiment, similar to the first capacitance in the first invention of the present application, the voltage is distributed between the third insulating film 315 and the first semiconductor layer 316, so the voltage applied to the third insulating film 315 becomes smaller. This is the same as the situation shown in FIG. 12C in the first invention of the present application. As a result, the reverse flow of the negative charges stored in the charge storage gate electrode 306 due to tunneling can be suppressed, and the time for maintaining the positive threshold voltage required for the normally-off operation can be extended.

[0044] As another form of the embodiment shown in FIG. 3, a third insulating film 315 may be provided on the side of the source electrode 308, and a first semiconductor layer 316 may be provided on the side of the charge storage gate electrode 306. The first semiconductor layer 316 may be p-type. This corresponds to the case where the charge injection electrode 1407 is replaced with the source electrode in FIGS. 14A, 14B, and 14C. In this case as well, the same effects as the structure shown in FIG. 3 can be obtained. Alternatively, the first semiconductor layer 316 may be eliminated and the first capacitance may be formed only by the third insulating film 315. In this case, although the leakage of the negative charge accumulated in the charge storage gate electrode 306 increases, the effect of the second invention of the present application, that is, the reduction in the number of electrodes, can be obtained in the same manner.

[0045] In the second invention of the present application, the first capacitance may be formed between the source electrode or the drain electrode and the charge storage gate electrode. In the embodiment shown in FIG. 3, the first capacitance is formed between the source electrode and the charge storage gate electrode. In order to accumulate a negative charge in the charge storage gate electrode, it is necessary to apply a positive voltage to the charge storage gate electrode with reference to the electrode on the opposite side of the first capacitance. Therefore, a positive voltage must be applied to the gate electrode with reference to the electrode on the opposite side of the charge storage gate electrode. If the electrode on the opposite side of the charge storage gate electrode of the first capacitance is the source electrode, in the normal usage method of the power switch, a positive voltage is applied to the gate electrode with reference to the source electrode. Therefore, the design of the drive circuit for accumulating negative charges becomes easy. However, even when the first capacitance is formed between the drain electrode and the charge storage gate electrode, the same effects can be obtained by designing the drive circuit and the like accordingly. The above points are the same for other embodiments of the second invention of the present application and the corresponding embodiments of the third invention of the present application described later.

[0046] FIG. 4 is a diagram showing another embodiment of the second invention of the present application. The difference from the embodiment shown in FIG. 3 of this embodiment is that in the portion forming the first capacitance, the source electrode 408 extends not on the upper surface of the charge storage gate electrode 406 but on the substrate 101 side. A first semiconductor layer 416 is provided on the source electrode 408 side of the portion forming the first capacitance, and a third insulating film 415 is provided on the charge storage gate electrode 406 side. The first semiconductor layer 416 is of n-type. The structure of other portions of the FET, the method of making the FET normally-off, the effects when the FET is used as a switch, and similar alternative forms are the same as those of the embodiment shown in FIG. 3 described in

[0042] ,

[0043] ,

[0044] , and

[0045] . In this embodiment, the charge storage gate electrode 406 forms the first capacitance in a manner of riding on the source electrode 408, and the edge portion at the upper end of the film forming the source electrode 408 is included in the structure within the first capacitance. Since the electric field concentrates at the electrode edge portion and tunneling is likely to occur, the accumulation of negative charges on the charge storage gate electrode 406 can be performed more efficiently.

[0047] FIG. 5 is a diagram showing another embodiment of the second invention of the present application. The difference from the embodiment shown in FIG. 3 of this embodiment is that instead of the source electrode 508 extending to the charge storage gate electrode 506, the charge storage gate electrode 506 extends to the source electrode 508 to form the first capacitance. A first semiconductor layer 516 is provided on the source electrode 508 side of the portion forming the first capacitance, and a third insulating film 515 is provided on the charge storage gate electrode 506 side. The first semiconductor layer 516 is of n-type. The structure of other portions of the FET, the method of making the FET normally-off, the effects when the FET is used as a switch, and similar alternative forms are the same as those of the embodiment shown in FIG. 3 described in

[0042] ,

[0043] ,

[0044] , and

[0045] .

[0048] FIG. 6 is a diagram showing another embodiment of the second invention of the present application. The difference from the embodiment shown in FIG. 3 of this embodiment is that the source electrode 608 does not extend to the charge storage gate electrode 606, but the charge storage gate electrode 606 extends to the source electrode 608 to form a first capacitor. Another difference from the embodiment shown in FIG. 5 is that the charge storage gate electrode 606 extends so as to ride on the source electrode 608. A first semiconductor layer 616 is provided on the source electrode 608 side of the portion forming the first capacitor, and a third insulating film 615 is provided on the charge storage gate electrode 606 side. The structure of other parts of the FET, the method of making the FET normally-off, the effects when the FET is used as a switch, and similar alternative forms are the same as those of the embodiment shown in FIG. 3 described in

[0042] ,

[0043] ,

[0044] , and

[0045] .

[0049] FIG. 7 is a diagram showing another embodiment of the second invention of the present application. The difference from the embodiment shown in FIG. 3 of this embodiment is that the source electrode 708 extends further toward the drain electrode 109 side than the gate electrode 712 and forms a first capacitor with the charge storage gate electrode 706. A first semiconductor layer 716 is provided on the source electrode 708 side of the portion forming the first capacitor, and a third insulating film 715 is provided on the charge storage gate electrode 706 side. The structure of other parts of the FET, the method of making the FET normally-off, the effects when the FET is used as a switch, and similar alternative forms are the same as those of the embodiment shown in FIG. 3 described in

[0042] ,

[0043] ,

[0044] , and

[0045] . In this embodiment, the source electrode 708 extending further toward the drain electrode 109 side than the charge storage gate electrode 706 also functions as a so-called field plate. When the drain electrode 109 becomes a high voltage, most of the voltage is applied between the extending source electrode 708 and the drain electrode 109, so that the electric field concentration at the end of the charge storage gate electrode 706 on the drain electrode 109 side can be suppressed. Thereby, it is possible to prevent the outflow of the stored charge in the charge storage gate electrode 706, which is likely to occur in the electric field concentration portion, and the shortening of the life even as a normally-off FET. In the embodiment shown in FIG. 7, the source electrode 708 forms a third capacitor by capacitive coupling over the entire direction perpendicular to A-A' at the end of the charge storage gate electrode 706 on the drain electrode 109 side. However, the capacitive coupling portion may be limited to a part of the direction perpendicular to A-A', and further, the capacitive coupling portion may be formed on the element isolation region 114. Since the first capacitor has a lower capacitance, a larger voltage can be applied to the first capacitor during negative charge injection, and negative charges can be efficiently injected.

[0050] FIG. 8 is a diagram showing the structure of a field effect transistor device which is an embodiment of the third invention of the present application. A buffer layer 102, a first nitride semiconductor layer 103, and a second nitride semiconductor layer 104 are sequentially deposited on a substrate 101. As the substrate, Si, GaN, sapphire, SiC, etc. are used. Further, at least a part of the bandgap of the second nitride semiconductor layer 104 is larger than at least a part of the bandgap of the first nitride semiconductor layer 103. Thereby, a conductive channel 110 is formed on the first nitride semiconductor layer 103 side of the interface between the first nitride semiconductor layer 103 and the second nitride semiconductor layer 104. For example, GaN is used for the first nitride semiconductor layer 103 and AlGaN is used for the second nitride semiconductor layer 104. Here, when the composition of AlGaN is described as AlxGa1-xN, x satisfies the relationship of 0 < x ≦ 1. As the nitride semiconductor material, in addition to this, InN, ScN, or a mixed crystal semiconductor of these nitride semiconductors may also be used. As a characteristic part of the third invention of the present application, a plurality of divided charge storage gate electrodes 806 are provided on the first nitride semiconductor layer 104 with a first insulating film 805 interposed therebetween. The coupling capacitance between the gate electrode lower conductive carrier 813 formed in the conductive channel 110 below the charge storage gate electrode 806 and the charge storage gate electrode 806 is called the third capacitance. Further, a gate electrode 812 is formed on the charge storage gate electrode 806 with a second insulating film 811 interposed therebetween. The coupling capacitance between the gate electrode 812 and the charge storage gate electrode 806 is called the second capacitance. Also, source electrodes 808 and drain electrodes 109 are formed while sandwiching the charge storage gate electrode 806 in the horizontal direction. Both the source electrode 808 and the drain electrode 109 are electrically connected to the conductive channel 110 in an internal region surrounded by the element isolation region 114. In this embodiment, the plurality of divided charge storage gate electrodes 806 are all arranged so as to intersect the current flowing between the source electrode 808 and the drain electrode 109. The gate electrode 812 is capacitively coupled to the gate electrode part conductive carrier 813 via the second capacitance and the third capacitance connected in series. By changing the number of carriers of the gate electrode part conductive carrier 813 with the voltage applied to the gate electrode 812, the current flowing between the source electrode 808 and the drain electrode 109 can be adjusted, and the operation as a field effect transistor (FET) can be obtained.The charge storage gate electrode 806, gate electrode 812, source electrode 808, and drain electrode 109 are all assumed to include all the metallically connected portions on the substrate 100. Therefore, these electrodes do not necessarily need to be formed in a single process, and may be formed by making metal contact with films formed in a plurality of processes. This is the same in other embodiments of the third invention of the present application. Also, as the film material, a conventionally known single metal, alloy, compound metal, semiconductor in which impurities such as polysilicon are doped at a high concentration to reduce the resistance, or a combination of these materials may be used. This is also the same in other embodiments of the third invention of the present application. A part of the source electrode 808 extends so as to overlap with any of the plurality of divided charge storage gate electrodes 806, and a first capacitance is formed by the capacitive coupling between the source electrode 808 and the charge storage gate electrode 806. Also, a third insulating film 815 is provided on the charge storage gate electrode 806 side and a first semiconductor layer 816 is provided on the source electrode 808 side at the portion where the first capacitance is formed. The peripheral portions of the first capacitance, the second capacitance, and the third capacitance are protected by a protective insulating film 117. The protective insulating film 117 may be the insulating film used to form the first capacitance, the second capacitance, and the third capacitance, or another insulating film may be used. The first capacitance is used when accumulating charge in the charge storage gate electrode 806. Note that as the materials of the first insulating film 805, the second insulating film 811, and the third insulating film 815, conventionally known insulating film materials such as silicon oxide, silicon nitride, silicon oxynitride, alumina, hafnia, zirconia, or a laminated film or a mixed film of these materials may be used. Also, as the material of the first semiconductor layer 816, a conventionally known semiconductor material such as silicon, silicon carbide, nitride, or a laminated film or a mixed film of these may be used. The semiconductor layer may be either single crystal or polycrystalline. As described above in

[0031] , silicon carbide is preferable because it has a large bandgap and a high breakdown electric field strength. On the other hand, polycrystalline silicon is preferable in that it is easy to form as a thin film, and a good interface with few trap levels can be obtained when silicon oxide is used for the third insulating film 815. Silicon has a small bandgap and a low breakdown electric field strength, but a desired breakdown voltage can be obtained by making it thick enough.Alternatively, if thin silicon is used for the portion in contact with the insulating film 815 and a material with a large bandgap such as silicon carbide is used for the other portions, a structure excellent in both interface characteristics and breakdown voltage can be obtained. Also, the conductivity type of the first semiconductor layer 816 is made n-type and formed so as to obtain an ohmic or near-ohmic low-resistance electrical contact with respect to the source electrode 808. The n-type impurity concentration may be uniform or may have a gradient, with a low concentration on the side of the third insulating film 815 and a high concentration on the opposite side. When a gradient is provided, a low-resistance electrical contact can be obtained with the source electrode 808 while ensuring the breakdown voltage. Alternatively, when a material that generates polarization charges is used for the first semiconductor layer 816, a thin high-concentration impurity layer may be introduced for the purpose of canceling out the polarization charges. In this embodiment according to the third invention, since the charge storage gate electrode 806 is composed of a plurality of electrodes that intersect the direction of the current flowing between the source electrode 808 and the drain electrode 109, even if current leakage due to defects or the like occurs in any one of the first capacitor, the second capacitor, or the third capacitor connected to one of the charge storage gate electrodes 806 and the stored charge flows out, or even if electric field concentration occurs at some point and current leakage due to tunneling occurs and the stored charge flows out, the remaining charge storage gate electrodes 806 are not affected, so the threshold voltage of the entire FET is hardly affected. Thereby, the threshold voltage can be adjusted to a positive value and the life of the normally-off FET obtained by normal-off conversion can be extended. Also, it is possible to prevent a device failure due to becoming normally-on during operation.

[0051] The FET shown in FIG. 8 is equivalent to the FET shown in FIG. 4 except that the charge storage gate electrode 806 is composed of a plurality of electrodes, and is also functionally equivalent to the FET shown in FIG. 3. Therefore, the structure of other parts of the FET, the method of making the FET normally-off, the effects when the FET is used as a switch, and similar alternative forms are the same as those of the embodiment shown in FIG. 3 described in

[0042] ,

[0043] ,

[0044] , and

[0045] . Also, since the first capacitor is formed by capacitive coupling between the charge storage gate electrode 806 and the source electrode 808, no separate electrode is required for the accumulation of negative charges on the charge storage gate electrode 808 by the first capacitor. That is, the second invention of the present application is used in the same way as the FETs shown in FIGS. 3 and 4. Therefore, the external circuit when operating the FET can be simplified, the manufacturing process of the FET can be simplified, and further the area occupied by the FET on the substrate can be reduced. However, as another form, it may be formed between the first capacitor and an electrode for charge injection provided separately. In this case, one electrode for charge injection may be provided collectively for the plurality of divided charge storage gate electrodes 806, or may be provided separately in plurality.

[0052] FIG. 9 is a diagram showing the structure of a field effect transistor device which is another embodiment of the third invention of the present application. In this embodiment, a plurality of gate electrodes 906 for charge storage are formed on a second nitride semiconductor layer 104 with a first insulating film 905 interposed therebetween, and a gate electrode 912 is formed on the gate electrode 906 for charge storage with a second insulating film 911 interposed therebetween. The difference from the embodiment shown in FIG. 8 of this embodiment is that a plurality of gate electrodes 906 for charge storage are arranged along the direction of the current flowing between the source electrode 908 and the drain electrode 109. The first capacitor is formed in such a manner that the gate electrode 906 for charge storage extends and rides on the source electrode 908. The embodiment shown in FIG. 8 was similar to the embodiment of the second invention of the present application shown in FIG. 4, whereas this embodiment is similar to the embodiment of the second invention of the present application shown in FIG. 6. Other parts are the same as those of the embodiment shown in FIG. 8. Therefore, the description regarding the embodiment shown in FIG. 8 applies almost equally to other details. In this embodiment, unlike the embodiment shown in FIG. 8, the plurality of divided gate electrodes 906 for charge storage do not completely block the direction connecting the source electrode 908 and the drain electrode 109. However, even in this case, since the depletion of carriers in the lower conductive carrier 913 of the gate electrode due to the capacitive coupling with the gate electrode 912 also occurs in the lateral direction, the carriers can be eliminated including the inter-electrode portion of the gate electrode 906 for charge storage, and an off state can be realized. However, when the negative charge accumulated from one of the plurality of gate electrodes 906 for charge storage flows out, the current cannot be blocked at that portion, and a leakage current occurs in the off state. However, since the off state is maintained in the remaining portion, even when the FET is used as a switch, the influence on the entire device can be minimized.

[0053] In the above specification, as an example, the case where a negative charge is accumulated in the gate electrode for charge storage has been described. As a result, in an FET in which the conductive channel is composed of n-type conductive carriers (conduction electrons), the threshold voltage can be changed in the positive direction, and normally-off characteristics can be obtained. On the other hand, the present invention of the present application can also be applied to the case where a positive charge is accumulated in the charge storage layer. In this case, in the laminated film composed of the first semiconductor layer and the third insulating film, if the laminated positions of the first semiconductor layer and the third insulating film are interchanged, the outflow of the accumulated positive charge when a voltage in the reverse direction to that during positive charge accumulation is applied to the first capacitor can be suppressed. For example, when applied to an FET in which the conductive channel is composed of p-type conductive carriers (conduction holes), normally-off characteristics can be obtained.

[0054] In the above, the case where the present invention of the present application is applied to a nitride semiconductor FET has been described. A nitride semiconductor FET, particularly a nitride semiconductor HEMT, usually also has a very large negative threshold voltage, and the present invention regarding the normally-off conversion of the FET is particularly effective. However, the present invention is not limited to nitride semiconductor FETs, and can also be applied to FETs using other semiconductor materials. For example, silicon carbide (SiC) is used as a material for FETs for power switches in the same way as nitride semiconductors, but the present invention can be similarly applied to FETs made using SiC. Furthermore, in the above invention, a so-called lateral FET in which the source electrode and the drain electrode are formed on the same plane has been described, but the present invention can be similarly applied to a vertical FET in which the current between the source electrode and the drain electrode passes through a so-called drift layer and flows in the vertical direction.

Industrial Applicability

[0055] The field effect transistor device according to the first to third inventions of the present application can be widely applied in addition to the power switch mainly described in this specification, and can be applied, for example, as a transistor in a high-frequency device such as a power amplifier for wireless communication.

Explanation of Reference Numerals

[0056] 101, 1001 ··· Substrate 102, 1002... Buffer layer 103, 1003... First nitride semiconductor layer 104, 1004... Second nitride semiconductor layer 105, 505, 605, 705, 805, 905, 1005... First insulating film 106, 206, 306, 406, 506, 606, 706, 806, 906, 1006... Gate electrode for charge storage 107, 207, 1007, 1207, 1407... Electrode for charge injection 108, 308, 408, 508, 608, 708, 808, 908, 1008... Source electrode 109, 1009... Drain electrode 110, 1010... Conductive channel 111, 511, 611, 711, 811, 911, 1011... Second insulating film 112, 512, 612, 712, 812, 912, 1012... Gate electrode 113, 813, 913, 1013... Conductive carrier in gate electrode part 114, 1014... Element isolation region 115, 215, 315, 415, 615, 715, 815, 915, 1015, 1215, 1415... Third insulating film 116, 216, 316, 416, 516, 616, 716, 816, 916, 1216, 1416... First semiconductor layer 117... Protective insulating film 1101, 1201, 1401... Positive voltage 1102, 1105, 1202, 1402... Tunnel current 1103, 1203, 1403... Negative charge 1104, 1204, 1404... Negative voltage 1301... Current reduction 1405... Conductive hole at interface 1406... Backflow of negative charge

Claims

Claim 1 A semiconductor, a conductive channel provided in or on the surface of the semiconductor, a first insulating film provided adjacent to the conductive channel, a charge storage gate electrode at least a part of which is provided on the side opposite to the conductive channel of the first insulating film, a second insulating film provided on the side opposite to the first insulating film of the charge storage gate electrode, a gate electrode at least a part of which is provided on the side opposite to the charge storage gate electrode of the second insulating film, a source electrode and a drain electrode provided on the semiconductor with the charge storage gate electrode interposed therebetween and electrically connected to the conductive channel, a charge injection electrode that forms a first capacitance by capacitive coupling with the charge storage gate electrode, and a laminated film composed of a third insulating film and a first semiconductor layer provided between the charge injection electrode and the charge storage gate electrode, wherein charge is accumulated in the charge storage gate electrode by a first current flowing through the first capacitance, at least a part of the first current flows through the laminated film, the third insulating film is provided on the side of the charge storage gate electrode, the first semiconductor layer is provided on the side of the charge injection electrode, and the first semiconductor layer contains an n-type impurity, a field effect transistor device. **Claim 2**: A field effect transistor device comprising a semiconductor, a conductive channel provided in or on the surface of the semiconductor, a first insulating film provided adjacent to the conductive channel, a charge storage gate electrode at least a part of which is provided on the side opposite to the conductive channel of the first insulating film, a second insulating film provided on the side opposite to the first insulating film of the charge storage gate electrode, a gate electrode at least a part of which is provided on the side opposite to the charge storage gate electrode of the second insulating film, source and drain electrodes provided on the semiconductor with the charge storage gate electrode therebetween and electrically connected to the conductive channel, a charge injection electrode forming a first capacitance by capacitive coupling with the charge storage gate electrode, and a stacked film composed of a third insulating film and a first semiconductor layer provided between the charge injection electrode and the charge storage gate electrode, wherein charge is accumulated in the charge storage gate electrode by a first current flowing through the first capacitance, at least a part of the first current flows through the stacked film, the third insulating film is provided on the side of the charge injection electrode, the first semiconductor layer is provided on the side of the charge storage gate electrode, and the first semiconductor layer contains p-type impurities. **Claim 3** The field effect transistor device according to claim 1 or 2, wherein the semiconductor is a nitride semiconductor. **Claim 4** **Claim 4**: A field effect transistor device comprising a semiconductor, a conductive channel provided in or on the surface of the semiconductor, a first insulating film provided adjacent to the conductive channel, a charge storage gate electrode at least a part of which is provided on the side opposite to the conductive channel of the first insulating film, a second insulating film provided on the side opposite to the first insulating film of the charge storage gate electrode, a gate electrode at least a part of which is provided on the side opposite to the charge storage gate electrode of the second insulating film, source and drain electrodes provided on the semiconductor with the charge storage gate electrode therebetween and electrically connected to the conductive channel, wherein the source electrode or the drain electrode forms a first capacitance by capacitive coupling with the charge storage gate electrode, charge is accumulated in the charge storage gate electrode by a first current flowing through the first capacitance, and the semiconductor is a nitride semiconductor. **Claim 5** The field-effect transistor device according to claim 4, wherein a stacked film composed of a third insulating film and a first semiconductor layer is provided between the source electrode or the drain electrode forming the first capacitance and the charge storage gate electrode, and at least a part of the first current flows through the stacked film.

6. The field-effect transistor device according to claim 5, wherein the third insulating film is provided on the side of the charge storage gate electrode, the first semiconductor layer is provided on the side of the source electrode or the drain electrode forming the first capacitance, and the first semiconductor layer contains n-type impurities.

7. The field-effect transistor device according to claim 5, wherein the third insulating film is provided on the side of the source electrode or the drain electrode forming the first capacitance, the first semiconductor layer is provided on the side of the charge storage gate electrode, and the first semiconductor layer contains p-type impurities.

8. A field-effect transistor device having a semiconductor, a conductive channel provided in or on the surface of the semiconductor, a first insulating film provided adjacent to the conductive channel, a charge storage gate electrode at least a part of which is provided on the side opposite to the conductive channel of the first insulating film, a second insulating film provided on the side opposite to the first insulating film of the charge storage gate electrode, a gate electrode at least a part of which is provided on the side opposite to the charge storage gate electrode of the second insulating film, and a source electrode and a drain electrode provided on the semiconductor with the charge storage gate electrode interposed therebetween and electrically connected to the conductive channel, wherein the charge storage gate electrode is composed of a plurality of separated electrodes, and the plurality of electrodes of the charge storage gate electrode are all arranged along the current direction of the conductive channel.

9. The field-effect transistor device according to claim 8, wherein the semiconductor is a nitride semiconductor.

10. The field-effect transistor device according to claim 8 or 9, further comprising a charge injection electrode that forms a first capacitance by capacitive coupling with the charge storage gate electrode, and charges are accumulated in the charge storage gate electrode by a first current flowing through the first capacitance.

11. The field effect transistor device according to claim 10, wherein a stacked film composed of a third insulating film and a first semiconductor layer is provided between the charge injection electrode and the charge storage gate electrode, and at least a part of the first current flows through the stacked film. **Claim 12**: A semiconductor, a conductive channel provided in or on the surface of the semiconductor, a first insulating film provided adjacent to the conductive channel, a charge storage gate electrode at least a part of which is provided on the side opposite to the conductive channel of the first insulating film, a second insulating film provided on the side opposite to the first insulating film of the charge storage gate electrode, a gate electrode at least a part of which is provided on the side opposite to the charge storage gate electrode of the second insulating film, a source electrode and a drain electrode provided on the semiconductor with the charge storage gate electrode interposed therebetween and electrically connected to the conductive channel, a charge injection electrode that forms a first capacitance by capacitive coupling with the charge storage gate electrode, and a stacked film composed of a third insulating film and a first semiconductor layer provided between the charge injection electrode and the charge storage gate electrode, wherein the charge storage gate electrode is composed of a plurality of separated electrodes, charge is accumulated in the charge storage gate electrode by a first current flowing through the first capacitance, at least a part of the first current flows through the stacked film, the third insulating film is provided on the side of the charge storage gate electrode, the first semiconductor layer is provided on the side of the charge injection electrode, and the first semiconductor layer contains n-type impurities.

13. A semiconductor, a conductive channel provided in or on the surface of the semiconductor, a first insulating film provided adjacent to the conductive channel, a charge storage gate electrode at least a part of which is provided on the side opposite to the conductive channel of the first insulating film, a second insulating film provided on the side opposite to the first insulating film of the charge storage gate electrode, a gate electrode at least a part of which is provided on the side opposite to the charge storage gate electrode of the second insulating film, a source electrode and a drain electrode provided on the semiconductor with the charge storage gate electrode interposed therebetween and electrically connected to the conductive channel, a charge injection electrode that forms a first capacitance by capacitive coupling with the charge storage gate electrode, and a laminated film composed of a third insulating film and a first semiconductor layer provided between the charge injection electrode and the charge storage gate electrode, wherein the charge storage gate electrode is composed of a plurality of separated electrodes, charges are stored in the charge storage gate electrode by a first current flowing through the first capacitance, at least a part of the first current flows through the laminated film, the third insulating film is provided on the side of the charge injection electrode, the first semiconductor layer is provided on the side of the charge storage gate electrode, and the first semiconductor layer contains p-type impurities, a field effect transistor device.

14. The field effect transistor device according to claim 12 or 13, wherein the semiconductor is a nitride semiconductor.

15. A field - effect transistor device, comprising: a semiconductor; a conductive channel provided in or on the surface of the semiconductor; a first insulating film provided adjacent to the conductive channel; a charge - storage gate electrode at least a part of which is provided on the side opposite to the conductive channel of the first insulating film; a second insulating film provided on the side opposite to the first insulating film of the charge - storage gate electrode; a gate electrode at least a part of which is provided on the side opposite to the charge - storage gate electrode of the second insulating film; a source electrode and a drain electrode provided on the semiconductor with the charge - storage gate electrode therebetween and electrically connected to the conductive channel. The charge - storage gate electrode is composed of a plurality of separated electrodes. The source electrode or the drain electrode forms a first capacitance by capacitive coupling with the charge - storage gate electrode, and charges are accumulated in the charge - storage gate electrode by a first current flowing through the first capacitance.

16. The field - effect transistor device according to claim 15, wherein the semiconductor is a nitride semiconductor.

17. The field - effect transistor device according to claim 15 or 16, further comprising a stacked film composed of a third insulating film and a first semiconductor layer provided between the source electrode or the drain electrode forming the first capacitance and the charge - storage gate electrode, and at least a part of the first current flows through the stacked film.

18. The field - effect transistor device according to claim 17, wherein the third insulating film is provided on the side of the charge - storage gate electrode, the first semiconductor layer is provided on the side of the source electrode or the drain electrode forming the first capacitance, and the first semiconductor layer contains n - type impurities.

19. The field - effect transistor device according to claim 17, wherein the third insulating film is provided on the side of the source electrode or the drain electrode forming the first capacitance, the first semiconductor layer is provided on the side of the charge - storage gate electrode, and the first semiconductor layer contains p - type impurities.

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