Semiconductor device

Abstract

To provide semiconductor devices that can improve EM life.SOLUTION: An emitter electrode of a semiconductor element 40 has an Al electrode 422 and a Ni electrode 423 disposed on the Al electrode 422. A solder 91 joining the emitter electrode and a conductive spacer 70 includes Cu and Sn. An alloy layer 100 interposed between the emitter electrode and the solder 91 includes Ni, Cu, and Sn. The solder 91 has a smaller grain size on the semiconductor element 40 side than on the conductive spacer 70 side, at least in the portion overlapping a diode region 411d in the plan view in the Z direction.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] The disclosure in this specification relates to a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a semiconductor device having an IGBT region and a diode region on a common semiconductor substrate. The description of the prior art document is incorporated herein by reference as an explanation of the technical elements in this specification.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By adopting an RC-IGBT in which an IGBT and a diode for reflux are integrated, the size can be reduced. However, since the area of the diode region becomes small due to integration into one chip, the current density becomes high in the diode region, and EM becomes a problem. EM is an abbreviation for ElectroMigration. From the above viewpoints, or from other viewpoints not mentioned, further improvements are required for semiconductor devices.

[0005] This disclosure has been made in view of such problems, and an object thereof is to provide a semiconductor device capable of improving the EM lifetime.

Means for Solving the Problems

[0006] One disclosed semiconductor device includes a semiconductor element (40) having a semiconductor substrate (41) including an IGBT region (411i) and a diode region (411d), and an upper electrode (42) disposed on one surface of the semiconductor substrate. an upper conductor (70) arranged to face the upper electrode, an upper solder (91) interposed between the upper electrode and the upper conductor and joining the upper electrode and the upper conductor, an alloy layer (100) interposed between the upper electrode and the upper solder, and comprising, the upper electrode has an Al electrode (422) disposed on one surface and a Ni electrode (423) disposed on the Al electrode, the upper solder contains Cu and Sn, the alloy layer contains Ni, Cu, and Sn, in at least a portion of the upper solder that overlaps with the diode region in a plan view in the thickness direction of the semiconductor substrate, the particle size on the semiconductor element side is smaller than the particle size on the upper conductor side.

[0007] According to the disclosed semiconductor device, in a portion overlapping with the diode region where the current density is high, the particle size on the semiconductor element side of the upper solder is small. Thereby, disappearance of the alloy layer and the Ni electrode due to EM can be delayed. As a result, a semiconductor device capable of improving the EM life can be provided.

[0008] In order to achieve their respective objects, the plurality of aspects disclosed in this specification employ different technical means. The reference numerals in parentheses described in the claims and in this section are exemplarily shown for the correspondence with the parts of the embodiments described later, and are not intended to limit the technical scope. The objects, features, and effects disclosed in this specification will become clearer by referring to the subsequent detailed description and the attached drawings.

Brief Description of the Drawings

[0009]

Figure 1

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Embodiments for Carrying Out the Invention

[0010] Hereinafter, a plurality of embodiments will be described with reference to the drawings. In each embodiment, the same reference numerals may be given to corresponding components, and redundant explanations may be omitted. When only a part of the configuration is described in each embodiment, the configuration of other embodiments described previously can be applied to other parts of the said configuration. Also, not only the combinations of configurations explicitly shown in the description of each embodiment, but also the configurations of a plurality of embodiments can be partially combined with each other as long as there is no problem with the combination, even if not explicitly shown.

[0011] The semiconductor device of the present embodiment is applied, for example, to a power conversion device of a moving body having a rotating electric machine as a drive source. The moving body is, for example, an electric vehicle (BEV), a hybrid vehicle (HEV), a plug-in hybrid vehicle (PHEV), or other electric vehicles, a flying body such as an electric vertical takeoff and landing aircraft or a drone, a ship, a construction machine, or an agricultural machine. Hereinafter, an example applied to a vehicle will be described.

[0012] (First Embodiment) First, based on FIG. 1, the schematic configuration of the drive system of the vehicle will be described.

[0013] <Drive System of Vehicle> As shown in FIG. 1, the drive system 1 of the vehicle includes a DC power supply 2, a motor generator 3, and a power conversion device 4.

[0014] The DC power supply 2 is a DC voltage source composed of a rechargeable secondary battery. The secondary battery is, for example, a lithium-ion battery or a nickel-metal hydride battery. The motor generator 3 is a three-phase AC rotating electric machine. The motor generator 3 functions as a driving source for the vehicle to travel, that is, as an electric motor. The motor generator 3 functions as a generator during regeneration. The power conversion device 4 performs power conversion between the DC power supply 2 and the motor generator 3.

[0015] <Power Conversion Device> Next, based on FIG. 1, the circuit configuration of the power conversion device 4 will be described. The power conversion device 4 includes a power conversion circuit. As shown in FIG. 1, the power conversion device 4 includes a smoothing capacitor 5 and an inverter 6 which is a power conversion circuit.

[0016] The smoothing capacitor 5 mainly smooths the DC voltage supplied from the DC power supply 2. The smoothing capacitor 5 is connected to the P line 7 which is the high-potential side power line and the N line 8 which is the low-potential side power line. The P line 7 is connected to the positive electrode of the DC power supply 2, and the N line 8 is connected to the negative electrode of the DC power supply 2. The positive electrode of the smoothing capacitor 5 is connected to the P line 7 between the DC power supply 2 and the inverter 6. Similarly, the negative electrode is connected to the N line 8 between the DC power supply 2 and the inverter 6. The smoothing capacitor 5 is connected in parallel with the DC power supply 2.

[0017] The inverter 6 is a DC-AC conversion circuit. The inverter 6 converts the DC voltage into a three-phase AC voltage according to the switching control by a control circuit (not shown) and outputs it to the motor generator 3. Thereby, the motor generator 3 is driven to generate a predetermined torque. During the regenerative braking of the vehicle, the inverter 6 converts the three-phase AC voltage generated by the motor generator 3 receiving the rotational force from the wheels into a DC voltage according to the switching control by the control circuit and outputs it to the P line 7. In this way, the inverter 6 performs bidirectional power conversion between the DC power supply 2 and the motor generator 3.

[0018] The inverter 6 is configured to include three-phase upper and lower arm circuits 9. The upper and lower arm circuits 9 are sometimes referred to as legs. The upper and lower arm circuits 9 each have an upper arm 9H and a lower arm 9L. With the upper arm 9H on the P line 7 side, the upper arm 9H and the lower arm 9L are connected in series between the P line 7 and the N line 8. The connection point between the upper arm 9H and the lower arm 9L is connected to the corresponding phase winding 3a in the motor generator 3 via the output line 10. The inverter 6 has six arms. At least a part of each of the P line 7, the N line 8, and the output line 10 is constituted by a conductive member such as a bus bar.

[0019] The elements constituting each arm include an IGBT 11 which is a switching element, and a reflux diode 12. IGBT is an abbreviation for Insulated Gate Bipolar Transistor. In this embodiment, an n-channel type IGBT 11 is adopted. The diode 12 is connected in anti-parallel to the corresponding IGBT 11. In the upper arm 9H, the collector of the IGBT 11 is connected to the P line 7. In the lower arm 9L, the emitter of the IGBT 11 is connected to the N line 8. And the emitter of the IGBT 11 in the upper arm 9H and the collector of the IGBT 11 in the lower arm 9L are connected to each other. The anode of the diode 12 is connected to the emitter of the corresponding IGBT 11, and the cathode is connected to the collector.

[0020] The power conversion device 4 may further include a converter as a power conversion circuit. The converter is a DC-DC conversion circuit that converts a DC voltage into DC voltages of different values. The converter is provided between the DC power supply 2 and the smoothing capacitor 5. The converter is configured, for example, with a reactor and the above-described upper and lower arm circuits 9. According to this configuration, step-up and step-down are possible. The power conversion device 4 may include a filter capacitor for removing power supply noise from the DC power supply 2. The filter capacitor is provided between the DC power supply 2 and the converter.

[0021] The power conversion device 4 may include a drive circuit for the switching elements constituting the inverter 6 and the like. The drive circuit supplies a drive voltage to the gate of the IGBT 11 of the corresponding arm based on a drive command from the control circuit. The drive circuit drives the corresponding IGBT 11, that is, turns it on and off, by applying the drive voltage. The drive circuit is sometimes referred to as a driver.

[0022] The power conversion device 4 may include a control circuit for the switching element. The control circuit generates a drive command for operating the IGBT 11 and outputs it to the drive circuit. The control circuit generates a drive command based on a torque request input from a higher-level ECU (not shown) and signals detected by various sensors. Examples of the various sensors include a current sensor, a rotation angle sensor, and a voltage sensor. The current sensor detects the phase current flowing through the winding 3a of each phase. The rotation angle sensor detects the rotation angle of the rotor of the motor generator 3. The voltage sensor detects the voltage across the smoothing capacitor 5. The control circuit outputs, for example, a PWM signal as the drive command. The control circuit is configured to include, for example, a processor and a memory. ECU is an abbreviation for Electronic Control Unit. PWM is an abbreviation for Pulse Width Modulation.

[0023] <Semiconductor device> Next, based on FIGS. 2 to 6, the schematic configuration of the semiconductor device will be described. FIG. 2 is a plan view showing the semiconductor device. FIG. 2 is a plan view of the upper surface of the semiconductor device. FIG. 3 is a cross-sectional view taken along line III-III of FIG. 2. FIG. 4 is a cross-sectional view taken along line IV-IV of FIG. 2. FIG. 5 is a plan view showing the semiconductor element. FIG. 6 is a cross-sectional view taken along line VI-VI of FIG. 5.

[0024] Hereinafter, the thickness direction of the semiconductor element (semiconductor substrate) is defined as the Z direction. One direction orthogonal to the Z direction is defined as the X direction. The direction orthogonal to both the Z direction and the X direction is defined as the Y direction. Unless otherwise specified, the shape viewed from the Z direction in plan view, in other words, the shape along the XY plane defined by the X direction and the Y direction, is defined as the planar shape. Also, the plan view from the Z direction may be simply referred to as the plan view.

[0025] As shown in FIGS. 2 to 6, the semiconductor device 20 includes a sealing body 30, a semiconductor element 40, wiring members 50 and 60, a conductive spacer 70, and external connection terminals 80. The semiconductor device 20 further includes bonding wires 90 and solders 91 to 93. The semiconductor device 20 constitutes one of the above-described arms. That is, two semiconductor devices 20 constitute the upper and lower arm circuits 9 for one phase.

[0026] The sealing body 30 seals a part of the other elements constituting the semiconductor device 20. The remaining part of the other elements is exposed outside the sealing body 30. The sealing body 30 is made of, for example, resin. An example of the resin is an epoxy resin. The sealing body 30 is formed by, for example, a transfer molding method using resin. Such a sealing body 30 may be referred to as a sealing resin body, a molded resin, a resin molded body, or the like. The sealing body 30 may be formed using, for example, a gel. The gel is filled (disposed) in, for example, the opposing region between the pair of wiring members 50 and 60.

[0027] As shown in FIGS. 2 to 4, the sealing body 30 has a substantially rectangular planar shape. The sealing body 30 has a front surface 30a as an outer surface and a back surface 30b that is opposite to the front surface 30a in the Z direction. The front surface 30a and the back surface 30b are, for example, substantially flat surfaces. Further, the sealing body 30 has side surfaces 30c, 30d, 30e, and 30f that are continuous with the front surface 30a and the back surface 30b. The side surface 30c is the surface from which the main terminals 81 and 82 of the external connection terminals 80 protrude. The side surface 30d is the surface opposite to the side surface 30c in the Y direction. The side surface 30d is the surface from which the signal terminal 83 protrudes. The side surfaces 30e and 30f are the surfaces from which the external connection terminals 80 do not protrude. The side surface 30e is the surface opposite to the side surface 30f in the X direction.

[0028] The semiconductor device 40 includes a semiconductor substrate 41, an emitter electrode 42, a collector electrode 43, and a pad 44. The semiconductor device 40 may be referred to as a semiconductor chip. The semiconductor substrate 41 is made of silicon (Si), a wide-bandgap semiconductor having a wider bandgap than silicon, etc., and a vertical device is formed thereon. Examples of the wide-bandgap semiconductor include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond.

[0029] The vertical device is configured to allow a main current to flow in the thickness direction of the semiconductor substrate 41 (semiconductor device 40), that is, in the Z direction. The vertical device in this embodiment is the IGBT 11 and the diode 12 that constitute one arm. The vertical device is an IGBT in which the diode 12 is connected in anti-parallel, that is, an RC-IGBT. RC is an abbreviation for Reverse Conducting. The vertical device is a heating device that generates heat when energized. A gate electrode (not shown) is formed on the semiconductor substrate 41. The gate electrode has, for example, a trench structure.

[0030] As shown in FIG. 5, the semiconductor substrate 41 has a substantially rectangular planar shape. The semiconductor substrate 41 has an active region 411 and an outer peripheral region 412. The active region 411 is a region where the vertical device is formed. The active region 411 may be referred to as a main region, a main cell region, a cell region, an element region, an element formation region, etc. A breakdown voltage structure portion (not shown) such as a guard ring is formed in the outer peripheral region 412.

[0031] The active region 411 is aligned with the pad 44 in the Y direction. The active region 411 has, for example, a substantially rectangular planar shape. The active region 411 of the RC-IGBT has an IGBT region 411i, which is the formation region of the IGBT, and a diode region 411d, which is the formation region of the diode. The IGBT region 411i and the diode region 411d are alternately provided in the X direction. A plurality of cells (unit structural parts) are provided in the active region 411. The plurality of cells are connected in parallel to each other to form the RC-IGBT. As an example, the IGBT region 411i and the diode region 411d are alternately provided at a predetermined pitch. Both ends in the alignment direction are the IGBT region 411i. The area in plan view is larger for the IGBT region 411i than for the diode region 411d.

[0032] The semiconductor substrate 41 has a front surface 41a and a back surface 41b as the surfaces on which the main electrodes are provided. The front surface 41a is the surface on the side of the front surface 30a of the sealing body 30 in the semiconductor substrate 41. The back surface 41b is the surface opposite to the front surface 41a in the plate thickness direction. The emitter electrode 42, which is one of the main electrodes, is disposed on the front surface 41a of the semiconductor substrate 41. The collector electrode 43, which is the other main electrode, is disposed on the back surface 41b of the semiconductor substrate 41.

[0033] When the IGBT 11 is turned on, a current (main current) flows between the main electrodes, that is, between the emitter electrode 42 and the collector electrode 43. The emitter electrode 42 also serves as the anode electrode of the diode 12. The collector electrode 43 also serves as the cathode electrode of the diode 12. The collector electrode 43 is formed over substantially the entire back surface 41b of the semiconductor substrate 41. The emitter electrode 42 is formed on a part of the front surface 41a of the semiconductor substrate 41. The emitter electrode 42 corresponds to the upper electrode, and the collector electrode 43 corresponds to the lower electrode.

[0034] Pad 44 is an electrode for signals. Pad 44 is formed in a region different from the formation region of emitter electrode 42 on one surface 41a of semiconductor substrate 41. Pad 44 is formed at an end on the opposite side of the formation region of emitter electrode 42 in the Y direction. Pad 44 is provided side by side with emitter electrode 42 in the Y direction. The number of pads 44 is not particularly limited. Pad 44 includes at least a pad for a gate electrode.

[0035] As shown in FIG. 5 as an example, semiconductor element 40 has five pads 44. Specifically, it has a pad for a gate electrode, a pad for detecting the emitter potential, a pad for detecting the cathode potential of a temperature-sensitive diode (not shown) provided in semiconductor element 40, a pad for detecting the anode potential in the same way, and a pad for current sense. The five pads 44 are arranged side by side along the X direction.

[0036] As shown in FIGS. 5 and 6, semiconductor element 40 includes a protective film 45 disposed on one surface 41a of semiconductor substrate 41. Protective film 45 is an insulating film provided on one surface 41a of semiconductor substrate 41 so as to cover the peripheral portion of emitter electrode 42, specifically, Al electrode 422 described later. As the material of protective film 45, for example, polyimide, silicon nitride film, etc. can be adopted.

[0037] Protective film 45 has an opening 451, an outer peripheral portion 452, and a partitioning portion 453. Opening 451 defines the bonding region between emitter electrode 42 and solder 91. Opening 451 is a through hole that penetrates protective film 45 in the Z direction. Opening 451 is provided so as to overlap emitter electrode 42 in a plan view. Opening 451 substantially coincides with active region 411 in a plan view. Similarly, protective film 45 has an opening (not shown) that defines the bonding region in pad 44.

[0038] The outer peripheral portion 452 is disposed on the outer periphery of the semiconductor element 40. The outer peripheral portion 452 is arranged to substantially coincide with the outer peripheral region 412 in a plan view. The partitioning portion 453 partitions the Ni electrodes 423 into a plurality. As an example, the partitioning portion 453 of the present embodiment is provided so as to substantially bisect the Ni electrodes 423 in the X direction. The partitioning portion 453 partitions the opening 451 into two. The partitioning portion 453 extends in the Y direction passing through the center of the semiconductor element 40. One of the ends of the partitioning portion 453 is continuous with the outer peripheral portion 452 on the pad 44 side, and the other end is continuous with the outer peripheral portion 452 on the side opposite to the pad 44.

[0039] The emitter electrode 42 has an exposed portion 421 that is exposed from the opening 451 of the protective film 45 to provide a bonding region. The exposed portion 421 forms a bonding portion with the solder 91. In a plan view, the outer contour of the exposed portion 421 coincides with the outer contour of the opening 451. The exposed portion 421 is disposed on the active region 411 of the semiconductor substrate 41. The emitter electrode 42 has a multilayer structure. The emitter electrode 42 has an Al electrode 422 and a Ni electrode 423. The pad 44 also has the same configuration as the emitter electrode 42.

[0040] The Al electrode 422 is a metal layer formed adjacent to the semiconductor substrate 41 in the multilayer emitter electrode 42. The Al electrode 422 is formed using a material mainly composed of Al (aluminum). As an example, in the present embodiment, it is an Al alloy such as AlSi or AlSiCu. The Al electrode 422 may be referred to as an underlying electrode, a wiring electrode, an underlying layer, a first metal layer, etc. The Al electrode 422 is connected to one surface 41a of the semiconductor substrate 41.

[0041] The Al electrode 422 extends up to the outer peripheral region 412 while enclosing the active region 411 in plan view. The Al electrode 422 is connected to the emitter and anode of the vertical element. The Al electrode 422 has a peripheral portion 422a that surrounds the exposed portion 421 in plan view. The peripheral portion 422a is the portion of the Al electrode 422 that overlaps with the protective film 45. The protective film 45 is disposed on one surface 41a of the semiconductor substrate 41 so as to cover the peripheral portion 422a of the Al electrode 422.

[0042] The Ni electrode 423 is laminated and disposed on the Al electrode 422 for the purpose of improving the bonding strength with the solder 91 and improving the wettability with the solder 91. The Ni electrode 423 is formed using a material mainly composed of Ni (nickel). In this embodiment as an example, it is NiP formed by electroless plating. The Ni electrode 423 is a Ni plating film containing P. The Ni electrode 423 may be referred to as an upper electrode, a connection electrode, an upper layer, a second metal layer, a plating layer, a sound layer, etc.

[0043] Ni is harder than the Al alloy constituting the Al electrode 422. In the manufacturing process, an Au electrode may be further provided on the Ni electrode 423. Au, for example, suppresses the oxidation of Ni and improves the wettability with the solder 91 which is the solder. Since Au diffuses into the solder during soldering, it exists in the state before bonding and does not exist in the bonded state.

[0044] The Ni electrode 423 is laminated and disposed on the Al electrode 422 and is exposed from the opening 451. As an example, the Ni electrode 423 of this embodiment is disposed on the Al electrode 422 within the opening 451. And the outer peripheral end portion of the Ni electrode 423 is in contact with the wall surface of the protective film 45 that defines the opening 451.

[0045] The wiring member 50 is electrically connected to the emitter electrode 42 and provides a wiring function. Similarly, the wiring member 60 is electrically connected to the collector electrode 43 and provides a wiring function. The wiring members 50 and 60 are arranged so as to sandwich the semiconductor element 40 in the Z direction. The wiring members 50 and 60 are arranged so that at least a part of them faces each other in the Z direction. The wiring members 50 and 60 enclose the semiconductor element 40 in a plan view. The wiring member 60 corresponds to the lower conductor.

[0046] The wiring members 50 and 60 provide a heat dissipation function for dissipating the heat generated by the semiconductor element 40. The wiring members 50 and 60 may be referred to as a heat sink, a heat sink, etc. The wiring members 50 and 60 in the present embodiment are metal plates made of a metal having good conductivity such as Cu or a Cu alloy. The metal plate is provided, for example, as a part of a lead frame. Instead of the metal plate, a substrate in which metal bodies are arranged on both sides of an insulating substrate may be employed. The wiring members 50 and 60 may be provided with a plating film such as Ni or Au on the surface.

[0047] The wiring member 50 has a facing surface 50a which is a surface on the semiconductor element 40 side, and a back surface 50b which is a surface opposite to the facing surface 50a. Similarly, the wiring member 60 also has a facing surface 60a and a back surface 60b. The wiring members 50 and 60 have, for example, a substantially rectangular shape in plan view. The back surfaces 50b and 60b of the wiring members 50 and 60 are exposed from the sealing body 30. The back surfaces 50b and 60b may be referred to as a heat dissipation surface, an exposed surface, etc. The back surface 50b of the wiring member 50 is substantially flush with one surface 30a of the sealing body 30. The back surface 60b of the wiring member 60 is substantially flush with the back surface 30b of the sealing body 30.

[0048] The conductive spacer 70 is interposed between the semiconductor element 40 and the wiring member 50. The conductive spacer 70 provides a spacer function for securing a predetermined interval between the semiconductor element 40 and the wiring member 50. For example, the conductive spacer 70 secures a height for electrically connecting the corresponding signal terminal 83 to the pad 44 of the semiconductor element 40. The conductive spacer 70 is positioned in the middle of the electrical conduction and heat conduction paths between the emitter electrode 42 of the semiconductor element 40 and the wiring member 50, and provides a wiring function and a heat dissipation function. The conductive spacer 70 corresponds to the upper conductor.

[0049] The conductive spacer 70 contains a metal material with good electrical and heat conductivity such as Cu. The conductive spacer 70 may have a plating film on its surface. The conductive spacer 70 may be referred to as a terminal, a terminal block, a metal block body, etc. The conductive spacer 70 of the present embodiment is a columnar body having a substantially rectangular planar shape.

[0050] The external connection terminal 80 is a terminal for electrically connecting the semiconductor device 20 to an external device. The external connection terminal 80 is formed using a metal material with good electrical conductivity such as copper. The external connection terminal 80 is, for example, a plate material. The external connection terminal 80 may be referred to as a lead. The external connection terminal 80 includes main terminals 81, 82 and a signal terminal 83. The main terminals 81, 82 are external connection terminals 80 electrically connected to the main electrodes of the semiconductor element 40.

[0051] The main terminal 81 is electrically connected to the emitter electrode 42. The main terminal 81 may be referred to as an emitter terminal. The main terminal 81 is connected to the emitter electrode 42 via the wiring member 50. The main terminal 81 is continuous with one end of the wiring member 50 in the Y direction. The thickness of the main terminal 81 is thinner than that of the wiring member 50. The main terminal 81 is continuous with the wiring member 50 so as to be substantially flush with the opposing surface 50a, for example. The main terminal 81 may be continuous by being continuously and integrally provided with respect to the wiring member 50, or may be provided as a separate member and be continuous by joining.

[0052] The main terminal 81 of this embodiment is provided integrally with the wiring member 50 as a part of the lead frame. The main terminal 81 extends in the Y direction from the wiring member 50 and protrudes outward from the side surface 30c of the sealing body 30. The main terminal 81 has a bent portion in the middle of the portion covered by the sealing body 30 and protrudes from near the center in the Z direction on the side surface 30c.

[0053] The main terminal 82 is electrically connected to the collector electrode 43. The main terminal 82 may be referred to as a collector terminal. The main terminal 82 is connected to the collector electrode 43 via the wiring member 60. The main terminal 82 is continuous with one end in the Y direction of the wiring member 60. The thickness of the main terminal 82 is thinner than that of the wiring member 60. The main terminal 82 is continuous with the wiring member 60 so as to be substantially flush with the opposing surface 60a, for example. The main terminal 82 may be continuous by being continuously and integrally provided with respect to the wiring member 60, or may be provided as a separate member and be continuous by bonding.

[0054] The main terminal 82 of this embodiment is provided integrally with the wiring member 60 as a part of a lead frame different from the main terminal 81. The main terminal 82 extends in the Y direction from the wiring member 60 and protrudes outward from the same side surface 30c as the main terminal 81. The main terminal 82 also has a bent portion in the middle of the portion covered by the sealing body 30 and protrudes from near the center in the Z direction on the side surface 30c. The two main terminals 81 and 82 are arranged side by side in the X direction so that their side surfaces face each other.

[0055] The signal terminal 83 is electrically connected to the corresponding pad 44 of the semiconductor element 40. The signal terminal 83 is electrically connected to the pad 44 via the bonding wire 90. The signal terminal 83 extends in the Y direction and protrudes outward from the side surface 30d of the sealing body 30. The semiconductor device 20 of this embodiment includes five signal terminals 83 corresponding to the pads 44. The five signal terminals 83 are arranged side by side in the X direction. The signal terminal 83 is formed, for example, on a lead frame common to the wiring member 60 and the main terminal 82. The plurality of signal terminals 83 are electrically separated from each other by cutting a tie bar (not shown).

[0056] The solder 91 is interposed between the emitter electrode 42 of the semiconductor element 40 and the conductive spacer 70, and joins the emitter electrode 42 and the conductive spacer 70. The solder 91 may be referred to as an on-element solder. The solder 91 corresponds to the upper solder. The solder 92 is interposed between the conductive spacer 70 and the wiring member 50, and joins the conductive spacer 70 and the wiring member 50. The solder 92 may be referred to as an on-spacer solder. The solder 93 is interposed between the collector electrode 43 of the semiconductor element 40 and the wiring member 60, and joins the collector electrode 43 and the wiring member 60. The solder 93 may be referred to as an under-element solder. The solder 93 corresponds to the lower solder.

[0057] The solders 91 to 93 may use the same material as each other, or may use different materials from each other. The solder 91 contains Cu and Sn. The solder 91 is, as an example, a multi-component lead-free solder containing Cu, Bi, Sb, etc., with the balance being Sn.

[0058] As described above, in the semiconductor device 20, the semiconductor element 40 that constitutes one arm is encapsulated by the encapsulation body 30. The encapsulation body 30 integrally encapsulates a part of the semiconductor element 40, a part of the wiring member 50, a part of the wiring member 60, the conductive spacer 70, and a part of the external connection terminal 80.

[0059] The semiconductor element 40 is disposed between the wiring members 50 and 60 in the Z direction. The semiconductor element 40 is sandwiched by the opposed wiring members 50 and 60. Thereby, the heat of the semiconductor element 40 can be dissipated to both sides in the Z direction. The semiconductor device 20 has a double-sided heat dissipation structure. The back surface 50b of the wiring member 50 is substantially flush with one surface 30a of the encapsulation body 30. The back surface 60b of the wiring member 60 is substantially flush with the back surface 30b of the encapsulation body 30. Since the back surfaces 50b and 60b are exposed surfaces, the heat dissipation performance can be enhanced.

[0060] <Element upper structure and particle size of solder> Next, based on FIGS. 7 and 8, the upper element structure and the solder particle size will be described. FIG. 7 is a cross-sectional view showing the upper element structure of the semiconductor device 20 according to the present embodiment. FIG. 7 is an enlarged cross-sectional view of the periphery of the emitter electrode 42. FIG. 7 is a cross-sectional view corresponding to line VII-VII in FIG. 5. FIG. 8 is a cross-sectional view showing the upper element structure of the reference example. In the reference example, the reference numerals of each element are those obtained by adding "r" to the end of the reference numerals of the related elements of the semiconductor device 20.

[0061] As shown in FIG. 7, the semiconductor device 20 includes an alloy layer 100 interposed between the Ni electrode 423 and the solder 91. The alloy layer 100 may be referred to as an IMC. IMC is an abbreviation for Intermetallic Compound. The alloy layer 100 is formed during bonding. The alloy layer 100 contains Ni, Cu, and Sn. The composition of the alloy layer 100 is, for example, (Ni-Cu)3Sn4.

[0062] The semiconductor device 20 further includes a P-rich layer 424. The P-rich layer 424 is formed on the surface of the Ni electrode 423. The P-rich layer 424 is formed by diffusion of a part of Ni in the Ni electrode 423 toward the solder 91 during bonding. The P-rich layer 424 is a layer richer in P than the Ni electrode 423 (NiP). The composition of the P-rich layer 424 is, for example, Ni3P.

[0063] The Ni electrode 423 has irregularities 4231 formed continuously on the surface of at least the portion overlapping with the diode region 411d. The irregularities 4231 are formed by, for example, continuous repetition of concave and convex in the X direction. The repetition direction of the irregularities 4231 is not limited to the X direction. For example, it may be the Y direction, or both the X direction and the Y direction. The irregularities 4231 may be provided in a checkerboard pattern. The step of the irregularities 4231 is, for example, about 1 μm. Since the Ni electrode 423 has the irregularities 4231, the P-rich layer 424 and the alloy layer 100 disposed on the Ni electrode 423 also have an irregular shape.

[0064] The concavo-convex portion 4231 is formed, for example, by patterning the surface of the Ni electrode 423. Instead of this, the concavo-convex portion 4231 may be provided on the surface of the Ni electrode 423 by providing a concavo-convex structure on the Al electrode 422 located directly below the Ni electrode 423. The concavo-convex portion 4231 may be provided on the surface of the Ni electrode 423 by providing a concavo-convex structure on one surface 41a of the semiconductor substrate 41 with an interlayer insulating film or the like.

[0065] The solder 91 starts grain growth during solidification of the solder 91 starting from the concavities and convexities derived from the Ni electrode 423. Grain boundaries 910 are formed by adjacent grains colliding with each other. The crystal grains grow starting from the concavities and convexities and become smaller on the semiconductor element 40 side. Therefore, in at least the portion of the solder 91 that overlaps with the diode region 411d, the grain size on the semiconductor element 40 side is smaller than the grain size on the conductive spacer 70 side. In the solder 91, the portion closer to the semiconductor element 40 than the center in the Z direction is the semiconductor element 40 side, and the portion closer to the conductive spacer 70 than the center is the conductive spacer 70 side.

[0066] Also, although not shown, the grain size on the semiconductor element 40 side in at least the portion of the solder 91 that overlaps with the diode region 411d is smaller than the grain size of the solder 93. The thickness of the solder 91 is, for example, about 100 μm. In the example shown in FIG. 7, the conductive spacer 70 has a plating film 71 on its surface. The plating film 71 has Ni as a main component, similar to the Ni electrode 423. The alloy layer between the plating film 71 and the solder 91 is not shown for the sake of convenience. As shown in FIG. 7, the plating film 71 is not provided with concavo-convex portions.

[0067] In the comparative example shown in FIG. 8, the surface of the Ni electrode 423r does not have uneven portions. That is, the particle size of the solder 91r is not controlled. For other configurations, they are the same as those of the semiconductor device 20 of the present embodiment. In such a case, the particle size of the solder 911r is about 100 μm. The crystal grains of the solder 911r are present one or two in number in the thickness direction (Z direction) of the solder 91. Therefore, in the entire area of the solder 91r, the particle sizes on the semiconductor element 40r side and the conductive spacer 70r side are both large. The particle size on the semiconductor element 40r side and the particle size on the conductive spacer 70r side are about the same as each other.

[0068] <em> Next, based on FIG. 9, electromigration (EM) will be described. FIG. 9 is a reference diagram showing the mechanism of EM progress. Also in FIG. 9, the reference numerals of each element are assumed to be those obtained by adding "r" to the end of the reference numerals of the related elements of the semiconductor device 20. In the example shown in the reference diagram, similar to the configuration shown in FIG. 8, the particle size control of the solder 91r is not performed. For other configurations, they are the same as those of the semiconductor device 20 of the present embodiment.

[0069] The 1st in FIG. 9 shows the initial stage before energization. An alloy layer 100r is interposed between the Ni electrode 423r and the solder 91r. Also, a P-rich layer 424r is formed on the surface of the Ni electrode 423r.

[0070] The 2nd, 3rd, and 4th in FIG. 9 show the application of the reflux current. The dashed arrow indicates the direction in which electrons (e-) flow. That is, the reflux current flows from the conductive spacer side (not shown) to the semiconductor element side. The reflux current is the current that flows during the diode operation.

[0071] As shown in the 2nd of FIG. 9, with the movement of electrons, Cu etc. in the alloy layer 100r on the diode region move (diffuse) to the conductive spacer side. Specifically, metals such as Cu are ionized and move to the conductive spacer side. As a result, the alloy layer 100r gradually becomes thinner and disappears as shown in the 3rd of FIG. 9.

[0072] When the alloy layer 100r disappears, as shown in the 3rd of FIG. 9, with the movement of electrons, Ni in the Ni electrode 423r moves (diffuses) to the conductive spacer side, the Ni electrode 423r decreases, and the P-rich layer 424r increases. Then, as shown in the 4th of FIG. 9, the Ni electrode 423r disappears, and the P-rich layer 424r reaches the Al electrode 422r. That is, the P-rich layer 424r replaces the Ni electrode 423r.

[0073] After the P-rich layer 424r reaches the Al electrode 422r, if it further progresses, the adhesion decreases, for example, voids are generated. Also, starting from the voids, cracks along the interface are generated.

[0074] As described above, in the configuration where the solder particle size is not controlled (see FIG. 8), the particle size of the solder 91 is large. There are few grain boundaries in the movement path of Cu. Therefore, the Cu in the alloy layer 100r is likely to move as the electrons move.

[0075] On the other hand, in the configuration of the present embodiment (see FIG. 7), directly above the diode region 411d where the current density is high, the particle size of the solder 91 on the semiconductor element 40 side is smaller than the particle size on the conductive spacer 70 side. That is, there are many grain boundaries 910 on the semiconductor element 40 side. Therefore, as the electrons move, the Cu in the alloy layer 100 is difficult to move. That is, the alloy layer 100 is difficult to disappear. The time required for the alloy layer 100 to disappear becomes longer. As a result, the time when the Ni electrode 423 starts to decrease and becomes the P-rich layer 424 is delayed. The time required for the Ni electrode 423 to disappear becomes longer.

[0076] <Summary of the First Embodiment> By adopting an RC-IGBT in which the IGBT 11 and the diode 12 are integrated into one chip, for example, the size of the semiconductor device 20 can be reduced. However, the area of the diode region 411d becomes smaller due to the integration into one chip, and the current density in the diode region 411d becomes high.

[0077] In the present embodiment, at least in the portion overlapping with the diode region 411d, the particle size of the solder 91 on the semiconductor element 40 side is smaller than the particle size on the conductive spacer 70 side. There are many grain boundaries 910 on the semiconductor element 40 side. The grain boundaries 910 inhibit the movement of Cu. Therefore, as the electrons move, the Cu in the alloy layer 100 is difficult to move. Thus, the time required for the alloy layer 100 to disappear can be lengthened. Also, the time required for the Ni electrode 423 to disappear can be lengthened. From the above, the EM life can be improved. In particular, in the present embodiment, the area of the diode region 411d is smaller than the area of the IGBT region 411i, and the current density in the conduction path in the diode region 411d is the maximum. However, since the particle size of the solder 91 on the semiconductor element 40 side is reduced, the EM life can be improved.

[0078] Note that the effect of the particle size of solder 91 has been confirmed through trial production. By reducing the particle size of solder 91 on the semiconductor element 40 side, it was confirmed that the disappearance of the alloy layer 100 is delayed, that is, the progress of EM can be delayed. At this time, the Ni electrode 423 was formed by electroless NiP plating. The composition of the alloy layer 100 was (Ni-Cu)3Sn4.

[0079] The particle size of solder 91 on the semiconductor element 40 side only needs to be smaller than the particle size on the conductive spacer 70 side at least in the portion overlapping with the diode region 411d. For example, only in the portion overlapping with the diode region 411d, the particle size of solder 91 on the semiconductor element 40 side may be smaller than the particle size on the conductive spacer 70 side. In the diode region 411d and the IGBT region 411i, the particle size of solder 91 on the semiconductor element 40 side may be smaller than the particle size on the conductive spacer 70 side.

[0080] In this embodiment, the particle size of solder 91 on the semiconductor element 40 side in at least the portion overlapping with the diode region 411d is smaller than the particle size of solder 93. Solder 93 has an uncontrolled particle size and a large particle size. By controlling the particle size, the particle size of solder 91 on the semiconductor element 40 side is smaller than that of solder 93 at least in the portion overlapping with the diode region 411d. Therefore, there are many grain boundaries 910 on the semiconductor element 40 side of solder 91 at least in the portion overlapping with the diode region 411d. The grain boundaries 910 inhibit the movement of Cu. For this reason, it is difficult for the Cu of the alloy layer 100 to move as the electrons move. Therefore, the time taken until the alloy layer 100 disappears can be lengthened. Also, the time taken until the Ni electrode 423 disappears can be lengthened.

[0081] In this embodiment, the Ni electrode 423 has uneven portions 4231 with continuously formed unevenness on the surface of at least the portion overlapping the diode region 411d. By providing the uneven portions 4231 on the Ni electrode 423 in this way, the particle size becomes smaller on the semiconductor element 40 side. With a simple structure, the EM life can be improved. Also, the portion with a small solder particle size can be controlled according to the formation range of the uneven portions 4231.

[0082] (Second Embodiment) This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be incorporated by reference. In the preceding embodiment, by providing the uneven portions 4231 on the surface of the Ni electrode 423, the solder particle size on the semiconductor element 40 side was reduced. Instead of this, unevenness may be provided at the end of the protective film 45.

[0083] FIG. 10 is a plan view showing the semiconductor element 40 in the semiconductor device 20 according to this embodiment. In FIG. 10, illustration of the active region 411 including the IGBT region 411i and the diode region 411d and the outer peripheral region 412 is omitted. The active region 411 including the IGBT region 411i and the diode region 411d and the outer peripheral region 412 have the same configuration as shown in FIG. 5.

[0084] Similar to the preceding embodiment, the protective film 45 has a partitioning portion 453. The partitioning portion 453 extends in the Y direction passing through the center of the semiconductor element 40. The partitioning portion 453 is provided so as to substantially bisect the Ni electrode 423 in the X direction. In plan view, the ends of the partitioning portion 453 have a continuous uneven shape. The protective film 45 has uneven portions 454 at the ends of the partitioning portion 453. As an example, the uneven portions 454 are provided at both ends of the partitioning portion 453. The uneven portions 454 are provided over the entire length of the partitioning portion 453 in the Y direction.

[0085] FIG. 11 is an enlarged view of region XI in FIG. 10. FIG. 11 shows solder 91 disposed on emitter electrode 42. In FIG. 11, only a part of grain boundary 910 is shown. Solder 91 grows in grains during solidification starting from the unevenness provided at the end of partition portion 453. Since it grows starting from such unevenness, the crystal grains become smaller on the semiconductor element 40 side. In particular, in plan view, the crystal grains at positions closer to the center of semiconductor element 40 become smaller.

[0086] <Summary of the Second Embodiment> According to the configuration described in this embodiment, the same effects as the configuration described in the previous embodiment can be achieved. Specifically, the end of partition portion 453 has a continuous uneven shape. Thus, since crystal grains grow starting from the unevenness of protective film 45, the particle size becomes smaller on the semiconductor element 40 side. Therefore, as in the previous embodiment, the EM lifetime can be improved.

[0087] Moreover, uneven portion 454 is provided at the end of partition portion 453 passing through the center of semiconductor element 40. The solder particle size becomes smaller the closer it is to uneven portion 454 and larger as it moves away in plan view. That is, the particle size of solder 91 becomes smaller near the center of semiconductor element 40. In particular, near the center where the temperature is high and EM is promoted, the solder particle size on diode region 411d can be made smaller.

[0088] The arrangement of partition portion 453 is not limited to the example described above. For example, partition portion 453 may be arranged in a planar cross shape so as to roughly quarter Ni electrode 423. Partition portion 453 includes a portion extending in the X direction and a portion extending in the Y direction. In such a configuration, uneven portions 454 may be provided at both ends of the portion extending in the X direction, or uneven portions may be provided at both ends of the portion extending in the Y direction. Of course, uneven portions 454 may be provided at both ends of both the portion extending in the X direction and the portion extending in the Y direction.

[0089] Although an example in which the uneven portion 454 is provided over the entire length of the partitioning portion 453 has been shown, the present invention is not limited thereto. The uneven portion 454 may be provided at least in part of the entire length of the partitioning portion 453. Further, it may be provided only at one end portion instead of both end portions of the partitioning portion 453. By making at least a part of the end portion of the partitioning portion 453 uneven, the solder particle size can be reduced.

[0090] (Third Embodiment) This embodiment is a modified example based on the preceding embodiment, and the description of the preceding embodiment can be incorporated. In the preceding embodiment, cooling during solidification of the solder 91 was not particularly mentioned. Instead, the solder 91 may be solidified by cooling from a predetermined direction.

[0091] <Manufacturing Method> An example of a manufacturing method will be described for the semiconductor device 20 shown in the first embodiment.

[0092] First, each element constituting the semiconductor device 20 is prepared. Specifically, a semiconductor element 40, wiring members 50, 60, a conductive spacer 70, and an external connection terminal 80 are prepared. At this time, a semiconductor element 40 having an uneven portion 4231 on the surface of the Ni electrode 423 is prepared. For the wiring member 60, for example, it is prepared as a lead frame including a main terminal 82 and a signal terminal 83.

[0093] Next, the semiconductor element 40 is disposed on the opposing surface 60a of the wiring member 60 via the solder 93. The semiconductor element 40 is disposed on the solder 93 such that the collector electrode 43 faces the wiring member 60. Next, the conductive spacer 70 is disposed on the emitter electrode 42 via the solder 91. The solder 92 is disposed on the surface of the conductive spacer 70 opposite to the semiconductor element 40. For the solder 92, an amount capable of absorbing height variations in the semiconductor device 20 is disposed. The solders 91, 92, 93 are provided, for example, as solder foils. The solder 92 may be applied as a receiving solder to the conductive spacer 70.

[0094] In this stacked state, the first reflow is performed. As a result, the semiconductor element 40, the wiring member 60, and the conductive spacer 70 are stacked, and a connected body that is integrally connected is obtained. Next, the pad 44 of the semiconductor element 40 and the signal terminal 83 are connected by the bonding wire 90.

[0095] Next, with the opposing surface 50a facing upward, the wiring member 50 is disposed on one surface of a pedestal (not shown). Then, the above-described connected body is disposed on the wiring member 50 such that the solder 92 faces the wiring member 50, and the second reflow is performed. In the second reflow, a load is applied in the Z direction from the side of the wiring member 60 so that the height of the semiconductor device 20 becomes a predetermined height.

[0096] Next, the sealing body 30 is formed. Although not shown, in this embodiment, the sealing body 30 is molded by the transfer molding method. The sealing body 30 is molded so as to completely cover the wiring members 50 and 60, and cutting is performed after molding. The sealing body 30 is cut together with a part of the wiring members 50 and 60. As a result, the back surfaces 50b and 60b are exposed. The back surface 50b is substantially flush with the one surface 30a, and the back surface 60b is substantially flush with the back surface 30b.

[0097] Note that the sealing body 30 may be molded in a state where the back surfaces 50b and 60b are pressed against and adhered to the cavity wall surface of the molding die. In this case, when the sealing body 30 is molded, the back surfaces 50b and 60b are exposed from the sealing body 30. Therefore, cutting after molding becomes unnecessary.

[0098] Next, the semiconductor device 20 can be obtained by removing unnecessary portions of the lead frame such as the tie bar and the outer peripheral frame.

[0099] <Cooling of the solder 91> FIG. 12 is a cross-sectional view showing the cooling process in the first reflow. In FIG. 12, for convenience, the solder 92 is omitted from the illustration.

[0100] In this embodiment, as shown in FIG. 12, during the cooling after heating in the reflow process, the connector is cooled from the wiring member 60 side. As a result, the solder 91 cools earlier from the semiconductor element 40 side. The solder 91 solidifies from the semiconductor element 40 side. The solder 91 starts to grow grains during solidification starting from the irregularities derived from the Ni electrode 423. By cooling from the wiring member 60 side, the grain growth starting from the irregularities can be promoted.

[0101] <Summary of the Third Embodiment> According to this embodiment, during the cooling after heating in the reflow process, the connector is cooled from the wiring member 60 side. That is, the solder 91 is cooled so that the semiconductor element 40 side cools earlier than the conductive spacer 70 side. As a result, the solder 91 solidifies from the semiconductor element 40 side. Therefore, it is possible to promote the occurrence of grain growth starting from the irregularities derived from the Ni electrode 423. Accordingly, the crystal grains become smaller on the semiconductor element 40 side. That is, by the above-described cooling, it is possible to promote the formation of small grains on the semiconductor element 40 side of the solder 91 at least in the portion overlapping with the diode region 411d.

[0102] The above-described cooling may be combined with the configuration described in the second embodiment. Since the solder 91 solidifies from the semiconductor element 40 side, it is possible to promote the occurrence of grain growth starting from the irregularities of the partition portion 453 of the protective film 45.

[0103] (Fourth Embodiment) This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be incorporated. In the preceding embodiment, by devising the semiconductor element 40, the particle size on the semiconductor element 40 side in the solder 91 was reduced. Instead, the particle size of the solder on the semiconductor element 40 side may be reduced by devising the solder 91.

[0104] FIG. 13 is a cross-sectional view showing the upper element structure in the semiconductor device 20 according to this embodiment. FIG. 13 is an enlarged cross-sectional view of the periphery of the emitter electrode 42. FIG. 13 corresponds to FIG. 7.

[0105] As shown in FIG. 13, conductive balls 94 are added to the solder 91. The balls 94 are mainly composed of Ni or Cu. Such balls 94 may be referred to as Ni balls or Cu balls. The balls 94, for example, guarantee the minimum thickness of the solder 91. Due to the presence of the balls 94, the solder 91 grows in grains starting from the balls 94 during solidification. Since the growth starts from the balls 94, the crystal grains on the semiconductor element 40 side are smaller compared to the configuration where the balls 94 are not added. In at least the portion overlapping the diode region 411d, the grain size of the solder 91 on the semiconductor element 40 side is smaller than the grain size on the conductive spacer 70 side.

[0106] <Summary of the Fourth Embodiment> According to the configuration described in this embodiment, the same effects as the configuration described in the previous embodiment can be achieved. Specifically, since the balls 94 are added to the solder 91, grain growth starts from the balls 94, and the crystal grains on the semiconductor element 40 side become smaller. As a result, in at least the portion overlapping the diode region 411d, the grain size of the solder 91 on the semiconductor element 40 side is smaller than the grain size on the conductive spacer 70 side. Therefore, the EM life can be improved.

[0107] Note that the effects of the balls 94 have also been confirmed through prototypes. It has been confirmed that by adding the balls 94, the grain size of the solder 91 on the semiconductor element 40 side becomes smaller. It has also been confirmed that the disappearance of the alloy layer 100 is delayed, that is, the progress of EM can be slowed down. At this time, the Ni electrode 423 was formed by electroless NiP plating. The composition of the alloy layer 100 was (Ni-Cu)3Sn4.

[0108] <Modification Example> The solder 91 may have a multilayer structure, and the occupancy rate of the balls 94 per unit volume may vary depending on the layer. In the example shown in FIG. 14, the solder 91 has a first layer 911 and a second layer 912. The first layer 911 is the layer on the semiconductor element 40 side, and the second layer 912 is the layer on the conductive spacer 70 side. The first layer 911 is the layer closest to the semiconductor element 40, and the second layer 912 is the remaining layers excluding the first layer 911. FIG. 14 corresponds to FIG. 13. In FIG. 14, for the sake of convenience, the grain boundary 910 is omitted.

[0109] In the example shown in FIG. 14, the occupancy rate of the balls 94 in the first layer 911 is higher than the occupancy rate of the balls 94 in the second layer 912. The first layer 911 has a larger amount of balls 94 than the second layer 912. Thereby, the effect of further reducing the particle size on the semiconductor element 40 side of the solder 91 can be enhanced.

[0110] Note that, by varying the diameter of the balls 94 between the first layer 911 and the second layer 912, the occupancy rate of the balls 94 in the first layer 911 may be made higher than the occupancy rate of the balls 94 in the second layer 912. Both the amount and the diameter of the balls may be varied.

[0111] The above-described structure can be realized, for example, by arranging two layers of solder foils having different ball contents. Instead of this, three layers of solder foils without balls may be laminated, and the amount and / or diameter of the balls 94 arranged between the solder foils may be varied.

[0112] The number of layers of the solder 91 is not limited to 2. Three or more layers may be used. Even in the case of three or more layers, it is sufficient that the occupancy rate of the balls 94 in the first layer 911 closest to the semiconductor element 40 is higher than the occupancy rate of the balls 94 in the remaining layers.

[0113] (Fifth Embodiment) This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be incorporated. In the preceding embodiment, the cooling when solidifying the solder 91 to which the ball 94 is added was not particularly mentioned. Instead, the solder 91 may be solidified by cooling from a predetermined direction.

[0114] FIG. 15 is a cross-sectional view showing the cooling process in reflow. FIG. 15 corresponds to FIG. 12.

[0115] In this embodiment, as shown in FIG. 15, in the cooling after heating in reflow, the connector is cooled from the side of the conductive spacer 70. The thermal resistance of the heat transfer path with respect to the solder 91 is smaller on the side of the conductive spacer 70 than on the side of the wiring member 60. By cooling from the side of the conductive spacer 70, the ball 94 cools faster. Since the solder 91 starts to aggregate starting from the ball 94, cooling from the side of the conductive spacer 70 can promote grain growth starting from the ball 94.

[0116] <Summary of the Fifth Embodiment> According to this embodiment, in the cooling after heating in reflow, the connector is cooled from the side of the conductive spacer 70. As a result, the ball 94 cools faster. Therefore, it is possible to promote the occurrence of grain growth of the solder 91 starting from the ball 94. Accordingly, it is possible to promote the formation of small grains of the solder 91 on the semiconductor element 40 side, at least in the portion overlapping with the diode region 411d.

[0117] <Modification Example> In a configuration in which the semiconductor element 40 and the solder 91 are not provided with the above-described contrivance, the connector may be cooled from the side of the conductive spacer 70. In this case, the solder 91 solidifies from the side of the conductive spacer 70. During the cooling process, as shown in FIG. 16, a liquid portion 913 remains on the semiconductor element 40 side. In the solder 91, the liquid portion 913 and the solidified portion 914 are mixed. The liquid portion 913 is the unfrozen portion of the solder 91, that is, the molten state portion. FIG. 16 corresponds to FIG. 15.

[0118] Void 915s and impurities such as microvoids gather in the liquid portion 913 as the solder 91 solidifies. Therefore, when the liquid portion 913 solidifies, grain growth starts from the void 915 or the like. As a result, in at least the portion overlapping with the diode region 411d, the particle size of the solder 91 on the semiconductor element 40 side can be made smaller than the particle size on the conductive spacer 70 side.

[0119] (Other embodiments) The disclosure in this specification, drawings, etc. is not limited to the illustrated embodiments. The disclosure includes the illustrated embodiments and modifications by those skilled in the art based thereon. For example, the disclosure is not limited to the combination of components and / or elements shown in the embodiments. The disclosure can be implemented by various combinations. The disclosure can have additional parts that can be added to the embodiments. The disclosure includes those in which components and / or elements of the embodiments are omitted. The disclosure includes the replacement or combination of components and / or elements between one embodiment and another. The disclosed technical scope is not limited to the description of the embodiments. Some of the disclosed technical scopes should be understood to be indicated by the description of the claims and to include all changes within the meaning and scope equivalent to the description of the claims.

[0120] The disclosure in the specification, drawings, etc. is not limited by the description of the claims. The disclosure in the specification, drawings, etc. includes the technical idea described in the claims and extends to more diverse and extensive technical ideas than the technical idea described in the claims. Therefore, various technical ideas can be extracted from the disclosure in the specification, drawings, etc. without being restricted by the description of the claims.

[0121] When an element or layer is referred to as being "on," "connected to," "attached to," or "coupled to" another element or layer, it may be directly on, connected to, attached to, or coupled to the other element or layer, and there may also be intervening elements or intervening layers. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly attached to," or "directly coupled to" another element or layer, there are no intervening elements or intervening layers. Other words used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" vs. "directly between," "adjacent" vs. "directly adjacent," etc.). As used in this specification, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0122] Spatial relative terms such as "inside," "outside," "beneath," "below," "lower," "above," "upper," etc. are used herein to facilitate the description of the relationship of one element or feature to another element or feature as illustrated. Spatial relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the drawings. For example, if the device in the figures is turned over, an element described as "beneath" or "directly beneath" another element or feature will be oriented "above" the other element or feature. Thus, the term "beneath" can encompass both upward and downward orientations. The device may be oriented in other directions (rotated 90 degrees or other orientations), and the spatially relative descriptors used in this specification are to be interpreted accordingly.

[0123] The drive system 1 of the vehicle is not limited to the above-described configuration. For example, although an example of including one motor generator 3 has been shown, it is not limited thereto. A plurality of motor generators may be provided. Although an example in which the power conversion device 4 includes the inverter 6 as a power conversion unit has been shown, it is not limited thereto. For example, a configuration including a plurality of inverters may be used. A configuration including at least one inverter and a converter may be used. Only a converter may be provided.

[0124] The configuration of the semiconductor device 20 is not limited to the above example. The semiconductor device 20 may include at least a semiconductor element, an upper conductor, a solder that joins the upper electrode of the semiconductor element and the upper conductor, and an alloy layer interposed between the upper electrode and the solder.

[0125] Instead of the conductive spacer 70, a convex portion may be provided on the wiring member 50. In this case, the wiring member 60 corresponds to the upper conductor.

[0126] Although an example of a double-sided heat dissipation structure has been shown as the semiconductor device 20, it is not limited thereto. It can also be applied to a single-sided heat dissipation structure. For example, the collector electrode 43 is connected to a heat sink or a metal body of a substrate, and the emitter electrode 42 is connected to a lead. In this case, the lead corresponds to the upper conductor.

[0127] Although an example in which the semiconductor device 20 includes only one semiconductor element 40 constituting one arm has been shown, it is not limited thereto. The semiconductor device 20 may include a plurality of semiconductor elements 40 constituting one arm. That is, a plurality of semiconductor elements 40 may be connected in parallel to each other to form one arm. Further, the semiconductor device 20 may include a plurality of semiconductor elements 40 constituting the upper and lower arm circuits 9 for one phase. A plurality of semiconductor elements 40 constituting the upper and lower arm circuits 9 for a plurality of phases may be provided.

[0128] The arrangement of the IGBT region 411i and the diode region 411d is not particularly limited. Instead of the alternating arrangement in the X direction, an alternating arrangement in the Y direction may be employed. Instead of the striped arrangement, an arrangement in which the diode regions 411d provided in an island shape are scattered may be used.

[0129] Although an example in which the back surfaces 50b and 60b of the wiring members 50 and 60 are exposed from the sealing body 30 has been shown, the present invention is not limited thereto. At least one of the back surfaces 50b and 60b may be covered by the sealing body 30. At least one of the back surfaces 50b and 60b may be covered by an insulating member (not shown) different from the sealing body 30. The semiconductor device 20 may be configured not to include the sealing body 30.

[0130] Although an example in which the area of the diode region 411d is smaller than the area of the IGBT region 411i has been shown, the present invention is not limited thereto. The present invention can also be applied to a configuration in which the area of the diode region 411d and the area of the IGBT region 411i are substantially equal to each other, or a configuration in which the area of the IGBT region 411i is smaller than the area of the diode region 411d. When the area of the IGBT region 411i is small, the EM life is less likely to be a problem. The direction in which the main current flows is opposite to the direction in which the reflux current flows. When the main current flows, electrons move from the side of the conductive spacer 70 toward the side of the semiconductor element 40. Since the area of the conductive spacer 70 is large, the EM life is less likely to be a problem.

[0131] (Disclosure of Technical Ideas) This specification discloses a plurality of technical ideas described in a plurality of claims listed below. Some claims may be described in a multiple dependent form in which a preceding claim is alternatively cited in a subsequent claim. Further, some claims may be described in a multiple dependent form that cites a claim in another multiple dependent form. The claims described in these multiple dependent forms define a plurality of technical ideas.

[0132] <Technical Idea 1> A semiconductor device (40) having a semiconductor substrate (41) including an IGBT region (411i) and a diode region (411d), and an upper electrode (42) disposed on one surface of the semiconductor substrate. An upper conductor (70) disposed to face the upper electrode. An upper solder (91) interposed between the upper electrode and the upper conductor and joining the upper electrode and the upper conductor. An alloy layer (100) interposed between the upper electrode and the upper solder. Comprising: The upper electrode has an Al electrode (422) disposed on the one surface and a Ni electrode (423) disposed on the Al electrode. The upper solder contains Cu and Sn. The alloy layer contains Ni, Cu, and Sn. The upper solder has a smaller particle size on the semiconductor device side than on the upper conductor side in at least a portion overlapping the diode region in a plan view in the thickness direction of the semiconductor substrate.

[0133] <Technical Idea 2> The semiconductor device has a lower electrode (43) disposed on the back surface of the semiconductor substrate. Further comprising a lower conductor (60) disposed to face the lower electrode, and a lower solder (93) interposed between the lower electrode and the lower conductor and joining the lower electrode and the lower conductor. The semiconductor device according to Technical Idea 1, wherein the particle size of the upper solder on the semiconductor device side in at least a portion overlapping the diode region is smaller than the particle size of the lower solder.

[0134] <Technical Idea 3> The semiconductor device according to Technical Idea 1 or Technical Idea 2, wherein the Ni electrode has uneven portions (4231) with continuously formed unevenness on the surface of at least a portion overlapping the diode region.

[0135] <Technical Idea 4> The semiconductor element has a protective film (45) disposed on one surface of the semiconductor substrate and including an opening (451) for exposing the Ni electrode so as to be joinable and a partitioning portion (453) for partitioning the Ni electrode into a plurality of portions. The semiconductor device according to Technical Idea 1 or Technical Idea 2, wherein, in plan view, an end portion of the partitioning portion forms a continuous concavo-convex shape.

[0136] <Technical Idea 5> The semiconductor device according to Technical Idea 1 or Technical Idea 2, wherein a conductive ball (94) is added to the upper solder.

[0137] <Technical Idea 6> The upper solder has a multilayer structure. The semiconductor device according to Technical Idea 5, wherein an occupancy rate of the balls per unit volume in the upper solder is higher in a first layer (911) closest to the semiconductor element than in remaining layers (912) excluding the first layer.

[0138] <Technical Idea 7> The semiconductor device according to Technical Idea 5 or Technical Idea 6, wherein the ball contains Ni or Cu.

[0139] <Technical Idea 8> The semiconductor device according to any one of Technical Ideas 1 to 7, wherein the Ni electrode is a Ni plating film containing P.

Explanation of Reference Numerals

[0140] 1... Drive system, 2... DC power supply, 3... Motor generator, 4... Power conversion device, 5... Smoothing capacitor, 6... Inverter, 7... P line, 8... N line, 9... Upper and lower arm circuits, 9H... Upper arm, 9L... Lower arm, 10... Output line, 11... IGBT, 12... Diode, 20... Semiconductor device, 30... Sealing body, 30a... One side, 30b... Back side, 30c, 30d, 30e, 30f... Side surfaces, 40... Semiconductor element, 41... Semiconductor substrate, 41a... One side, 41b... Back side, 411... Active region, 411d... Diode region, 411i... IGBT region, 412... Outer peripheral region, 42... Emitter electrode, 421... Exposed portion, 422... Al electrode, 423... Ni electrode, 4231... Concavo-convex portion, 424... P-rich layer, 43... Collector electrode, 44... Pad, 45... Protective film, 451... Opening, 452... Outer peripheral portion, 453... Partition portion, 454... Concavo-convex portion, 50... Wiring member, 50a... Opposing surface, 50b... Back side, 60... Wiring member, 60a... Opposing surface, 60b... Back side, 70... Conductive spacer, 71... Plating film, 80... External connection terminal, 81, 82... Main terminals, 83... Signal terminal, 90... Bonding wire, 91... Solder, 910... Grain boundary, 911... First layer, 912... Second layer, 913... Solidified portion, 914... Liquid portion, 915... Void, 94... Ball, 100... Alloy layer< / em>

Claims

1. A semiconductor device (40) having a semiconductor substrate (41) including an IGBT region (411i) and a diode region (411d), and an upper electrode (42) disposed on one surface of the semiconductor substrate. An upper conductor (70) disposed to face the upper electrode. An upper solder (91) interposed between the upper electrode and the upper conductor to join the upper electrode and the upper conductor. An alloy layer (100) interposed between the upper electrode and the upper solder. Comprising: The upper electrode has an Al electrode (422) disposed on the one surface and a Ni electrode (423) disposed on the Al electrode. The upper solder contains Cu and Sn. The alloy layer contains Ni, Cu, and Sn. The upper solder has a smaller particle size on the semiconductor element side than on the upper conductor side in at least a portion overlapping the diode region in a plan view in the thickness direction of the semiconductor substrate.

2. The semiconductor device further has a lower electrode (43) disposed on the back surface of the semiconductor substrate. A lower conductor (60) disposed to face the lower electrode, and a lower solder (93) interposed between the lower electrode and the lower conductor to join the lower electrode and the lower conductor. The semiconductor device according to claim 1, wherein the particle size of the upper solder on the semiconductor element side in at least a portion overlapping the diode region is smaller than the particle size of the lower solder.

3. The semiconductor device according to claim 1 or claim 2, wherein the Ni electrode has uneven portions (4231) with continuously formed unevenness on the surface of at least a portion overlapping the diode region.

4. The semiconductor device has a protective film (45) disposed on one surface of the semiconductor substrate, having an opening (451) for exposing the Ni electrode so as to be joinable, and a partitioning portion (453) for partitioning the Ni electrode into a plurality. The semiconductor device according to claim 1 or claim 2, wherein, in the plan view, the ends of the partitioning portion form a continuous uneven shape.

5. The semiconductor device according to claim 1 or claim 2, wherein conductive balls (94) are added to the upper solder.

6. The upper solder has a multilayer structure. The occupancy rate of the balls per unit volume in the upper solder is higher in the first layer (911) closest to the semiconductor element than in the remaining layers (912) excluding the first layer, for the semiconductor device according to claim 5.

7. The balls contain Ni or Cu, for the semiconductor device according to claim 5.

8. The Ni electrode is a Ni plating film containing P, for the semiconductor device according to claim 1 or claim 2.

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