Semiconductor device and semiconductor apparatus

Abstract

To provide a semiconductor element and a semiconductor device with improved electrical characteristics and heat dissipation, especially useful for a power device.SOLUTION: A semiconductor element at least includes a semiconductor layer including a crystalline oxide semiconductor as a main component, an electrode layer stacked on the semiconductor layer, and a conducting substrate stacked on the electrode layer. The semiconductor element is provided with a first metal layer and a second metal layer including a metal of group 11 of the periodic table and a diffusion bonding layer interposed between the first metal layer and the second metal layer between the electrode layer and the conducting substrate.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present invention relates to a semiconductor device useful as a power device or the like.

Background Art

[0002] As a next-generation switching device capable of achieving high breakdown voltage, low loss, and high heat resistance, semiconductor devices using gallium oxide (Ga2O3) with a large bandgap have attracted attention, and application to power semiconductor devices such as inverters is expected. Moreover, application as a light-emitting / receiving device such as an LED or a sensor is also expected due to its wide bandgap. According to Patent Document 1, the gallium oxide can control the bandgap by forming a mixed crystal with indium, aluminum, or a combination thereof, and constitutes a very attractive material system as an InAlGaO-based semiconductor. Here, the InAlGaO-based semiconductor means In X Al Y Ga Z O3 (0 ≦ X ≦ 2, 0 ≦ Y ≦ 2, 0 ≦ Z ≦ 2, X + Y + Z = 1.5 to 2.5), and it can be viewed as the same material system including gallium oxide.

[0003] As a base substrate used to realize semiconductor devices using these InAlGaO-based semiconductors, β-gallium oxide substrates and sapphire substrates have been studied. According to Patent Document 2, when a β-gallium oxide substrate is used, homoepitaxial growth of gallium oxide is possible, and high-quality aluminum gallium oxide thin films can be obtained. However, the available substrate size is limited, and it is difficult to increase the diameter compared to materials such as silicon and sapphire that have already been mass-produced. According to Patent Documents 3 and 4, when a sapphire substrate is used, Al having a corundum structure X Ga YAlthough it is possible to improve the quality of the O3 (0 ≦ X ≦ 2, 0 ≦ Y ≦ 2, X + Y = 2) thin film, it is difficult to improve the quality of the β-gallium structure film. In addition, since sapphire is an insulator, there is also a problem that current cannot flow through the underlying material. In this case, an electrode cannot be formed on the underlying material, which limits the output current per unit area of the semiconductor device. When the diameter is increased to 6 inches or 8 inches, the industrial application of these large-diameter sapphires has not advanced so much, so there are concerns about stable procurement and the problem of rising procurement costs.

[0004] In addition, the low thermal conductivity of gallium oxide and sapphire also poses problems for heat generation and high-temperature operation associated with increasing the current of semiconductor devices. Furthermore, the characteristics of the underlying material also cause problems in electrical characteristics for realizing a low-loss semiconductor device. For example, in order to realize a semiconductor with high breakdown voltage and low loss, in addition to reducing losses in the channel layer, it is necessary to reduce losses outside the channel layer. For example, low loss in the contact region constituting the semiconductor device is required, and furthermore, in a vertical semiconductor device, low loss of the underlying material and the layer between the underlying material and the channel layer is required.

[0005] Patent Document 5 describes a laminated semiconductor structure in which a support layer mainly composed of a conductive material having a different coefficient of thermal expansion from the semiconductor layer is laminated via a conductive adhesive layer on a semiconductor layer using an InAlGaO-based semiconductor. However, the semiconductor structure described in Cited Document 5 was not sufficiently satisfactory in terms of warping, which is a problem specific to InAlGaO-based semiconductors. Also, even if the warping could be improved, the thickness of the entire laminate increased by interposing the conductive adhesive layer, resulting in a problem that the thermal resistance could not be sufficiently suppressed.

[0006] Patent Document 6 describes a technique for achieving a strong bond at room temperature by surface-activated bonding of an epitaxial layer and a high thermal conductivity substrate. However, the addition of a high thermal conductivity substrate in addition to the epitaxial layer may prevent the forward characteristics of the semiconductor from being sufficiently obtained. Further, prior to surface-activated bonding, the bonding surfaces of the epitaxial layer and the high thermal conductivity substrate must be activated in a vacuum environment, which complicates the bonding process and makes it difficult to adopt easily.

[0007] For these reasons, a semiconductor structure with excellent heat dissipation and electrical characteristics in which the semiconductor characteristics of the InAlGaO-based semiconductor can be fully exhibited has been eagerly awaited.

[0008] Note that Patent Document 1 and Patent Document 5 relate to patent applications by the present applicant.

Prior Art Documents

Patent Documents

[0009]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Summary of the Invention

Problems to be Solved by the Invention

[0010] An object of the present invention is to provide a semiconductor device having excellent electrical characteristics and excellent heat dissipation characteristics.

Means for Solving the Problems

[0011] As a result of intensive studies to achieve the above object, the present inventors have found that in the production (pre-process) of a semiconductor device using a semiconductor layer containing a crystalline oxide semiconductor as a main component, by connecting an electrode layer and a conductive substrate using a first metal and a second metal containing a Group 11 metal (such as gold, silver, copper, etc.) of the periodic table and a diffusion bonding layer interposed between these first metal layer and second metal layer, not only is the adhesion to electrodes and an adhesive layer in the resulting semiconductor device further improved, but warpage is suppressed and the electrical characteristics of the resulting semiconductor device become more excellent. As a result of further studies, a semiconductor device comprising at least a semiconductor layer containing a crystalline oxide semiconductor as a main component, an electrode layer laminated on the semiconductor layer, and a conductive substrate laminated on the electrode layer, wherein between the electrode layer and the conductive substrate, a first metal layer and a second metal layer containing a Group 11 metal (such as gold, silver, copper, etc.) of the periodic table and a diffusion bonding layer interposed between the first metal layer and the second metal layer are provided, has excellent electrical characteristics and has been found to be capable of solving the above-described conventional problems all at once. In addition, after obtaining the above findings, the present inventors further repeated studies and completed the present invention.

[0012] That is, the present invention relates to the following inventions. [1] A semiconductor device comprising at least a semiconductor layer containing a crystalline oxide semiconductor as a main component, an electrode layer laminated on the semiconductor layer, and a conductive substrate laminated on the electrode layer, wherein between the electrode layer and the conductive substrate, a first metal layer and a second metal layer containing a Group 11 metal of the periodic table and a diffusion bonding layer interposed between the first metal layer and the second metal layer are provided. [2] The semiconductor device according to [1], wherein the first metal layer and the second metal layer contain any one of gold, silver, or copper. [3] The semiconductor device according to [2], wherein at least one of the first metal layer and the second metal layer contains copper. The semiconductor device according to [3], wherein both the first metal layer and the second metal layer contain copper. The semiconductor device according to [1], wherein the diffusion bonding layer contains the metals contained in the first metal layer and the second metal layer, respectively. The semiconductor device according to [5], wherein the diffusion bonding layer contains a metal different from the Group 11 metal of the periodic table. The semiconductor device according to [6], wherein the diffusion bonding layer contains silicon. The semiconductor device according to any one of [1] to [7], wherein the crystalline oxide semiconductor contains at least one metal selected from aluminum, indium, and gallium. The semiconductor device according to any one of [1] to [8], wherein the crystalline oxide semiconductor contains at least gallium. The semiconductor device according to any one of [1] to [9], further comprising another electrode layer on a surface facing the surface on which the electrode layer of the semiconductor layer is laminated. The semiconductor device according to any one of [1] to

[10] , wherein the semiconductor layer includes an n+-type semiconductor layer and an n−-type semiconductor layer provided on the n+-type semiconductor layer, and the electrode layer is provided on the n+-type semiconductor layer. The present invention also relates to the following inventions. A semiconductor device including at least a semiconductor layer containing a crystalline oxide semiconductor as a main component, an electrode layer laminated on the semiconductor layer, a bonding layer laminated on the electrode layer, and a conductive substrate laminated on the bonding layer, wherein the bonding layer is a layer formed by diffusion bonding of a metal containing a Group 11 metal of the periodic table. The semiconductor device according to claim

[12] , wherein the bonding layer contains any one of gold, silver, or copper. The semiconductor device according to

[13] , wherein the bonding layer contains copper. The semiconductor device according to any one of

[12] to

[14] , wherein the bonding layer contains a metal different from the Group 11 metal of the periodic table.

[16] The semiconductor device according to

[15] , wherein the bonding layer contains silicon.

[17] The semiconductor device according to any one of

[12] to

[16] , wherein the crystalline oxide semiconductor contains at least one metal selected from aluminum, indium, and gallium.

[18] The semiconductor device according to any one of

[12] to

[17] , wherein the crystalline oxide semiconductor contains at least gallium.

[19] The semiconductor device according to any one of

[12] to

[18] , further comprising another electrode layer on a surface facing the surface on which the electrode layer of the semiconductor layer is laminated.

[20] The semiconductor device according to any one of

[12] to

[20] , wherein the semiconductor layer includes an n+-type semiconductor layer and an n−-type semiconductor layer provided on the n+-type semiconductor layer, and the electrode layer is provided on the n+-type semiconductor layer.

[21] The semiconductor device according to any one of [1] to

[20] , which is a power device.

[22] A semiconductor device in which at least a semiconductor device is joined by a joining member to a lead frame, a circuit board, or a heat dissipation board, wherein the semiconductor device is the semiconductor device according to any one of [1] to

[20] .

[23] A power conversion device using the semiconductor device according to

[22] .

[24] A control system using the semiconductor device according to

[23] . [Effect of the Invention]

[0013] The semiconductor device of the present invention is excellent in electrical characteristics and also excellent in heat dissipation characteristics. [Brief Description of the Drawings]

[0014]

Figure 1

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Figure 5

Figure 6

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Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

BEST MODE FOR CARRYING OUT THE INVENTION

[0015] The semiconductor device of the present invention is a semiconductor device comprising at least a semiconductor layer containing a crystalline oxide semiconductor as a main component, an electrode layer laminated on the semiconductor layer, and a conductive substrate laminated on the electrode layer, wherein a first metal layer and a second metal layer containing a Group 11 metal of the periodic table are provided between the electrode layer and the conductive substrate, and a diffusion bonding layer is interposed between the first metal layer and the second metal layer. Further, the semiconductor device of the present invention is a semiconductor device comprising at least a semiconductor layer containing a crystalline oxide semiconductor as a main component, an electrode layer laminated on the semiconductor layer, a bonding layer laminated on the electrode layer, and a conductive substrate laminated on the bonding layer, wherein the bonding layer is a layer formed by diffusion bonding of a metal containing a Group 11 metal of the periodic table.

[0016] In an embodiment of the present invention, for example, (1) after laminating the semiconductor layer directly or via another layer on a base substrate, (2) after forming an electrode layer on the semiconductor layer, (3) creating a laminate in which an electrode surface layer is formed on the electrode layer, and (4) bonding this laminate and a conductive substrate on which a substrate surface layer is formed by diffusion bonding, and (5) removing the base substrate using known means, the semiconductor device can be preferably manufactured by a manufacturing method including the above steps. Hereinafter, examples of the main steps (1) to (5) for manufacturing the semiconductor device will be described in more detail with reference to the drawings.

[0017] In step (1), the semiconductor layer is laminated directly or via another layer on a base substrate. By step (1), for example, a laminate as shown in FIG. 1 can be obtained. In the laminate shown in FIG. 1, a semiconductor layer 101 is laminated on a base substrate 108. In the present invention, the semiconductor film 101 obtained in step (1) can be used as the semiconductor layer (hereinafter, also referred to as "semiconductor film"). Hereinafter, step (1) will be described.

[0018] (Base Substrate) The lower base substrate is in a plate shape and is not particularly limited as long as it can serve as a support for the semiconductor film. It may be an insulator substrate, a semiconductor substrate, a metal substrate, or a conductive substrate. In particular, the lower base substrate is preferably an insulator substrate and also preferably a substrate having a metal film on its surface. Examples of the lower base substrate include a lower base substrate containing, as a main component, a substrate material having a corundum structure, a lower base substrate containing, as a main component, a substrate material having a β-gallia structure, and a lower base substrate containing, as a main component, a substrate material having a hexagonal crystal structure. Here, the "main component" means that the substrate material having the specific crystal structure is preferably contained in an atomic ratio of 50% or more, more preferably 70% or more, still more preferably 90% or more, and may be 100%, based on all components of the substrate material.

[0019] The substrate material is not particularly limited as long as it does not inhibit the object of the present invention and may be a known one. Examples of the substrate material having a corundum structure include α-Al2O3 (sapphire substrate) or α-Ga2O3, and more preferable examples include an a-plane sapphire substrate, an m-plane sapphire substrate, an r-plane sapphire substrate, a c-plane sapphire substrate, and an α-type gallium oxide substrate (a-plane, m-plane, or r-plane). Examples of the lower base substrate containing, as a main component, a substrate material having a β-gallia structure include a β-Ga2O3 substrate or a mixed crystal substrate containing Ga2O3 and Al2O3 and having Al2O3 in an amount greater than 0 wt% and not more than 60 wt%. Examples of the lower base substrate containing, as a main component, a substrate material having a hexagonal crystal structure include a SiC substrate, a ZnO substrate, and a GaN substrate.

[0020] The semiconductor layer is not particularly limited as long as it contains a crystalline oxide semiconductor as a main component. The crystal structure of the crystalline oxide semiconductor is also not particularly limited as long as it does not inhibit the object of the present invention. Examples of the crystal structure of the crystalline oxide semiconductor include a corundum structure, a β-gallium structure, a hexagonal crystal structure (e.g., ε-type structure, etc.), a tetragonal crystal structure (e.g., κ-type structure, etc.), a cubic crystal structure, or a tetragonal crystal structure, etc. In an embodiment of the present invention, it is preferable that the crystalline oxide semiconductor has a corundum structure, a β-gallium structure or a hexagonal crystal structure (e.g., ε-type structure, etc.), and more preferably has a corundum structure. Examples of the crystalline oxide semiconductor include metal oxides containing one or more metals selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt and iridium. In an embodiment of the present invention, it is preferable that the crystalline oxide semiconductor contains at least one metal selected from aluminum, indium and gallium, more preferably contains at least gallium, and most preferably is α-Ga2O3 or a mixed crystal thereof. Note that the "main component" means that the crystalline oxide semiconductor is preferably contained in an atomic ratio of 50% or more, more preferably 70% or more, and even more preferably 90% or more with respect to all components of the semiconductor layer, and may be 100%. Also, the thickness of the semiconductor layer is not particularly limited and may be 1 μm or less or 1 μm or more. However, in an embodiment of the present invention, it is preferably 1 μm or more. The surface area of the semiconductor layer is not particularly limited and may be 1 mm 2 or more, or may be 1 mm 2 or less, but it is preferably 10 mm 2 to 300 cm 2 and more preferably 100 mm 2 to 100 cm 2It is more preferable. Further, the semiconductor layer is usually single crystal, but may be polycrystalline. Further, the semiconductor layer is a multilayer film including at least a first semiconductor layer and a second semiconductor layer, and when a Schottky electrode is provided on the first semiconductor layer, it is also preferable that the carrier density of the first semiconductor layer is smaller than the carrier density of the second semiconductor layer. In this case, the second semiconductor layer usually contains a dopant, and the carrier density of the semiconductor layer can be appropriately set by adjusting the doping amount.

[0021] The semiconductor layer preferably contains a dopant. The dopant is not particularly limited and may be a known one. Examples of the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium or niobium, or p-type dopants such as magnesium, calcium, zinc and the like. In an embodiment of the present invention, it is preferable that the n-type dopant is Sn, Ge or Si. The content of the dopant is preferably 0.00001 atomic% or more in the composition of the semiconductor layer, more preferably 0.00001 atomic% to 20 atomic%, and most preferably 0.00001 atomic% to 10 atomic%. More specifically, the concentration of the dopant is usually about 1×10 16 / cm 3 ~1×10 22 / cm 3 It may be, or the concentration of the dopant may be, for example, reduced to a low concentration of about 1×10 17 / cm 3 or less. Further, according to the present invention, the dopant may be contained at a high concentration of about 1×10 20 / cm 3 or more. In an embodiment of the present invention, it is preferable to contain it at a carrier concentration of 1×10 17 / cm 3 or more.

[0022] The semiconductor layer may be formed by known means. Examples of the means for forming the semiconductor layer include, for example, CVD method, MOCVD method, MOVPE method, mist CVD method, mist epitaxy method, MBE method, HVPE method, pulse growth method, or ALD method. In an embodiment of the present invention, the means for forming the semiconductor layer is preferably the mist CVD method or the mist epitaxy method. In the mist CVD method or the mist epitaxy method, for example, using the mist CVD apparatus shown in FIG. 11, the raw material solution is atomized (atomization step), the droplets are suspended, and after atomization, the obtained atomized droplets are transported to the substrate with a carrier gas (transport step). Then, in the film formation chamber, the semiconductor layer is formed by thermally reacting the atomized droplets to stack a semiconductor film mainly composed of a crystalline oxide semiconductor on the substrate (film formation step).

[0023] (Atomization step) In the atomization step, the raw material solution is atomized. The atomization means of the raw material solution is not particularly limited as long as it can atomize the raw material solution and may be known means. However, in an embodiment of the present invention, the atomization means using ultrasonic waves is preferred. The atomized droplets obtained using ultrasonic waves are preferably those having an initial velocity of zero and floating in the air. This is because, for example, instead of spraying like a spray, it is a mist that can float in space and be transported as a gas, so there is no damage due to collision energy, which is very suitable. The droplet size is not particularly limited and may be droplets of about several mm, but is preferably 50 μm or less, and more preferably 100 nm to 10 μm.

[0024] (Raw material solution) The raw material solution is not particularly limited as long as it can be atomized or made into droplets and contains a raw material capable of forming a semiconductor film, and may be an inorganic material or an organic material. In an embodiment of the present invention, the raw material is preferably a metal or a metal compound, and more preferably contains one or more metals selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium.

[0025] In an embodiment of the present invention, as the raw material solution, a solution in which the metal is dissolved or dispersed in an organic solvent or water in the form of a complex or a salt can be preferably used. Examples of the form of the complex include acetylacetonate complex, carbonyl complex, ammine complex, hydride complex, and the like. Examples of the form of the salt include organometallic salts (such as metal acetates, metal oxalates, metal citrates, etc.), metal sulfide salts, metal nitrate salts, metal phosphate salts, metal halide salts (such as metal chloride salts, metal bromide salts, metal iodide salts, etc.).

[0026] In addition, it is preferable to mix additives such as hydrohalic acids and oxidants in the raw material solution. Examples of the hydrohalic acid include hydrobromic acid, hydrochloric acid, hydroiodic acid, etc. Among them, hydrobromic acid or hydroiodic acid is preferable because the generation of abnormal grains can be more efficiently suppressed. Examples of the oxidant include peroxides such as hydrogen peroxide (H2O2), sodium peroxide (Na2O2), barium peroxide (BaO2), benzoyl peroxide (C6H5CO)2O2, hypochlorous acid (HClO), perchloric acid, nitric acid, ozone water, organic peroxides such as peracetic acid and nitrobenzene, and the like.

[0027] The raw material solution may contain a dopant. By including a dopant in the raw material solution, doping can be performed well. The dopant is not particularly limited as long as it does not inhibit the object of the present invention. Examples of the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium, or niobium, or p-type dopants such as Mg, H, Li, Na, K, Rb, Cs, Fr, Be, Ca, Sr, Ba, Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Zn, Cd, Hg, Ti, Pb, N, or P. The content of the dopant is appropriately set by using a calibration curve showing the relationship between the concentration of the dopant in the raw material and the desired carrier density.

[0028] The solvent of the raw material solution is not particularly limited, and may be an inorganic solvent such as water, an organic solvent such as alcohol, or a mixed solvent of an inorganic solvent and an organic solvent. In an embodiment of the present invention, it is preferable that the solvent contains water, and more preferably, it is water or a mixed solvent of water and alcohol.

[0029] (Transportation step) In the transportation step, the atomized droplets are transported into the film formation chamber by a carrier gas. The carrier gas is not particularly limited as long as it does not inhibit the object of the present invention. For example, oxygen, ozone, an inert gas such as nitrogen or argon, or a reducing gas such as hydrogen gas or forming gas are preferable examples. Also, the type of carrier gas may be one type, but may also be two or more types. A dilution gas with a reduced flow rate (for example, a 10-fold dilution gas, etc.) may be further used as the second carrier gas. Also, the supply location of the carrier gas may be not only one location, but also two or more locations. The flow rate of the carrier gas is not particularly limited, but is preferably 0.01 to 20 L / min, and more preferably 1 to 10 L / min. In the case of a dilution gas, the flow rate of the dilution gas is preferably 0.001 to 2 L / min, and more preferably 0.1 to 1 L / min.

[0030] (Film formation step) In the film formation step, the semiconductor film is formed on the substrate by causing the atomized droplets to undergo a thermal reaction in the film formation chamber. The thermal reaction only requires the atomized droplets to react with heat, and the reaction conditions and the like are not particularly limited as long as they do not impede the object of the present invention. In this step, the thermal reaction is usually carried out at a temperature equal to or higher than the evaporation temperature of the solvent, but preferably at a temperature not too high (for example, 1000 ° C) or lower, more preferably 650 ° C or lower, and most preferably 300 ° C to 650 ° C. Further, the thermal reaction may be carried out in any atmosphere such as under vacuum, in a non-oxygen atmosphere (for example, in an inert gas atmosphere), in a reducing gas atmosphere, and in an oxygen atmosphere as long as it does not impede the object of the present invention, but it is preferably carried out in an inert gas atmosphere or an oxygen atmosphere. Further, it may be carried out under any condition such as atmospheric pressure, increased pressure, and reduced pressure, but in the embodiment of the present invention, it is preferably carried out under atmospheric pressure. Note that the film thickness can be set by adjusting the film formation time.

[0031] In an embodiment of the present invention, annealing treatment may be performed after the film formation step. The annealing treatment temperature is not particularly limited as long as it does not impede the object of the present invention, and is usually 300 ° C to 650 ° C, preferably 350 ° C to 550 ° C. Further, the annealing treatment time is usually 1 minute to 48 hours, preferably 10 minutes to 24 hours, and more preferably 30 minutes to 12 hours. Note that the annealing treatment may be carried out in any atmosphere as long as it does not impede the object of the present invention. It may be in a non-oxygen atmosphere or in an oxygen atmosphere. Examples of the non-oxygen atmosphere include an inert gas atmosphere (for example, a nitrogen atmosphere) or a reducing gas atmosphere, etc., but in the embodiment of the present invention, an inert gas atmosphere is preferable, and a nitrogen atmosphere is more preferable.

[0032] In step (2), an electrode layer 105b is formed on the semiconductor layer 101. By step (2), a laminate as shown in FIG. 2 can be obtained, for example. The laminate of FIG. 2 is composed of a base substrate 108, a semiconductor layer 101, and an electrode layer 105b.

[0033] The electrode layer is not particularly limited as long as it has conductivity and does not inhibit the object of the present invention. The constituent material of the electrode layer may be a conductive inorganic material or a conductive organic material. In an embodiment of the present invention, the material of the electrode is preferably a metal. Preferably, examples of the metal include at least one metal selected from Group 4 to Group 10 of the periodic table. Examples of the metal of Group 4 of the periodic table include titanium (Ti), zirconium (Zr), hafnium (Hf), etc. Examples of the metal of Group 5 of the periodic table include vanadium (V), niobium (Nb), tantalum (Ta), etc. Examples of the metal of Group 6 of the periodic table include chromium (Cr), molybdenum (Mo), and tungsten (W), etc. Examples of the metal of Group 7 of the periodic table include manganese (Mn), technetium (Tc), rhenium (Re), etc. Examples of the metal of Group 8 of the periodic table include iron (Fe), ruthenium (Ru), osmium (Os), etc. Examples of the metal of Group 9 of the periodic table include cobalt (Co), rhodium (Rh), iridium (Ir), etc. Examples of the metal of Group 10 of the periodic table include nickel (Ni), palladium (Pd), platinum (Pt), etc. In an embodiment of the present invention, the electrode layer preferably contains at least one metal selected from Group 4 and Group 9 of the periodic table, and more preferably contains a Group 9 metal of the periodic table. The layer thickness of the electrode layer is not particularly limited, but is preferably 0.1 nm to 10 μm, more preferably 5 nm to 500 nm, and most preferably 10 nm to 200 nm. Also, in an embodiment of the present invention, the electrode layer may be composed of two or more layers having different compositions from each other.

[0034] The means for forming the electrode layer is not particularly limited and may be a known means. Specifically, examples of the means for forming the electrode layer or the other electrode layer include a dry method and a wet method. Examples of the dry method include sputtering, vacuum evaporation, CVD, etc. Examples of the wet method include screen printing, die coating, etc.

[0035] In step (3), as shown in FIG. 3, an electrode surface layer (first metal layer) 106 containing at least one metal selected from Group 11 of the periodic table is formed on the surface of the electrode layer 105b. Examples of the metal of Group 11 of the periodic table include copper (Cu), silver (Ag), and gold (Au). The electrode surface layer 106 is preferably surface-treated by a method such as polishing so that its surface roughness (Sa) becomes 2 nm or less after being formed on the electrode layer 105b by, for example, the above-described dry method or wet method. The thickness of the electrode surface layer 106 after polishing is not particularly limited, but it may be thinner than the electrode layer 105b, preferably 10 nm to 500 μm, more preferably 100 nm to 100 μm, and most preferably 0.5 μm to 10 μm.

[0036] In step (4), as shown in FIG. 4, the laminate obtained in the above-described step (3) including the semiconductor layer 101 is bonded to the conductive substrate 107. The conductive substrate 107 has conductivity and preferably has rigidity capable of supporting the semiconductor layer. Further, the conductive substrate 107 may be composed of a laminate of a plurality of layers. The thickness of the conductive substrate 107 is not particularly limited, but is preferably 200 μm or less, and more preferably 100 μm or less. Thereby, excellent heat dissipation can be imparted while thinning the laminated structure without impairing the electrical characteristics of the semiconductor element.

[0037] In an embodiment of the present invention, a substrate surface layer (second metal layer) 107a having conductivity equivalent to that of the conductive substrate 107 is formed on the surface of the conductive substrate 107. The substrate surface layer 107a contains at least one metal selected from Group 11 of the periodic table. Examples of the metal of Group 11 of the periodic table include copper (Cu), silver (Ag), and gold (Au).

[0038] Also, when the conductive substrate 107 is composed of a plurality of layers, it is preferably at least composed of metals having different linear thermal expansion coefficients of the layers formed adjacent to each other. Note that the "linear thermal expansion coefficient" is measured according to JIS R 3102 (1995). In an embodiment of the present invention, it is also preferable that the metals constituting the plurality of layers in the adjacent conductive substrate 107 including the substrate surface layer 107a are the same type of metal and have different linear thermal expansion coefficients. For example, the substrate surface layer 107a may contain copper, and the uppermost layer of the conductive substrate 107 adjacent to the substrate surface layer 107a may be a layer containing copper having a different linear thermal expansion coefficient from that of the substrate surface layer 107a. In an embodiment of the present invention, the plurality of layers constituting the conductive substrate 107 may contain a metal other than the Group 11 metal of the periodic table. In particular, it is preferable that the layer formed adjacent to the layer containing the Group 11 metal of the periodic table contains the Group 6 metal of the periodic table. Further, it is more preferable to adopt a configuration in which the layer containing the Group 6 metal of the periodic table is sandwiched between the layers containing the Group 11 metal of the periodic table. These configurations are preferable because they can suppress the warpage of the semiconductor element while further improving the forward characteristics. Examples of the Group 6 metal of the periodic table include chromium (Cr), molybdenum (Mo), tungsten (W), and the like. In an embodiment of the present invention, the Group 6 metal of the periodic table is preferably molybdenum (Mo). In an embodiment of the present invention, when the conductive substrate 107 contains molybdenum and copper, it is also preferable to use a Cu-Mo composite substrate (hereinafter, also simply referred to as "Cu-Mo composite substrate") obtained by an impregnation method in which copper is impregnated into molybdenum compact powder as the conductive substrate. The thickness of each layer constituting the conductive substrate 107 is preferably 5 μm or more, and more preferably 10 μm or more.

[0039] The substrate surface layer 107a is preferably surface-treated by a method such as polishing so that its surface roughness (Sa) becomes 2 nm or less. The layer thickness of the substrate surface layer 107a after polishing is not particularly limited, but is preferably 10 nm or more, and more preferably 1 μm or more, similar to the thickness of each layer constituting the conductive substrate 107. Further, the surface area and surface shape of the substrate surface layer 107a are not particularly limited. However, in an embodiment of the present invention, it is preferably substantially the same as the surface area and surface shape of the conductive substrate 107 and the semiconductor layer 101. Note that "substantially the same" includes, for example, the case where they are the same as the surface area and surface shape of the conductive substrate and the semiconductor layer, and includes those in which the ratio of the area of the substrate surface layer to the area of the conductive substrate or the semiconductor layer is within the range of 0.9 to 1.4.

[0040] The forming means for each layer constituting the conductive substrate 107 and the substrate surface layer 107a is not particularly limited and may be known means. Specific examples of the forming means for these layers include, for example, dry methods and wet methods. Examples of dry methods include sputtering, vacuum evaporation, CVD, etc. Examples of wet methods include electrolytic plating and electroless plating.

[0041] In the above configuration, from the state where the electrode surface layer 106 and the substrate surface layer 107a are arranged to face each other as shown in FIG. 4, both are moved and brought into contact with each other in the direction of the arrow in the figure. Then, the electrode surface layer 106 and the substrate surface layer 107a are directly bonded, preferably by diffusion bonding. Specifically, in a vacuum atmosphere, an inert gas atmosphere, or a reducing gas atmosphere, the electrode surface layer 106 and the substrate surface layer 107a are brought into close contact with each other, and while maintaining a temperature condition below the melting point of the constituent materials of the electrode surface layer 106 and the substrate surface layer 107a, the bonding surfaces are pressed so that plastic deformation hardly occurs, thereby performing diffusion bonding. As a result, the diffusion of atoms occurring between the bonding surfaces starts, the metal atoms are mixed, and the voids disappear, resulting in bonding.

[0042] FIG. 5 shows the state after the diffusion bonding between the electrode surface layer 106 and the substrate surface layer 107a is performed, and a diffusion bonding layer (bonding layer) 109 is formed between the electrode surface layer 106 and the substrate surface layer 107a. That is, a semiconductor element is formed in which the diffusion bonding layer 109 is interposed between the electrode surface layer 106 and the substrate surface layer 107a. The diffusion bonding layer 109 is defined as a bonding interface or an oxide film, an impurity, or a trace thereof having a slight thickness generated by the diffusion bonding between the electrode surface layer 106 and the substrate surface layer 107a. And, although the structure is slightly different from that of the electrode surface layer 106 and the substrate surface layer 107a, a Group 11 metal of the periodic table is included. When the electrode surface layer 106 and the substrate surface layer 107a are different metals, a diffusion bonding layer containing a compound of these different metals may be formed. That is, the electrode surface layer 106 and the substrate surface layer 107a are bonded by the interposition of the diffusion bonding layer 109. Note that the diffusion bonding layer 109 may be formed by the partial integration of the electrode surface layer 106 and the substrate surface layer 107a by diffusion bonding.

[0043] In an embodiment of the present invention, both the electrode surface layer and the substrate surface layer contain a metal selected from Group 11 of the periodic table, but it is preferable that the same kind of metals such as "copper and copper", "silver and silver", and "gold and gold" are selected, and among them, "copper and copper", that is, a combination of copper-containing layers is particularly preferable. In addition to these, "gold and silver", "silver and copper", "copper and gold", or other combinations may be used. In any of these cases, since the electrode surface layer and the substrate surface layer contain at least one metal selected from Group 11 of the periodic table, in addition to electrical characteristics such as forward characteristics, a semiconductor element excellent in heat dissipation while being thin can be provided. In particular, when the crystalline oxide semiconductor contains at least one metal selected from aluminum, indium, and gallium, particularly gallium, or is α-Ga2O3 or a mixed crystal thereof, the conditions for electrical characteristics and heat dissipation characteristics associated with the low thermal conductivity of the crystalline oxide semiconductor become high. Therefore, the effect obtained by the present invention, which particularly contributes to the thinning of the semiconductor element, is extremely large.

[0044] In addition, for the purpose of promoting bonding in diffusion bonding, a so-called insert metal may be interposed between the bonding surfaces. This enables control of the bonding interface, such as diffusion in the bonded portion, adhesion of the bonding interface, and destruction and removal of the oxide film. As the insert metal, known materials can be appropriately selected. Examples include nickel (Ni), boron (B), silicon (Si), chromium (Cr), cobalt (Co), aluminum (Al), titanium (Ti), molybdenum (Mo), tantalum (Ta), hafnium (Hf), carbon (C), zirconium (Zr), iron (Fe), silver (Ag), copper (Cu), tin (Sn), and the like. In the present embodiment, it is preferably selected from metals different from the metals in Group 11 of the periodic table, and it is preferable to use an insert metal containing silicon (Si). In particular, it is particularly preferable to use an insert metal containing silicon (Si) in the case of diffusion bonding of "copper to copper". When an insert metal is used, the insert metal is contained in the diffusion bonding layer formed between the electrode surface layer and the substrate surface layer. Since the insert metal is for the purpose of promoting diffusion bonding, its amount and thickness may be small, which is advantageous for thinning compared to a structure in which an individual adhesive layer is provided separately.

[0045] In step (5), the base substrate 108 is removed from the state where the diffusion bonding between the electrode surface layer 106 and the substrate surface layer 107a has been performed. Examples of the method for removing the base substrate include a method of removing it by applying mechanical impact, a method of removing it by applying heat and utilizing thermal stress, a method of removing it by applying vibration such as ultrasonic waves, a method of removing it by etching, a method of removing it by grinding, a method of removing it by performing ion implantation such as the smart cut method and then performing heat treatment, a method of removing it by the laser lift-off method, and a method combining these.

[0046] In an embodiment of the present invention, after step (5), the crystal of the crystalline oxide semiconductor film may be regrown, or a different semiconductor layer, another electrode layer, etc. may be provided on the crystalline oxide semiconductor film.

[0047] In an embodiment of the present invention, it is preferable to further provide another electrode layer on a surface facing the surface on which the electrode layer of the semiconductor layer is laminated. That is, in addition to the conductive substrate 107, the substrate surface layer 107a, the diffusion bonding layer 109, the electrode surface layer 106, the electrode layer 105b, and the semiconductor layer 101, by forming a laminated structure in which another electrode layer is laminated in this order, as a vertical device in which current flows in the thickness direction of the semiconductor layer 101, the forward characteristics of the semiconductor element can be made more excellent. The other electrode layer is not particularly limited as long as it has conductivity and does not inhibit the object of the present invention. The constituent material of the other electrode layer may be a conductive inorganic material or a conductive organic material. In an embodiment of the present invention, the material of the other electrode is preferably a metal. Suitable examples of the metal include at least one metal selected from Groups 8 to 13 of the periodic table. Examples of the metals in Groups 8 to 10 of the periodic table include the metals respectively exemplified as the metals in Groups 8 to 10 of the periodic table in the description of the electrode layer. Examples of the Group 11 metal of the periodic table include copper (Cu), silver (Ag), gold (Au), etc. Examples of the Group 12 metal of the periodic table include zinc (Zn), cadmium (Cd), etc. Examples of the Group 13 metal of the periodic table include aluminum (Al), gallium (Ga), indium (In), etc. In an embodiment of the present invention, the other electrode layer preferably contains at least one metal selected from Group 11 and Group 13 metals of the periodic table, and more preferably contains at least one metal selected from silver, copper, gold, and aluminum. Note that the layer thickness of the other electrode layer is not particularly limited, but is preferably 1 nm to 500 μm, more preferably 10 nm to 100 μm, and most preferably 0.5 μm to 10 μm.

[0048] The forming means of the other electrode layer is not particularly limited and may be a known means. Specific examples of the forming means of the electrode layer or the other electrode layer include, for example, dry methods and wet methods. Examples of dry methods include sputtering, vacuum evaporation, CVD, etc. Examples of wet methods include screen printing, die coating, etc.

[0049] The semiconductor device according to an embodiment of the present invention is useful for semiconductor devices of various types and applications, and in particular, is useful for power devices. Further, the semiconductor device can be classified into a lateral device (lateral device) in which electrodes are formed on one side of the semiconductor layer and current flows in a direction perpendicular to the film thickness direction of the semiconductor layer, and a vertical device (vertical device) having electrodes on both the front and back surfaces of the semiconductor layer and current flowing in the film thickness direction of the semiconductor layer. In the embodiments of the present invention, the semiconductor device can be preferably used for both lateral devices and vertical devices, but it is preferably used for vertical devices among them. Examples of the semiconductor device include, for example, a Schottky barrier diode (SBD), a PN diode, a junction barrier Schottky diode, a metal semiconductor field effect transistor (MESFET), a high electron mobility transistor (HEMT), a metal oxide semiconductor field effect transistor (MOSFET), a static induction transistor (SIT), a junction field effect transistor (JFET), an insulated gate bipolar transistor (IGBT), or a light emitting diode. In the embodiments of the present invention, it is preferable that the semiconductor device is an SBD, a MOSFET, an SIT, a JFET, or an IGBT, more preferably an SBD, a MOSFET, or an SIT, and most preferably an SBD.

[0050] Hereinafter, a preferred example of the semiconductor device will be described with reference to the drawings, but the present invention is not limited to these embodiments. In the semiconductor devices exemplified below, other layers (for example, an insulator layer, a semi-insulator layer, a conductor layer, a semiconductor layer, a buffer layer, or other intermediate layers, etc.) may be included as long as the object of the present invention is not impaired, and a buffer layer (buffer layer) or the like may be appropriately omitted.

[0051] (SBD) FIG. 6 shows an example of a Schottky barrier diode (SBD) according to an embodiment of the present invention. In addition to the n-type semiconductor layer 101a, the n+-type semiconductor layer 101b, and the conductive substrate 107, the SBD of FIG. 6 includes a Schottky electrode 105a formed on the n-type semiconductor layer 101a, and an ohmic electrode 110 composed of an electrode layer 105b and an electrode surface layer 106. Since the diffusion bonding layer 109 and the substrate surface layer 107a have the same electrical characteristics as the electrode surface layer, these can also be regarded as components of the ohmic electrode 110.

[0052] The Schottky electrode 105a may be a known electrode material. Examples of the electrode material include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, or Ag, or alloys thereof, metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, or polypyrrole, or mixtures thereof.

[0053] The formation of the Schottky electrode 105a can be performed by known means such as vacuum deposition or sputtering, similar to the formation of the electrode layer (ohmic electrode 110) described above. More specifically, for example, when forming a Schottky electrode, a layer made of Mo and a layer made of Al are laminated, and patterning using a photolithography technique is performed on the layer made of Mo and the layer made of Al.

[0054] In an embodiment of the present invention, the electrode surface layer (first metal layer) 106 and the substrate surface layer (second metal layer) 107a contain a metal composed of a Group 11 metal of the periodic table. Thereby, while improving the electrical characteristics of the semiconductor element, the thermal resistance of the entire semiconductor element can be further reduced. Further, in an embodiment of the present invention, as the conductive substrate 107, it is preferable to use a conductive substrate containing a Group 11 metal of the periodic table and a Group 6 metal of the periodic table, and it is more preferable to use a conductive substrate containing copper and molybdenum. FIG. 17 shows a preferred embodiment of the conductive substrate. FIG. 17 shows a conductive substrate (hereinafter, also referred to as "Cu-Mo laminated substrate") having a laminated structure in which at least one layer of a molybdenum-containing layer and a copper-containing layer are laminated. The substrate surface layer 107a and the metal layers 107c and 107e are made of copper, while the metal layers 107b and 107d are made of molybdenum. When a Cu-Mo composite substrate or a Cu-Mo laminated substrate is used as the conductive substrate, the thermal resistance of the semiconductor element is reduced as compared with the case of using a general-purpose Si substrate. That is, by using a substrate in which a layer containing a Group 11 metal (for example, copper) of the periodic table is used as the substrate surface layer and at least one layer of a layer containing a Group 6 metal (for example, molybdenum) of the periodic table is laminated, it can be seen that the thermal resistance of a semiconductor element using an oxide semiconductor (for example, gallium oxide, etc.) can be further improved.

[0055] Generally, the bonding between an electrode and a substrate is performed via a thermosetting adhesive, solder, or other bonding materials, and in each case, it is necessary to heat and melt the bonding material. Therefore, when the bonding material cools down to room temperature, strain due to residual stress occurs in the electrode and the substrate. Depending on the thickness and characteristics of the materials constituting the electrode and the substrate, the electrode and the substrate after bonding may peel off. Also, by interposing solder or other bonding materials, the thickness of the semiconductor element increases and the thermal resistance increases. However, in an embodiment of the present invention, the electrode surface layer (first metal layer) 106 and the substrate surface layer (second metal layer) 107a are directly bonded by diffusion bonding using a metal belonging to Group 11 of the periodic table, thereby integrating the electrode and the substrate to form a semiconductor element. Since diffusion bonding does not require melting of the bonding material, bonding treatment at room temperature (about 25°C) is possible depending on the conditions. Therefore, the strain generated in the electrode and the substrate due to residual stress can be suppressed as much as possible, and the quality such as the electrical characteristics of the semiconductor element can be maintained and improved. Also, there is no need to interpose a bonding material or the like on the bonding surface in diffusion bonding, and the thickness of the material itself for performing diffusion bonding can be thin, so that the semiconductor element can be thinned without increasing the thermal resistance.

[0056] FIG. 7 shows an example of a Schottky barrier diode (SBD) according to the present invention. The SBD in FIG. 7 further includes an insulator layer 104 in addition to the configuration of the SBD in FIG. 6. More specifically, in addition to the n-type semiconductor layer 101a, the n+-type semiconductor layer 101b, the conductive substrate 107, the Schottky electrode 105a, and the ohmic electrode 110, it includes an insulator layer 104. Since the diffusion bonding layer 109 and the substrate surface layer 107a have the same electrical characteristics as the electrode surface layer, these can also be regarded as components of the ohmic electrode 110.

[0057] Examples of the material of the insulator layer 104 include, for example, GaO, AlGaO, InAlGaO, AlInZnGaO4, AlN, Hf2O3, SiN, SiON, Al2O3, MgO, GdO, SiO2, or Si3N4. However, in embodiments of the present invention, it is preferably one having a corundum structure. By using an insulator having a corundum structure for the insulator layer, the function of semiconductor characteristics at the interface can be favorably exhibited. The insulator layer 104 is provided between the n-type semiconductor layer 101 and the Schottky electrode 105a. The formation of the insulator layer can be performed by known means such as, for example, a sputtering method, a vacuum evaporation method, or a CVD method.

[0058] Regarding the formation and materials of the Schottky electrode 105a and the like, it is the same as in the case of the SBD in FIG. 6 above. For example, using known means such as a sputtering method, a vacuum evaporation method, a pressure bonding method, a CVD method, etc., for example, metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, or Ag, or alloys thereof, metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, or polypyrrole, or electrodes made of mixtures thereof can be formed.

[0059] The SBD in FIG. 7 has even better insulating characteristics and higher current controllability than the SBD in FIG. 6.

[0060] (MOSFET) Fig. 8 shows an example of a semiconductor device according to an embodiment of the present invention when the semiconductor device is a MOSFET. The MOSFET in Fig. 8 is a trench-type MOSFET and includes an n-type semiconductor layer 131a, n+-type semiconductor layers 131b and 131c, a conductive substrate 137, a gate insulating film 134, a gate electrode 135a, a source electrode 135b, and a drain electrode 140 composed of an electrode layer 135c and an electrode surface layer 136. Since the diffusion bonding layer 139 and the substrate surface layer 137a have electrical characteristics equivalent to those of the electrode surface layer, these can also be regarded as components of the drain electrode 140.

[0061] A substrate surface layer 137a, a diffusion bonding layer 139, and an electrode surface layer 136 are formed between the conductive substrate 137 and the electrode layer 135c. An n+-type semiconductor layer 131b is formed on the electrode layer 135c, and an n-type semiconductor layer 131a is formed on this n+-type semiconductor layer 131b. The n+-type semiconductor layer 131b is formed, for example, with a thickness of 100 nm to 100 μm, and the n-type semiconductor layer 131a is formed, for example, with a thickness of 100 nm to 100 μm. Further, an n+-type semiconductor layer 131c is formed on the n-type semiconductor layer 131a, and a source electrode 135b is formed on the n+-type semiconductor layer 131c.

[0062] Also, a plurality of trench grooves having a depth that penetrates the n+-type semiconductor layer 131c and reaches halfway through the n-type semiconductor layer 131a are formed in the n-type semiconductor layer 131a and the n+-type semiconductor layer 131c. A gate electrode 135a is embedded and formed in these trench grooves via a gate insulating film 134 having a thickness of, for example, 10 nm to 1 μm.

[0063] In the MOSFET of FIG. 8, when a voltage is applied between the source electrode 135b and the drain electrode 140 and a positive voltage with respect to the source electrode 135b is applied to the gate electrode 135a, a channel layer is formed on the side surface of the n-type semiconductor layer 131a, electrons are injected into the n-type semiconductor layer, and it turns on to enter the on state. On the other hand, by setting the voltage of the gate electrode to 0V, the channel layer cannot be formed, the n-type semiconductor layer 131a is filled with a depletion layer, and it turns off to enter the off state.

[0064] FIG. 9 shows a part of the manufacturing process of the MOSFET of FIG. 8. For example, as shown in FIG. 9(a), a laminate including an electrode surface layer 136, a substrate surface layer 137a, and a diffusion bonding layer 139 is prepared in advance by diffusion bonding. Then, an etching mask is provided in a predetermined region of the n-type semiconductor layer 131a and the n+-type semiconductor layer 131c, and anisotropic etching is performed by a reactive ion etching method or the like using the etching mask as a mask. As shown in FIG. 9(b), a trench groove having a depth reaching from the surface of the n+-type semiconductor layer 131c to the middle of the n-type semiconductor layer 131a is formed. Next, as shown in FIG. 9(c), using known means such as a thermal oxidation method, a vacuum evaporation method, a sputtering method, a CVD method, etc., a gate insulating film 134 having a thickness of, for example, 50 nm to 1 μm is formed on the side surface and the bottom surface of the trench groove. Then, using a CVD method, a vacuum evaporation method, a sputtering method, etc., a gate electrode material such as polysilicon is formed in the trench groove to a thickness not exceeding that of the n-type semiconductor layer.

[0065] Then, a source electrode 135b is formed on the n+-type semiconductor layer 131c and a drain electrode 140 is formed on the n+-type semiconductor layer 131b by using known means such as a vacuum evaporation method, a sputtering method, a CVD method, etc., thereby manufacturing a power MOSFET. Note that the electrode material of the source electrode may be a known electrode material respectively. Examples of the electrode material include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag, or alloys thereof, metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), organic conductive compounds such as polyaniline, polythiophene or polypyrrole, or mixtures thereof.

[0066] The MOSFET thus obtained has more excellent breakdown voltage characteristics than a conventional trench-type MOSFET. In FIG. 8, an example of a trench-type vertical MOSFET is shown, but in the embodiments of the present invention, the present invention is not limited thereto and can be applied to various forms of MOSFETs. For example, the depth of the trench groove in FIG. 8 may be dug down to reach the bottom surface of the n-type semiconductor layer 131a to reduce the series resistance.

[0067] (SIT) FIG. 10 shows an example in the case where the semiconductor element according to the embodiment of the present invention is an SIT. The SIT in FIG. 10 includes an n-type semiconductor layer 141a, n+-type semiconductor layers 141b and 141c, a conductive substrate 147, a gate electrode 145a, a source electrode 145b, and a drain electrode 150 composed of an electrode layer 145c and an electrode surface layer 146. Note that since the diffusion bonding layer 149 and the substrate surface layer 147a have electrical characteristics equivalent to those of the electrode surface layer, these can also be regarded as components of the drain electrode 150.

[0068] Between the conductive substrate 147 and the electrode layer 145c, a substrate surface layer 147a, a diffusion bonding layer 149, and an electrode surface layer 146 are formed. Further, an n+-type semiconductor layer 141b is formed on the drain electrode 150, and an n−-type semiconductor layer 141a is formed on this n+-type semiconductor layer 141b. The n+-type semiconductor layer 141b is formed, for example, to have a thickness of 100 nm to 100 μm, and the n−-type semiconductor layer 141a is formed, for example, to have a thickness of 100 nm to 100 μm. Further, an n+-type semiconductor layer 141c is formed on the n−-type semiconductor layer 141a, and a source electrode 145b is formed on the n+-type semiconductor layer 141c.

[0069] Further, in the n−-type semiconductor layer 141a, a plurality of trench grooves having a depth that penetrates the n+-type semiconductor layer 141c and reaches a depth in the middle of the n−-type semiconductor layer 141a are formed. A gate electrode 145a is formed on the n−-type semiconductor layer 141a within the trench grooves.

[0070] In the SIT of FIG. 10, when a voltage is applied between the source electrode 145b and the drain electrode 150 and a positive voltage is applied to the gate electrode 145a with respect to the source electrode 145b, a channel layer is formed in the n−-type semiconductor layer 141a, electrons are injected into the n−-type semiconductor layer, and it turns on to enter the on state. On the other hand, by setting the voltage of the gate electrode to 0 V, the channel layer cannot be formed, the n−-type semiconductor layer 141b is filled with a depletion layer, and it turns off to enter the off state.

[0071] In an embodiment of the present invention, the SIT of FIG. 10 can be manufactured in the same manner as the MOSFET of FIG. 9. More specifically, for example, a laminate including an electrode surface layer 146, a substrate surface layer 147a, and a diffusion bonding layer 149 is prepared in advance by diffusion bonding. Then, an etching mask is provided in a predetermined region of the n-type semiconductor layer 141a and the n+-type semiconductor layer 141c, and anisotropic etching is performed using, for example, a reactive ion etching method or the like with the etching mask as a mask to form a trench groove having a depth reaching from the surface of the n+-type semiconductor layer 141c to the middle of the n-type semiconductor layer. Next, a gate electrode material such as polysilicon is formed in the trench groove to a thickness equal to or less than that of the n-type semiconductor layer by a CVD method, a vacuum evaporation method, a sputtering method, or the like. Further, a source electrode 145b is formed on the n+-type semiconductor layer 141c and a drain electrode 145c is formed on the n+-type semiconductor layer 141b by using known means such as a vacuum evaporation method, a sputtering method, or a CVD method, whereby the SIT can be manufactured. The electrode material of the source electrode may be a known electrode material, and examples of the electrode material include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, or Ag, or alloys thereof, metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, or polypyrrole, or mixtures thereof.

[0072] In each of the above embodiments, an example in which a p-type semiconductor is not used is shown. However, in an embodiment of the present invention, the present invention is not limited thereto, and a p-type semiconductor may be used. These semiconductor elements can be manufactured in the same manner as in the above example. The p-type semiconductor may be the same material as the n-type semiconductor and contain a p-type dopant, or may be a different p-type semiconductor.

[0073] In an embodiment of the present invention, the semiconductor element, in addition to the above matters, can be suitably used as a semiconductor device by being joined to a lead frame, a circuit board, a heat dissipation board, etc. by a conventional method. In particular, it is suitably used as a power module, an inverter or a converter, and further, for example, it is suitably used in a semiconductor system using a power supply device. A preferred example of the semiconductor device is shown in FIG. 12. In the semiconductor device of FIG. 12, both surfaces of the semiconductor element 400 are joined to a lead frame, a circuit board or a heat dissipation board 402 by solder 401 respectively. By configuring in this way, a semiconductor device excellent in heat dissipation can be obtained. In the embodiment of the present invention, it is preferable that the periphery of the joining member such as solder is sealed with resin.

[0074] The semiconductor element or semiconductor device according to the embodiment of the present invention described above can be applied to a power conversion device such as an inverter or a converter in order to exhibit the above-described functions. More specifically, it can be applied as a diode incorporated in an inverter or a converter, a thyristor, a power transistor, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), etc. which are switching elements. FIG. 13 is a block configuration diagram showing an example of a control system using the semiconductor element or semiconductor device according to the embodiment of the present invention, and FIG. 14 is a circuit diagram of the control system, and it is a control system particularly suitable for mounting on an electric vehicle.

[0075] As shown in FIG. 13, the control system 500 includes a battery (power source) 501, a boost converter 502, a buck converter 503, an inverter 504, a motor (object to be driven) 505, and a drive control unit 506, and these are mounted on an electric vehicle. The battery 501 is composed of a storage battery such as a nickel-metal hydride battery or a lithium-ion battery, stores electric power by charging at a charging station or regenerative energy during deceleration, etc., and can output a DC voltage required for the operation of the drive system and electrical equipment system of the electric vehicle. The boost converter 502 is a voltage conversion device equipped with a chopper circuit, for example, and can boost a DC voltage of, for example, 200V supplied from the battery 501 to, for example, 650V by the switching operation of the chopper circuit and output it to the drive system such as a motor. The buck converter 503 is also a voltage conversion device equipped with a chopper circuit, but can output a DC voltage of, for example, 200V supplied from the battery 501 to the electrical equipment system including a power window, a power steering, or in-vehicle electrical equipment, etc., by stepping it down to about 12V.

[0076] The inverter 504 converts the DC voltage supplied from the boost converter 502 into a three-phase AC voltage by a switching operation and outputs it to the motor 505. The motor 505 is a three-phase AC motor that constitutes the drive system of the electric vehicle, is rotationally driven by the three-phase AC voltage output from the inverter 504, and transmits the rotational driving force to the wheels of the electric vehicle via a transmission (not shown), etc.

[0077] On the one hand, using various sensors (not shown), measured values such as the rotational speed, torque of the wheels, and the depression amount of the accelerator pedal (accelerator amount) of the electric vehicle during driving are measured, and these measurement signals are input to the drive control unit 506. At the same time, the output voltage value of the inverter 504 is also input to the drive control unit 506. The drive control unit 506 has the function of a controller equipped with an arithmetic unit such as a CPU (Central Processing Unit) and a data storage unit such as a memory. By using the input measurement signals to generate a control signal and outputting it to the inverter 504 as a feedback signal, the switching operation by the switching element is controlled. As a result, the AC voltage applied by the inverter 504 to the motor 505 is instantaneously corrected, enabling the accurate execution of the driving control of the electric vehicle and realizing the safe and comfortable operation of the electric vehicle. Note that it is also possible to control the output voltage to the inverter 504 by applying the feedback signal from the drive control unit 506 to the boost converter 502.

[0078] FIG. 14 shows a circuit configuration excluding the buck converter 503 in FIG. 13, that is, a circuit configuration showing only the configuration for driving the motor 505. As shown in the figure, the semiconductor device of the present invention is employed in the boost converter 502 and the inverter 504 as, for example, a Schottky barrier diode for switching control. In the boost converter 502, it is incorporated into a chopper circuit to perform chopper control, and in the inverter 504, it is incorporated into a switching circuit including an IGBT to perform switching control. Note that the current is stabilized by interposing an inductor (such as a coil) in the output of the battery 501, and the voltage is stabilized by interposing a capacitor (such as an electrolytic capacitor) between the battery 501, the boost converter 502, and the inverter 504, respectively.

[0079] Also, as shown by the dotted line in FIG. 14, an arithmetic unit 507 composed of a CPU (Central Processing Unit) and a storage unit 508 composed of a non-volatile memory are provided in the drive control unit 506. The signal input to the drive control unit 506 is given to the arithmetic unit 507, and by performing necessary calculations, a feedback signal for each semiconductor element is generated. The storage unit 508 temporarily holds the calculation results by the arithmetic unit 507, accumulates physical constants, functions, etc. necessary for drive control in the form of a table, and appropriately outputs them to the arithmetic unit 507. The arithmetic unit 507 and the storage unit 508 can adopt known configurations, and their processing capabilities, etc. can also be arbitrarily selected.

[0080] As shown in FIGS. 13 and 14, in the control system 500, diodes, thyristors which are switching elements, power transistors, IGBTs, MOSFETs, etc. are used for the switching operations of the boost converter 502, the buck converter 503, and the inverter 504. By using gallium oxide (Ga2O3), particularly corundum-type gallium oxide (α-Ga2O3) as the material for these semiconductor elements, the switching characteristics are significantly improved. Furthermore, by applying the semiconductor device and the like according to the embodiment of the present invention, extremely good switching characteristics can be expected, and further miniaturization and cost reduction of the control system 500 can be realized. That is, each of the boost converter 502, the buck converter 503, and the inverter 504 can be expected to have the effects of the present invention, and the effects of the present invention can be expected in any one of these, or any combination of two or more, or in any form including the drive control unit 506. Note that the above-described control system 500 can be applied not only to the control system of an electric vehicle for the semiconductor device according to the embodiment of the present invention, but also to control systems for all applications such as boosting and bucking the power from a DC power source and converting the power from DC to AC. It is also possible to use a power source such as a solar cell as the battery.

[0081] FIG. 15 is a block configuration diagram showing another example of a control system employing a semiconductor element or a semiconductor device according to an embodiment of the present invention, and FIG. 16 is a circuit diagram of the control system. It is a control system suitable for mounting on infrastructure devices and home appliances that operate on power from an AC power source.

[0082] As shown in FIG. 15, the control system 600 inputs power supplied from an external, for example, three-phase AC power source (power source) 601, and has an AC / DC converter 602, an inverter 604, a motor (object to be driven) 605, and a drive control unit 606, and these can be mounted on various devices (described later). The three-phase AC power source 601 is, for example, a power generation facility (thermal power plant, hydroelectric power plant, geothermal power plant, nuclear power plant, etc.) of an electric power company, and its output is supplied as an AC voltage while being stepped down through a substation. Also, for example, it is installed in a building or a neighboring facility in the form of a home generator and supplied by a power cable. The AC / DC converter 602 is a voltage conversion device that converts an AC voltage into a DC voltage, and converts an AC voltage of 100V or 200V supplied from the three-phase AC power source 601 into a predetermined DC voltage. Specifically, it is converted into a desired DC voltage generally used, such as 3.3V, 5V, or 12V, by voltage conversion. When the object to be driven is a motor, conversion to 12V is performed. Note that it is also possible to employ a single-phase AC power source instead of the three-phase AC power source, and in that case, the same system configuration can be achieved by using a single-phase input AC / DC converter.

[0083] The inverter 604 converts the DC voltage supplied from the AC / DC converter 602 into a three-phase AC voltage by a switching operation and outputs it to the motor 605. The motor 604 has a different form depending on the object to be controlled. When the object to be controlled is a train, it is a three-phase AC motor for driving wheels, when it is factory equipment, it is a pump or various power sources, and when it is a home appliance, it is a compressor or the like. It is rotationally driven by the three-phase AC voltage output from the inverter 604, and transmits the rotational driving force to an object to be driven (not shown).

[0084] Incidentally, in home appliances, for example, there are many drive targets that can be directly supplied with the DC voltage output from the AC / DC converter 302 (such as personal computers, LED lighting devices, video devices, audio devices, etc.). In this case, the inverter 604 is not required in the control system 600. As shown in FIG. 15, a DC voltage is supplied from the AC / DC converter 602 to the drive target. In this case, for example, a DC voltage of 3.3V is supplied to a personal computer, and a DC voltage of 5V is supplied to an LED lighting device.

[0085] On the other hand, using various sensors (not shown), measured values such as the rotational speed and torque of the drive target, or the temperature and flow rate of the surrounding environment of the drive target are measured, and these measurement signals are input to the drive control unit 606. At the same time, the output voltage value of the inverter 604 is also input to the drive control unit 606. Based on these measurement signals, the drive control unit 606 gives a feedback signal to the inverter 604 and controls the switching operation by the switching element. As a result, the AC voltage applied by the inverter 604 to the motor 605 is instantaneously corrected, so that the operation control of the drive target can be accurately executed, and a stable operation of the drive target is realized. Also, as described above, when the drive target can be driven by a DC voltage, it is also possible to perform feedback control on the AC / DC converter 602 instead of providing feedback to the inverter.

[0086] FIG. 16 shows the circuit configuration of FIG. 15. As shown in the figure, the semiconductor device of the present invention is used for switching control by being adopted in, for example, an AC / DC converter 602 and an inverter 604 as a Schottky barrier diode. The AC / DC converter 602 uses, for example, a circuit configuration in which Schottky barrier diodes are formed in a bridge shape, and performs DC conversion by converting and rectifying the negative voltage component of the input voltage into a positive voltage. In the inverter 604, it is incorporated into the switching circuit of the IGBT to perform switching control. An inductor (such as a coil) is interposed between the three-phase AC power supply 601 and the AC / DC converter 602 to stabilize the current, and a capacitor (such as an electrolytic capacitor) is interposed between the AC / DC converter 602 and the inverter 604 to stabilize the voltage.

[0087] Also, as shown by the dotted line in FIG. 16, an arithmetic unit 607 composed of a CPU and a storage unit 608 composed of a non-volatile memory are provided in the drive control unit 606. The signal input to the drive control unit 606 is given to the arithmetic unit 607, and a feedback signal for each semiconductor element is generated by performing necessary calculations. The storage unit 608 temporarily holds the calculation results by the arithmetic unit 607, accumulates physical constants, functions, etc. necessary for drive control in the form of a table, and appropriately outputs them to the arithmetic unit 607. The arithmetic unit 607 and the storage unit 608 can adopt known configurations, and their processing capabilities and the like can also be arbitrarily selected.

[0088] Even in such a control system 600, similar to the control system 500 shown in FIGS. 13 and 14, diodes and switching elements such as thyristors, power transistors, IGBTs, MOSFETs, etc. are used for the rectifying operation and switching operation of the AC / DC converter 602 and the inverter 604. By using gallium oxide (Ga2O3), particularly corundum-type gallium oxide (α-Ga2O3) as the material for these semiconductor elements, the switching characteristics are improved. Furthermore, by applying the semiconductor film and semiconductor device according to the present invention, extremely good switching characteristics can be expected, and further miniaturization and cost reduction of the control system 600 can be achieved. That is, each of the AC / DC converter 602 and the inverter 604 can be expected to have the effects of the present invention, and the effects of the present invention can be expected in any one of these, or in a combination, or in a form including the drive control unit 606 as well.

[0089] In FIGS. 15 and 16, the motor 605 is illustrated as the drive target, but the drive target is not necessarily limited to those that operate mechanically, and many devices that require an AC voltage can be targeted. In the control system 600, it can be applied as long as power is input from an AC power source to drive the drive target, and it can be mounted for drive control of devices such as infrastructure devices (for example, power facilities, communication facilities, traffic control devices, water and sewage treatment facilities, system devices, labor-saving devices, trains, etc.) and home appliances (for example, refrigerators, washing machines, personal computers, LED lighting devices, video devices, audio devices, etc.).

[0090] It is of course possible to combine a plurality of embodiments according to the present invention or apply some of the components to other embodiments, and such things also belong to the embodiments of the present invention.

Example

[0091] Hereinafter, examples of the present invention will be described, but the present invention is not limited thereto.

[0092] (Example 1) 1. Formation of n-type semiconductor layer 1-1. Film formation apparatus Using FIG. 11, the mist CVD apparatus 1 used in this example will be described. The mist CVD apparatus 1 includes a carrier gas source 2a for supplying a carrier gas, a flow rate regulating valve 3a for regulating the flow rate of the carrier gas sent out from the carrier gas source 2a, a carrier gas (dilution) source 2b for supplying a carrier gas (dilution), a flow rate regulating valve 3b for regulating the flow rate of the carrier gas (dilution) sent out from the carrier gas (dilution) source 2b, a mist generation source 4 containing a raw material solution 4a, a container 5 containing water 5a, an ultrasonic vibrator 6 attached to the bottom surface of the container 5, a film formation chamber 7, a supply pipe 9 connecting the mist generation source 4 to the film formation chamber 7, a hot plate 8 installed in the film formation chamber 7, and an exhaust port 11 for discharging the mist, droplets and exhaust gas after the thermal reaction. Note that a substrate 10 is installed on the hot plate 8.

[0093] 1-2. Formation of crystalline oxide semiconductor film Using the mist CVD apparatus shown in FIG. 11, an n-type semiconductor layer was formed on a sapphire substrate (substrate 10).

[0094] 1-3. Evaluation When the phase of the film obtained in 1-2. above was identified using an XRD diffractometer, the obtained film was α-Ga2O3.

[0095] 2. Formation of n+-type semiconductor layer An n+-type semiconductor layer was formed on the n-type semiconductor layer in the same manner as in 1-2. above, except that tin was used as the dopant. When the phase of the obtained film was identified using an XRD diffractometer, the obtained film was α-Ga2O3.

[0096] 3. Formation of ohmic electrode On the n+-type semiconductor layer of the laminate obtained in 2. above, a Ti layer as an electrode layer and a Cu layer as an electrode surface layer were laminated by sputtering, respectively. The thickness of the Ti layer was 70 nm, and the thickness of the Cu layer was 200 nm. The Cu layer mentioned here corresponds to the electrode surface layer.

[0097] 4. Fabrication of Conductive Substrate As a conductive substrate, a Cu-Mo composite substrate having a three-layer laminated structure composed of two Cu layers and a Mo layer interposed therebetween (Mo content: 70% by mass, Cu content: 30% by mass) was fabricated. The thickness of the conductive substrate was 200 μm.

[0098] 5. Bonding of Ohmic Electrode and Conductive Substrate The surfaces of the Cu layer (electrode surface layer) on the ohmic electrode and the Cu layer (substrate surface layer) on the conductive substrate were polished so that the surface roughness (Sa) of each surface was about 0.1 nm to 2 nm. Then, in order to avoid surface oxidation, the crystalline oxide semiconductor film and the ohmic electrode laminated on the sapphire substrate and the conductive substrate fabricated in 4. above were transferred to a vacuum environment, and both were heated at a temperature of 120°C to 350°C by the radiant heat of a heater, and pressure was applied and diffusion bonding was performed in a state where the two were directly adhered without any inclusions between the electrode surface layer and the substrate surface layer. For both diffusion-bonded parts, although slight residues of oxides and impurities were confirmed as a diffusion-bonded layer formed at the bonding interface, they were bonded with sufficient strength. Also, an increase in thermal resistance was suppressed as compared with the case where solder or other bonding materials were interposed. Moreover, by increasing the degree of vacuum after setting the surface roughness (Sa) to 0.1 nm to 1 nm, diffusion bonding at room temperature (25°C) was performed, and the same bonding state as above could be confirmed.

[0099] 6. Substrate Removal In the laminate obtained in 5. above, the sapphire substrate was removed.

[0100] 7. Formation of Schottky Electrode On the second n-type semiconductor layer of the laminate obtained in the above 6., a Co film (thickness 100 nm), a Ti film (50 nm), and an Al film (thickness 5 μm) were respectively formed by EB evaporation to form a Schottky electrode.

[0101] (Example 2) An SBD was fabricated according to Example 1, except that an Si substrate was used as the conductive substrate.

[0102] (Evaluation of Electrical Characteristics) When the IV characteristics of the semiconductor elements (SBDs) obtained in Example 1 and Example 2 were evaluated, it was found that the Schottky barrier diode of Example 1 had excellent electrical characteristics. Also, when a Cu-Mo laminated substrate was used as the conductive substrate, electrical characteristics equivalent to those of Example 1 were obtained.

[0103] (Example 3) In the above 5., Si was interposed between the Cu layer on the ohmic electrode and the Cu layer on the conductive substrate, and then the two were directly brought into close contact and pressed under the same conditions as in the above (5). In the diffusion-bonded laminate, although a slight Si residue was observed as a diffusion-bonded layer formed at the bonding interface, it was bonded with sufficient strength. The electrical characteristics and thermal characteristics were also excellent, similar to those of Example 1.

[0104] (Comparative Example 1) Instead of the Cu layer on the ohmic electrode, Algomax (registered trademark) made of a sintered body of silver was used to bond to the Cu layer on the surface of the conductive substrate. The obtained laminate was inferior in heat dissipation compared to the laminate obtained in Example 1.

[0105] The semiconductor element of the present invention can be used in all fields such as semiconductors (for example, compound semiconductor electronic devices, etc.), electronic component and electrical equipment components, optical and electrophotographic related devices, and industrial members. In particular, it is useful for power devices.

Explanation of Reference Numerals

[0106] 1 Film forming apparatus (mist CVD apparatus) 2a Carrier gas source 2b Carrier gas (diluted) source 3a Flow rate regulating valve 3b Flow rate regulating valve 4 Mist generating source 4a Raw material solution 4b Raw material fine particles 5 Container 5a Water 6 Ultrasonic vibrator 7 Film forming chamber 8 Hot plate 9 Supply pipe 10 Substrate 101 Semiconductor layer 101a n-type semiconductor layer 101b n+-type semiconductor layer 105 Electrode layer 105a Schottky electrode (other electrode layer) 106 Electrode surface layer (first metal layer) 107 Conductive substrate 107a Substrate surface layer (second metal layer) 108 Underlying substrate 109 Diffusion bonding layer (bonding layer) 110 Ohmic electrode 131a n-type semiconductor layer 131b First n+-type semiconductor layer 131c Second n+-type semiconductor layer 132 p-type semiconductor layer 134 Gate insulating film 135a Gate electrode 135b Source electrode 135c Electrode layer 136 Electrode surface layer (first metal layer) 137 Conductive substrate 137a Substrate surface layer (second metal layer) 139 Diffusion bonding layer (bonding layer) 140 Drain electrode 141a n-type semiconductor layer 141b First n+-type semiconductor layer 141c Second n+-type semiconductor layer 145a Gate electrode 145b Electrode layer 145c Drain electrode (electrode layer) 146 Electrode surface layer (first metal layer) 147 Conductive substrate 147a Substrate surface layer (second metal layer) 149 Diffusion bonding layer (bonding layer) 150 Drain electrode 400 Semiconductor element 401 Solder 402 Heat sink substrate 500 Control system 501 Battery (power source) 502 Boost converter 503 Buck converter 504 Inverter 505 Motor (driven object) 506 Drive control unit 507 Arithmetic unit 508 Memory unit 600 Control system 601 Three-phase AC power supply (power source) 602 AC / DC converter 604 Inverter 605 Motor (driven object) 606 Drive control unit 607 Arithmetic unit 608 Memory unit

Claims

1. A semiconductor device comprising at least a semiconductor layer containing a crystalline oxide semiconductor as a main component, an electrode layer laminated on the semiconductor layer, and a conductive substrate laminated on the electrode layer, wherein a first metal layer and a second metal layer containing a Group 11 metal of the periodic table are provided between the electrode layer and the conductive substrate, and a diffusion bonding layer is interposed between the first metal layer and the second metal layer, the diffusion bonding layer contains the metals contained in the first metal layer and the second metal layer respectively, and the diffusion bonding layer contains a metal different from the Group 11 metal of the periodic table. A semiconductor device characterized by that.

2. The semiconductor device according to claim 1, wherein the diffusion bonding layer contains silicon.

3. The semiconductor device according to claim 1 or 2, wherein the first metal layer and the second metal layer contain any one of gold, silver, or copper.

4. The semiconductor device according to claim 3, wherein at least one of the first metal layer and the second metal layer contains copper.

5. The semiconductor device according to claim 4, wherein both the first metal layer and the second metal layer contain copper.

6. The semiconductor device according to any one of claims 1 to 5, wherein the crystalline oxide semiconductor contains at least one metal selected from aluminum, indium, and gallium.

7. The semiconductor device according to any one of claims 1 to 6, wherein the crystalline oxide semiconductor contains at least gallium.

8. The semiconductor device according to any one of claims 1 to 7, further comprising another electrode layer on a surface of the semiconductor layer facing the surface on which the electrode layer is laminated.

9. The semiconductor device according to any one of claims 1 to 8, wherein the semiconductor layer is composed of an n+-type semiconductor layer and an n-type semiconductor layer provided on the n+-type semiconductor layer, and the electrode layer is provided on the n+-type semiconductor layer.

10. A semiconductor device comprising at least a semiconductor layer containing a crystalline oxide semiconductor as a main component, an electrode layer laminated on the semiconductor layer, a bonding layer laminated on the electrode layer, and a conductive substrate laminated on the bonding layer, wherein the bonding layer is a layer formed by diffusion bonding of a metal containing a Group 11 metal of the periodic table, and the bonding layer contains copper. A semiconductor device characterized by that.

11. A semiconductor device comprising at least a semiconductor layer containing a crystalline oxide semiconductor as a main component, an electrode layer laminated on the semiconductor layer, a bonding layer laminated on the electrode layer, and a conductive substrate laminated on the bonding layer, wherein the bonding layer is a layer formed by diffusion bonding of a metal containing a Group 11 metal of the periodic table, and the bonding layer contains a metal different from the Group 11 metal of the periodic table.

12. The semiconductor device according to claim 11, wherein the bonding layer contains silicon.

13. The semiconductor device according to claim 11 or 12, wherein the bonding layer contains any one of gold, silver, or copper.

14. The semiconductor device according to any one of claims 11 to 13, wherein the crystalline oxide semiconductor contains at least one metal selected from aluminum, indium, and gallium.

15. The semiconductor device according to any one of claims 11 to 14, wherein the crystalline oxide semiconductor contains at least gallium.

16. The semiconductor device according to any one of claims 11 to 15, further comprising another electrode layer on a surface of the semiconductor layer opposite to the surface on which the electrode layer is laminated.

17. The semiconductor device according to any one of claims 11 to 16, wherein the semiconductor layer comprises an n+-type semiconductor layer and an n−-type semiconductor layer provided on the n+-type semiconductor layer, and the electrode layer is provided on the n+-type semiconductor layer.

18. The semiconductor device according to any one of claims 1 to 17, which is a power device.

19. A semiconductor device in which at least a semiconductor device is joined by a joining member to a lead frame, a circuit board, or a heat dissipation board, wherein the semiconductor device is the semiconductor device according to any one of claims 1 to 18.

20. A power conversion device using the semiconductor device according to claim 19.

21. A control system using the semiconductor device according to claim 20.

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