Graded Doping in Power Devices

Abstract

An exemplary method of forming a semiconductor structure may include forming a doped silicon layer on a semiconductor substrate. The level of doping may increase with increasing distance from the semiconductor substrate. The method may include etching the doped silicon layer to define a trench that extends to the semiconductor substrate. The doped silicon layer may define sloped sidewalls of the trench. The trench may be characterized by a depth of about 30 μm or greater. The method may include lining the trench with a first oxide material. The method may include depositing a second oxide material in the trench. The method may include forming a contact to produce a power device.

Description

Technical Field

[0001] Cross - Reference to Related Applications

[0001] This application claims the benefit and priority of U.S. Provisional Application No. 17 / 169,916, filed on February 8, 2021, entitled "GRADED DOPING IN POWER DEVICES", the content of which is hereby incorporated by reference in its entirety for all purposes.

[0002]

[0002] This technology relates to semiconductor processes and devices. More specifically, this technology relates to the manufacture of semiconductor structures characterized by adjusting doping based on structural characteristics.

Background Art

[0003]

[0003] Integrated circuits are made possible by a process of forming intricately patterned layers of material on a substrate surface. To manufacture patterned materials on a substrate, methods for controlling the deposition and removal of materials are required. However, in new device designs, it can be difficult to manufacture high - quality material layers.

[0004]

[0004] Accordingly, there is a need for improved systems and methods that can be used to manufacture high - quality devices and structures. These and other needs are addressed by this technology.

Summary of the Invention

[0005]

[0005] An exemplary method of forming a semiconductor structure may include forming a doped silicon layer on a semiconductor substrate. The doping level may increase as the distance from the semiconductor substrate increases. The method may include etching the doped silicon layer to define a trench that extends to the semiconductor substrate. The doped silicon layer may define the sloped sidewalls of the trench. The trench may be characterized by a depth of about 30 μm or more. The method may include lining the trench with a first oxide material. The method may include depositing a second oxide material in the trench. The method may include forming a contact to manufacture a power device.

[0006]

[0006] In some embodiments, after etching, the doped silicon layer may be characterized by a width of about 2 μm to about 5 μm. The thickness of the first oxide material lining the trench may be about 5 nm or less. The method may include performing an implantation on the exposed surface of the doped silicon layer. The power device may include a P-N junction. The contact may include a region of metal silicide on the semiconductor structure. The region of metal silicide may be characterized by ions of implanted boron, phosphorus, or arsenic. The region of metal silicide may be characterized by a barrier height of about 0.6 V or more to form a Schottky contact. The first oxide material may be aluminum oxide or may include aluminum oxide, and the second oxide material may be silicon oxide or may include silicon oxide. The semiconductor substrate may be antimony-doped silicon or may include antimony-doped silicon. The sloped sidewalls of the trench may be characterized by a continuous slope. The doped silicon layer may be characterized by a linear increase in doping from a position close to the semiconductor substrate to a position close to the surface opposite the surface adjacent to the semiconductor substrate. The semiconductor structure may be characterized by a breakdown voltage of about 650 V or more. The dopant of the doped silicon layer may be phosphorus or may include phosphorus. The dopant concentration at a position close to the semiconductor substrate is about 8e15cm -3The following may be applicable. The dopant concentration at a position distal from the semiconductor substrate may be about 9e15 cm -3 or more.

[0007]

[0007] Some embodiments of the present technology may include a semiconductor structure. This structure may include a doped silicon layer formed on a substrate. The level of doping in the doped silicon may increase as the distance from the substrate increases. This structure may include trenches formed on both sides of the doped silicon layer. The trenches may include a liner of a first oxide material and a filler of a second oxide material. The trenches may be characterized by sloped sidewalls. This structure may include contacts.

[0008]

[0008] In some embodiments, the dopant in the doped silicon layer may be phosphorus or may include phosphorus. The dopant concentration at a position close to the substrate may be about 8e15 cm -3 or less. The dopant concentration at a position distal from the substrate may be about 9e15 cm -3 or more. The sloped sidewalls of the trenches may be characterized by a continuous slope. The doped silicon layer may be characterized by a linear increase in doping from a position close to the substrate to a position close to the surface opposite to the surface adjacent to the substrate. The substrate may be antimony-doped silicon or may include antimony-doped silicon. The first oxide material may be aluminum oxide or may include aluminum oxide. The second oxide material may be silicon oxide or may include silicon oxide. The exposed surface of the semiconductor structure may be boron implantation that forms a P-N junction of the semiconductor structure or may include it. The contact may include a metal silicide region. The metal silicide region may be characterized by implanted boron, phosphorus, or arsenic ions. The metal silicide region may be characterized by a barrier height of about 0.6 V or more to form a Schottky contact.

[0009]

[0009] Some embodiments of the present technology may include a method of forming a semiconductor structure. The method may include forming a doped silicon layer on a semiconductor substrate. The dopant may be included with a gradient such that the dopant concentration increases as the distance from the semiconductor substrate increases. The method may include etching the doped silicon layer to define a trench that extends to the semiconductor substrate. The doped silicon layer may define the sloped sidewalls of the trench. The trench may be characterized by a depth of about 30 μm or more. The doped silicon layer may be characterized by a width of about 2 μm to about 5 μm. The method may include lining the trench with a first oxide material characterized by a thickness of about 5 nm or less. The method may include depositing a second oxide material in the trench. The method may include forming contacts to fabricate a power device.

[0010]

[0010] In some embodiments, the semiconductor substrate may be antimony-doped silicon or may include antimony-doped silicon. The first oxide material may be aluminum oxide or may include aluminum oxide. The second oxide material may be silicon oxide or may include silicon oxide. The method may include performing an implantation on the exposed surface of the doped silicon layer. The power device may be a P-N junction. The method may include forming a region of metal silicide on the semiconductor structure. The region of metal silicide may be characterized by implanted boron, phosphorus, or arsenic ions. The region of metal silicide may be characterized by a barrier height of about 0.6 V or more to form a Schottky contact.

[0011]

[0011] Such a technique can provide a number of advantages over conventional systems and techniques. For example, the process can manufacture devices with improved charge density for any number of devices. Further, the process can improve the breakdown voltage of the manufactured structure and can overcome the complexity of the process. These and other embodiments will be described in more detail below in conjunction with the following description and the accompanying figures, along with many of their advantages and features.

[0012]

[0012] A further understanding of the nature and advantages of the disclosed technology can be realized by reference to the remainder of this specification and the drawings.

Brief Description of the Drawings

[0013]

Figure 1

Figure 2

Figure 3A

Figure 3B

Figure 3C

[0014]

[0016] Some of the figures are included as schematic diagrams. It should be understood that the figures are for illustrative purposes only and should not be regarded as to scale unless specifically stated otherwise. Further, as schematic diagrams, the figures are provided to aid understanding and may not include all aspects or information, and may include exaggerated material for illustrative purposes, as compared to a realistic representation.

[0015]

[0017] In the accompanying drawings, similar components and / or features may be labeled with the same reference labels. Further, various components of the same type may be distinguished by attaching a character that distinguishes the similar components after the reference label. When only the first reference label is used in this specification, the description is applicable to any one of the similar components having the same first reference label, regardless of the character.

Best Mode for Carrying Out the Invention

[0016]

[0018] As devices manufactured by semiconductor processing continue to be miniaturized, uniformity, material quality, process control, and reproducibility are becoming increasingly difficult for each process. In order to continue to improve the performance of devices at a reduced scale, alternative films and processes for further improving performance compared to conventional devices are being studied.

[0017]

[0019] For example, in power devices including power diodes, many structures are formed on materials with a wide bandgap such as silicon carbide and gallium nitride in order to increase the breakdown voltage, which can be extremely expensive, but there is a possibility that the height of the device can be lowered to facilitate manufacturing. However, when using alternative materials such as silicon as a device substrate for high-power devices including 500V or more, it becomes more difficult to balance charges between various regions of the device, and it may become more difficult to limit the height of the device. Further, a power diode may be characterized by deep trenches formed to facilitate charge balance between the N-type semiconductor material and the P-type semiconductor material of the device. In order to improve device scaling, a thin layer of high P-type charge material can be used to balance the N-type charge of silicon, thereby reducing the dimensions of the P-type region material.

[0018]

[0020] During the formation process of some power devices, a layer of material for charge balancing may extend along the sidewalls of the formed trenches and along the plane or horizontal surface of the structure formed along the substrate. This layer, which may be a liner, can balance charges not only along the surface of the substrate but also through the trenches. However, this liner layer can be characterized by fixed charges during manufacturing. Based on the height of the device, which can be several tens of micrometers, the fixed charges may not be able to correct for the complexity of the process. For example, during trench formation, a certain degree of tilt may occur throughout the structure. As a result, the width of the semiconductor material may be different at the top and bottom. The charge density within the device can be affected as a function of the doping within the semiconductor material, which can affect the breakdown voltage within the device. Consequently, the narrower the width at the top of the device, the earlier breakdown occurs, reducing the breakdown voltage of the device and potentially limiting its applicability to high-power devices.

[0019]

[0021] The present technology can overcome these problems by forming a doping gradient throughout the semiconductor material. By increasing the doping from the bottom to the top along the gradient, the semiconductor material can be used to overcome the performance costs associated with the tapered structure, improving the scaling and performance of the device. In the remaining disclosure, while specific structures such as diodes to which the present structure and method can be adopted are always specified, it will be readily understood that the present system and method are equally applicable to any number of structures and devices that can benefit from doping adjustment or other processes during semiconductor processing. Therefore, the present technology should not be considered limited to use with only any specific structure. Further, while an exemplary tool system is described to provide the basis of the present technology, it should be understood that the present technology can be manufactured in any number of semiconductor processing chambers and tools capable of performing some or all of the described processes.

[0020]

[0022] FIG. 1 is a top view showing an embodiment of a processing system 100 of deposition, etching, firing, and curing chambers according to some embodiments of the present technology. In the figure, a pair of front-opening unified pods 102 supply substrates of various sizes, and these substrates are received by a robot arm 104 and placed in a low-pressure holding area 106 before being placed in one of the substrate processing chambers 108a-f positioned in tandem sections 109a-c. A second robot arm 110 can be used to reciprocally transport the substrate wafers from the holding area 106 to the substrate processing chambers 108a-f. Each of the substrate processing chambers 108a-f can be equipped to perform a number of substrate processing steps including the dry etching process described herein, in addition to cyclic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, annealing, plasma processing, degassing, orientation, and other substrate processes.

[0021]

[0023] The substrate processing chambers 108a - f may include one or more system components for depositing, annealing, curing, and / or etching a material film on a substrate or wafer. In one configuration, two pairs of processing chambers, such as 108c - d and 108e - f, can be used to deposit material on the substrate, and a third pair of processing chambers, such as 108a - b, can be used to cure, anneal, or process the deposited film. In another configuration, three pairs of chambers, such as 108a - f, can all be configured to perform both depositing and curing a film on the substrate. Any one or more of the described processes can be performed in additional chambers separate from the manufacturing systems shown in different embodiments. It will be understood that additional configurations of deposition, etching, annealing, and curing chambers for the material film are contemplated by the system 100. Further, any number of other processing systems can be utilized with this technology that can incorporate chambers for performing any of the specific processes. In some embodiments, a chamber system that can provide access to multiple processing chambers while maintaining a vacuum environment in various sections such as the described holding and transfer areas can enable performing processes in multiple chambers while maintaining a specific vacuum environment between individual processes.

[0022]

[0024] System 100, or more specifically, a chamber incorporated within system 100 or other processing system, can be used to fabricate structures according to some embodiments of the present technology. FIG. 2 is a diagram showing exemplary steps in a method 200 for forming a semiconductor structure according to some embodiments of the present technology. Method 200 can be executed in one or more processing chambers, such as a chamber incorporated within system 100, for example. Method 200 may or may not include one or more pre-method steps including pre-steps, deposition, etching, polishing, cleaning, or any other steps that can be performed prior to the steps described. The method may specifically relate to or may not relate to some embodiments of the methods according to the present technology and may include a number of optional steps as shown in the figures. Method 200 will be described with reference to the steps schematically shown in FIGS. 3A-3C, which will be described in relation to the steps of method 200. FIGS. 3A-3C show only partial schematic views with limited detail, and in some embodiments, it should be understood that the substrate can include any number of semiconductor sections having an aspect as illustrated in the figures, as well as alternative structural aspects that can also benefit from any aspect of the present technology.

[0023]

[0025] Method 200 may include optional steps for developing a semiconductor structure to a particular manufacturing process. In some embodiments, method 200 may be performed on a base structure, but in some embodiments, the method may be performed following the formation of other materials. As shown in FIG. 3A, the semiconductor structure may represent device 300 after preprocessing or other processing has been completed. For example, substrate 305 may be a planar material, or a structured device that may include a plurality of materials configured as posts, trenches, or other structures similarly encompassed by the present technology. Substrate 305 may include any number of conductive materials and / or dielectric materials including transition metals, post-transition metals, metalloids, metals including oxides, nitrides, and carbides of any of these materials, and any other materials that may be incorporated into the structure. In some embodiments, substrate 305 may be silicon or may include silicon, which may be doped with any number of materials, or may be doped silicon. Doping may be N-type doping in some processes, and silicon can be formed or grown by any number of techniques. Further, in embodiments, one or more doped regions may be included in the substrate. For example, any number of N-type or P-type doping regions may be included in the substrate. N-type doping can be performed using any dopant that produces N-type doping, and may include antimony, among any other dopants, for example. It should be understood that this figure is not to scale and substrate 305 may be on the order of tens of microns in some embodiments.

[0024]

[0026] Method 200 may include forming, on a substrate, a material that may be or may include any material used for a power device. Materials such as gallium nitride or silicon carbide can be used, but in some embodiments, silicon can be deposited or grown on the substrate. As a non-limiting example, method 200 may include epitaxially growing silicon 310 on the substrate in step 205. The silicon can be doped during the growth process and, as shown, can be characterized by a doping gradient in which the level of doping increases as the distance from the semiconductor substrate increases. As will be further described below, doping can be used to correct for a wider structure closer to the substrate that can be fabricated during etching by incorporating a doping level that decreases closer to substrate 305. The dopant can be any number of materials commonly used for doping and, in some embodiments, can be, for example, phosphorus. Phosphorus doping can be included in a gradient that can include any amount of N+ or N- doping along the structure. Silicon 310 can be grown to any height and, in some embodiments, can be used to form a device with a height of less than 60 μm, and can be formed to a height of about 55 μm or less, about 50 μm or less, about 45 μm or less, about 40 μm or less, about 35 μm or less, or less than that.

[0025]

[0027] Device 300 can be used to fabricate any number of power devices and can provide different contact structures for different devices. For example, in some embodiments, the device can be used to form a P-N junction and, in some embodiments, may have ohmic contacts. Thus, in some embodiments, method 200 may include performing an implantation process in optional step 210 to form the junction. As an example, an implantation process of boron can be performed to a depth of about 1 micron or more within the surface of the silicon structure. An annealing such as spike annealing can be performed to activate the implantation and form implantation region 315 as shown in FIG. 3B.

[0026]

[0028] The doped silicon layer can then be etched in step 215. By etching, one or more trenches can be formed that extend from the first surface of the silicon into the substrate 305 to a level as shown in FIG. 3B. The trenches can be deep trench features for not only diodes or other power device structures, but also any other feature formed within the semiconductor substrate. The trenches can be characterized by an increased aspect ratio that facilitates the occurrence of a target breakdown voltage throughout the structural material. For example, each trench can be characterized by a depth-to-width ratio of about 10 or more, and about 15 or more, about 20 or more, about 25 or more, about 30 or more, about 35 or more, about 40 or more, about 45 or more, about 50 or more, or more. An active region may be generated from the remaining silicon material 310 between the trenches, which may be a land for an anode or cathode, and an edge termination region may be present outside the trenches. Each of these regions can balance the charge with respect to the substrate as described above.

[0027]

[0029] As described above, the etching may reach throughout the depth through the N-type doped silicon and may reach into the substrate 305 as shown. Thus, the etching process may etch tens of micrometers in some embodiments of the present technology. Any number of etching processes capable of anisotropically etching the entire silicon or other material are executable. In a non-limiting example, a reactive ion etching process may be performed to fabricate the trench structure. Due to the depth of the structure, a taper may be formed that extends to or into the substrate as shown, and as a result, the sidewalls of the trench may be inclined. As a result, the silicon material may come to be characterized by a first width at the top of the structure and a second width greater than the first width at the bottom of the structure proximate to the substrate. The width of the structure along the depth of the silicon may be about 2 μm or more, about 2.5 μm or more, about 3.0 μm or more, about 3.1 μm or more, about 3.2 μm or more, about 3.3 μm or more, about 3.4 μm or more, about 3.5 μm or more, about 3.6 μm or more, about 3.7 μm or more, about 3.8 μm or more, about 3.9 μm or more, about 4.0 μm or more, about 4.5 μm or more, about 5.0 μm or more, or more.

[0028]

[0030] The width distribution may also exist from the top to the bottom, and the bottom width may be greater than or about 1% wider than the top width, greater than or about 2% wider than the top width, greater than the top width or about 3% wider, greater than the top width or about 4% wider, greater than the top width or about 5% wider, greater than the top width or about 6% wider, greater than the top width or about 7% wider, greater than the top width or about 8% wider, greater than the top width or about 9% wider, greater than the top width or about 10% wider, greater than the top width or about 11% wider, greater than the top width or about 12% wider, greater than the top width or about 13% wider, greater than the top width or about 14% wider, greater than the top width or about 15% wider, or more.

[0029]

[0031] A sufficient operating breakdown of a power device may be based on a function of an optimal charge density across a substrate, which may distribute voltage across the device and increase the breakdown voltage of the structure. The charge density may be based on the doping of silicon or other structural materials and the width of the structure being formed. Since the charge density can be fixed for a structure, if the width varies along the depth of the device, the uniformity of the charge density may be limited. This may cause thinner regions to break down earlier and potentially reduce the breakdown voltage of the entire device. However, since the charge density is a function of both doping and device width, this structure can overcome the challenges due to manufacturing complexity by using a doping gradient to correct for differences in width caused by the etching process.

[0030]

[0032] Therefore, by creating a dopant gradient throughout the structure, the inverse width gradient can be corrected to maintain a sufficient charge density. In other words, according to embodiments of the present technique, when the width is large close to the substrate, the dopant level can be lowered, and when the width is large distal to the substrate, the dopant level can be raised. This ensures an improved charge density distribution throughout the device and can improve the breakdown voltage of the device by obtaining a more uniform distribution. Since the etching process can create a linear slope along the silicon layer, a linear increase in dopants can correct the structure. However, it should be understood that any number of dopant adjustments can be made, including varying the amount of dopant incorporation. Thus, in some embodiments, doping can be set to a first level close to the bottom of the silicon layer and linearly increased in relation to the identified linear slope that can be caused by the etching process. The dopant gradient may extend completely along the thickness of the silicon material, from a position close to the semiconductor substrate including the position directly adjacent to the substrate to a position close to the surface opposite to the surface adjacent to the semiconductor substrate. The dopant gradient may also extend through any small portion where the sidewall slope may extend. The dopant incorporation may be at any range of dopant levels and may be a function of the device, material, and dimensions. Thus, it should be understood that a wide range of dopant levels may be encompassed by the present technique.

[0031]

[0033] As one non-limiting example, the structure can be formed to have a thickness of from about 40 μm to about 45 μm, an upper width of about 3 μm, and an increasing width extending towards the substrate, which can be 3.5 μm at the substrate surface. A dopant such as phosphorus or any other dopant material can be incorporated at a concentration of about 8.5e15 cm -3 or less at a position close to the substrate, about 8.4e15 cm -3 or less, about 8.3e15 cm -3 or less, about 8.2e15 cm -3 or less, about 8.1e15 cm -3 or less, about 8.0e15 cm-3 Hereinafter, about 7.9e15 cm -3 Hereinafter, about 7.8e15 cm -3 Hereinafter, about 7.7e15 cm -3 Hereinafter, or at a concentration less than that, it can be incorporated. At a position distal from the substrate including up to the surface of the implantation region, the dopant can be incorporated at a concentration of about 8.5e15 cm -3 or higher, about 8.6e15 cm -3 or higher, about 8.7e15 cm -3 or higher, about 8.8e15 cm -3 or higher, about 8.9e15 cm -3 or higher, about 9.0e15 cm -3 or higher, about 9.1e15 cm -3 or higher, about 9.2e15 cm -3 or higher, about 9.3e15 cm -3 or higher, about 9.4e15 cm -3 or higher, about 9.5e15 cm -3 or at a concentration higher than that, it can be incorporated. To correct the formation of the sloped trench sidewalls, a linear gradient or any other gradient of doping can be generated or extend from the bottom to the top between these incorporation ranges.

[0032]

[0034] In accordance with any number of embodiments of the present technology, including using several optional steps, one or more material layers can be formed along the trench. The layer can be formed within or along the trench, such as on both sides of the silicon structure. For example, in step 220, a first oxide layer 320, which may be a liner, can be formed. The liner layer can be a conformal layer formed over the substrate and each feature. As shown in FIG. 3B, the liner layer 320 can extend along the sidewalls of the silicon layer in the same manner as the substrate 305. The liner can be a charge balance layer and can include any material configured to accommodate the charge of the substrate. As a non-limiting example, the liner layer can be aluminum oxide or any other metal oxide. The thickness of the first oxide can be about 5.0 nm or less, about 4.5 nm or less, about 4.0 nm or less, about 3.5 nm or less, about 3.0 nm or less, about 2.5 nm or less, about 2.0 nm or less, about 1.5 nm or less, about 1.0 nm or less, or less, which can help limit the trench width. As previously explained, fixed charges can be generated along the liner layer and can be consistent along the liner.

[0033]

[0035] Thereafter, in step 225, the trench can be filled, and can be filled with a dielectric material 325 such as silicon dioxide, or any other filler or dielectric material. For manufacturing a power device, subsequent contact formation can be performed in step 230. The contact 330 can be an ohmic contact formed over the implanted region of the P-N junction, or a Schottky contact can be formed. In the case of a Schottky contact, the optional implanted dopant 315 can be excluded, and a metal silicide contact 330 can be formed. The contact can also be characterized by implanted ions such as boron, phosphorus, arsenic, or any other material to generate a barrier height of about 0.60 V or more, and can generate a barrier height of about 0.65 V or more, about 0.70 V or more, about 0.75 V or more, about 0.80 V or more, about 0.85 V or more, or more.

[0034]

[0036] As a result, a charge density of about 1.35e12 cm -2 or more can be characterized, and a charge density of about 1.40e12 cm -2 or more, about 1.45e12 cm -2 or more, about 1.50e12 cm -2 or more, about 1.55e12 cm -2 or more can be characterized, and power devices such as power diodes can be manufactured. As a result, a device characterized by a breakdown voltage of about 650 V can be manufactured, and a device characterized by a breakdown voltage of about 660 V or more, about 670 V or more, about 680 V or more, about 690 V or more, about 700 V or more, about 710 V or more, about 720 V or more, about 730 V or more, or higher can be manufactured. By forming a Schottky contact, the height of the silicon material in which an injection region on the P-N junction can be formed is added, so the voltage may increase by 10 V to 20 V. By manufacturing a device according to an embodiment of the present technology, it is possible to achieve an improvement in device performance while compensating for the complexity of the process. In the conventional technology, since it may be necessary to form a thicker silicon material, it may not be possible to obtain an equivalent breakdown voltage. However, such an approach causes further problems. For example, increasing the epitaxial region requires deeper oxide trench formation, and the etching process may become more difficult. Furthermore, increasing the height of the device increases the series resistance and degrades the performance of the entire device. Therefore, the present technology can manufacture a device superior to the conventional design.

[0035]

[0037] In the previous descriptions, for the purpose of explanation, a number of details have been described so that various embodiments of the present technology can be understood. However, it will be apparent to those skilled in the art that some of these details can be omitted or additional details can be added to implement a particular embodiment.

[0036]

[0038] Although several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents can be used without departing from the spirit of the embodiments. Further, some well-known processes and elements have not been described so as not to unnecessarily obscure the present technology. Accordingly, the above description should not be construed as limiting the scope of the present technology. Further, although a method or process may be described sequentially or stepwise, it should be understood that the steps can be performed simultaneously or in an order different from that recited.

[0037]

[0039] When a range of values is provided, it should be understood that each intervening value, to the minimum part of the unit of the lower limit, between the upper and lower limits of that range is also specifically disclosed, unless the context clearly dictates otherwise. Any narrower range between any of the recited values or unrecited intervening values in the recited range and any other recited value or intervening value in that recited range is also included. The upper and lower limits of these smaller ranges may independently be included in or excluded from the range, and each range in which one or both of the limiting values are included, or neither are included, is also included within the present technology, subject to any specifically excluded limiting value in the recited range. When one or both of the limiting values of the recited range are included, ranges excluding one or both of those included limiting values are also included.

[0038]

[0040] As used in this specification and the appended claims, the singular forms "a", "an", and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, reference to "a trench" includes a plurality of such trenches, reference to "the layer" includes reference to one or more layers well known to those skilled in the art and their equivalents, and the like.

[0039]

[0041] Also, as used in this specification and the following claims, the terms "comprise," "comprising," "contain," "containing," "include," and "including" are intended to specify the presence of the stated features, integers, components, or steps, but do not preclude the presence or addition of one or more other features, integers, components, steps, acts, or groups.

Claims

1. A method of forming a semiconductor structure, comprising: forming a doped silicon layer on a semiconductor substrate, wherein a doping level linearly increases as a distance from the semiconductor substrate increases; etching the doped silicon layer to define a trench extending to the semiconductor substrate, wherein the doped silicon layer defines an inclined sidewall of the trench, and the trench is characterized by a depth of about 30 μm or more; lining the trench with a first oxide material; depositing a second oxide material in the trench; forming a contact for manufacturing a power device .

2. The method of forming a semiconductor structure according to claim 1, wherein after the etching, the doped silicon layer is characterized by a width of about 2 μm to about 5 μm.

3. The method of forming a semiconductor structure according to claim 2, wherein a thickness of the first oxide material lining the trench is about 5 nm or less.

4. further comprising performing an implantation on an exposed surface of the doped silicon layer, wherein the power device includes a P-N junction, the method of forming a semiconductor structure according to claim 1.

5. The method of forming a semiconductor structure according to claim 1, wherein the contact includes a region of metal silicide on the semiconductor structure, the region of metal silicide is characterized by implanted boron, phosphorus, or arsenic ions, and the region of metal silicide is characterized by a barrier height of about 0.6 V or more for forming a Schottky contact.

6. The method of forming a semiconductor structure according to claim 1, wherein the first oxide material includes aluminum oxide and the second oxide material includes silicon oxide.

7. The method of forming a semiconductor structure according to claim 1, wherein the semiconductor substrate includes antimony-doped silicon.

8. The method of forming a semiconductor structure according to claim 1, wherein the inclined sidewall of the trench is characterized by a continuous inclination, and the doped silicon layer is characterized by a linear increase in doping from a position close to the semiconductor substrate to a position close to a surface opposite to a surface adjacent to the semiconductor substrate.

9. ​ The method for forming a semiconductor structure according to claim 1, wherein the semiconductor structure is characterized by a breakdown voltage of about 650 V or more.

10. The dopant of the doped silicon layer contains phosphorus, and the dopant concentration at a position close to the semiconductor substrate is about 8e15 cm －３ or less, and the dopant concentration at a position distal from the semiconductor substrate is about 9e15 cm －３ or more. A method for forming the semiconductor structure according to claim 1.

11. A semiconductor structure comprising: A doped silicon layer formed on a substrate, wherein the doping level in the doped silicon increases linearly as the distance from the substrate increases; and Trenches formed on both sides of the doped silicon layer, the trenches including a liner of a first oxide material and a filler of a second oxide material, and characterized by slanted sidewalls; and Contacts A semiconductor structure comprising.

12. The dopant of the doped silicon layer contains phosphorus, and the dopant concentration at a position close to the substrate is about 8e15 cm －３ or less, and the dopant concentration at a position distal from the substrate is about 9e15 cm －３ or more. The semiconductor structure according to claim 11.

13. The semiconductor structure according to claim 11, wherein the slanted sidewalls of the trenches are characterized by a continuous slope, and the doped silicon layer is characterized by a linear increase in doping from a position close to the substrate to a position close to the surface opposite to the surface adjacent to the substrate.

14. The semiconductor structure according to claim 11, wherein the substrate includes antimony-doped silicon, the first oxide material includes aluminum oxide, and the second oxide material includes silicon oxide.

15. The semiconductor structure according to claim 11, wherein an exposed surface of the semiconductor structure includes a boron implant to form a P-N junction of the semiconductor structure.

16. The semiconductor structure according to claim 11, wherein the contact includes a metal silicide region, the metal silicide region is characterized by implanted boron, phosphorus, or arsenic ions, and the metal silicide region is characterized by a barrier height of about 0.6 V or more for forming a Schottky contact.

17. A method for forming a semiconductor structure, the method comprising: Forming a doped silicon layer on a semiconductor substrate, wherein dopants are included with a gradient such that the dopant concentration increases as the distance from the semiconductor substrate increases. Etching the doped silicon layer to define a trench that extends to the semiconductor substrate, wherein the doped silicon layer defines the sloped sidewalls of the trench, the trench is characterized by a depth of about 30 μm or more, and the doped silicon layer is characterized by a width of from about 2 μm to about 5 μm, etching the doped silicon layer; Lining the trench with a first oxide material characterized by a thickness of about 5 nm or less; Depositing a second oxide material in the trench; Forming a contact for manufacturing a power device; A method comprising.

18. The method of forming a semiconductor structure according to claim 17, wherein the semiconductor substrate includes antimony-doped silicon, the first oxide material includes aluminum oxide, and the second oxide material includes silicon oxide.

19. Further comprising performing implantation on the exposed surface of the doped silicon layer, wherein the power device includes a P-N junction, the method of forming a semiconductor structure according to claim 17.

20. Further comprising forming a region of metal silicide on the semiconductor structure, wherein the region of metal silicide is characterized by implanted boron, phosphorus, or arsenic ions, and the region of metal silicide is characterized by a barrier height of about 0.6 V or more for forming a Schottky contact, the method of forming a semiconductor structure according to claim 17. ​ ​

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