On-chip heater temperature calibration

Abstract

Systems, methods, and circuitry are provided for calibrating a heater (225) used to heat an adjustable resistive network (224) during a trimming procedure. In one example, a circuit is provided that includes an adjustable resistive network including a first resistive segment (R8-R17), a heater element (225) thermally coupled to the adjustable resistive network (224), a calibration resistor (R13) including a second resistive segment thermally coupled to the first resistive segment (R8-R17), and interface circuitry (275, 276) coupled to the calibration resistor.

Description

Background Art

[0001] Integrated circuits (ICs), particularly analog integrated circuits, rely on precise and temperature-stable voltage sources and / or current sources. Conventionally, extremely precise voltage sources have been able to be fabricated, for example, by using bandgap circuit elements or buried zener circuit elements. It is desirable to generate a current source that exhibits both process stability and temperature stability.

Summary of the Invention

[0002] In one example, a circuit is provided that includes an adjustable resistance network including a first resistance segment, a heater element thermally coupled to the adjustable resistance network, a calibration resistor including a second resistance segment thermally coupled to the first resistance segment, and an interface circuit element coupled to the calibration resistor.

[0003] In one example, a system is provided that includes an adjustable resistance network, a calibration resistor thermally coupled to the adjustable resistance network, an interface circuit element coupled to the calibration resistor, and a heater thermally coupled to the adjustable resistance network. The system includes a processor coupled to the heater and the interface circuit, and the processor retrieves a calibration value from non-volatile memory, generates a power control signal to apply a power pulse to the heater, measures the resistance value of the calibration resistor using the interface circuit element, and adjusts the power control signal to change the voltage level or duration of the power pulse based on a comparison between the calibration value and a value based on the measured resistance value.

[0004] In one example, a method is provided that includes using a processor to command a power source to provide a power pulse to a heater, measuring the resistance value of a calibration resistor thermally coupled to an adjustable resistance network, reading a calibration value for the calibration resistor, and adjusting the power pulse based on a comparison between the calibration value and a value based on the measured resistance value.

Brief Description of the Drawings

[0005] Some examples of circuits, devices, and / or methods are described below by way of example only. In this context, refer to the accompanying figures.

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DETAILED DESCRIPTION OF THE INVENTION

[0019] The drawings may not be drawn to scale.

[0020] Resistive components used in integrated circuit (IC) processing often have a very large (e.g., on the order of 1000 ppm / °C as measured) temperature coefficient of resistance (TCR) and a large process tolerance (e.g., ±30%). To compensate for such variations, an IC device that is required to generate a precisely controlled current may include an adjustable resistance network that can be adjusted for each IC to provide a temperature coefficient that is zero or near zero over the operating temperature range. An adjustable resistance network includes one or more resistors having a positive temperature coefficient (hereinafter RP) and one or more resistors having a negative temperature coefficient (hereinafter RN) connected together. As will be described in more detail below, an adjustable resistance network is adjusted or trimmed by selectively shorting, opening, or otherwise isolating one or more of these resistors to provide a desired resistance at one particular temperature and to reduce the variation of this resistance over a certain operating temperature range, resulting in an adjustable resistance network.

[0021] FIG. 1 illustrates a block diagram of an exemplary current source circuit element 100 that provides a high-precision on-chip bias current IBIAS. The current source circuit element 100 includes a differential amplifier 118, a transistor 119, an adjustable resistor network 124, a heating element 125, an adjustable voltage source 114, and a bonding pad 108. In operation, the adjustable voltage source 114 provides a voltage having a lower temperature coefficient than the temperature coefficient of the adjustable resistor network 124 after a trimming operation. The voltage output by the adjustable voltage source 114 is input to the differential amplifier 118, and the differential amplifier 118 adjusts the gate voltage of the transistor 119 such that the voltage across the adjustable resistor network 124 tends toward the voltage generated by the adjustable voltage source 114. Thus, the voltage generated by the adjustable voltage source 114 does not significantly affect the output current of the current source circuit element. Also, the current flowing through the adjustable resistor network 124 flows from the drain of the transistor 119 to the source of the transistor 119. The current flowing into the drain of the transistor 119 becomes the current IBIAS generated by the current source circuit element 100. The heater element 125 receives a voltage applied to the bonding pad 108 of the integrated circuit. By applying a voltage to the bonding pad 108, the heater element 125 heats the adjustable resistor network 124. As described below, this heating technique enables measurement of the temperature coefficient, and based on this information, the adjustable resistor network 124 can be appropriately adjusted.

[0022] FIG. 2 shows, more particularly, an exemplary current source 200 that includes an adjustable resistance network 224. The current source 200 also includes an adjustable voltage source 214 (which is shown in more detail), an amplifier 202, an NMOS transistor 203, and a heater element 225. The adjustable voltage source 214 operates to provide the voltage shown at node 201 to the amplifier 202. By making the voltage at node 201 adjustable rather than fixed, means are provided for compensating for process variations in the resistance values of the adjustable resistance network used to generate the bias current. The adjustment of the adjustable voltage source 214 is performed independently of the trim process for adjusting the temperature coefficient of the bias current. The voltage at node 201 is typically set after the temperature coefficient has been adjusted. The adjustable voltage source 214 includes reference resistors R1 - R7 coupled in series with each other between a fixed temperature - invariant reference voltage (shown as V1) and ground. NMOS transistors Q4 - Q7 are coupled across resistors R3 - R6, respectively. Also, an inverter 215 is coupled to the gate of transistor Q4.

[0023] The voltage at node 201 is changed or adjusted based on the states of digital control signals IREF0 - IREF3. These control signals are generated by a digital non - volatile memory (NVM) 262. The value programmed in NVM262 determines which of resistors R3 - R6 are short - circuited and which are not. Assume that the resistance values of R3 - R6 are binary - weighted such that R3 is the largest. Thus, IREF3 is the most significant bit of the digital control word IREF0 - 3. In other examples, the relative resistance values of R3 - R6 may have different weightings. The inverter 215 is used such that the voltage at node 201 generated when NVM262 has not yet been programmed (IREF0 - 3 are all low) is located approximately in the center of the range of voltages that can be generated by the adjustable voltage source 214. This simplifies the laboratory testing of the current source 200. A capacitor 213 is connected to the output of the adjustable voltage source 214 to provide noise filtering.

[0024] The adjustable resistance network 224 provides the resistance value required to convert the voltage generated by the adjustable voltage source 214 into a current. The amplifier 202 confines the voltage across the adjustable resistance network 224 within a predetermined equivalent range (based on the tolerance of the amplifier 202) of the voltage at node 201. The adjustable resistance network 224 includes resistors R8 - R17 and is thermally coupled to the heater element 225 and an optional (groundable) Faraday shield 212. The resistors R8 - R17 are described as being connected in series, although in other examples these resistors may be arranged in parallel or series-parallel. The adjustable resistance network is arranged in several trim sets coupled in series with each other. Each trim set includes a pair of trim resistors coupled in series with each other, R9~R10, R11~R12, R13~R14, and R15~R16. Pairs of NMOS trim transistors, Q8~Q9, Q10~Q11, Q12~Q13, and Q14~Q15 are associated with each pair of trim resistors such that one NMOS transistor is coupled across one of the resistors R9~R16. Inverters 204, 208, 210, and 212 each invert one of the TC0~3 inputs. Also, the gate of transistor Q9 and inverter 204 are coupled to inverter 206.

[0025] In operation, trim signals TC0 to TC3 are provided by the NVM261 to the NMOS transistors Q8 to Q15 to control the temperature coefficient of the adjustable resistance network 224. Also, the resistors R9, R11, R13, and R15 are made of a first material (e.g., a material having a positive temperature coefficient RP), and the resistors R10, R12, R14, and R16 are made of a second material (e.g., a material having a negative temperature coefficient RN). The resistors in a given pair (R9 - R10, R11 - R12, R13 - R14, or R15 - R16) are selected to have the same nominal resistance value at a test temperature (e.g., 25°C). Thus, regardless of the values of TC0 to 3, the total resistance value of the series of resistors R8 to R17 remains approximately the same. Although differences occur between these resistors due to process variations, means are provided to trim and remove this error after the temperature coefficient is set by programming the NVM261 that controls TC0 to 3, by virtue of the presence of the adjustable voltage source 214.

[0026] The resistors controlled by TC0 to 3 are binary weighted, with resistors R9 and R10 being the largest. Thus, the resistance value of resistor R9 is equal to twice the resistance value of resistor R11, the resistance value of resistor R11 is equal to four times the resistance value of resistor R13, and the resistance value of resistor R13 is equal to eight times the resistance value of resistor R15. Also, the resistance value of resistor R10 is equal to twice the resistance value of resistor R12, the resistance value of resistor R12 is equal to four times the resistance value of resistor R14, and the resistance value of resistor R14 is equal to eight times the resistance value of resistor R16. The resistance value of resistor R9 is approximately equal to the resistance value of resistor R10, the resistance value of resistor R11 is approximately equal to the resistance value of resistor R12, the resistance value of resistor R13 is approximately equal to the resistance value of resistor R14, and the resistance value of resistor R15 is approximately equal to the resistance value of resistor R16.

[0027] An example of how one of the control signals, TC0, functions is as follows. When the TC0 signal is low, the resistor R16 is not shorted by Q15, and the resistor R16 is added to the resistor network 224 that can adjust the temperature coefficient term of the first polarity. When the TC0 signal is high, the resistor R15 is not shorted by Q14, and the resistor R15 is added to the resistor network 224 that can adjust the temperature coefficient term of the second polarity. TC1 and TC2 behave in the same manner as TC0. When TC3 is low, the resistor R9 adds the temperature coefficient term of the second polarity, and when TC3 is high, the resistor R10 adds the temperature coefficient term of the first polarity. Due to the inversion of the polarity of TC3 with respect to TC0~2 caused by the insertion of the inverter 206, when the NVM261 is not programmed and TC0~3 are all low, the temperature coefficient of the series-connected resistors R8~R17 is located approximately in the middle of the possible value range. This simplifies the laboratory test. The resistors R8 and R17 can be made of either the first material type (e.g., a material having a positive temperature coefficient RP) or the second material type (e.g., a material having a negative temperature coefficient RN). For the nominal values of the resistance and the temperature coefficient, the material type and size settings of the resistors R8 and R17 with respect to the resistors R9~R16 are selected such that the total series resistance value of the series-connected resistors R8~R17 exhibits a zero temperature coefficient.

[0028] In addition to the specific resistive materials and nominal resistance values of the adjustable resistor network, the physical layout of the resistors of the adjustable resistor network on the integrated circuit is appropriate to achieve zero or low temperature coefficients without introducing undesirable thermal sensitivity. FIG. 3 illustrates a top view of an exemplary layout of an adjustable resistor network 324, and FIG. 4 shows a cross-section of the integrated circuit along the cross-section line A-A in FIG. 3. Examining the cross-section of FIG. 4, the resistors are present on the semiconductor wafer 406. An insulating layer 405 of a deposited or grown insulating material such as silicon dioxide is formed on top of the semiconductor wafer 406 during fabrication. A layer of a resistive thin film material 424 such as doped polysilicon is deposited and patterned on top of the insulating layer 405 to create an array of physical resistive segments made from a resistive material of substantially uniform thickness. The members of the array of physical resistive segments formed by the resistive thin film material function as calibration resistive segments 311 and an adjustable resistor network 324.

[0029] There are several ways to form an array of physical resistive segments. In one example, a resistive thin film material is deposited, a photoresist is spin-coated, the photoresist is patterned with openings, the material within the openings is etched away, and then the photoresist is removed. In another example, a molecular beam or an ion beam is scanned to selectively deposit (if at a low speed) the resistive material. In another example, the resistive material is selectively deposited through a shadow mask. In yet another example, a photoresist is spin-coated, holes are opened in the photoresist where the resistive material is desired, the resistive material is deposited over the entire area, and the resistive material that did not enter the holes of the patterned array is removed by a process for lift-off of the photoresist.

[0030] Segment 311 of the calibration resistor is shown in FIGS. 3 and 4 as being in the same layer as the other segments of the adjustable resistor network, although other arrangements are possible. For example, the segments of the calibration resistor and the segments of the adjustable resistor network can be arranged between three adjacent or proximate layers of the IC. Adjacent or proximate layers mean layers that exhibit similar average temperatures during the trimming process. The segments of the calibration resistor can be arranged in the first and third layers, and the segments of the adjustable resistor network can be arranged in the second layer. As long as the average temperatures of the first and third layers are similar to the temperature of the second layer, the calibration resistor provides a good proxy for representing the temperature of the adjustable resistor network.

[0031] A second layer of insulating material 407 (such as silicon dioxide) is deposited on top of the resistive thin film material 424 and planarized. Then, openings are etched through the second layer of insulating material 407 to form contacts 413 to the resistive thin film material. These contacts 413 can be deposited together with the first metallization layer 412 or, in a second process, deposited on the surface of the second layer of insulating material 407 and polished to the surface, in which case the contacts 413 can be made from a different conductive material (such as tungsten).

[0032] Next, a first metallization layer 412, such as aluminum or an aluminum alloy, is formed by evaporation or sputtering and then patterned and etched. A third insulating layer 408 (such as silicon dioxide) is deposited on top of the first metallization layer 412 and then planarized. Although not shown in FIG. 4, vias can be formed through the third insulating layer. Next, a second metallization layer 425, such as aluminum or an aluminum alloy, is deposited and patterned. A fourth insulating layer 409 (such as silicon dioxide) is deposited on top of the second metallization layer and then planarized. Vias 417 are patterned and etched through the fourth insulating layer 409. The conductive material filling these vias can be the third metal 416 or another conductive material (such as tungsten) deposited and polished on the surface of the fourth insulating layer 409.

[0033] Next, a third metallization layer 416, such as aluminum or an aluminum alloy, is deposited and patterned. Finally, a fifth insulating layer 411 is deposited on the third metallization layer 416. This process completes the fabrication of the semiconductor wafer 406. In the above description, metallization with aluminum or an aluminum alloy is assumed, but using fabrication techniques based on single or dual damascene processing, metallization with copper or a copper alloy can be fabricated without substantially changing the final cross-section shown in FIG. 4.

[0034] FIG. 3 shows a top view of the layout of an exemplary adjustable resistance network 324 and a serpentine metal line 325 forming a resistive element of a heater. The adjustable resistance network 324 includes a plurality of resistance segments (hereinafter “segments”) 302, 304. Segment 302 is made of a first resistive material and segment 304 is made of a second resistive material. In an actual implementation of the resistance network, there may be more segments of each type than shown in this simplified example. In this example, the first resistive material has a small negative temperature coefficient and the second resistive material has a larger positive temperature coefficient. However, in other examples, the first resistive material has a large negative temperature coefficient and the second resistive material has a smaller positive temperature coefficient. In any given process, the relative magnitudes of the two temperature coefficients depend on the composition of the two resistive materials. In other words, the positive temperature coefficient material may have a temperature coefficient that is smaller than, equal to, or larger than the absolute value of the temperature coefficient of the negative temperature coefficient material. The relative numbers of segments 302, 304 are selected such that an overall zero or nearly zero temperature coefficient can be achieved after trimming.

[0035] In the cross-section of FIG. 4, the serpentine metal resistor used as a heater is constructed on the second metallization layer 426. The metal plate on the third metallization layer 416 (shown in FIG. 4 but not in FIG. 3) helps improve the lateral thermal conductivity and thus functions as a heat spreader. Since the metal has a much higher thermal conductivity than most of the insulating materials used in integrated circuits such as silicon dioxide, the heat spreader improves the lateral thermal conductivity across the entire array of resistor segments. The heat spreader has important value because, although the longitudinal dimension of the resistor segment array is much smaller than the lateral dimension, a large longitudinal heat flow to the substrate still occurs because the insulating material has poor thermal conductivity. One or more of the heat spreaders can also be connected to ground or another low-impedance circuit node to reduce capacitive coupling between the resistor and other circuit components such as the heater. Such a capacitive shielding structure is sometimes called a Faraday shield. The Faraday shield constructed on the first metallization layer 412 also serves as a heat spreader itself. In a process with only one metallization layer, the Faraday shield and the heat spreader may be omitted, and the heater can be constructed on the only first metallization layer. With a process using multiple metallization layers, the metal layer for constructing the heater can be selected, and a Faraday shield and one or more heat spreader layers for reducing noise coupling between the segment and the heater can be included.

[0036] The examples of FIGS. 3 and 4 assume that both resistive materials are doped polysilicon, but alternatively, one or both of the resistive materials may include alternative thin film materials deposited under, between, or on top of the first metallization layer. Polysilicon resistors may have a poor TCR and a narrow absolute thickness tolerance, but the doping level of the polysilicon resistor can be constructed and arranged to produce a material having either a negative or a positive temperature coefficient. In additional examples, polysilicon is selectively silicided to reduce the MOS gate resistance value and improve the contact resistance value. This is because the silicided polysilicon exhibits a large positive temperature coefficient. The polysilicon resistor changes approximately linearly with temperature, and the silicide changes approximately linearly with temperature.

[0037] As an example, one of the resistive materials in the adjustable resistive network 324 (e.g., the first resistive material of segment 302) is a high sheet resistance (HSR) polysilicon resistor, and the other resistive material in the adjustable resistive network 324 (e.g., the second resistive material of segment 304) is a low sheet resistance (LSR) polysilicon resistor. The LSR polysilicon resistor segment 304 and the HSR polysilicon resistor segment 302 have the same or substantially the same thermal properties such as thickness, density, specific heat, and thermal conductivity, but have a positive TCR and a negative TCR, respectively. For example, when the illustrated LSR polysilicon resistor segment 304 is heated, its resistance value increases uniformly or linearly at about +800 ppm / °C. In contrast, when the HSR polysilicon resistor segment 302 is heated, the resistance value decreases uniformly or linearly at about -400 ppm / °C. In the trimming process, the combination of the positive TCR, LSR polysilicon resistor segment 304 and the negative TCR, HSR polysilicon resistor segment 302 in the adjustable resistive network 324 is adjusted to provide an overall network temperature coefficient of zero or close to zero for the resistance value. Also, the resistor segment 302 and the resistor segment 304 can be advantageously constructed and arranged to reduce the influence of external thermal gradient effects, for example, by using a common centroid layout.

[0038] The trimming process begins with measuring the combined resistance value of the resistor network at the temperature of the test facility, hereinafter referred to as "room temperature". This temperature may be measured by equipment external to the integrated circuit or may rely on air conditioning to maintain a nominal temperature of, for example, 25°C. Next, the power supply is controlled to provide a predetermined power pulse at a predetermined voltage level applied to the heater for a predetermined time period, and the voltage and time are selected such that the temperature of the resistor network rises to a desired value. Then a second measurement of the resistance value is made. Appropriate times and temperatures can be determined by laboratory measurement of the sample device in a suitable heating chamber or system. Subsequently, after operating the heater at various voltages over various durations, the heater voltage and duration that should result in the desired temperature are selected by comparing the resistance values at the temperature of the same sample. However, the performance of the samples used for characterization may not exactly match the performance of the actual production units, and the factors for this are addressed by the circuit elements, systems, and methods described herein.

[0039] By disposing a resistive heater element in a second metallization layer 425 immediately above (or below) a layer of resistive thin film material 424 that forms an adjustable resistive network, better thermal coupling is promoted and the heating element is confined to a small portion of the overall circuit area, whereby only the adjustable resistive network is heated. The very close thermal coupling reduces the thermal gradient across both the negative TCR portion (including segment 302) and the positive TCR portion (including segment 304) of the adjustable resistive network. Also, the thermal coupling results in a fast primary thermal response time constant in the range of about 20 to about 50 microseconds (μs). As a result, the settling time is less than about 100 μs and does not significantly affect the test and trimming times. In one example, when the resistive heater element in the second metallization layer 425 is energized, the local temperature of the adjustable resistive network in the layer of resistive thin film material 424 is about 30 to 60 °C higher than the average temperature of the bulk silicon substrate or die. While the adjustable resistive network 120 is being heated, the average temperature of the bulk silicon substrate or die remains relatively constant throughout the energization phase.

[0040] Alternatively, the resistive heater element can be rapidly energized, for example, by utilizing a voltage jump from 0 V to a second voltage that is, in one example, about 48 V, thereby generating a heat pulse. By energizing the resistive heater element, the temperature (ΔT) of the resistive segments 302 and 304 of the adjustable resistive network 324, for example about 40 °C, changes rapidly. This temperature can be set by the pulse voltage level. Thus, ΔT can affect the trimming process more than the absolute temperature. This is because a repeatable temperature look-ahead signal can be provided, whereby the combination of the first resistive segment 302 and the second resistive segment 304 can be adjusted to achieve a zero or near-zero TCR.

[0041] Returning to FIG. 2, a trim controller 260 (e.g., a 4-bit controller such as a processor, a current splitter, a current miner, etc.) interfaces with an adjustable resistor network 224 adjustable on lines TC0-3 and a voltage source 214 adjustable on lines IREF0-3. Although four lines TC0-3 and four lines IREF0-3 are illustrated, the number of lines for the TC and IREF control signals may be different, and a number other than four may be selected according to the desired trim resolution. For each of lines IREF0-3 and TC0-3, the trim controller 260 places a constant voltage representing either a logic high or 1, or a logic low or 0. Thus, the values IREF0-3 can be represented as one digital word, and the values TC0-3 can be represented as a second digital word. The trim controller 260 may be entirely integrated on the IC, or only a part of the controller may be integrated, and the rest may be implemented in external test hardware. In any case, the trim controller calculates the values to place on TC0-3 to provide the lowest possible TCR and stores these calculated values in a non-volatile memory (NVM) 261 that forms part of the trim controller 260 placed on the integrated circuit. Also, the trim controller 260 calculates the values to place on IREF0-3 to set a total resistance value as close as possible to the desired value and stores these calculated values in an NVM 262 that forms part of the trim controller 260 placed on the integrated circuit. Thereafter, when power is applied, the integrated part of the trim controller can retrieve these values from NVM 261 and NVM 262 and apply these values to IREF0-3 and TC0-3, thereby trimming the adjustable resistor network to the appropriate value and minimum temperature coefficient. In other examples, the values of IFEF0-3 and TC0-3 can be stored in the same NVM. In other examples, NVM 261 and / or NVM 262 may not be part of the trim controller 260 and may be located elsewhere on the integrated circuit.

[0042] In a simple trimming algorithm, the trim controller 260 applies default values of TC0 to 3 that can reduce temperature variations when both the resistivity and the temperature coefficient of the two resistive materials are equal to predetermined nominal values. Next, the trim controller measures the resistance value of the adjustable resistance network 224 before and after the heater element 225 is energized. Using these data and the process minimum values of the resistivity and the temperature coefficient, the trim controller can change the overall TCR of the adjustable resistance network 224 by changing the value of the digital word represented by TC0 to 3, thereby changing the number of the first resistive material segments 302 and the number of the second resistive material segments 304 of the adjustable resistance network 224.

[0043] The voltage level and the duration of a predetermined power pulse applied to the heater element 225 are two factors that control the amount of heating generated in the adjustable resistance network 224 during the trimming process. The voltage level and the duration of the power pulse are determined during the initial characterization of the IC device as described above. However, the packaging of the IC may also affect the amount of heating of the adjustable resistance network. For example, different packages include substrates of different thicknesses, so the heat capacity of the substrate changes. In another example, the mold compound used to encapsulate a plastic-packaged integrated circuit may be changed. In a third example, the device may be placed in different types of packages, such as a hermetically sealed metal container or a chip-scale package with only a minimal thickness of insulating film applied to the surface of the integrated circuit. Therefore, when the IC is installed in a packaging configuration different from that used in the initial test, or when any other test parameters change, simply applying the same voltage pulse may not result in the same change in the temperature of the adjustable resistance network.

[0044] In particular, consider the case where the temperature-sensitive component is a polysilicon (poly) resistor. Since polysilicon changes only approximately linearly with temperature, a more accurate model of its behavior involves not just a single (linear) temperature coefficient calculated by linear least squares regression, but both a linear temperature coefficient and a quadratic temperature coefficient calculated by quadratic least squares regression from the measurement data. The following applies when the poly resistor is characterized by both linear and quadratic temperature coefficients. Assume a process by which poly resistors with positive and negative linear temperature coefficients (RP and RN, respectively) can be fabricated. By appropriately selecting the values of RP and RN and connecting them in series, parallel, or series-parallel, the linear temperature coefficient of the entire adjustable resistance network can be made approximately zero. Since both the values and temperature coefficients of RP and RN exhibit process variations, the temperature coefficient of the resistance network varies according to the process. Also, the quadratic temperature coefficients of RP and RN will almost certainly not cancel each other out.

[0045] An on-chip heater can be used to measure the residual temperature coefficient and adjust the values of RP and RN in an adjustable resistance network, thereby reducing the overall variation caused by the remaining linear and quadratic coefficients of the combined adjustable resistance network. This represents a significant improvement over the simplest possible trim algorithm that assumes process nominal values for sheet resistance and temperature coefficient in order to extrapolate trim codes based on measured values at room temperature and high temperature. Regardless of the nature of the IC packaging, it is desirable for a known and repeatable temperature rise to occur when the heater is operating in order to obtain information for reducing the residual quadratic component of the temperature coefficient of the adjustable resistance value network. This can be achieved at least approximately by using a selected resistance segment having only either a positive or negative temperature coefficient as a temperature-variable calibration resistor. In one example, the calibration resistor is electrically coupled to the adjustable resistance network. In other examples, the calibration resistor is not electrically coupled to the adjustable resistance network but is thermally coupled to the adjustable resistance network. It is advantageous to select a resistance segment made of a material having a larger temperature coefficient and a smaller process variation of the temperature coefficient as the calibration resistor. An estimated high temperature value can be obtained by measuring the resistance value of the calibration resistor at both room temperature and the high temperature resulting from the operation of the heater.

[0046] Figure 5 illustrates the resistance value of a certain silicided polyresistor as a function of temperature. The silicide is a stoichiometric compound of silicon and some other element, such as titanium, cobalt, and nickel. Since the silicide is a definite compound, it has relatively stable material properties. Also, since the silicide is essentially metallic, it has a relatively large positive linear temperature coefficient (TCL) (e.g., 2000 - 4000 ppm / °C). Also, the polyresistor has a very small quadratic temperature coefficient (TCQ) (e.g., 1 ppm / °C 2It may have (less than). Due to these characteristics, silicide is ideal for constructing integrated calibration resistors integrated into a polysilicon resistor array (e.g., an adjustable resistance network). These same calibration resistors can function as the positive segment (or negative segment) of an adjustable resistance network.

[0047] Line 505 in Figure 5 shows the nominal behavior of a particular silicided polysilicon, expressed as the normalized value R / R0. Here, R is the resistance value at some temperature, R0 is the resistance value at room temperature, and room temperature is assumed to be 25°C. 1 ppm / °C 2 Due to the material having a secondary temperature coefficient of less than, the relationship between the resistance value and temperature is approximately linear. The gray triangle 510 formed by the dashed line represents the limit of process variation. The small size of the triangle 510 illustrates that this resistor can be used as a fairly accurate temperature sensor even without knowing the exact temperature coefficient of this resistor. Since the process variation of the nominal resistance value is relatively small and the calibration resistor has almost perfect linearity, temperature extrapolation is possible. Therefore, to characterize the resistance value of the calibration resistor over the operating temperature range (e.g., -40°C to 150°C), it is sufficient to measure the resistance values at two temperatures (e.g., 25°C and 85°C).

[0048] However, doped polysilicon exhibits somewhat greater non-linearity than silicided poly, and since most of the linear temperature coefficient (TCL) is canceled out by trimming, the quadratic temperature coefficient (TCQ) (also called the parabolic temperature coefficient or the quadratic temperature coefficient) forms an important component of the ultimately trimmed resistance value of the resistor device, as illustrated by line 605 in FIG. 6. Since the TCR of the adjustable resistance network is of a parabolic nature, the trimming process should be performed at an accurate temperature. FIG. 7 illustrates the case where the adjustable resistance network is trimmed at the actual temperature of 100° C. rather than the intended temperature of 85° C. (as indicated by line 705). The extrapolation of the normalized resistance values based on these two cases is clearly different, as suggested by the dotted and dashed lines. This inaccurate temperature can be the result of a voltage pulse calibrated based on different packaging arrangements of the same IC being supplied to the on-chip resistance heater.

[0049] One way to calculate the temperature coefficient of an adjustable resistance network depends on observations regarding the nature of non-linear temperature variations. Here, referring to FIG. 8, assume that the temperature T mid is defined as T mid =(T min +T max ) / 2. Here, T min and T max are the minimum and maximum operating temperatures, respectively. The function of the resistance value with respect to temperature can be expanded in a Taylor series about T mid . In most cases, it is observed that the cubic and all higher-order terms affect the resistance value to a much smaller extent than the quadratic term. Assuming that the linear term is canceled out and only the constant and quadratic terms remain as large contributions to the resistance value, the resistance-versus-temperature function (the function indicated by line 805) is symmetric about T mid . This shift of the resistance-versus-temperature function is illustrated by line 905 in FIG. 9. Here, when measuring the resistance value at room temperature T nom and at a temperature T mid that is as much higher than T nom as T heated is higher than T heated =2·Tmid -T nom ) When the line components are properly canceled out, T heated The resistance value at nom should be equal to the resistance value at heated If the resistance value at nom is greater than the resistance value at heated the positive linear temperature coefficient remains, and nom if the resistance value at TIFF0007709254000001.tif651

[0050] When the temperature is measured in degrees Celsius, TCL has the unit of ppm / °C. The trimming of the temperature coefficient can be set based on the knowledge of the weight of each bit and the value of the linear temperature coefficient calculated as described above. As an example of this procedure, as shown in FIGS. 8 to 9, min = -40 °C, and max assuming mid = 125 °C. Then, nom When heated = 25 °C,

[0051] heated = 60 °C. When the linear temperature coefficient is properly canceled out, R(25 °C) should be equal to R(60 °C). Measure the actual resistance values at these two temperatures and assume R(25 °C) = 101.6 kΩ and R(60 °C) = 102.2 kΩ. Then, the linear temperature coefficient is equal to TCL = 169 ppm / °C.Referring again to FIG. 3, to address this potential variation in the thermal response of the adjustable resistance network and the resulting trimming process that does not reach the optimal state, a calibration resistor segment 311 that is very sensitive to temperature is placed in very close proximity to the adjustable resistance network so that the calibration resistor segment 311 is thermally coupled to the adjustable resistance network 324. As used herein, "thermally coupled" means that the calibration resistor segment 311 is in close thermal contact with the adjustable resistance network or is close enough to exhibit a very similar thermal or temperature response compared to the adjustable resistance network. The segments of the calibration resistor can be distributed as evenly as possible across the adjustable resistance network. The calibration resistor and the adjustable resistance network are not used simultaneously, so that one or more segments of the adjustable resistance network can be selectively connected to act as the calibration resistor.

[0052] For example, the resistance segments 311 of the calibration resistor can be interdigitated with the remaining segments of the adjustable resistance network. Interdigitated means that the segments of the calibration resistor are in the same integrated circuit layer as the segments of the adjustable resistance network and are interspersed among the segments of the adjustable resistance network.

[0053] Interlocking is a type of common centroid layout. The centroid of a two-dimensional shape (e.g., an integrated device) is equal to the geometric mean of the locations of all points within that shape. An easy way to find the centroid is to apply the principle of centroid symmetry, which states that the centroid of a shape lies on any axis of symmetry passing through it. A rectangle is bisected by its vertical and horizontal axes of symmetry, and the centroid is at their intersection. The concept of common centroid layout is that the effect of a static spatial temperature gradient on two matching devices is proportional to the separation between their centroids. Therefore, if the centroid separation between devices is reduced to zero, the effect of the (linear) temperature gradient on the matching is canceled out. For example, in an adjustable resistor array, each device may include two separate rectangular regions (e.g., resistor segments), such as two of the rectangular regions belonging to resistor A and two of the rectangular regions belonging to resistor B. When these segments are arranged in the order ABBA, the centroid of the two A segments is in the middle between them (another example of the application of the principle of centroid symmetry). Similarly, the centroid of the two B segments is in the middle between them. Therefore, these two centroids are aligned, and the device is arranged in a common centroid array. This type of common centroid array is called interlocking because the segments slide between each other like two interlocked fingers.

[0054] In this example, the calibration resistor segment 311 includes four RP segments 304 of an adjustable resistor network 324. In other examples, the calibration resistor can be electrically separated from the adjustable resistor network 324 but can have segments that interfit with the adjustable resistor network 324. The calibration resistor can be a selected plurality of the RN segments or a selected plurality of the RP segments, and either type (RN or RP) can have a relatively large linear temperature coefficient. The relative variation in the temperature coefficient of the selected segments over the process is much smaller than the relative variation of the combined adjustable resistor network. This is because the combined resistor network incorporates both RP and RN segments in an attempt to lower the overall temperature coefficient of the adjustable resistor network. RP and RN are typically interfit for matching purposes, resulting in close thermal contact and also reducing the effect of lateral thermal gradients generated by other components on the integrated circuit during normal operation.

[0055] Returning to FIG. 2, the interface circuit element provides one or more electrical connections that enable measurement of the resistance value of the calibration resistor. In the illustrated example, the interface circuit element includes bonding pads 275 and NMOS transistors 276, 277 such that the resistance value of the calibration resistor can be directly measured by an external ohmmeter or other resistance measurement device. The conductive pad or bonding pad 275 enables connection by wire bonding (or probe needles in the case of testing with a probe) to the top of resistor R13, which is the calibration resistor including segment 311 of FIG. 3. The NMOS transistors 276, 277, when actuated, electrically isolate the calibration resistor from the adjustable resistor network, enabling measurement of the resistance value of the calibration resistor.

[0056] The NMOS transistor 276, also referred to as the calibration switch, grounds the low side of the resistor R13 when performing a calibration measurement. The calibration measurement process is triggered by applying a calibration signal including a constant voltage representing a logical high or 1 to the calibration trigger input C at the gate of the NMOS transistor 276. In an alternative example, for the measurement of the calibration resistor, a different type of switch may be used with a logical low or zero. In response to the pause signal (which is also the calibration signal C in the example of FIG. 2), the NMOS transistor 277, also referred to as the current source pause switch, disables the NMOS transistor 203 from the amplifier 202, so that no current flows from IBIAS to the bonding pad 275 during calibration. Thus, only the current flowing from IBIAS to the bonding pad 275 during calibration is the current flowing from the bonding pad 275 to ground (through the calibration resistor R13).

[0057] The calibration resistance value of the calibration resistor measured using the interface circuit element serves as a proxy representing the temperature of the calibration resistor and the temperature of the adjustable resistor network due to being thermally proximate. Thus, by measuring the calibration resistance value, it can be confirmed that the adjustable resistor network is heated to the desired temperature during trimming.

[0058] The exemplary heater calibration system 270 includes a processor 272 and an ohmmeter 271 (or other circuitry for measuring resistance values) connectable to bonding pad 275. In one example, the heater calibration system 270 is implemented as circuit elements external to the IC. In another example, the heater calibration system 270 is implemented as circuit elements disposed within the IC. During the calibration process, the processor 272 generates a power supply (PS) control signal to control an external power source to provide a predetermined power pulse (PP) to input V3 for the heater during trimming of the adjustable resistance network 224. Also, the processor 272 generates a logic high or 1 value for calibration trigger C. The ohmmeter 271 measures the calibrated resistance value of calibration resistor R13 via bonding pad 275. The processor 272 compares the calibration value (e.g., calibrated resistance value or “expected” / calibrated temperature rise) stored in NVM 287 with the value the processor 272 derives from the measured calibrated resistance value. Although NVM 287 is shown as being included in trim controller 260, NVM 287 may be located elsewhere on the IC. The calibration value may be stored in other NVMs that store other values, such as NVM 261 or NVM 262.

[0059] The ohmmeter 271 may or may not be external to the IC while other components such as NVM 287 are included in the IC. In another example, instead of an external ohmmeter, an analog - to - digital converter (ADC) on the IC may be used to convert the voltage measured across the calibration resistor when a given current is injected into the calibration resistor and send the digital result, thereby measuring the calibrated resistance value. In fact, the ADC and current source function as an on - chip ohmmeter. In this example, the interface circuit elements may or may not include NMOS transistors 276, 277 or bonding pad 275, but instead may include appropriate connection features for connecting the calibration resistor to the ADC and current source.

[0060] The heater calibration system 270 generates temperature results that can indicate the estimated heating amount of an adjustable resistance network based on the measured calibration resistance value. This result can be a yes / no indication as to whether the adjustable resistance network has been heated to within the allowable range of the desired temperature (i.e., the measured resistance value matches the calibration resistance value). This result can be used to trigger a recalibration of the power pulse PP provided to the heater element 225.

[0061] FIG. 10 is a flowchart outlining an exemplary method 1000 for calibrating the temperature coefficient of an adjustable resistance network within an integrated circuit (IC) installed in a packaging arrangement. Method 1000 can be implemented, for example, by the trim controller 260 of FIG. 2. The method includes, at 1010, measuring a first resistance value of the adjustable resistance network at a first temperature. The first temperature is often room temperature or about 25° C., but can also be another temperature imposed on the chip by a temperature forcing system. It should be noted that this resistance value measurement is for the entire adjustable resistance network as described above for the trimming process and not for the calibration resistor. The resistance value can be measured by applying predetermined values to TC0-3 and IREF0-3 of FIG. 2 and measuring the bias current IBIAS, or by any other technique that can measure the total resistance value of the adjustable resistance network 224.

[0062] At 1020, a predetermined power pulse is selected based on the packaging arrangement. The predetermined power pulse has a power of a predetermined magnitude for a predetermined time. The appropriate power and duration of the power pulse can be estimated by characterizing the integrated circuit constructed in a particular packaging arrangement. First, these devices are placed in an oven or a thermal forcing system, and the calibration resistor is measured at various known temperatures. The device is then brought to the first temperature referred to in step 1010, a power pulse is applied, and immediately thereafter (e.g., within a few microseconds), the calibrated resistance value is measured. The temperature can be estimated by comparing this resistance value with the resistance values of the calibration resistors at various temperatures measured previously. This process is repeated using different power pulses to determine the amount of power and the power application time to be used as the predetermined power pulse to achieve a desired second temperature, e.g., 85 °C. Thus, the predetermined power pulse is selected to bring about a calibrated temperature rise (e.g., 60 °C) in the device under test.

[0063] At 1030, a predetermined power pulse is applied to a heater element within the IC, heating an adjustable resistance network to a second temperature. At 1040, the resistance value of the resistance network is (again) measured using the same predetermined values of TC0~3 and IREF0~3 as applied at 1010. At 1050, the linear two-point temperature coefficient of the adjustable resistance network is calculated. In one example, the linear two-point temperature coefficient is calculated by taking the difference between the second resistance value and the first resistance value, dividing by the first resistance to normalize the result, dividing by one million to convert the result to parts per million (ppm), and dividing by the "expected" / calibrated temperature rise calculated at 1020. At 1060, an appropriate trim is selected to reduce the temperature coefficient of the adjustable resistance network. This can be accomplished by selecting appropriate values of TC0~3 based on the temperature coefficient calculated at 1050 and knowledge of the effect of each trim bit TC0~3 on the temperature coefficient of the adjustable resistance network as derived from simulation or characterization. The effects of both the linear and quadratic components of the temperature coefficient of the adjustable resistance network can be considered, and a trim configuration can be selected that reduces the resistance value deviation over the entire temperature range. At 1070, the NVM is programmed using the appropriate trim to reduce the temperature coefficient of the adjustable resistance network (e.g., the selected values of TC0~3 are programmed into NVM261 (see FIG. 2)).

[0064] One advantage of the integrated calibration resistor is that the packaging configuration of the integrated circuit under test can be used to confirm that the packaging configuration initially used during the determination of a given power pulse for the heater is being adhered to. FIG. 11 is a flowchart outlining an exemplary method 1100 for setting the temperature coefficient of an adjustable resistor network that includes this packaging confirmation. Method 1100 may be implemented, for example, by the processor 272 of the heater calibration system 270 of FIG. 2. At 1110, a first resistance value of the adjustable resistor network is measured at a first temperature (e.g., room temperature). At 1120, a first resistance value of the calibration resistor is measured at the first temperature. At 1130, a given power pulse is selected (e.g., based on the packaging configuration used during initial characterization). At 1140, the power pulse is applied to the heater. At 1150, a second resistance value of the adjustable resistor network at a second (elevated) temperature is measured. At 1160, a second resistance value of the calibration resistor is measured at the (same) second temperature. At 1170, the temperature coefficient of the resistance value of the adjustable resistor network is calculated.

[0065] At 1175, the calculated (elevated) temperature of the adjustable resistance network is calculated based on the first and second measured resistance values of the calibration resistor. In one example, the "estimated" calculated temperature is determined by dividing the second measured resistance value of the calibration resistor by the first measured resistance value to determine the value of R / R0, and indexing this value against line 505 of FIG. 5 representing the nominal behavior of the calibration resistor to determine the second temperature. For example, if line 505 represents the calibration resistor used and the second measured calibration resistance value is 1.2 times the first measured calibration resistance value, the second temperature is 100° C., and the "estimated" calculated temperature rise resulting from operating the heater with a given power pulse is 75° C. At 1180, a determination is made as to whether the "estimated" calculated temperature rise is equivalent (e.g., within an acceptable range) to the "expected" / calibrated temperature rise (e.g., 60° C. determined during characterization at 1020 of method 1000). Since the room temperature can vary slightly, the "estimated" calculated temperature rise is used to reduce the effect of variations in the first temperature rather than the absolute calculated temperature. If the "estimated" calculated temperature rise matches the "expected" / calibrated temperature rise within a reasonable error margin (e.g., ±20%), the method proceeds to 1185 and the adjustable resistance network is adjusted such that its temperature coefficient is reduced. If the "estimated" / calculated temperature rise is not within the expected range, at 1196 the unit is discarded as defective and the testing of the unit is terminated. If a number of units are discarded in this way, the test engineer may decide to determine a new amount of power and / or the time for which the power is applied as the new power pulse used when testing the units.

[0066] FIG. 12 is a flowchart outlining an exemplary method 1200 for automatically adjusting the power pulse applied to a heater element during a trimming process. Method 1200 can be implemented, for example, by a processor 272 of the heater calibration system 270 of FIG. 2. Method 1200 may also not involve operator intervention or test program rewriting to adjust the power pulse. This is because the same test method can be used for all packaging configurations of an IC including an adjustable resistor network. Also, since method 1200 automatically corrects for variations in the metallization resistance value of the heater, using method 1200 means that a constant power is not applied to the heater and only a constant voltage can be applied.

[0067] At 1210, a first resistance value of an adjustable resistor network is measured at a first temperature (e.g., room temperature). At 1220, a first resistance value of a calibration resistor is measured at the first temperature. At 1230, a predetermined power pulse is selected (e.g., based on the packaging configuration used during initial characterization). At 1240, the power pulse is applied to the heater. At 1250, a second resistance of the adjustable resistor network is measured at a second (elevated) temperature. At 1260, a second resistance value of the calibration resistor is measured at the same second temperature. At 1270, a temperature coefficient of the resistance value of the adjustable resistor network is calculated.

[0068] At 1275, the calculated (elevated) temperature of the adjustable resistance network is calculated based on the first and second measured resistance values of the calibration resistor. In one example, the "estimated" / calculated temperature is determined by dividing the second measured resistance value of the calibration resistor by the first measured resistance value to determine the value of R / R0, and normalizing this value with respect to line 505 of FIG. 5 representing the nominal behavior of the calibration resistor to determine the second temperature. For example, if line 505 represents the calibration resistor used and the second measured calibration resistance value is 1.2 times the first measured calibration resistance value, the "estimated" / calculated temperature is 100° C., and the "estimated" / calculated temperature rise resulting from operating the heater with a given power pulse is 75° C. At 1280, a determination is made as to whether the "estimated" / calculated temperature rise is equal (e.g., within an acceptable range) to the value of the "expected" / calibrated temperature rise (e.g., 60° C. determined during the characterization at 1020 of method 1000). Since the room temperature can vary slightly, the "estimated" / calculated temperature rise is used instead of the absolute calculated temperature to reduce the effect of the variation of the first temperature. If the "estimated" / calculated temperature rise matches the "expected" / calibrated temperature rise within a reasonable error margin (e.g., ±10%), the method proceeds to 1285 and the adjustable resistance network is adjusted such that its temperature coefficient is reduced.

[0069] If the "presumed" / calculated temperature rise does not fall within the expected range, at 1290, it is determined whether the "presumed" / calculated temperature rise is within some extended range of the "expected" / calibrated temperature rise. If it is within the range, at 1297, a modified power pulse is determined for use in testing subsequent units. The current power pulse can be modified based on the "presumed" / calculated temperature rise, and the parameters describing the modified pulse are stored for further unit testing. At 1298, after cooling, the modified pulse is applied to the unit to complete the trimming operation. At 1280, if the "presumed" / calculated temperature rise does not fall within the expected range and is outside the extended range of the "expected" / calibrated temperature rise, at 1299, this unit is considered defective and discarded.

[0070] (For example, at 1297) There are several ways to modify a predetermined power pulse based on the "presumed" / calculated temperature rise. In one example, the modified value of the voltage applied (while keeping the application time constant) is calculated by multiplying the voltage of the predetermined power pulse by the "presumed" / calibrated temperature rise and dividing by the "presumed" / calculated temperature rise. In another example, the modified value of the voltage V mod of a predetermined pulse is calculated from the previously used voltage V old , the "expected" / calibrated temperature rise ΔT exp , and the "presumed" / calculated temperature rise ΔT est using the following formula. TIFF0007709254000002.tif449 Here, the decay constant k is a constant greater than zero and less than 1 (for example, 0.1). By using the constant k, attenuation is provided so that a single measurement deviating significantly from the desired value due to a defect in the device under test does not overly affect subsequent unit measurements.

[0071] In another example, a new time period to which an existing voltage is applied is calculated to determine a modified power pulse. By this technique, a constant voltage source can be used to drive the heater, which can be advantageous, for example, when testing multiple units in parallel.

[0072] FIG. 13 is a flowchart outlining an exemplary method 1300 for calibrating a heater that heats an adjustable resistive network during a trimming procedure in response to a power pulse having a predetermined voltage level and duration. Method 1300 can be implemented by the processor 272 of FIG. 2. The method includes, at 1310, commanding a power supply to provide a power pulse to the heater. The method includes, at 1320, measuring a resistance value of a calibration resistor that is thermally coupled to the adjustable resistive network. The method includes, at 1330, reading a calibration value for the calibration resistor. The method includes, at 1340, adjusting a predetermined voltage level or the duration of the power pulse based on a comparison of the calibration value and a value based on the measured resistance value.

[0073] As described above, the quality of the trimming results can be improved by providing a calibration resistor to more directly determine the temperature of the adjustable resistive network during trimming.

[0074] In this description, the term "coupled" can include a connection, communication, or signal path that enables a functional relationship consistent with this description. Thus, if device A generates a signal for controlling device B to perform a certain action, (a) in a first example, device A is directly coupled to device B, or (b) in a second example, device A is coupled to device B via an intervening component C, provided that the intervening component C does not substantially alter the functional relationship between device A and device B such that device B is controlled by device A via the control signal generated by device A.

[0075] These methods are illustrated and described above as a series of acts or events, but the illustrated order of such acts or events is not limiting. For example, some acts or events may occur in a different order and / or concurrently with other acts or events than those illustrated and / or described herein. Also, some of the illustrated acts or events are optional in order to implement one or more aspects or embodiments of this description. Further, one or more of the acts or events shown herein may be performed in one or more separate acts and / or phases. In some embodiments, the methods described above may be implemented on a computer-readable medium using instructions stored in a memory.

[0076] Within the scope of the claims, modifications are possible in the examples described and other implementations are possible.

Claims

1. An integrated circuit, comprising: An adjustable resistance network having a first terminal, a second terminal coupled to a connection terminal, and a third terminal, the adjustable resistance network including a first resistance segment; A heater element thermally coupled to the adjustable resistance network; An amplifier having a first amplifier input coupled to the first terminal of the adjustable resistance network, a second amplifier input, and an amplifier output; A calibration resistor including a second resistance segment coupled to the second terminal, the second resistance segment being thermally coupled to the first resistance segment; A first transistor coupled between a bias current terminal and the adjustable resistance network, the first transistor having a first control terminal coupled to the amplifier output; A second transistor coupled between the second amplifier input and a ground terminal, the second transistor having a second control terminal; A third transistor coupled between the third terminal of the adjustable resistance network and the ground terminal, the third transistor having a third control terminal coupled to the second control terminal; The integrated circuit comprising the above components.

2. The integrated circuit according to claim 1, wherein The first and second resistance segments are disposed in a layer of the integrated circuit device.

3. The integrated circuit according to claim 1, wherein The first resistance segment is disposed in a first layer of the integrated circuit device, and the second resistance segment is disposed in a second layer of the integrated circuit device adjacent to or proximate to the first layer.

4. The integrated circuit according to claim 1, wherein The first resistance segment is a member of an array of physical resistance segments fabricated from a resistive material, and the second resistance segment is a member of the array of physical resistance segments.

5. The integrated circuit according to claim 1, wherein The second resistance segment is inter-fitted with the first resistance segment.

6. The integrated circuit according to claim 1, wherein The second resistance segment belongs to the first resistance segment.

7. The integrated circuit according to claim 1, further comprising An interface circuit element including a conductive pad coupled to the calibration resistor.

8. An integrated circuit according to claim 1, further comprising an interface circuit element including one or more switches that electrically isolate the calibration resistor from the adjustable resistor network when actuated.

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