Method and apparatus for synchronizing timestamp counters

Abstract

A method and apparatus for synchronizing time stamp counters (TSCs) associated with processor cores in a computer system includes initializing the TSCs associated with the processor cores by synchronizing the TSCs with at least one other TSC in a hierarchy of TSCs. One or more processor cores are powered down. When the one or more processor cores are powered up, the TSCs associated with the processor cores are synchronized with at least one other TSC in the hierarchy of TSCs.

Description

Technical Field

[0001] (Cross - Reference to Related Applications) This application claims the benefit of U.S. Patent Application No. 16 / 721,886, filed on Dec. 19, 2019, the content of which is incorporated herein by reference.

Background Art

[0002] One of the major challenges in multi - core processor systems is to maintain the synchronization of the timestamp counter (TSC) across all the different cores that may be running at different frequencies. This becomes an increasingly difficult problem as the distance between cores, and further between sockets, grows. Another challenge is to maintain the synchronization of the TSC during power management events such as CC1, CC6, or other sleep states. In conventional designs, when waking up from a clock stop or sleep state, it is necessary to reprogram the core - specific logic with a new TSC value.

[0003] A more detailed understanding may be obtained from the following description given as an example in conjunction with the accompanying drawings.

Brief Description of the Drawings

[0004] [Figure 1] It is a block diagram of an exemplary device capable of implementing one or more features of the present disclosure. [Figure 2] It is a schematic diagram of an exemplary processor including a plurality of cores. [Figure 3] It is a flowchart of an exemplary method for synchronizing a timestamp counter.

Mode for Carrying Out the Invention

[0005] This method and apparatus are developed in more detail below, but a brief explanation of the use of the Timestamp Counter (TSC) and its synchronization as an important aspect of a computer system is included here. In a computer system, it may be useful to utilize the concept of a Global Timestamp (GT). The GT is a value that always increments and is common to all processor threads that can be used to indicate the completion order of global events. This GT can be used by individual processor threads to coordinate their activities and indicate the correct order. This mechanism is commonly used in a distributed database system to determine whether to continue processing a multi-step transaction or whether to reschedule a multi-step transaction due to a change in one of the dependent transactions scheduled with a GT newer than the GT of the transaction attempting to complete. There are software mechanisms that can be used to implement a Global Timestamp Counter (GTC), but these software mechanisms typically involve semaphore transactions to shared variables and tend to be very slow due to the communication overhead and collision resolution of many processes attempting to update a single shared location. Instead, since each physical processor implements a local Timestamp Counter (TSC), access is fast and synchronization with all other TSCs is maintained, so that globally all processes recognize the same value in approximately the same period, avoiding the overhead of maintaining a software GTC. To utilize this mechanism, all local TSCs must always be synchronized with each other regardless of power management events.

[0006] A method for synchronizing a timestamp counter (TSC) associated with a processor core in a computer system includes initializing the TSC associated with the processor core by synchronizing the TSC associated with the processor core with at least one other TSC within a hierarchy of TSCs. One or more processor cores are powered down. When one or more processor cores are powered up, the TSC associated with the processor core is synchronized with at least one other TSC within the hierarchy of TSCs.

[0007] An apparatus for synchronizing a timestamp counter (TSC) in a computer system includes a processor die including a plurality of processor cores, a first TSC associated with a processor core of the plurality of processor cores, and a second TSC within a hierarchy of TSCs that communicates with the first TSC. The first TSC is initialized by synchronizing the first TSC with the second TSC. When one or more processor cores are powered up after a power down, the first TSC associated with the processor core is synchronized with the second TSC within the hierarchy of TSCs.

[0008] A non-transitory computer-readable storage medium for synchronizing a timestamp counter (TSC) associated with a processor core in a computer system has instructions recorded thereon that, when executed by a processor, cause the processor to perform operations. The operations include initializing the TSC associated with the processor core by synchronizing the TSC associated with the processor core with at least one other TSC within a hierarchy of TSCs, powering down one or more processor cores, and synchronizing the TSC associated with the processor core with at least one other TSC within the hierarchy of TSCs when one or more processor cores are powered up.

[0009] FIG. 1 is a block diagram of an exemplary device 100 that can implement one or more features of the present disclosure. Device 100 can include, for example, a computer, a gaming device, a handheld device, a set-top box, a television, a mobile phone, or a tablet computer. Device 100 includes a processor 102, a memory 104, a storage 106, one or more input devices 108, and one or more output devices 110. Also, device 100 can optionally include an input driver 112 and an output driver 114. Further, device 100 includes a memory controller 115 that can communicate with processor 102 and memory 104 and also communicate with an external memory 116. It should be understood that device 100 can include additional components not shown in FIG. 1.

[0010] In various alternatives, processor 102 includes a central processing unit (CPU), a graphics processing unit (GPU), a CPU and a GPU located on the same die, or one or more processor cores, where each processor core can be a CPU or a GPU. In various alternatives, memory 104 is located on the same die as processor 102 or separately from processor 102. Memory 104 includes volatile or non-volatile memory (e.g., random access memory (RAM), dynamic RAM, cache).

[0011] Storage 106 includes fixed storage or removable storage (e.g., hard disk drive, solid state drive, optical disk, flash drive). Input device 108 includes, but is not limited to, a keyboard, keypad, touch screen, touch pad, detector, microphone, accelerometer, gyroscope, biometrics scanner, or a network connection (e.g., a wireless local area network card for transmitting and / or receiving wireless IEEE802 signals). Output device 110 includes, but is not limited to, a display, speaker, printer, tactile feedback device, one or more lights, antenna, or a network connection (e.g., a wireless local area network card for transmitting and / or receiving wireless IEEE802 signals).

[0012] Input driver 112 communicates with processor 102 and input device 108, enabling processor 102 to receive inputs from input device 108. Output driver 114 communicates with processor 102 and output device 110, enabling processor 102 to send outputs to output device 110. Note that input driver 112 and output driver 114 are optional components, and device 100 operates similarly in the absence of input driver 112 and output driver 114.

[0013] External memory 116 may be similar to memory 104 and may exist in the form of off-chip memory. Further, the external memory may be memory resident on a server to which memory controller 115 communicates via a network interface to access memory 116.

[0014] FIG. 2 is a schematic diagram of an exemplary processor including a plurality of cores. In the example shown in FIG. 2, the processor 102 of device 100 is depicted as having a plurality of cores 122 (referred to as 1221, 1222, 1223, 1224, 1225, 1226). The processor 102 includes a TSC1230 that is part of the hierarchy of TSC123 and communicates with the master TSC123T. Further, each core 122 includes a TSC123 (referred to as 1231, 1232, 1233, 1234, 1235, 1236). As described above, each TSC123 is synchronized with all other TSCs.

[0015] The steps of "permitting TSC update" and "adding TSC offset" described herein are depicted as occurring in order, but these steps can be performed in any order. Both need to be completed before indicating that the TSCs are synchronized. In some embodiments, one order is utilized, and in other embodiments, a different order is utilized. The choice of order may depend on the logic for communicating the "TSC offset". If the physical distance required to transmit the "TSC offset" is small, it is transferred over a dedicated wire, so the offset is added after the TSC update has started. If the physical distance required to transmit the "TSC offset" is large, the "TSC offset" can be serially transmitted to the TSC using the "TSC update" signal. In this case, the TSC update is held for a sufficient number of TSC cycles to allow the "TSC offset" to be transmitted before the first TSC update pulse is sent.

[0016] FIG. 3 is a flowchart of an exemplary method 300 for synchronizing a timestamp counter such as TSC123.

[0017] In step 310, the TSC is reset (initialized). At this point, TSC updates are disabled and the TSC offset value is stored for the next TSC update (step 320). Thereby, during a power management event, the TSC123 associated with core 122 is in a synchronized state at power-up.

[0018] When the power-up cycle starts, the TSC update of the TSC123 becomes effective again (step 330). At this point, the stored offset value is added to the counter (step 340), and the TSC123 is synchronized (step 350).

[0019] To execute the above method 300, there is a hierarchy of TSC counters that execute this sequence. At the top level, there is one master TSC counter (TSCT) that is always on and always increments with the TSC clock (not shown). The next lower level (e.g., the die-level TSC - TSC1230 of the processor die 102) obtains a die-by-die reference in synchronization with the master TSCT. From there, each TSC123 associated with a core 122 obtains a TSC offset from the die-level counter in synchronization with the die-level TSC. This allows each branch of the tree (e.g., core 122) to be powered down individually, and this method can be repeated as necessary to resynchronize all the TSCs on that branch downward starting from the highest TSC.

[0020] The provided method can be implemented in a general-purpose computer, processor, or processor core. Suitable processors include, by way of example, general-purpose processors, dedicated processors, conventional processors, digital signal processors (DSPs), multiple microprocessors, one or more microprocessors associated with DSP cores, controllers, microcontrollers, application specific integrated circuits (ASICs), field programmable gate array (FPGA) circuits, other types of integrated circuits (ICs), and / or state machines. Such processors can be manufactured by configuring a manufacturing process using the results of hardware description language (HDL) instructions or other intermediate data including a netlist (such as instructions storable on a computer-readable medium). The result of such processing may be a mask work used in a semiconductor manufacturing process to fabricate a processor implementing the features of the present disclosure. Further, although the methods and apparatuses described above are described in the context of controlling and configuring PCIe links and ports, the methods and apparatuses may be utilized in any interconnect protocol where the link width is negotiated.

[0021] The methods or flowcharts provided herein can be implemented by a computer program, software, or firmware incorporated in a non-transitory computer-readable storage medium for execution by a general-purpose computer or processor. Examples of non-transitory computer-readable storage media include magnetic media such as read only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, internal hard disks, and removable disks, magneto-optical media, and optical media such as CD-ROM disks and digital versatile disks (DVDs). For example, the methods described above may be implemented in processor 102 or other processors within computer 100.

Claims

1. A method for synchronizing a timestamp counter (TSC) associated with a first processor core within a computer system, comprising: Initializing the first TSC associated with the first processor core by synchronizing the first TSC associated with the first processor core with at least one second TSC associated with a second processor core within a hierarchy of TSCs, the hierarchy of TSCs including at least a die-level TSC coupled to the at least one second TSC and a master TSC coupled to the die-level TSC; Powering down one or more processor cores including the first processor core; When powering up the one or more processor cores including the first processor core, synchronizing the first TSC associated with the first processor core with at least the second TSC within the hierarchy of TSCs. A method.

2. The method of claim 1, further comprising disabling updates to the first TSC when powering down the first processor core. The method of claim 1.

3. The method of claim 2, further comprising storing a TSC offset value when powering down the first processor core. The method of claim 2.

4. The method of claim 3, further comprising enabling updates to the first TSC when powering up the first processor core. The method of claim 3.

5. The method of claim 4, further comprising adding the TSC offset value to the first TSC associated with the first processor core when powering up the first processor core to synchronize the first TSC with at least the second TSC within the hierarchy of TSCs. The method of claim 4.

6. The method of claim 5, further comprising delaying updates to the first TSC until the TSC offset value is added. The method of claim 5.

7. At least the second TSC within the hierarchy of TSCs is a die-level TSC that communicates with a plurality of TSCs associated with a plurality of processor cores. The method of claim 1.

8. The die-level TSC communicates with a master TSC that is always powered on. The method of claim 7.

9. The die-level TSC receives a TSC offset value from the master TSC and communicates the TSC offset value to a plurality of TSCs associated with the plurality of processor cores. The method of claim 8.

10. An apparatus for synchronizing a time stamp counter (TSC) in a computer system, comprising: a processor die including a plurality of processor cores; a first TSC associated with a first processor core among the plurality of processor cores; a second TSC associated with a second processor core within a hierarchy of TSCs, the second TSC communicating with the first TSC, the hierarchy of TSCs including a die-level TSC coupled to the second TSC and a master TSC coupled to the die-level TSC; the first TSC being initialized by synchronizing the first TSC with the second TSC; when one or more processor cores including the first processor core are powered up after being powered down, the first TSC associated with the first processor core is synchronized with the second TSC within the hierarchy of TSCs; An apparatus.

11. Updating of the first TSC associated with the first processor core is disabled when powered down. The apparatus of Claim 10.

12. When the first processor core is powered down, a TSC offset value is stored. The apparatus of Claim 11.

13. Updating of the first TSC associated with the first processor core is enabled when powered up. The apparatus of Claim 12.

14. The second TSC within the hierarchy of TSCs is the die-level TSC that communicates with the first TSC and a plurality of TSCs each associated with a plurality of processor cores. The apparatus of Claim 13.

15. Updating of the first TSC associated with the first processor core is delayed until the TSC offset value is added. The apparatus of Claim 14. 【Claim {16}】 At least the second TSC within the hierarchy of TSCs is the die-level TSC that communicates with the first TSC and a plurality of TSCs each associated with a plurality of processor cores. The apparatus of Claim 15.

17. Further comprising a master TSC that communicates with the die-level TSC. The apparatus of Claim 16.

18. The master TSC is always powered on. The apparatus of Claim 17.

19. The die-level TSC receives the TSC offset value from the master TSC and communicates the TSC offset value to the first TSC and the TSCs associated with the plurality of cores. The apparatus of claim 18.

20. A computer-readable storage medium for synchronizing a timestamp counter (TSC) associated with a first processor core within a computer system, the computer-readable storage medium having instructions recorded thereon that, when executed by a processor, cause the processor to perform operations, wherein the operations include initializing the TSC associated with the first processor core by synchronizing the TSC associated with the first processor core with at least one second TSC within a hierarchy of TSCs, the hierarchy of TSCs including at least a die-level TSC coupled to the at least one second TSC and a master TSC coupled to the die-level TSC, powering down one or more processor cores including the first processor core, and, when powering up the one or more processor cores including the first processor core, synchronizing the TSC associated with the first processor core with at least the second TSC within the hierarchy of TSCs. Computer-readable storage medium.

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