Semiconductor device manufacturing method

Abstract

To provide a method for manufacturing a semiconductor device capable of improving surface roughness of a nitride semiconductor layer.SOLUTION: A method for manufacturing a semiconductor device includes the steps of: forming a first nitride semiconductor layer containing Ga on a substrate; forming a first layer on the first nitride semiconductor layer; forming a second layer on the first layer; forming an opening for exposing the first nitride semiconductor layer on the second layer and the first layer; forming a second nitride semiconductor layer of a first conductivity type on a surface exposed from the opening of the first nitride semiconductor layer; removing the second layer using an acid solution; and forming an electrode on the second nitride semiconductor layer after the second layer removing step. A first etching rate to the acid solution of the first layer is lower than a second etching rate to the acid solution of the second layer.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art In order to reduce contact resistance in semiconductor devices using nitride semiconductors, a structure has been proposed in which a nitride semiconductor layer containing a high concentration of impurities is regrown. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-033155 Summary of the Invention [Problem to be solved by the invention]

[0004] Conventional manufacturing methods can result in roughness on the surface of the regrown nitride semiconductor layer.

[0005] An object of the present disclosure is to provide a method for manufacturing a semiconductor device that can improve the surface roughness of a nitride semiconductor layer. [Means for solving the problem]

[0006] The method for manufacturing a semiconductor device according to the present disclosure includes the steps of forming a first nitride semiconductor layer containing Ga on a substrate, and forming a first nitride semiconductor layer on the first nitride semiconductor layer. Silicon nitride forming a layer; Silicon nitride Layer on layer zinc oxide forming a layer; forming a second silicon nitride layer on the zinc oxide layer; The aforementioned zinc oxide layer and the first Silicon nitride forming an opening in the layer exposing the first nitride semiconductor layer; widening the opening formed in the zinc oxide layer; forming a second nitride semiconductor layer of a first conductivity type on a surface of the first nitride semiconductor layer exposed through the opening; Contains hydrochloric acid or phosphoric acid Using an acidic solution zinc oxideRemove the layer and removing the second silicon nitride layer. and zinc oxide forming an electrode on the second nitride semiconductor layer after the step of removing the layer; The surface of the first nitride semiconductor layer that contacts the second nitride semiconductor layer is an N-polar surface. . [Effects of the Invention]

[0007] According to the present disclosure, the surface roughness of a nitride semiconductor layer can be improved. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view (part 1) illustrating the method for manufacturing a semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 3] FIG. 3 is a cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 5] FIG. 5 is a cross-sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view (part 6) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] FIG. 7 is a cross-sectional view (part 7) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] FIG. 8 is a cross-sectional view (part 8) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] 9A to 9C are cross-sectional views showing a method for manufacturing a semiconductor device according to a modified example of the first embodiment. [Figure 10] FIG. 10 is a cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the second embodiment. [Figure 11] FIG. 11 is a cross-sectional view (part 2) showing the method for manufacturing the semiconductor device according to the second embodiment. [Figure 12]FIG. 12 is a cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the second embodiment. [Figure 13] FIG. 13 is a cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the second embodiment. [Figure 14] FIG. 14 is a cross-sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the second embodiment. [Figure 15] 15A to 15C are cross-sectional views showing a method for manufacturing a semiconductor device according to a modified example of the second embodiment. [Figure 16] FIG. 16 is a cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the third embodiment. [Figure 17] FIG. 17 is a cross-sectional view (part 2) showing the method for manufacturing the semiconductor device according to the third embodiment. [Figure 18] FIG. 18 is a cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the third embodiment. [Figure 19] FIG. 19 is a cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the third embodiment. [Figure 20] FIG. 20 is a cross-sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the third embodiment. [Figure 21] FIG. 21 is a cross-sectional view (part 6) illustrating the method for manufacturing the semiconductor device according to the third embodiment. [Figure 22] FIG. 22 is a cross-sectional view (part 7) illustrating the method for manufacturing the semiconductor device according to the third embodiment. [Figure 23] FIG. 23 is a cross-sectional view (part 8) illustrating the method for manufacturing the semiconductor device according to the third embodiment. [Figure 24] FIG. 24 is a ninth cross-sectional view illustrating the method for manufacturing the semiconductor device according to the third embodiment. [Figure 25] 25A to 25C are cross-sectional views showing a method for manufacturing a semiconductor device according to a modification of the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described.

[0010] [1] A method for manufacturing a semiconductor device according to one aspect of the present disclosure includes the steps of: forming a first nitride semiconductor layer containing Ga on a substrate; forming a first layer on the first nitride semiconductor layer; forming a second layer on the first layer; forming openings in the second layer and the first layer to expose the first nitride semiconductor layer; forming a second nitride semiconductor layer of a first conductivity type on a surface of the first nitride semiconductor layer exposed from the opening; removing the second layer using an acidic solution; and, after the step of removing the second layer, forming an electrode on the second nitride semiconductor layer, wherein a first etching rate of the first layer in the acidic solution is lower than a second etching rate of the second layer in the acidic solution.

[0011] When forming the second nitride semiconductor layer, the second nitride semiconductor layer can also be formed on the second layer. The second nitride semiconductor layer formed on the second layer is removed along with the removal of the second layer. At this time, the first layer remains on the first nitride semiconductor layer. Furthermore, although the second layer is removed using an acidic solution, the surface of the second nitride semiconductor layer is not etched by the acidic solution. Therefore, the second nitride semiconductor layer has good surface roughness even after the removal of the second layer.

[0012] [2] In [1], the first layer may be a silicon nitride layer, the second layer may be a zinc oxide layer or a silicon oxide layer, and the acidic solution may contain hydrochloric acid, phosphoric acid, or hydrofluoric acid. In this case, the difference between the first etching rate and the second etching rate is likely to be large.

[0013] [3] In the configuration [1] or [2], the second nitride semiconductor layer may be an n-type GaN layer, which makes it easier to reduce the contact resistance between the electrode and the first nitride semiconductor layer.

[0014] [4] In any of [1] to [3], the surface of the first nitride semiconductor layer in contact with the second nitride semiconductor layer may be an N-polar surface, which makes it easy to reduce the resistance of the current path in the first nitride semiconductor layer while avoiding an increase in contact resistance.

[0015] [5] In [4], the step of forming the first nitride semiconductor layer may include the steps of forming a barrier layer and forming a channel layer on the barrier layer. In this case, a high electron mobility transistor having low contact resistance between an electrode and the first nitride semiconductor layer can be configured.

[0016] [6] In any of [1] to [5], the surface of the second nitride semiconductor layer may be subjected to two-fluid cleaning or scrub cleaning between the step of removing the second layer and the step of forming the electrode, which increases the cleanliness of the surface of the second nitride semiconductor layer and makes it easier to reduce contact resistance.

[0017] [7] In any of [1] to [6], a step of forming a third layer on the second layer may be included between the step of forming the second layer and the step of forming the opening, the opening being also formed in the third layer, and a step of widening the opening formed in the second layer may be included between the step of forming the opening and the step of forming the second nitride semiconductor layer. In this case, the second nitride semiconductor layer is less likely to adhere to a sidewall surface of the second layer, and the second layer is easily removed by an acidic solution.

[0018] [8] A method for manufacturing a semiconductor device according to another aspect of the present disclosure includes the steps of: forming a first nitride semiconductor layer containing Ga on a substrate; forming a first silicon nitride layer on the first nitride semiconductor layer; forming a zinc oxide layer on the first silicon nitride layer; forming a second silicon nitride layer on the zinc oxide layer; forming an opening in the second silicon nitride layer, the zinc oxide layer, and the first silicon nitride layer to expose the first nitride semiconductor layer; widening the opening formed in the zinc oxide layer; forming a second nitride semiconductor layer of a first conductivity type on a surface of the first nitride semiconductor layer exposed from the opening; removing the zinc oxide layer and the second silicon nitride layer using an acidic solution containing hydrochloric acid or phosphoric acid; and forming an electrode on the second nitride semiconductor layer after the step of removing the zinc oxide layer, wherein a surface of the first nitride semiconductor layer in contact with the second nitride semiconductor layer is an N-polar surface.

[0019] [Details of the embodiments of the present disclosure] Hereinafter, embodiments of the present disclosure will be described in detail, but the present disclosure is not limited thereto. In this specification and drawings, components having substantially the same functional configurations may be designated by the same reference numerals to avoid redundant description.

[0020] (First embodiment) First, a first embodiment will be described. The first embodiment relates to a method for manufacturing a semiconductor device including a GaN-based high electron mobility transistor (HEMT). Figures 1 to 8 are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment.

[0021] 1, first, a nitride semiconductor layer 110 containing Ga is formed on a substrate 101 by, for example, metal organic chemical vapor deposition (MOCVD). In forming the nitride semiconductor layer 110, a buffer layer 111, a barrier layer 112, and a channel layer 113 are formed in this order. The nitride semiconductor layer 110 is an example of a first nitride semiconductor layer.

[0022] The substrate 101 is, for example, a substrate for growing a GaN-based semiconductor, and one example is a semi-insulating SiC substrate. When the substrate 101 is a SiC substrate, the surface of the substrate 101 is a carbon (C) polarity plane. When the surface of the substrate 101 is a C polarity plane, the buffer layer 111, the barrier layer 112, and the channel layer 113 can be grown as crystals with the nitrogen (N) polarity plane as the growth surface. A sapphire substrate may be used as the substrate for growing a GaN-based semiconductor. The substrate 101 does not have to be a substrate for crystal growth. In this case, the substrate 101 may be removed from the buffer layer 111, the barrier layer 112, and the channel layer 113 grown on another substrate, and the substrate 101 may be bonded to the buffer layer 111, the barrier layer 112, and the channel layer 113. In this case, a semi-insulating substrate made of various materials may be used as the substrate 101, and examples thereof include a sapphire substrate, a Si substrate, a SiC substrate, an AlN substrate, and a sintered body.

[0023] The buffer layer 111 is, for example, an AlN layer. The thickness of the AlN layer is, for example, 5 nm or more and 100 nm or less. The buffer layer 111 may include an AlN layer and a GaN layer or an AlGaN layer on the AlN layer. The thickness of the GaN layer or the AlGaN layer is, for example, 300 nm or more and 2000 nm or less.

[0024] The barrier layer 112 is, for example, an AlGaN layer. The band gap of the barrier layer 112 is larger than the band gap of the channel layer 113, which will be described later. The thickness of the barrier layer 112 is, for example, in the range of 5 nm to 50 nm, and in one embodiment, is 30 nm. x Ga 1-xIn the case of an N layer, the Al composition x is, for example, 0.15 to 0.55, inclusive, and in one embodiment, 0.35. The conductivity type of the barrier layer 112 is, for example, n-type or undoped (i-type). Instead of an AlGaN layer, an InAlN layer or an InAlGaN layer may be used.

[0025] The channel layer 113 is, for example, a GaN layer. The band gap of the channel layer 113 is smaller than the band gap of the barrier layer 112. The thickness of the channel layer 113 is, for example, 5 nm to 30 nm, and in one embodiment, 9 nm. Strain occurs between the channel layer 113 and the barrier layer 112 due to the difference in lattice constants therebetween, and this strain induces piezoelectric charges at the interface between them. As a result, a two-dimensional electron gas (2DEG) is generated in the region of the channel layer 113 on the barrier layer 112 side, forming a channel region 113c. The conductivity type of the channel layer 113 is, for example, n-type or undoped (i-type). The surface of the channel layer 113 constitutes the surface 110A of the nitride semiconductor layer 110. A spacer layer may be formed between the barrier layer 112 and the channel layer 113. The spacer layer is, for example, an AlN layer. The thickness of the spacer layer is, for example, in the range of 0.5 nm to 3.0 nm, and in one embodiment is 1.0 nm.

[0026] On the C-polar surface of the SiC substrate, the buffer layer 111, the barrier layer 112, and the channel layer 113 undergo crystal growth with the N-polar surface as the growth surface. Therefore, the surfaces of the buffer layer 111, the barrier layer 112, and the channel layer 113 opposite to the substrate 101 side are N-polar surfaces, and the back surfaces facing the substrate 101 are gallium (Ga)-polar surfaces.

[0027] Next, as shown in FIG. 2, a silicon nitride (SiN) layer 121 is formed in contact with the surface 110A of the nitride semiconductor layer 110. The SiN layer 121 can be formed by, for example, low-pressure CVD (LPCVD). The SiN layer 121 may be formed continuously on the buffer layer 111, the barrier layer 112, and the channel layer 113 by, for example, MOCVD, without exposing the surface of the channel layer 113 to the atmosphere. Next, a zinc oxide (ZnO) layer 122 is formed on the SiN layer 121. The ZnO layer 122 can be formed by, for example, sputtering. The ZnO layer 122 may also be formed by a sol-gel method, MOCVD, or molecular beam epitaxy (MBE). Next, a SiN layer 123 is formed on the ZnO layer 122. The SiN layer 123 can be formed by, for example, plasma-enhanced CVD (PECVD). Next, a resist pattern 124 is formed on the SiN layer 123. The resist pattern 124 has an opening 124S for a source and an opening 124D for a drain. The SiN layer 121 is an example of a first layer, or a first silicon nitride layer. The ZnO layer 122 is an example of a second layer. The SiN layer 123 is an example of a third layer, or a second silicon nitride layer.

[0028] 3, the SiN layer 123, the ZnO layer 122, and the SiN layer 121 are etched using the resist pattern 124 as a mask. This etching is, for example, reactive ion etching (RIE) using a fluorine-based gas or a chlorine-based gas. As a result, openings 123S, 122S, and 121S are formed in the SiN layer 123, the ZnO layer 122, and the SiN layer 121, respectively, on the substrate 101 side of the opening 124S. Furthermore, openings 123D, 122D, and 121D are formed in the SiN layer 123, the ZnO layer 122, and the SiN layer 121, respectively, on the substrate 101 side of the opening 124D. Portions of the nitride semiconductor layer 110 are exposed through the openings 123S, 122S, and 121S, and other portions of the nitride semiconductor layer 110 are exposed through the openings 123D, 122D, and 121D.

[0029] 4, the resist pattern 124 is removed using a chemical solution to widen the openings 122S and 122D. As a result, the sidewall surface of the opening 122S is recessed from the sidewall surfaces of the openings 121S and 123S, and the sidewall surface of the opening 122D is recessed from the sidewall surfaces of the openings 121D and 123D.

[0030] Next, as shown in FIG. 5 , an n-type GaN layer 131 is formed on the surfaces of the nitride semiconductor layer 110 exposed from the openings 123S, 122S, and 121S and on the surfaces exposed from the openings 123D, 122D, and 121D. The upper surface of the n-type GaN layer 131 may or may not be flush with the upper surface of the SiN layer 121. The n-type GaN layer 131 can be formed by, for example, sputtering, MOCVD, or MBE. At this time, the n-type GaN layer 131 is deposited not only on the nitride semiconductor layer 110 but also on the SiN layer 123. For example, the concentration of the n-type dopant is 1×10 17 cm -3 The n-type dopant is Si or Ge. The n-type GaN layer 131 is an example of a second nitride semiconductor layer.

[0031] The n-type GaN layer 131 grows as a crystal on the N-polar plane of the nitride semiconductor layer 110. Therefore, on the N-polar plane of the nitride semiconductor layer 110, the surface of the n-type GaN layer 131 opposite to the substrate 101 side is the N-polar plane, and the back surface on the substrate 101 side is the Ga-polar plane.

[0032] Next, as shown in FIG. 6, the ZnO layer 122 is removed using an acidic solution. The acidic solution contains, for example, hydrochloric acid (HCl) or phosphoric acid (H3PO4). As the ZnO layer 122 is removed, the SiN layer 123 and the n-type GaN layer 131 on the ZnO layer 122 are also removed. As a result, the n-type GaN layer 131 remains in the openings 121S and 121D, the n-type GaN layer 131S is formed in the opening 121S, and the n-type GaN layer 131D is formed in the opening 121D. Note that the etching rate of the SiN layer 121 in the acidic solution is lower than the etching rate of the ZnO layer 122 in the acidic solution. Therefore, the SiN layer 121 remains without being removed.

[0033] 7, a source electrode 132S is formed on the n-type GaN layer 131S, and a drain electrode 132D is formed on the n-type GaN layer 131D. To form the source electrode 132S and the drain electrode 132D, first, a plurality of metal layers (e.g., Ta / Al / Ta or Ti / Al / Ti) constituting the source electrode 132S and the drain electrode 132D are sequentially evaporated to form a laminated structure. This laminated structure is then heat-treated to form an alloy.

[0034] 8, an opening 121G is formed in the SiN layer 121 between the source electrode 132S and the drain electrode 132D. A portion of the nitride semiconductor layer 110 is exposed from the opening 121G. Next, a gate electrode 141 is formed in contact with the nitride semiconductor layer 110 through the opening 121G. In forming the gate electrode 141, a plurality of metal layers (for example, Ni / Pa / Au) that constitute the gate electrode 141 are sequentially vapor-deposited to form a stacked structure. Next, an insulating layer 142 is formed on the SiN layer 121 by, for example, plasma CVD, and the gate electrode 141 is covered with the insulating layer 142.

[0035] In this manner, the semiconductor device 100 can be manufactured.

[0036] In this embodiment, the ZnO layer 122 and the SiN layer 123 are formed before the formation of the n-type GaN layer 131. The n-type GaN layer 131 formed on the SiN layer 123 is removed along with the removal of the ZnO layer 122. At this time, the SiN layer 121 remains on the nitride semiconductor layer 110. The ZnO layer 122 is removed using an acidic solution, but the surface of the n-type GaN layer 131 is not etched by the acidic solution. Therefore, although the surfaces of the n-type GaN layers 131S and 131D are also exposed to the acidic solution when the ZnO layer 122 is removed, the surfaces of the n-type GaN layers 131S and 131D have good surface roughness. This improves the adhesion between the source electrode 132S and the drain electrode 132D and the n-type GaN layers 131S and 131D, thereby reducing the contact resistance between the source electrode 132S and the drain electrode 132D and the nitride semiconductor layer 110.

[0037] When the acidic solution contains hydrochloric acid or phosphoric acid, it is easy to increase the difference in etching rate between the ZnO layer 122 and the SiN layer 121. In other words, it is easy to remove the ZnO layer 122 while leaving the SiN layer 121. Note that a silicon oxide (SiO2) layer may be used instead of the ZnO layer 122. In this case, it is preferable that the acidic solution for removing the SiO2 layer contains hydrofluoric acid, as this makes it easy to remove the SiO2 layer while leaving the SiN layer 121. Note that the ZnO layer 122 may also be replaced by a layer of a metal oxide such as GeO2 or CaO.

[0038] Since the nitride semiconductor layers formed between the nitride semiconductor layer 110 and the source electrode 132S and the drain electrode 132D are the n-type GaN layers 131S and 131D, the contact resistance is easily reduced.

[0039] Because the surface 110A of the nitride semiconductor layer 110 is an N-polar surface, an increase in contact resistance can be avoided even if the Al composition of the barrier layer 112 is increased. This makes it easy to increase the concentration of the 2DEG and reduce the resistance of the channel region 113c. In particular, because the channel layer 113 is formed on the barrier layer 112, it is easy to reduce the resistance of the channel region 113c.

[0040] After removing the ZnO layer 122, two-fluid cleaning or scrub cleaning using pure water and nitrogen (N) gas may be performed. By performing two-fluid cleaning or scrub cleaning, the cleanliness of the surfaces of the n-type GaN layers 131S and 131D is improved, and the contact resistance is more likely to be reduced.

[0041] Since the SiN layer 123 is formed on the ZnO layer 122 and the opening of the ZnO layer 122 is widened, the n-type GaN layer 131 is less likely to adhere to the sidewall surface of the ZnO layer 122, and the ZnO layer 122 is easily removed with an acidic solution.

[0042] In the first embodiment, a gate insulating film may be formed between the formation of the opening 121G and the formation of the gate electrode 141. FIG. 9 is a cross-sectional view showing a manufacturing method of a semiconductor device according to a modified example of the first embodiment. For example, as shown in FIG. 9, the gate insulating film 143 may be formed after the formation of the opening 121G. In forming the gate insulating film 143, for example, an Al2O3 film is formed by, for example, atomic layer deposition (ALD), and the Al2O3 film is etched into a predetermined shape. Thereafter, the gate electrode 141 is formed on the gate insulating film 143. Then, the insulating layer 142 is formed.

[0043] According to the first embodiment, a transistor with a Schottky gate structure is obtained, whereas according to the modification of the first embodiment, a transistor with an MIS gate structure is obtained.

[0044] (Second embodiment) Next, a second embodiment will be described. The second embodiment relates to a method for manufacturing a semiconductor device including a GaN-based HEMT. Figures 10 to 14 are cross-sectional views showing the method for manufacturing a semiconductor device according to the second embodiment.

[0045] In the second embodiment, first, similarly to the first embodiment, processing up to the formation of the openings 123S, 122S, 121S, 123D, 122D, and 121D is performed (see FIG. 3). Next, as shown in FIG. 10, the nitride semiconductor layer 110 is etched using a resist pattern 124 as a mask, thereby forming a recess 210S connected to the openings 123S, 122S, and 121S and a recess 210D connected to the openings 123D, 122D, and 121D in the nitride semiconductor layer 110. This etching is, for example, RIE using a chlorine-based gas. This etching may also be performed in a mixed atmosphere containing hydrogen (H) and ammonia (NH). For example, the recesses 210S and 210D are formed to a depth that does not reach the channel region 113c. That is, the depth of the recesses 210S and 210D is smaller than the depth of the channel region 113c when the surface 110A of the nitride semiconductor layer 110 is used as a reference.

[0046] Next, as shown in FIG. 11, similarly to the first embodiment, the resist pattern 124 is removed using a chemical solution, and the openings 122S and 122D are widened.

[0047] 12, an n-type GaN layer 131 is formed to fill the recesses 210S and 210D and the openings 121S and 121D. As in the first embodiment, the n-type GaN layer 131 is deposited not only on the nitride semiconductor layer 110 but also on the SiN layer 123.

[0048] 13, the ZnO layer 122 is removed using an acid solution, as in the first embodiment. As a result, an n-type GaN layer 131S is formed in the opening 121S, and an n-type GaN layer 131D is formed in the opening 121D.

[0049] Thereafter, as shown in FIG. 14, the processes subsequent to the formation of the source electrode 132S and the drain electrode 132D are carried out in the same manner as in the first embodiment.

[0050] In this manner, the semiconductor device 200 can be manufactured.

[0051] In the second embodiment, the distance between the n-type GaN layers 131S and 131D and the channel region 113c is smaller than that in the first embodiment, which makes it possible to further reduce the contact resistance.

[0052] In the second embodiment, too, a gate insulating film may be formed between the formation of the opening 121G and the formation of the gate electrode 141. FIG. 15 is a cross-sectional view showing a manufacturing method of a semiconductor device according to a modified example of the second embodiment. For example, as shown in FIG. 15, the gate insulating film 143 may be formed after the formation of the opening 121G. In forming the gate insulating film 143, for example, an Al2O3 film is formed by, for example, the ALD method, and the Al2O3 film is etched into a predetermined shape. Thereafter, the gate electrode 141 is formed on the gate insulating film 143. Then, the insulating layer 142 is formed.

[0053] According to the second embodiment, a transistor with a Schottky gate structure is obtained, whereas according to the modified example of the second embodiment, a transistor with an MIS gate structure is obtained.

[0054] (Third embodiment) Next, a third embodiment will be described. The third embodiment relates to a method for manufacturing a semiconductor device including a GaN-based HEMT. Figures 16 to 24 are cross-sectional views showing the method for manufacturing a semiconductor device according to the third embodiment.

[0055] 16, first, a nitride semiconductor layer 310 containing Ga is formed on a substrate 301 by, for example, MOCVD. In forming the nitride semiconductor layer 310, a channel layer 311, a barrier layer 312, and a cap layer 313 are formed in this order. The nitride semiconductor layer 310 is an example of a first nitride semiconductor layer.

[0056] The substrate 301 is, for example, a substrate for growing a GaN-based semiconductor, and is, for example, a semi-insulating SiC substrate. When the substrate 301 is a SiC substrate, the surface of the substrate 301 is a silicon (Si) polar surface. When the surface of the substrate 301 is a Si polar surface, the channel layer 311, the barrier layer 312, and the cap layer 313 can be grown as crystals with the Ga polar surface as the growth surface.

[0057] The channel layer 311 is, for example, a GaN layer. The thickness of the channel layer 311 is, for example, in the range of 200 nm to 2000 nm, and in one embodiment, is 1000 nm. A buffer layer may be formed between the channel layer 311 and the substrate 301.

[0058] The barrier layer 312 is, for example, an AlGaN layer. The band gap of the barrier layer 312 is larger than the band gap of the channel layer 311. The thickness of the barrier layer 312 is, for example, in the range of 5 nm to 30 nm, and in one embodiment, is 15 nm. x Ga 1-xIn the case of an N layer, the Al composition x is, for example, 0.15 to 0.35, inclusive, and in one embodiment, 0.25. Strain occurs between the channel layer 311 and the barrier layer 312 due to the difference in their lattice constants, and this strain induces piezoelectric charges at the interface between them. This generates a 2DEG in the region of the channel layer 311 on the barrier layer 312 side, forming a channel region 311c. An InAlN layer or an InAlGaN layer may be used instead of the AlGaN layer. A spacer layer may also be formed between the channel layer 311 and the barrier layer 312. The spacer layer is, for example, an AlN layer. The thickness of the spacer layer is, for example, 0.5 nm to 3.0 nm, inclusive, and in one embodiment, is 1.0 nm.

[0059] The cap layer 313 is, for example, a GaN layer. The thickness of the cap layer 313 is, for example, in the range of 0 nm to 5 nm, and in one embodiment, is 2 nm. The surface of the cap layer 313 constitutes the surface 310A of the nitride semiconductor layer 310.

[0060] On the Si-polar surface of the SiC substrate, the channel layer 311, the barrier layer 312, and the cap layer 313 are crystal-grown with the Ga-polar surface as the growth surface. Therefore, the surfaces of the channel layer 311, the barrier layer 312, and the cap layer 313 opposite to the substrate 301 side are Ga-polar surfaces, and the back surfaces of the channel layer 311, the barrier layer 312, and the cap layer 313 facing the substrate 301 are N-polar surfaces.

[0061] 17, a silicon nitride (SiN) layer 121 is formed in contact with the surface 310A of the nitride semiconductor layer 310. Next, a zinc oxide (ZnO) layer 122 is formed on the SiN layer 121. Next, a SiN layer 123 is formed on the ZnO layer 122. Next, a resist pattern 124 is formed on the SiN layer 123. The resist pattern 124 has an opening 124S for a source and an opening 124D for a drain.

[0062] 18 , the SiN layer 123, the ZnO layer 122, and the SiN layer 121 are etched using the resist pattern 124 as a mask. As a result, openings 123S, 122S, and 121S are formed in the SiN layer 123, the ZnO layer 122, and the SiN layer 121, respectively, on the substrate 301 side of the opening 124S. Furthermore, openings 123D, 122D, and 121D are formed in the SiN layer 123, the ZnO layer 122, and the SiN layer 121, respectively, on the substrate 301 side of the opening 124D. Portions of the nitride semiconductor layer 310 are exposed through the openings 123S, 122S, and 121S, and other portions of the nitride semiconductor layer 310 are exposed through the openings 123D, 122D, and 121D.

[0063] Next, as shown in FIG. 19, the nitride semiconductor layer 310 is etched using the resist pattern 124 as a mask to form a recess 310S connected to the openings 123S, 122S, and 121S and a recess 310D connected to the openings 123D, 122D, and 121D. This etching is, for example, RIE using a chlorine-based gas. This etching may be performed in a mixed atmosphere containing hydrogen (H) and ammonia (NH). For example, the recesses 310S and 310D are formed to a depth that penetrates the channel region 311c. That is, the depth of the recesses 310S and 310D is greater than the depth of the channel region 311c when the surface 310A of the nitride semiconductor layer 310 is taken as the reference. The formation of the recesses 310S and 310D may be stopped midway through the barrier layer 312. That is, the recesses 310S and 310D may be formed so that the bottom surfaces of the recesses 310S and 310D are located within the barrier layer 312.

[0064] 20, the resist pattern 124 is removed using a chemical solution, and the openings 122S and 122D are widened. As a result, the sidewall surface of the opening 122S is recessed from the sidewall surfaces of the openings 121S and 123S, and the sidewall surface of the opening 122D is recessed from the sidewall surfaces of the openings 121D and 123D.

[0065] 21, an n-type GaN layer 331 is formed to fill the recesses 310S and 310D and the openings 121S and 121D. The n-type GaN layer 331 is deposited not only on the nitride semiconductor layer 310 but also on the SiN layer 123.

[0066] The n-type GaN layer 331 grows as a crystal with the N-polar plane as the growth plane on the Ga-polar plane of the nitride semiconductor layer 310. Therefore, on the Ga-polar plane of the nitride semiconductor layer 310, the surface of the n-type GaN layer 331 opposite to the substrate 301 side is a Ga-polar plane, and the back surface on the substrate 301 side is an N-polar plane.

[0067] 22, the ZnO layer 122 is removed using an acidic solution, as in the first embodiment. As a result, an n-type GaN layer 331S is formed in the opening 121S, and an n-type GaN layer 331D is formed in the opening 121D.

[0068] Next, as shown in FIG. 23, a source electrode 132S is formed on the n-type GaN layer 331S, and a drain electrode 132D is formed on the n-type GaN layer 331D.

[0069] 24, a gate electrode 141 is formed on the SiN layer 121 between the source electrode 132S and the drain electrode 132D. Next, an insulating layer 142 is formed on the SiN layer 121 by, for example, plasma CVD, and the gate electrode 141 is covered with the insulating layer 142.

[0070] In this manner, the semiconductor device 300 can be manufactured.

[0071] In this embodiment, the ZnO layer 122 and the SiN layer 123 are formed before the formation of the n-type GaN layer 331, and the n-type GaN layer 331 formed on the SiN layer 123 is removed along with the removal of the ZnO layer 122. At this time, the SiN layer 121 remains on the nitride semiconductor layer 110. Furthermore, although the ZnO layer 122 is removed using an acidic solution, the surface of the n-type GaN layer 331 is not etched by the acidic solution. Therefore, even after the ZnO layer 122 is removed, the n-type GaN layers 331S and 331D have good surface roughness. This reduces the contact resistance between the source electrode 132S and the drain electrode 132D and the nitride semiconductor layer 110.

[0072] The Ga-polar surface of the n-type GaN layer is highly resistant to alkaline solutions. Therefore, it is also possible to form the recesses 310S and 310D without forming the ZnO layer 122, and then form the n-type GaN layer 331 so as to fill the recesses 310S and 310D and the openings 121S and 121D. In this case, the n-type GaN layer 331 is also deposited on the SiN layer 121, but it is possible to remove the n-type GaN layer 331 on the SiN layer 121 using an alkaline solution. However, the interface between the SiN layer 121 and the n-type GaN layer 331 inside the openings 121S and 121D is not a Ga-polar surface, so etching of the n-type GaN layer 331 may proceed from this portion. Furthermore, if minute crystal defects occur on the surface of the n-type GaN layer 331, exposing a surface inclined from the Ga-polar surface, etching of the n-type GaN layer 331 may proceed from this portion. In this embodiment, such etching can be suppressed because treatment using an alkaline solution is not performed.

[0073] In the third embodiment, an opening for a gate may be formed in the SiN layer 121 between the formation of the source electrode 132S and the drain electrode 132D and the formation of the gate electrode 141, and the gate electrode 141 may be formed so as to be in contact with the cap layer 313. Fig. 25 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a modified example of the third embodiment. For example, as shown in Fig. 25, after the source electrode 132S and the drain electrode 132D are formed, an opening 310G for a gate may be formed in the SiN layer 121, and the gate electrode 141 may be formed so as to be in contact with the cap layer 313 through the opening 310G. Then, the insulating layer 142 is formed.

[0074] According to the third embodiment, a transistor with an MIS gate structure is obtained, whereas according to the modification of the third embodiment, a transistor with a Schottky gate structure is obtained.

[0075] It should be noted that the semiconductor device manufactured according to the present disclosure is not limited to a transistor, and for example, a light emitting diode may also be manufactured.

[0076] Although the embodiments have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0077] 100, 200, 300: Semiconductor device 101: Circuit board 110: Nitride semiconductor layer 110A: Surface 111: Buffer layer 112: Barrier layer 113: Channel layer 113c: Channel region 121:SiN layer 121: layer 121D, 121G, 121S: Aperture 122: ZnO layer 122: layer 122D, 122S: Opening 123:SiN layer 123D, 123S: Opening 124: Resist pattern 124D, 124S: Opening 131, 131D, 131S: n-type GaN layer 132D: Drain electrode 132S: Source electrode 141: Gate electrode 142: Insulating layer 143: Gate insulating film 200: Semiconductor device 210D, 210S: recessed 301: Substrate 310: Nitride semiconductor layer 310A: Surface 310D, 310S: recessed 310G:Aperture 311: Channel layer 311c: Channel region 312: Barrier layer 313: Cap layer 331, 331D, 331S: n-type GaN layer

Claims

[Claim 1] forming a first nitride semiconductor layer containing Ga on a substrate; forming a first silicon nitride layer on the first nitride semiconductor layer; forming a zinc oxide layer on the first silicon nitride layer; forming a second silicon nitride layer on the zinc oxide layer; forming openings in the second silicon nitride layer, the zinc oxide layer, and the first silicon nitride layer to expose the first nitride semiconductor layer; widening the opening formed in the zinc oxide layer; forming a second nitride semiconductor layer of a first conductivity type on a surface of the first nitride semiconductor layer exposed through the opening; removing the zinc oxide layer and the second silicon nitride layer using an acidic solution containing hydrochloric acid or phosphoric acid; forming an electrode on the second nitride semiconductor layer after the step of removing the zinc oxide layer; and A method for manufacturing a semiconductor device, wherein a surface of the first nitride semiconductor layer in contact with the second nitride semiconductor layer is an N-polar surface.

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