Method for manufacturing silicon carbide semiconductor device and method for manufacturing silicon carbide epitaxial substrate

Abstract

To provide a silicon carbide epitaxial substrate, a method for manufacturing a silicon carbide epitaxial substrate, a silicon carbide semiconductor device, and a method for manufacturing a silicon carbide semiconductor device that reduce conversion of BPD to through BPD.SOLUTION: A silicon carbide epitaxial substrate 100 includes a first conductivity type silicon carbide semiconductor substrate 1, a first conductivity type first semiconductor layer 2 with a lower impurity concentration than silicon carbide semiconductor substrate 1 provided on the front surface of the silicon carbide semiconductor substrate 1, and a foreign element high density region 24 having a higher density of a foreign element other than carbon and silicon than the silicon carbide semiconductor substrate 1 and provided at a predetermined depth from the front surface of the silicon carbide semiconductor substrate 1.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This invention is Method for manufacturing silicon carbide semiconductor device and Method for manufacturing silicon carbide epitaxial substrate By law Regarding. [Background technology]

[0002] Single-crystal silicon (Si) has traditionally been used as the material for power semiconductor devices that handle high voltages and large currents. There are several types of silicon power semiconductor devices, each tailored to its intended application. Examples of bipolar devices include PiN (P-intrinsic-N) diodes, bipolar transistors, and insulated gate bipolar transistors (IGBTs). While these devices can handle high current densities, they lack high-speed switching capabilities. Their operational limits are a few kHz for bipolar transistors and around 20 kHz for IGBTs. Meanwhile, power MOSFETs (metal oxide semiconductor field-effect transistors) cannot handle high currents, but they can operate at high speeds of up to several MHz. However, the market demand for power devices that combine high current and high speed has driven significant efforts to improve silicon IGBTs and power MOSFETs. Development has progressed to nearly the limits of silicon's physical properties.

[0003] Materials are also being considered from the perspective of power semiconductor elements, and silicon carbide (SiC) has recently attracted particular attention as a next-generation power semiconductor element due to its low on-state voltage and excellent high-speed and high-temperature characteristics. This is because SiC is a chemically very stable material, has a wide band gap of 3 eV, can be used extremely stably as a semiconductor even at high temperatures, and its maximum electric field strength is more than one order of magnitude greater than that of silicon. SiC has great potential to exceed the material limits of silicon, and there are high expectations for its future growth in power semiconductor applications.

[0004] 14 is a cross-sectional view showing the structure of a conventional silicon carbide epitaxial substrate. In a conventional silicon carbide semiconductor device, n-type epitaxial layers made of single crystal 4H—SiC (four-layer hexagonal silicon carbide) are + A silicon carbide epitaxial substrate 200 is used, in which an n-type silicon carbide epitaxial layer 102 is provided by epitaxial growth on the front surface of a silicon carbide substrate 101. Since the n-type silicon carbide epitaxial layer 102 is formed by epitaxial growth, it has high purity, and the dopant concentration and film thickness can be controlled to desired values. Device structures such as SBDs, MOSFETs, IGBTs, and PiN diodes are fabricated in this n-type silicon carbide epitaxial layer 102. Crystal defects such as basal plane dislocations (BPDs) 120 and 122 and threading edge dislocations (TEDs) 121 exist inside the silicon carbide epitaxial substrate. Summary of the Invention [Problem to be solved by the invention]

[0005] 15 is a cross-sectional view showing the structure of a conventional silicon carbide substrate. + The silicon carbide substrate 101 contains 10 defects called basal plane dislocations 120. 2 ~10 3 / cm 2 Most of the basal plane dislocations 120 are converted into threading edge dislocations 121 during epitaxial growth of the n-type silicon carbide epitaxial layer 102, but some become threading BPDs 122 that penetrate the n-type silicon carbide epitaxial layer 102 (see FIG. 14).

[0006] If a through-hole BPD 122 is present in the n-type silicon carbide epitaxial layer 102, when a device such as a MOSFET, IGBT, or PiN diode is operated in bipolar mode, a triangular stacking fault (SF) expands from the through-hole BPD 122 in the n-type silicon carbide epitaxial layer 102. The stacking fault acts as a resistance component, and therefore increases the forward on-state voltage in devices such as a MOSFET, IGBT, or PiN diode.

[0007] In order to solve the above-mentioned problems of the prior art, the present invention provides: High reliability Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device and a method for manufacturing a silicon carbide epitaxial substrate The purpose is to provide the following. [Means for solving the problem]

[0008] In order to solve the above-mentioned problems and achieve the object of the present invention, A method for manufacturing a silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type in contact with a back electrode, a semiconductor layer of a second conductivity type in contact with a front electrode, and a drift layer of the first conductivity type provided between the silicon carbide semiconductor substrate and the semiconductor layer and having a lower impurity concentration than the silicon carbide semiconductor substrate, the method comprising: a heterogeneous element implantation step of ion-implanting a heterogeneous element having a size different from that of carbon and silicon into the silicon carbide semiconductor substrate; and an impurity implantation step of ion-implanting an impurity of the second conductivity type into the silicon carbide semiconductor substrate, the heterogeneous element being any of hydrogen, magnesium, calcium, scandium, titanium, vanadium, chromium, manganese, and iron.

[0009] In order to solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a silicon carbide epitaxial substrate according to the present invention comprises: A method for manufacturing a silicon carbide epitaxial substrate comprising: a silicon carbide semiconductor substrate of a first conductivity type; and a silicon carbide epitaxial layer provided on the silicon carbide semiconductor substrate, the method comprising: a heterogeneous element implantation step of ion-implanting a heterogeneous element having a size different from that of carbon and silicon into the silicon carbide semiconductor substrate; and a step of heating the silicon carbide semiconductor substrate to 500°C or higher prior to the heterogeneous element implantation step, wherein the heterogeneous element is any one of hydrogen, magnesium, calcium, scandium, titanium, vanadium, chromium, manganese, and iron. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a cross-sectional view showing the structure of a silicon carbide epitaxial substrate according to an embodiment. [Figure 2] 1A to 1C are cross-sectional views (part 1) schematically illustrating a state during the manufacture of a silicon carbide epitaxial substrate according to an embodiment. [Figure 3] 4A and 4B are cross-sectional views (part 2) schematically illustrating a state during the manufacture of the silicon carbide epitaxial substrate according to the embodiment. [Figure 4] FIG. 1 is a diagram showing through-hole BPD conversion in a conventional silicon carbide epitaxial substrate. [Figure 5] 1 is a graph showing a temperature profile of an epitaxial growth furnace in a normal temperature rise. [Figure 6]1 is a graph showing a temperature profile of an epitaxial growth furnace with an annealing time. [Figure 7] 10 is a graph showing the relationship between annealing time and the number of penetrating BPDs. [Figure 8] FIG. 1 is a top view of a silicon carbide semiconductor substrate showing locations where through-hole BPDs have increased. [Figure 9] FIG. 1 is a diagram showing TED conversion in a silicon carbide epitaxial substrate according to an embodiment. [Figure 10] 1 is a cross-sectional view showing a structure of a silicon carbide semiconductor device according to an embodiment; [Figure 11] 1A to 1C are cross-sectional views (part 1) schematically showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment. [Figure 12] 5A and 5B are cross-sectional views (part 2) schematically showing a state during the manufacture of the silicon carbide semiconductor device according to the embodiment. [Figure 13] FIG. 1 is a cross-sectional view showing the structure of a trench silicon carbide MOSFET. [Figure 14] FIG. 1 is a cross-sectional view showing the structure of a conventional silicon carbide epitaxial substrate. [Figure 15] FIG. 1 is a cross-sectional view showing the structure of a conventional silicon carbide substrate. DETAILED DESCRIPTION OF THE INVENTION

[0012] The present invention will be described below with reference to the accompanying drawings. Method for manufacturing silicon carbide semiconductor device and Method for manufacturing silicon carbide epitaxial substrate of law Preferred embodiments will be described in detail. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - symbols attached to n or p indicate higher and lower impurity concentrations than layers and regions without these symbols, respectively. The same n or p symbol, including + and -, indicates similar concentrations, but does not necessarily mean that the concentrations are the same. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference numerals, and redundant explanations will be omitted.

[0013] (Embodiment) Of the silicon carbide epitaxial substrate, method for manufacturing the silicon carbide epitaxial substrate, silicon carbide semiconductor device, and method for manufacturing the silicon carbide semiconductor device according to the present invention, the silicon carbide epitaxial substrate will be described first. Fig. 1 is a cross-sectional view showing the structure of a silicon carbide epitaxial substrate according to an embodiment.

[0014] As shown in FIG. 1, a silicon carbide epitaxial substrate 100 has an n + The semiconductor device includes an n-type silicon carbide substrate 1 and an n-type silicon carbide epitaxial layer 2. The n-type silicon carbide epitaxial layer 2 is + The n-type silicon carbide substrate 1 is provided on the front surface thereof. + The semiconductor layer is formed by epitaxial growth and has a lower impurity concentration than the silicon carbide substrate 1.

[0015] n + The silicon carbide substrate 1 has an n-type + A different element high density region 24 is provided at a predetermined depth from the front surface of the silicon carbide substrate 1. The different element high density region 24 has a density of different elements 23 of n + It is a region that is higher than the silicon carbide substrate 1. The different element high density region 24 preferably has a film thickness h of, for example, 0.1 μm or more and 1 μm or less.

[0016] In the silicon carbide epitaxial substrate 100 of the embodiment, the foreign element 23 in the foreign element high density region 24 prevents the movement of the basal plane dislocations 20, and therefore, n + This increases the rate at which basal plane dislocations 20 in the silicon carbide substrate 1 are converted to threading edge dislocations 21, and decreases the rate at which they are converted to threading basal plane dislocations, thereby improving the BPD conversion efficiency. The BPD conversion efficiency is the rate at which basal plane dislocations 20 are converted to threading edge dislocations 21, and the higher the BPD conversion efficiency, the more basal plane dislocations 20 are converted to threading edge dislocations 21. As a result, the number of dislocations converted to threading basal plane dislocations decreases, the number of triangular stacking faults also decreases, and the increase in forward on-state voltage can be reduced.

[0017] The higher the density of the heterogeneous element 23, the greater the effect of preventing the movement of the basal plane dislocations 20. However, if the heterogeneous element 23 is introduced in excess, defects in the n-type silicon carbide epitaxial layer 2 formed thereon increase. 14 / cm 3 That's it, 1×10 18 / cm 3 It is preferable that:

[0018] The silicon carbide epitaxial substrate according to the embodiment is manufactured as follows. Figures 2 and 3 are cross-sectional views schematically showing the silicon carbide epitaxial substrate according to the embodiment in the course of its manufacture. First, n + A silicon carbide substrate 1 is prepared. + The silicon carbide substrate 1 contains defects called basal plane dislocations 20. 2 ~10 3 / cm 2 The state up to this point is depicted in Figure 2.

[0019] Next, n + The heterogeneous element 25 is ion-implanted from the front surface of the n-type silicon carbide substrate 1 to introduce the heterogeneous element 23 into the SiC crystal, thereby forming a heterogeneous element high density region 24. Examples of the heterogeneous element 25 that can be used include hydrogen, magnesium, calcium, scandium, titanium, vanadium, chromium, manganese, and iron. The heterogeneous element 25 preferably has a size significantly different from that of the silicon atoms and carbon atoms that constitute the silicon carbide. Furthermore, the ion-implantation of the heterogeneous element 25 is performed so that the heterogeneous element is n-type so that it is not removed by etching before epitaxially growing the n-type silicon carbide epitaxial layer 2. + It is preferable that the ions are implanted to a depth of 0.1 μm or more from the front surface of the silicon carbide substrate 1. The state up to this point is shown in FIG.

[0020] Next, n +A silicon carbide epitaxial layer to become n-type silicon carbide epitaxial layer 2 is deposited on silicon carbide substrate 1 while doping with nitrogen (N) as an n-type impurity. The surface on which n-type silicon carbide epitaxial layer 2 is formed may be the Si surface, the C surface, or any other surface, but in this embodiment, the Si surface is used. In this manner, silicon carbide epitaxial substrate 100 of the embodiment shown in FIG. 1 is manufactured.

[0021] Next, the model of through-hole BPDs proposed by the inventors will be described in detail. Fig. 4 is a diagram showing through-hole BPD conversion in a conventional silicon carbide epitaxial substrate. Figs. 4(a) to 4(d) are cross-sectional views of a silicon carbide epitaxial substrate 200. As shown in Fig. 4(a), n + Near the surface of the n-type silicon carbide substrate 101, there exists a BPD 120 consisting of two partial dislocations (Si(g)) and (C(g)) and a minute stacking fault (hatched area in FIG. 4(a)) between them. Next, as shown in FIG. 4(b), when thermal stress is applied before epitaxial growth of the n-type silicon carbide epitaxial layer 2, the Si-core partial dislocation Si(g) among the partial dislocations in the BPD 120 moves in the direction of arrow A, expanding the stacking fault. Next, as shown in FIG. 4(c), when the front surface is hydrogen-etched under the thermal stress, the surface is removed by hydrogen etching, but at the same time, the stacking fault expands below in the direction of arrow A. Next, as shown in FIG. 4(d), an n-type silicon carbide epitaxial layer (not shown) is epitaxially grown. In FIG. 4(d), the dotted line C indicates the n-type silicon carbide epitaxial layer. + 4(d) shows the interface between the n-type silicon carbide substrate 101 and the n-type silicon carbide epitaxial layer. As shown in FIG. 4(d), the stacking faults shrink slightly with the start of epitaxial growth, but do not shrink completely and become threading BPDs 122. On the other hand, if the stacking faults have shrunk sufficiently, cross-slip of partial dislocations occurs during epitaxial growth, converting them into TEDs.

[0022] To verify the model, the inventors investigated the extent to which BPDs penetrate due to thermal stress. Thermal stress was applied by the temperature distribution in the epitaxial growth furnace. The inventors applied thermal stress by providing an annealing time during the temperature rise for epitaxial growth, maintaining a constant temperature, and compared the number of penetrated BPDs. Figure 5 is a graph showing the temperature profile of an epitaxial growth furnace with a normal temperature rise, and Figure 6 is a graph showing the temperature profile of an epitaxial growth furnace with an annealing time. In Figures 5 and 6, the horizontal axis represents time in minutes, and the vertical axis represents temperature in degrees Celsius.

[0023] 5 shows the temperature profile during epitaxial growth of the n-type silicon carbide epitaxial layer 2. As shown in FIG. + The n-type silicon carbide substrate 1 is placed in an epitaxial growth furnace, heated to 1600° C., and etched with hydrogen (H 2 ). Then, an n-type silicon carbide epitaxial layer 2 is epitaxially grown, and the temperature is lowered after growth.

[0024] Figure 6 shows the temperature profile with an annealing time before epitaxial growth. + The silicon carbide substrate 1 is placed in an epitaxial growth furnace, heated to 900° C., and annealed for 60 minutes. + The n-type silicon carbide substrate 1 is placed in an epitaxial growth furnace, heated to 1600° C., and etched with hydrogen (H 2 ). Then, an n-type silicon carbide epitaxial layer 2 is epitaxially grown, and the temperature is lowered after growth.

[0025] Figure 7 is a graph showing the experimental relationship between annealing time and the number of through-hole BPDs. In Figure 7, the horizontal axis represents annealing time in minutes. The vertical axis represents the number of through-hole BPDs per semiconductor wafer in units of pieces. Figure 7 also shows the number of through-hole BPDs when the temperature and time of annealing before epitaxial growth are varied. As shown in Figure 7, the longer the annealing time, that is, the longer the thermal stress caused by annealing is applied, the more the number of through-hole BPDs per semiconductor wafer increases.

[0026] Furthermore, the inventors investigated the locations of increased through-hole BPDs within the wafer surface. Fig. 8 is a top view of a silicon carbide semiconductor substrate showing the locations of increased through-hole BPDs. Fig. 8 shows the difference in the area of ​​1 × 1.4 mm2 in a silicon carbide semiconductor substrate where annealing during temperature rise was performed at 1250°C for 30 minutes compared to a silicon carbide semiconductor substrate where annealing during temperature rise was not performed. 2 The rectangles in Fig. 8 show the areas where the number of threading BPDs increased by two or more. In Fig. 8, compared to the case where annealing was not performed during the temperature rise, the areas where the number of threading BPDs increased by two or more are concentrated in the circled areas.

[0027] Comparing the thermal stress distribution (not shown) calculated by the inventors from the temperature distribution within the wafer surface with Figure 8, it was found that the areas where the number of through-hole BPDs increased were areas with strong shear stress (thermal stress).From the above experimental results, the inventors verified that, for the proposed model, the longer the thermal stress caused by annealing is applied, the more the number of through-hole BPDs per semiconductor wafer increases.

[0028] Based on this model, the inventors then propose the following method for reducing threading BPDs. That is, by preventing partial dislocations from moving even when thermal stress is applied, the expansion of stacking faults is suppressed and the number of threading BPDs is reduced. To prevent the movement of partial dislocations, ions such as hydrogen, magnesium, calcium, scandium, titanium, vanadium, chromium, manganese, and iron are implanted to reduce the number of threading BPDs. + A heterogeneous element high density region 24 is formed in the silicon carbide substrate 1. As is well known in metallurgy, the dislocation glide motion is suppressed by the solid solution strengthening mechanism of the heterogeneous element. The more the size of the heterogeneous element differs from that of the target element, the more strongly the dislocation motion can be suppressed.

[0029] 9A to 9D are diagrams showing TED conversion in a silicon carbide epitaxial substrate according to an embodiment. FIGS. 9A to 9D are cross-sectional views of a silicon carbide epitaxial substrate 20. As shown in FIG. 9A, n +Near the surface of the n-type silicon carbide substrate 1, there are BPDs 20 consisting of two partial dislocations (Si(g)) and (C(g)) and a fine stacking fault (hatched portion in FIG. 9(a)) between them. Next, as shown in FIG. 9(b), even if thermal stress is applied before epitaxially growing the n-type silicon carbide epitaxial layer 2, in the silicon carbide epitaxial substrate according to the embodiment, the partial dislocations Si(g) do not move due to the solid solution strengthening mechanism of the heterogeneous element 23, so stacking faults do not expand. Next, as shown in FIG. 9(c), even if the front surface is hydrogen-etched while thermal stress is applied, the surface is removed by hydrogen etching, but the heterogeneous element 23 is not removed, remaining, and the pinning effect continues, so crystal defects do not expand. Next, as shown in FIG. 9(d), an n-type silicon carbide epitaxial layer (not shown) is epitaxially grown. In FIG. 9(d), the dotted line C indicates the n-type silicon carbide epitaxial layer. + 4(d), the interface between the n-type silicon carbide substrate 101 and the n-type silicon carbide epitaxial layer is shown. As the epitaxial growth begins, stacking faults are reduced and BPDs 20 are converted to TEDs 21.

[0030] As described above, the silicon carbide epitaxial substrate of the embodiment has n + A region with a high density of foreign elements is created within the silicon carbide substrate. The foreign elements act as obstacles to dislocation movement, preventing the movement of dislocations. This prevents the expansion of stacking faults in the BPDs even when thermal stress is applied, making it easier for the BPDs to be converted to TEDs, and improving the BPD conversion efficiency.

[0031] Next, a silicon carbide PiN diode will be described as an example of a silicon carbide semiconductor device using a silicon carbide epitaxial substrate according to the embodiment. Fig. 10 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the embodiment.

[0032] As shown in FIG. 10, the silicon carbide semiconductor device has n + The semiconductor device is constructed using a silicon carbide substrate in which an n-type silicon carbide epitaxial layer (first semiconductor layer of first conductivity type) 2 and a p-type silicon carbide layer (second semiconductor layer of second conductivity type) 3 are sequentially stacked on the front surface of a silicon carbide substrate (silicon carbide semiconductor substrate of first conductivity type) 1.

[0033] n + The silicon carbide substrate 1 is, for example, a silicon carbide single crystal substrate doped with nitrogen, and the polytypes of silicon carbide include 3C—SiC, 4H—SiC, and 6H—SiC. + The silicon carbide substrate 1 has an n-type + The density of the different element 23 at a predetermined depth from the front surface of the silicon carbide substrate 1 is n + A different element high density region 24 higher than that of the silicon carbide substrate 1 is provided.

[0034] The n-type silicon carbide epitaxial layer 2 is + The n-type silicon carbide epitaxial layer 2 is a p-type silicon carbide drift layer having a lower carrier concentration than the n-type silicon carbide substrate 1 and doped with, for example, nitrogen. + A cathode electrode 6 is provided on the back surface of the p-type silicon carbide substrate 1 , and an anode electrode 5 is provided on the surface of the p-type silicon carbide layer 3 .

[0035] Furthermore, n + Alternatively, a buffer layer serving as a short-lifetime layer for minority carriers may be provided between the p-type silicon carbide substrate 1 and the n-type silicon carbide epitaxial layer 2. The buffer layer may be, for example, a silicon carbide epitaxial layer doped with nitrogen (N) at a high concentration (hereinafter referred to as a high-density nitrogen layer), or a silicon carbide epitaxial layer co-doped with nitrogen and a different element such as boron (B), vanadium (V), titanium (Ti), iron (Fe), or chromium (Cr) (hereinafter referred to as a co-doped layer). By providing the buffer layer, holes injected from the p-layer recombine in the buffer layer, forming n-type silicon carbide epitaxial layers. + The silicon carbide substrate 1 is prevented from reaching the n-type silicon carbide substrate 1. + This can prevent stacking faults from occurring in silicon carbide substrate 1.

[0036] Furthermore, before ion implantation of a different element, annealing may be performed at a uniform temperature of 500°C or higher to sufficiently reduce stacking faults in the BPD. Stacking faults in SiC are unstable due to temperature, and are known to reduce at temperatures above 500°C in the absence of external stress or ultraviolet irradiation.

[0037] (Method for manufacturing silicon carbide semiconductor device according to embodiment) A method for manufacturing a silicon carbide semiconductor device according to an embodiment will be described by taking as an example a case where a PiN diode is fabricated using silicon carbide as a semiconductor material. Figures 11 and 12 are cross-sectional views showing a state during the fabrication of the silicon carbide semiconductor device according to the embodiment.

[0038] First, n + A silicon carbide substrate 1 is prepared, and as described above, a silicon carbide epitaxial substrate having a different element high density region 24 is manufactured (see FIGS. 2 and 3). The state up to this point is shown in FIG.

[0039] Next, a p-type silicon carbide layer 3 is deposited by epitaxial growth on the n-type silicon carbide epitaxial layer 2. Here, the p-type silicon carbide layer 3 can also be formed on the surface of the n-type silicon carbide epitaxial layer 2 by ion implantation of p-type impurities. The state up to this point is shown in FIG. 12. Next, activation annealing (heat treatment) is performed to activate the diffusion regions formed by ion implantation.

[0040] Next, for example, titanium (Ti) and aluminum (Al) are deposited on the surface of the p-type silicon carbide layer 3 to form an anode electrode 5. Next, for example, nickel (Ni) is deposited on the surface of the p-type silicon carbide layer 3 to form an n-type silicon carbide layer 5. + A film is formed on the rear surface of the silicon carbide substrate 1 and heat-treated to form the cathode electrode 6. In this way, the vertical PiN diode shown in FIG.

[0041] Although the above embodiments have been described taking PiN diodes as examples, the present invention is also applicable to built-in diodes in silicon carbide MOSFETs. Fig. 13 is a cross-sectional view showing the structure of a trench type silicon carbide MOSFET.

[0042] In FIG. 13, the reference numerals 31 to 42 and 48 respectively represent n + Silicon carbide substrate, n - Drift layer, 1p + Type region, 2nd p + type region, n-type region, p-type base layer, n + Type source region, p + The gate electrode, the interlayer insulating film, the source electrode, and the trench are also included in the trench-type silicon carbide MOSFET. + The silicon carbide substrate 31 has an n-type + The density of the different element 23 at a predetermined depth from the front surface of the silicon carbide substrate 1 is n + A higher heterogeneous element density region 24 than that of the silicon carbide substrate 31 is provided. A vertical MOSFET having such a trench gate structure has a p-type base layer 36 and an n-type base layer 37 as a body diode between the source and drain. - The semiconductor device includes a built-in diode (parasitic pn diode) formed by the semiconductor layer and the type drift layer 32.

[0043] In such a MOSFET, in addition to a mode in which current flows through the MOS channel (synchronous rectification mode), there is also a mode in which current flows through the built-in diode (bipolar mode) as shown by arrow A in Figure 13. As with the PiN diode, in bipolar mode, - When the hole density in the drift layer 32 exceeds a predetermined value, n - Stacking faults expand due to the through-hole BPD in the type drift layer 32, and the resistance of the element increases, causing a deterioration in the forward voltage (Vf).

[0044] For this reason, in the embodiment, a silicon carbide epitaxial substrate having a heterogeneous element high density region with improved BPD conversion efficiency is used. As a result, in the MOSFET as well as in the PiN diode, +This can suppress the occurrence of stacking faults in silicon carbide substrate 31, thereby suppressing performance degradation.

[0045] Furthermore, as in the case of PiN diodes, + The silicon carbide substrate 31 and the n - A buffer layer serving as a short-lifetime layer for minority carriers may be provided between the pn-type drift layer 32 and the n-type drift layer 33. The buffer layer may be a high-density nitrogen layer or a co-doped layer. By providing a buffer layer, holes injected from the pn interface recombine in the buffer layer, forming n + The silicon carbide substrate 31 is prevented from reaching the n-type silicon carbide substrate 31. + This can prevent stacking faults from occurring in silicon carbide substrate 31.

[0046] As described above, the silicon carbide device according to the embodiment uses a silicon carbide epitaxial substrate having a hetero-element high density region with improved BPD conversion efficiency, thereby suppressing the expansion of stacking faults even when a high current is applied in the forward direction of the silicon carbide semiconductor device. Therefore, a highly reliable silicon carbide semiconductor device can be provided in which the forward on-state voltage does not increase.

[0047] The present invention can be modified in various ways without departing from the spirit of the present invention, and in each of the above-described embodiments, for example, the dimensions of each part and the impurity concentration are variously set according to the required specifications, etc. Also, in each of the embodiments of the present invention, the first conductivity type is p-type and the second conductivity type is n-type, but the present invention is equally valid even if the first conductivity type is n-type and the second conductivity type is p-type. [Industrial Applicability]

[0048] As described above, the present invention Method for manufacturing silicon carbide semiconductor device and Method for manufacturing silicon carbide epitaxial substrate The law The present invention is useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices for various industrial machines, inverters for electric vehicles, and the like. [Explanation of symbols]

[0049] 1, 101 n + Silicon carbide substrate 2, 102 n-type silicon carbide epitaxial layer 3 p-type silicon carbide layer 5 Anode electrode 6 cathode electrode 20, 120 Basal plane dislocations (BPDs) 21, 121 Threading edge dislocation (TED) 22, 122 Threading basal plane dislocations (threading BPDs) 23 Foreign elements in SiC 24 High density region of different elements 25 Different elements 31n + Silicon carbide substrate 32n - Mold drift layer 33 1st p. + type area 34 2nd p. + type area 35 n-type region 36 p-type base layer 37n + Type Source Area 38 pages + Mold contact area 39 Gate insulating film 40 gate electrode 41 Interlayer insulating film 42 Source electrode 48 Trench 100, 200 Silicon carbide epitaxial substrate

Claims

1. A method for manufacturing a silicon carbide semiconductor device comprising: a silicon carbide semiconductor substrate of a first conductivity type in contact with a back surface electrode; a semiconductor layer of a second conductivity type in contact with a front surface electrode; and a drift layer of the first conductivity type provided between the silicon carbide semiconductor substrate and the semiconductor layer, the drift layer having a lower impurity concentration than the silicon carbide semiconductor substrate, a heterogeneous element implantation step of ion-implanting a heterogeneous element other than carbon and silicon into the silicon carbide semiconductor substrate; an impurity implantation step of forming the semiconductor layer by ion implantation of impurities of a second conductivity type; Including, 2. A method for manufacturing a silicon carbide semiconductor device, wherein the different element is any one of hydrogen, magnesium, calcium, scandium, titanium, vanadium, chromium, manganese, and iron.

2. 2. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the silicon carbide semiconductor device is a PiN diode or a MOSFET.

3. 3. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein a solid solution strengthening mechanism is formed by the different element implantation step.

4. 4. The method for manufacturing a silicon carbide semiconductor device according to claim 1, further comprising an annealing step after the different element implantation step and the impurity implantation step.

5. 5. The method for manufacturing a silicon carbide semiconductor device according to claim 1, further comprising the step of heating the silicon carbide semiconductor substrate to 500° C. or higher before the step of implanting the different element.

6. the drift layer is a silicon carbide epitaxial layer formed by epitaxially growing the silicon carbide semiconductor substrate, 6. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the semiconductor layer is formed by the ion implantation into the silicon carbide epitaxial layer.

7. 7. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein in the different element implantation step, the different element high density region having a high density of the different element is formed to a thickness of 0.1 μm or more and 1.0 μm or less.

8. 8. The method for manufacturing a silicon carbide semiconductor device according to claim 7, wherein the different element high density region is present at an interface between the silicon carbide semiconductor substrate and the drift layer.

9. 9. The method for manufacturing a silicon carbide semiconductor device according to claim 1, further comprising the step of hydrogen etching a front surface of the silicon carbide semiconductor substrate.

10. 10. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the different element implantation step comprises ion-implanting the different element to a depth of at least 0.1 μm or more from the front surface of the silicon carbide semiconductor substrate.

11. The method for manufacturing a silicon carbide semiconductor device according to claim 7, wherein the different element high density region has a different element density of 1×10 14 / cm 3 or more and 1×10 18 / cm 3 or less.

12. A method for manufacturing a silicon carbide semiconductor device described in any one of claims 1 to 11, characterized in that it includes a step of forming a buffer layer of a first conductivity type between the silicon carbide semiconductor substrate and the drift layer.

13. A method for manufacturing a silicon carbide epitaxial substrate comprising: a silicon carbide semiconductor substrate of a first conductivity type; and a silicon carbide epitaxial layer provided on the silicon carbide semiconductor substrate, comprising: a heterogeneous element implantation step of ion-implanting a heterogeneous element other than carbon and silicon into the silicon carbide semiconductor substrate; a step of heating the silicon carbide semiconductor substrate to 500° C. or higher before the step of implanting the different element; Including, 2. A method for producing a silicon carbide epitaxial substrate, wherein the different element is any one of hydrogen, magnesium, calcium, scandium, titanium, vanadium, chromium, manganese, and iron.

Images