Semiconductor Devices

Abstract

In the present invention, an adhesive layer including a first metal region is disposed in at least a portion of the region of the top surface of a support substrate. A ground layer that includes a sub-collector region made from an electrically conductive semiconductor material that is electrically connected to the first metal region is disposed on the adhesive layer. A first transistor that includes a collector layer that is electrically connected to the sub-collector region, a base layer that is disposed on the collector layer, and an emitter layer that is disposed on the base layer is disposed on the sub-collector region. A collector electrode that is electrically connected to the sub-collector region is disposed at a position that is outside the first transistor in the plan view, and that overlaps the first metal region on the sub-collector region.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] A semiconductor device is known in which a semi-insulating GaAs substrate is bonded onto a Si substrate via a bonding layer such as an Au film (Patent Document 1). An n-type sub-collector layer is disposed on the semi-insulating GaAs substrate, and a heterojunction bipolar transistor (HBT) is disposed on the n-type sub-collector layer. In addition to the HBT, a collector electrode is disposed on the n-type sub-collector layer. The collector electrode is connected to the collector layer of the HBT via the n-type sub-collector layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-2644 Summary of the Invention [Problem to be solved by the invention]

[0004] In conventional semiconductor devices, the collector electrode is connected to the collector layer via a sub-collector layer. The n-type sub-collector layer is a semiconductor layer that is heavily doped with n-type dopants to reduce its resistance, but its resistance is higher than that of metal, and the parasitic resistance that occurs between the collector electrode and collector layer prevents improvements in the operating speed of the transistor.

[0005] An object of the present invention is to provide a semiconductor device capable of reducing the parasitic resistance between the collector electrode and the collector layer and improving the operating speed of the transistor. [Means for solving the problem]

[0006] According to one aspect of the present invention, A support substrate; an adhesive layer including a first metal region disposed on at least a portion of an upper surface of the support substrate; an underlayer disposed on the adhesion layer and including a subcollector region made of a conductive semiconductor material electrically connected to the first metal region; a first transistor including a collector layer disposed above the sub-collector region and electrically connected to the sub-collector region, a base layer disposed above the collector layer, and an emitter layer disposed above the base layer; a collector electrode disposed on the sub-collector region, outside the first transistor in a plan view, and at a position overlapping the first metal region, the collector electrode being electrically connected to the sub-collector region; Equipped with 、 the adhesion layer further includes at least one second metal region electrically isolated from the first metal region; The semiconductor device further includes an insulating region made of oxide or nitride, which is disposed between the first metal region and the second metal region in a plan view. A semiconductor device is provided. [Effects of the Invention]

[0007] Since the first metal region is connected to the sub-collector region, the parasitic resistance between the collector layer and the collector electrode of the first transistor is reduced, thereby improving the operating speed of the first transistor. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along the dashed line 2-2 in FIG. [Figure 3] 3A to 3F are schematic cross-sectional views of a semiconductor device at intermediate stages in its manufacture. [Figure 4] 4A, 4B, and 4C are schematic cross-sectional views of a semiconductor device at intermediate stages in its manufacture, and FIG. 4D is a schematic cross-sectional view of the completed semiconductor device. [Figure 5] FIG. 5 is a schematic diagram of a first transistor of the semiconductor device according to the first embodiment. [Figure 6]FIG. 6 is a cross-sectional view of a semiconductor device according to the second embodiment. [Figure 7] 7A, 7B, and 7C are cross-sectional views of the semiconductor device according to the second embodiment during the manufacturing process. [Figure 8] FIG. 8 is a diagram schematically showing a cross-sectional structure of a semiconductor device according to a third embodiment. [Figure 9] FIG. 9 is a diagram schematically showing a cross-sectional structure of a semiconductor device according to a third embodiment. [Figure 10] FIG. 10 is a diagram schematically showing a cross-sectional structure of a semiconductor device according to a fourth embodiment. [Figure 11] FIG. 11 is a diagram schematically showing a cross-sectional structure of a semiconductor device according to a fifth embodiment. [Figure 12] FIG. 12 is an equivalent circuit diagram of the semiconductor device according to the sixth embodiment. [Figure 13] FIG. 13 is a diagram schematically showing a cross-sectional structure of a semiconductor device according to a sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] [First Example] A semiconductor device according to a first embodiment will be described with reference to FIGS. 1 to 5. FIG. Fig. 1 is a schematic plan view of a semiconductor device according to a first embodiment. An adhesive layer 21 including a metal region 21A is disposed on a support substrate 20, which will be described later with reference to Fig. 2. A sub-collector region 40A made of a semiconductor material is disposed so as to substantially overlap with the metal region 21A. A plurality of first transistors 41 are disposed on the sub-collector region 40A, lined up in one direction (the vertical direction in Fig. 1), for example.

[0010] Each of the first transistors 41 includes a collector layer 41C, a base layer 41B, and an emitter layer 41E. The collector layer 41C and the base layer 41B substantially overlap in a plan view. The emitter layer 41E is smaller than the base layer 41B in a plan view and is included in the base layer 41B.

[0011] The emitter electrode 42E is disposed so as to substantially overlap the emitter layer 41E in a planar view. The emitter electrode 42E has a shape that is long in a direction perpendicular to the arrangement direction of the first transistors 41 (the left-right direction in FIG. 1) in a planar view. The emitter electrode 42E has, for example, a rectangular shape in a planar view. In a planar view, U-shaped base electrodes 42B are disposed at intervals from each of two long sides and one short side of the emitter electrode 42E. The base electrodes 42B all open in the same direction (toward the right in FIG. 1).

[0012] A collector electrode 42C is disposed between two adjacent first transistors 41 and on the outside of each of the first transistors 41 on both ends. In Fig. 1, the emitter electrode 42E, the base electrode 42B, and the collector electrode 42C are indicated by relatively dark hatching sloping upward to the right.

[0013] A first-layer base wiring 43B is connected to each of the multiple base electrodes 42B at a distance from the short side of the emitter electrode 42E. Each of the base wirings 43B extends away from the emitter electrode 42E to the outside of the sub-collector region 40A. In a plan view, each of the base wirings 43B intersects with a common second-layer base wiring 44B. An input capacitor Cin is formed at the intersection of each of the first-layer base wirings 43B and the second-layer base wiring 44B. A high-frequency signal is input from the second-layer base wiring 44B to the base electrode 42B via the input capacitor Cin and the first-layer base wiring 43B.

[0014] A first-layer collector wiring 43C is connected to each of the multiple collector electrodes 42C. The collector wiring 43C extends from the point where it overlaps with each of the collector electrodes 42C in the opposite direction to the direction in which the base wiring 43B extends, and is connected to each other outside the sub-collector region 40A. In FIG. 1, the base wiring 43B and the collector wiring 43C are indicated by relatively light hatching slanting downward to the right. The first-layer emitter wiring 43E is arranged so as to substantially overlap each of the emitter electrodes 42E.

[0015] A second-layer emitter wiring 44E is arranged so as to overlap all of the emitter wirings 43E, from the emitter wiring 43E at one end in the arrangement direction of the first transistors 41 to the emitter wiring 43E at the other end. The second-layer emitter wiring 44E connects the plurality of emitter wirings 43E in the first layer to each other. In this manner, the emitters of the plurality of first transistors 41 are connected to each other, and the collectors are connected to each other, so that the plurality of first transistors 41 are connected in parallel. The second-layer collector wiring 44C is arranged so as to overlap the collector wiring 43C outside the sub-collector region 40A. In FIG. 1, the emitter wiring 44E, collector wiring 44C, and base wiring 44B in the second layer are indicated by relatively thick outlines.

[0016] FIG. 2 is a cross-sectional view taken along dashed line 2-2 in FIG. 1. An adhesive layer 21 is disposed on a support substrate 20. The adhesive layer 21 includes at least one metal region 21A. FIG. 2 shows a cross-section of one metal region 21A of the adhesive layer 21. For example, a high-resistivity silicon substrate can be used as the support substrate 20. For example, an Au film can be used as the adhesive layer 21. Note that instead of Au, a metal film containing Ag, Pt, Cu, Al, W, Ti, or Ta may also be used.

[0017] An underlayer 40 made of a semiconductor material is bonded to the adhesive layer 21. The underlayer 40 includes a sub-collector region 40A that is made conductive and an insulated element isolation region. FIG. 2 shows a cross section of the sub-collector region 40A, but not the element isolation region. A plurality of first transistors 41 are disposed on the sub-collector region 40A.

[0018] Each of the first transistors 41 includes a collector layer 41C, a base layer 41B, and an emitter layer 41E stacked in this order on the base layer 40. The first transistors 41 are, for example, heterojunction bipolar transistors. As an example, the subcollector region 40A and the collector layer 41C of the base layer 40 are formed of n-type GaAs, and the base layer 41B is formed of p-type GaAs. The emitter layer 41E includes, for example, two layers: an n-type InGaP layer and an n-type GaAs layer thereon. Note that these semiconductor layers may also be formed of other compound semiconductors, such as InP, GaN, SiGe, or SiC.

[0019] A plurality of collector electrodes 42C are arranged on the sub-collector region 40A so as to sandwich the first transistors 41. One collector electrode 42C is arranged between two adjacent first transistors 41, and is shared by the first transistors 41 on both sides.

[0020] The collector electrode 42C is electrically connected to the collector layer 41C via the sub-collector region 40A. The sub-collector region 40A is also electrically connected to the underlying metal region 21A. Here, the state in which the sub-collector region 40A is electrically connected to the metal region 21A includes a state in which the two are in ohmic contact, and a state in which the two are in Schottky contact but the Schottky barrier is sufficiently thin to be considered substantially ohmic contact. For example, if the sub-collector region 40A is made of highly doped n-type GaAs and the two are in Schottky contact, the Schottky barrier will be sufficiently thin. A first-layer collector wiring 43C is disposed on each of the collector electrodes 42C via an interlayer insulating film (not shown). The collector wiring 43C is connected to the collector electrode 42C through an opening in the interlayer insulating film.

[0021] The emitter layer 41E is disposed on a partial region of the base layer 41B. Alternatively, a ledge structure may be formed in which the emitter layer 41E is disposed on the entire base layer 41B and an emitter mesa is disposed on a partial region of the emitter layer 41E. In this configuration, the region overlapping with the emitter mesa in a plan view essentially functions as the emitter layer.

[0022] A base electrode 42B is disposed on the base layer 41B, and an emitter electrode 42E is disposed on the emitter layer 41E. The base electrode 42B is electrically connected to the base layer 41B, and the emitter electrode 42E is electrically connected to the emitter layer 41E.

[0023] A first-layer emitter wiring 43E is disposed on each of the emitter electrodes 42E via an interlayer insulating film (not shown). The emitter wiring 43E passes through an opening provided in the interlayer insulating film and is electrically connected to the emitter electrode 42E.

[0024] A single emitter wiring 44E in the second layer is disposed on a plurality of emitter wirings 43E in the first layer via an interlayer insulating film (not shown). The emitter wiring 44E in the second layer is connected to the plurality of emitter wirings 43E in the first layer through an opening provided in the interlayer insulating film. An emitter pad 82E is disposed on the emitter wiring 44E, and an emitter protrusion electrode 83E is disposed thereon. For example, a Cu pillar bump is used as the emitter protrusion electrode 83E. Solder 84 is placed on the emitter protrusion electrode 83E.

[0025] Next, a method for manufacturing a semiconductor device according to a first embodiment will be described with reference to Figures 3A to 4D. Figures 3A to 4C are schematic cross-sectional views of a semiconductor device at intermediate stages in its manufacture, and Figure 4D is a schematic cross-sectional view of the completed semiconductor device.

[0026] As shown in FIG. 3A, a release layer 201 is epitaxially grown on a mother substrate 200 made of a single crystal of a compound semiconductor such as GaAs, and an element formation layer 202 is formed on the release layer 201. The element structure from the base layer 40 shown in FIG. 2 to the second-layer emitter wiring 44E is formed in the element formation layer 202. These element structures are formed by a general semiconductor process. In FIG. 3A, the element structure formed in the element formation layer 202 is omitted. At this stage, the element structures corresponding to multiple semiconductor devices are formed in the element formation layer 202 and have not been separated into individual semiconductor devices. Furthermore, the emitter pads 82E, emitter protruding electrodes 83E, and solder 84 (FIG. 2) have not yet been formed.

[0027] 3B, a resist pattern (not shown) is used as an etching mask to pattern the element formation layer 202 and the release layer 201. At this stage, the element formation layer 202 is separated into individual semiconductor devices.

[0028] Next, as shown in Fig. 3C, connecting supports 204 are attached onto the separated element formation layers 202. As a result, the multiple element formation layers 202 are connected to each other via the connecting supports 204. Note that the resist pattern used as an etching mask in the patterning step of Fig. 3B may be left, and a resist pattern may be interposed between the element formation layers 202 and the connecting supports 204.

[0029] 3D, the release layer 201 is selectively etched with respect to the mother substrate 200 and the element formation layer 202. As a result, the element formation layer 202 and the connecting support 204 are peeled off from the mother substrate 200. In order to selectively etch the release layer 201, a compound semiconductor having an etching resistance different from that of both the mother substrate 200 and the element formation layer 202 is used as the release layer 201.

[0030] As shown in FIG. 3E, an adhesive layer 21 is formed on the upper surface of a support substrate 20. The adhesive layer 21 includes a plurality of metal regions 21A distributed within the surface and insulating regions 21Z disposed in regions where the metal regions 21A are not disposed. The adhesive layer 21 can be formed, for example, by a damascene process. The insulating regions 21Z are formed, for example, of an insulating oxide or nitride, specifically, silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0031] As shown in FIG. 3F, the element formation layer 202 is bonded to the adhesive layer 21. The element formation layer 202 and the adhesive layer 21 are bonded by van der Waals bonding or hydrogen bonding. Alternatively, the element formation layer 202 may be bonded to the adhesive layer 21 by electrostatic force, covalent bonding, eutectic alloy bonding, or the like. For example, if the metal region 21A is made of Au, the element formation layer 202 may be bonded to the Au film by adhering the element formation layer 202 to the Au film and applying pressure.

[0032] Next, as shown in Fig. 4A, the connecting support 204 is peeled off from the element formation layer 202. After the connecting support 204 is peeled off, as shown in Fig. 4B, an interlayer insulating film 86 and a rewiring layer are formed on the adhesive layer 21 and the element formation layer 202. The rewiring layer includes an emitter pad 82E arranged on the emitter wiring 44E (Fig. 2), an interconnection wiring 82W that connects a circuit included in the element formation layer 202 to one metal region of the adhesive layer 21, and the like.

[0033] Next, as shown in FIG. 4C, a protective film 87 is formed on the rewiring layer including the emitter pads 82E, interconnection wiring 82W, etc., and a plurality of openings 87A are formed in the protective film 87. Each of the plurality of openings 87A is encompassed by a plurality of emitter pads 82E in a plan view. An emitter protrusion electrode 83E is formed in the opening 87A. The emitter protrusion electrode 83E extends onto the protective film 87 around the opening 87A. The emitter protrusion electrode 83E protrudes in a direction away from the support substrate 20. Furthermore, solder 84 is placed on the top surface of the emitter protrusion electrode 83E, and a reflow process is performed.

[0034] Finally, as shown in Fig. 4D, the support substrate 20 is diced. This results in individual semiconductor devices 28 each including the support substrate 20, the adhesive layer 21, the element formation layer 202, the emitter pads 82E, the emitter protrusion electrodes 83E, the interconnection wiring 82W, and the like. In the individual semiconductor devices 28, the support substrate 20 is larger than the element formation layer 202 in plan view. The individual semiconductor devices are flip-chip mounted on a module substrate or the like.

[0035] Next, the advantageous effects of the first embodiment will be described with reference to FIG. 5. FIG. 5 is a schematic diagram of a first transistor 41 of a semiconductor device according to the first embodiment. A collector electrode 42C contacts one surface of a sub-collector region 40A, and a metal region 21A contacts the other surface. When the first transistor 41 is in operation, a current flows from the collector electrode 42C, which contacts one surface of the sub-collector region 40A, through the sub-collector region 40A, the collector layer 41C, the base layer 41B, and the emitter layer 41E to the emitter electrode 42E. The parasitic resistance of the sub-collector region 40A is denoted as R1.

[0036] The resistance component R2 of the metal region 21A in contact with the other surface of the sub-collector region 40A is connected in parallel to the parasitic resistance R1 of the sub-collector region 40A. This reduces the parasitic resistance between the collector electrode 42C and the collector layer 41C. This reduction in parasitic resistance increases the operating frequency of the first transistor 41. In this way, the adhesive layer 21 not only functions to bond the support substrate 20 and the element formation layer 202 (see FIG. 4A, etc.), but also functions to reduce the parasitic resistance between the collector electrode 42C and the collector layer 41C of the first transistor 41.

[0037] Next, another excellent effect of the semiconductor device according to the first embodiment will be described. During the manufacturing process of the semiconductor device according to the first embodiment (FIG. 3B), electrodes connected to the second-layer emitter wiring 44E, collector wiring 44C, and base wiring 44B (FIG. 1) are exposed on the surface of the element formation layer 202. Therefore, before the element formation layer 202 is bonded to the support substrate 20, probes can be brought into contact with these electrodes to perform an evaluation test of the first transistor 41.

[0038] Furthermore, in the semiconductor device according to the first embodiment (FIG. 2), heat generated in the first transistor 41 is conducted to the support substrate 20 via the adhesive layer 21, and also to the module substrate on which the semiconductor device is mounted via the emitter wirings 43E, 44E, the emitter protruding electrode 83E, and the like. Because heat generated in the first transistor 41 is conducted in two directions, upward and downward, heat dissipation from the first transistor 41 can be improved. To improve heat dissipation, it is preferable to use a material for the support substrate 20 that has a higher thermal conductivity than the semiconductor materials constituting the collector layer 41C, base layer 41B, and emitter layer 41E of the first transistor 41, and the semiconductor material constituting the sub-collector region 40A. In the first embodiment, the thermal conductivity of Si, the material for the support substrate 20, is higher than the thermal conductivity of GaAs, the material for the collector layer 41C, base layer 41B, and sub-collector region 40A, and InGaP, the material for the emitter layer 41E. Therefore, the heat dissipation from the first transistor 41 can be sufficiently improved.

[0039] [Second Example] Next, a semiconductor device according to a second embodiment will be described with reference to Figures 6 to 7C. Below, a description of the configuration common to the semiconductor device according to the first embodiment described with reference to Figures 1 to 5 will be omitted.

[0040] 6 is a cross-sectional view of a semiconductor device according to a second embodiment. In the semiconductor device according to the first embodiment (FIG. 1), the adhesive layer 21 includes at least one single-layer metal region 21A. In contrast, in the semiconductor device according to the second embodiment, the adhesive layer 21 includes two layers: a lower adhesive layer 21L on the support substrate 20 side and an upper adhesive layer 21U on the base layer 40 side.

[0041] The lower adhesive layer 21L includes at least one metal region 21LA, and the upper adhesive layer 21U includes at least one metal region 21UA. In a plan view, the metal region 21LA of the lower adhesive layer 21L and the metal region 21UA of the upper adhesive layer 21U overlap each other and are bonded together. The metal regions 21LA and 21UA may be made of, for example, Au, Ag, Pt, Cu, Al, W, Ti, or Ta. The metal region 21LA and the metal region 21UA may be made of the same metal or different metals. The subcollector region 40A of the underlayer 40 is electrically connected to the metal region 21UA of the upper adhesive layer 21U. In addition, the structure in which the metal region 21UA of the upper adhesive layer 21U and the metal region 21LA of the lower adhesive layer 21L are bonded includes a structure in which the two are in contact with each other without any gaps over their entire area, and a structure in which a gap is formed between some areas of the metal region 21UA of the upper adhesive layer 21U and some areas of the metal region 21LA of the lower adhesive layer 21L, and they are in contact in other areas.

[0042] Next, a method for manufacturing a semiconductor device according to a second embodiment will be described with reference to Figures 7A, 7B, and 7C. Figures 7A, 7B, and 7C are cross-sectional views of a semiconductor device according to the second embodiment at intermediate stages of manufacture. The configuration shown in Figure 7A is the same as the configuration of the first embodiment at intermediate stages of manufacture shown in Figure 3D. In the first embodiment, the element formation layer 202 is bonded to the support substrate 20 by being in close contact with the metal region 21A (Figure 3F) of the adhesive layer 21. In contrast, in the second embodiment, as shown in Figure 7B, an upper adhesive layer 21U is formed on the surface of the element formation layer 202 (the lower surface of the base layer 40 in Figure 6).

[0043] The upper adhesive layer 21U can be formed by depositing a metal film using, for example, vacuum deposition, sputtering, etc., and then etching away unnecessary portions. Alternatively, a lift-off method may be used.

[0044] As shown in FIG. 7C, a lower adhesive layer 21L is formed on the support substrate 20. The lower adhesive layer 21L can be formed in the same manner as described with reference to FIG. 3E in the first embodiment. The metal region 21UA of the upper adhesive layer 21U is brought into close contact with the metal region 21LA of the lower adhesive layer 21L, and the two are bonded together. The subsequent procedures are the same as those described with reference to FIGS. 4A to 4D in the first embodiment.

[0045] Next, the excellent effects of the second embodiment will be described. 7C, the element formation layer 202 is bonded to the support substrate 20 by bringing metals into contact with each other. This makes the bonding process easier than when bonding by bringing a metal into contact with a semiconductor.

[0046] Furthermore, since the formation of the upper adhesive layer 21U shown in FIG. 7B is performed in a clean environment such as a vacuum chamber, the interface between the underlayer 40 (FIG. 6) and the upper adhesive layer 21U (FIG. 6) can be maintained in a clean state. As a result, the contact resistance between the sub-collector region 40A of the underlayer 40 and the metal region 21UA of the upper adhesive layer 21U can be reduced. This further reduces the resistance component R2 connected in parallel to the parasitic resistance R1 (FIG. 5) of the sub-collector region 40A. This enhances the effect of reducing the parasitic resistance between the collector layer 41C and the collector electrode 42C.

[0047] [Third Example] Next, a semiconductor device according to a third embodiment will be described with reference to Figures 8 and 9. Below, a description of the configuration common to the semiconductor device according to the first embodiment described with reference to Figures 1 to 5 will be omitted.

[0048] 8 and 9 are diagrams showing a cross-sectional structure of a semiconductor device according to a third embodiment. It should be noted that FIGS. 8 and 9 do not show a cross section of the semiconductor device cut along a particular plane, but rather show a schematic view of the structure in the stacking direction and in-plane direction. In the first embodiment, a plurality of first transistors 41 are disposed on an underlayer 40. In contrast, in the third embodiment, in addition to the plurality of first transistors 41, a second transistor 61 and a diode 71 are disposed on the underlayer 40. Although FIG. 8 shows one first transistor and FIG. 9 shows two first transistors 41, the number of first transistors 41 may be three or more.

[0049] In the first embodiment, one collector electrode 42C (FIG. 2) is arranged between two first transistors 41, and one collector electrode 42C is shared by the first transistors 41 on both sides. In the third embodiment, as shown in FIG. 9, two collector electrodes 42C are arranged between two first transistors 41. That is, two collector electrodes 42C are arranged for each first transistor 41.

[0050] Similar to the second embodiment (FIG. 6), the adhesive layer 21 has a two-layer structure consisting of a lower adhesive layer 21L and an upper adhesive layer 21U. The lower adhesive layer 21L includes metal regions 21LB and 21LC in addition to the metal region 21LA. The metal regions 21LA, 21LB, and 21LC are electrically isolated from one another by an insulating region 21Z. The upper adhesive layer 21U includes metal regions 21UB and 21UC in addition to the metal region 21UA. The metal regions 21UA, 21UB, and 21UC are isolated from one another in the in-plane direction by cavities. The multiple metal regions 21LA, 21LB, and 21LC of the lower adhesive layer 21L may also be isolated from one another by cavities. The multiple metal regions 21UA, 21UB, and 21UC of the upper adhesive layer 21U may also be electrically isolated from one another by insulating regions.

[0051] In addition to the sub-collector region 40A, the base layer 40 includes a sub-collector region 40B and a conductive region 40C. The sub-collector regions 40A, 40B, and the conductive region 40C are isolated from one another by an element isolation region 40Z. The element isolation region 40Z is formed by, for example, performing ion implantation into the base layer 40 made of n-type GaAs to increase its resistance.

[0052] Subcollector region 40A and metal regions 21UA and 21LA overlap and are electrically connected to each other in a planar view. Similarly, subcollector region 40B and metal regions 21UB and 21LB overlap and are electrically connected to each other in a planar view, and conductive region 40C and metal regions 21UC and 21LC overlap and are electrically connected to each other in a planar view. Here, "components A, B, and C overlap" means that at least a portion of component A, at least a portion of component B, and at least a portion of component C overlap in a planar view. Two components can be said to overlap each other when one component is contained within another component in a planar view, or when the perimeters of the two components coincide.

[0053] The second transistor 61 is disposed on the sub-collector region 40B and, like the first transistor 41, includes a collector layer 61C, a base layer 61B, and an emitter layer 61E. A collector electrode 62C disposed on the sub-collector region 40B is electrically connected to the collector layer 61C via the sub-collector region 40B. A base electrode 62B is connected to the base layer 61B, and an emitter electrode 62E is connected to the emitter layer 61E. A first-layer collector wiring 63C is connected to the collector electrode 62C, and a first-layer emitter wiring 63E is connected to the emitter electrode 62E. The emitter electrode 62E of the second transistor 61 is not connected to a protruding electrode.

[0054] The diode 71 is disposed on the conductive region 40C and includes a cathode layer 71C made of n-type GaAs and an anode layer 71A made of p-type GaAs. The collector layer 41C of the first transistor 41, the collector layer 61C of the second transistor 61, and the cathode layer 71C of the diode 71 are formed by patterning a common n-type GaAs layer. The base layer 41B of the first transistor 41, the base layer 61B of the second transistor 61, and the anode layer 71A of the diode 71 are formed by patterning a common p-type GaAs layer. The emitter layer 41E of the first transistor 41 and the emitter layer 61E of the second transistor 61 are formed by patterning a common n-type InGaP layer or the like.

[0055] A cathode electrode 72C is disposed on the conductive region 40C, and the cathode electrode 72C is electrically connected to the cathode layer 71C via the conductive region 40C. A first layer of cathode wiring 73C is disposed on the cathode electrode 72C. An anode electrode 72A is disposed on the anode layer 71A. The anode electrode 72A is electrically connected to the anode layer 71A.

[0056] An interlayer insulating film 80 is disposed so as to cover the first transistor 41, the second transistor 61, the diode 71, the first-layer emitter wirings 43E, 63E, the collector wirings 43C, 63C, and the cathode wiring 73C. Note that an interlayer insulating film is also disposed between the emitter electrode 42E and the first-layer emitter wiring 43E, etc., but this interlayer insulating film is not shown. A second-layer emitter wiring 44E is disposed on the interlayer insulating film 80. The second-layer emitter wiring 44E is connected to the first-layer emitter wiring 43E through an opening provided in the interlayer insulating film 80. The element structure from the base layer 40 to the second-layer emitter wiring 44E corresponds to an element formation layer 202 (FIG. 7A).

[0057] An interlayer insulating film 86 is disposed on the second-layer emitter wiring 44E and the interlayer insulating film 80, and an opening that exposes the second-layer emitter wiring 44E is provided in the interlayer insulating film 86. As shown in FIG. 4B , the interlayer insulating film 86 extends onto the support substrate 20 outside the element formation layer 202 in plan view.

[0058] An emitter pad 82E is disposed on the second-layer emitter wiring 44E in an opening provided in the interlayer insulating film 86, and on the interlayer insulating film 86 around the opening. A protective film 87 is disposed on the emitter pad 82E and the interlayer insulating film 86, and an opening is provided in the protective film 87 to expose the emitter pad 82E.

[0059] An emitter protruding electrode 83E is disposed on the emitter pad 82E within the opening of the protective film 87 and on the protective film 87 around the opening. Solder 84 is placed on the emitter protruding electrode 83E.

[0060] Next, the excellent effects of the third embodiment will be described. In the third embodiment, the metal regions 21LA, 21LB, and 21LC of the lower adhesive layer 21L are electrically isolated from one another, and the metal regions 21UA, 21UB, and 21UC of the upper adhesive layer 21U are also electrically isolated from one another. Therefore, these metal regions 21UA, 21UB, 21UC, 21LA, 21LB, and 21LC of the adhesive layer 21 can be used as low-resistance layers to reduce parasitic resistance for each element disposed on the underlayer 40. For example, the parasitic resistance between the collector layer 61C and collector electrode 62C of not only the first transistor 41 but also the second transistor 61 can be reduced. Furthermore, the parasitic resistance between the cathode layer 71C and cathode electrode 72C of the diode 71 can be reduced.

[0061] [Fourth Example] Next, a semiconductor device according to a fourth embodiment will be described with reference to Fig. 10. Below, a description of the configuration common to the semiconductor device according to the first embodiment described with reference to Figs. 1 to 5 will be omitted.

[0062] 10 is a diagram schematically illustrating a cross-sectional structure of a semiconductor device according to a fourth embodiment. In the fourth embodiment, in addition to a first transistor 41, a capacitor 100, a resistive element 110, and an inductor 120 are arranged. The capacitor 100, the resistive element 110, and the inductor 120 are arranged on an element isolation region 40Z of an underlayer 40.

[0063] The capacitor 100 has a lower electrode 100L and an upper electrode 100U disposed thereon with an interlayer insulating film interposed therebetween. The resistor element 110 has a high-resistance portion 110R and end connection wiring 110W connected to both ends thereof. The inductor 120 includes a spiral wiring having a two-layer structure consisting of a lower layer 120L and an upper layer 120U. The lower electrode 100L of the capacitor 100, the end connection wiring 110W of the resistor element 110, and the lower layer 120L of the inductor 120 are formed, for example, by patterning the same metal film as the collector electrode 42C. The upper electrode 100U of the capacitor 100 and the upper layer 120U of the inductor 120 are formed by patterning the same metal film as the first layer of collector wiring 43C, etc.

[0064] In addition to the metal region 21LA, the lower adhesive layer 21L includes a plurality of metal regions 21LD and an insulating region 21LZ. The insulating region 21LZ is formed by, for example, a damascene method similar to that used to form the insulating region 21Z in the process shown in FIG. 3E of the first embodiment. The insulating region 21LZ may be a native oxide film formed on the surface of the support substrate 20 made of Si.

[0065] In addition to the metal region 21UA, the upper adhesive layer 21U includes a plurality of metal regions 21UD and an insulating region 21UZ. In plan view, the metal region 21LA of the lower adhesive layer 21L and the metal region 21UD of the upper adhesive layer 21U overlap each other and are in close contact with each other. In plan view, the capacitor 100, the resistor element 110, and the inductor 120 are included in the insulating region 21LZ and the insulating region 21UZ.

[0066] As an example, the plurality of first transistors 41 constitute a high-frequency amplifier circuit. The capacitor 100 is a DC-cut capacitor that removes direct current components from high-frequency signals, and the resistor element 110 is a base ballast resistor element. In addition, the capacitor 100 and the inductor 120 may constitute an impedance matching circuit.

[0067] Next, the excellent effects of the fourth embodiment will be described. In the fourth embodiment, by arranging various passive elements in addition to the multiple first transistors 41 on the base layer 40, it is possible to reduce the size of the electronic circuit compared to a configuration in which the passive elements are arranged externally. Each of the multiple passive elements is contained in the insulating regions 21UZ and 21LZ in a plan view and does not overlap with the metal regions 21UD and 21LD, thereby reducing the parasitic capacitance between the passive elements and the metal regions 21UD and 21LD. This makes it possible to avoid operational instability due to high-frequency coupling between the first transistors 41 and the passive elements.

[0068] [Fifth Example] Next, a semiconductor device according to a fifth embodiment will be described with reference to Fig. 11. Hereinafter, a description of the configuration common to the semiconductor device according to the fourth embodiment described with reference to Fig. 10 will be omitted. Fig. 11 is a diagram schematically showing the cross-sectional structure of the semiconductor device according to the fifth embodiment.

[0069] In the fourth embodiment (FIG. 10), the metal regions 21LA and 21LD of the lower adhesive layer 21L are electrically isolated from each other by an insulating region 21LZ, and the metal regions 21UA and 21UD of the upper adhesive layer 21U are electrically isolated from each other by an insulating region 21UZ. In contrast, in the fifth embodiment, a cavity is formed between the metal regions 21LA and 21LD of the lower adhesive layer 21L, and a cavity is also formed between the metal regions 21UA and 21UD of the upper adhesive layer 21U. For example, in the process shown in FIG. 3E of the first embodiment, a metal film is formed on the support substrate 20 and patterned to form the metal regions 21LA and 21LD separated by the cavity. The capacitor 100, resistor 110, and inductor 120 are contained in the cavity portions of the lower adhesive layer 21L and the upper adhesive layer 21U in a plan view.

[0070] Next, the excellent effects of the fifth embodiment will be described. In the fifth embodiment, as in the fourth embodiment (FIG. 10), it is possible to reduce the size of the electronic circuit and to avoid operational instability due to high-frequency coupling between the first transistor 41 and the passive element.

[0071] [Sixth Example] Next, a semiconductor device according to a sixth embodiment will be described with reference to Figures 12 and 13. Hereinafter, a description of the configuration common to the semiconductor device according to the third embodiment described with reference to Figures 8 and 9 will be omitted.

[0072] 12 is an equivalent circuit diagram of a semiconductor device according to a sixth embodiment. A power stage amplifier circuit is formed by a first transistor 41. A power supply voltage Vcc is applied to the collector of the first transistor 41 through a choke coil Lc, and the emitter of the first transistor 41 is grounded.

[0073] A second transistor 61 is included in the base bias circuit of the first transistor 41. The emitter of the second transistor 61 is connected to the base of the first transistor 41 via a base ballast resistor Rb. A battery voltage Vbatt is applied to the collector of the second transistor 61, and a bias control signal Vbias is supplied to the base of the second transistor 61. A base bias is supplied to the base of the first transistor 41 via the second transistor 61 and the base ballast resistor Rb. A radio frequency signal RFin is input to the base of the first transistor 41 through an input capacitor Cin. An output signal RFout is output from the collector of the first transistor 41.

[0074] The collector of the first transistor 41 is grounded via a plurality of serially connected diodes 71. The plurality of diodes 71 are connected with a polarity in the forward direction from the collector of the first transistor 41 toward the ground potential, and function as clamp diodes.

[0075] 13 is a diagram schematically showing a cross-sectional structure of a semiconductor device according to a sixth embodiment. In the third embodiment (FIGS. 8 and 9), the lower adhesive layer 21L is in direct contact with the silicon surface of the support substrate 20. In contrast, in the sixth embodiment, the support substrate 20 has a multilayer wiring layer 20A on its surface, and the lower adhesive layer 21L is in contact with the surface of the multilayer wiring layer 20A.

[0076] The base layer 40 includes a conductive region 40E, the upper adhesive layer 21U includes a metal region 21UE, and the lower adhesive layer 21L includes a metal region 21LE. A connection electrode 72B is disposed on the conductive region 40E. In a plan view, the conductive region 40E and the metal regions 21UE and 21LE overlap each other and are electrically connected. The anode electrode 72A of the diode 71 is connected to the connection electrode 72B via a first-layer anode wiring 73A.

[0077] Wiring 20W included in multilayer wiring layer 20A connects metal region 21LA and metal region 21LE. That is, collector layer 41C of first transistor 41 is electrically connected to anode layer 71A of diode 71 via wiring 20W in multilayer wiring layer 20A. Collector electrode 42C and collector wiring 43C electrically connected to collector layer 41C of first transistor 41 are used as electrodes to which probes come into contact for evaluation testing at the stage shown in FIG. 3B of the first embodiment.

[0078] Next, the excellent effects of the sixth embodiment will be described. In the sixth embodiment, the wiring 20W in the multilayer wiring layer 20A of the support substrate 20 connects the first transistor 41 and the diode 71. This increases the degree of freedom in arranging the wiring on the base layer 40. Furthermore, by using the collector wiring 43C connected to the sub-collector region 40A and the collector wiring 44C (FIG. 1) thereon as electrodes for evaluation testing, the evaluation test can be performed without the base layer 40 being bonded to the support substrate 20 (FIG. 3B). The metal region 21LA of the lower adhesive layer 21L and the metal region 21UA of the upper adhesive layer 21U have the function of reducing the parasitic resistance between the collector electrode 42C and the collector layer 41C by flowing a current in the in-plane direction, and the function of connecting the collector layer 41C and the wiring 20W in the support substrate 20 by flowing a current in the thickness direction.

[0079] The above-described embodiments are merely examples, and it goes without saying that partial substitution or combination of the configurations shown in different embodiments is possible. Similar effects resulting from similar configurations of multiple embodiments will not be mentioned sequentially for each embodiment. Furthermore, the present invention is not limited to the above-described embodiments. For example, it will be obvious to those skilled in the art that various modifications, improvements, combinations, etc. are possible. [Explanation of symbols]

[0080] 20 Support substrate 20A multilayer wiring layer 20W wiring 21 Adhesive layer 21A Metal area 21L Lower adhesive layer 21LA, 21LB, 21LC, 21LD, 21LE Metal area 21LZ Insulation area 21U upper adhesive layer 21UA, 21UB, 21UC, 21UD, 21UE Metal area 21UZ Insulation area 21Z Insulation Area 28 Semiconductor Devices 40 Base layer 40A, 40B Sub-collector region 40C, 40E conductive area 40Z isolation region 41 First transistor 41B Base Layer 41C Collector layer 41E Emitter layer 42B base electrode 42C Collector electrode 42E Emitter electrode 43B 1st layer base wiring 43C 1st layer collector wiring 43E 1st layer emitter wiring 44C 2nd layer collector wiring 44E Second layer emitter wiring 61 Second transistor 61B Base Layer 61C Collector layer 61E Emitter layer 62B Base electrode 62C Collector electrode 62E Emitter electrode 63C 1st layer collector wiring 63E 1st layer emitter wiring 71 Diode 71A anode layer 71C cathode layer 72A anode electrode 72B Connection electrode 72C cathode electrode 73A anode wiring 73C Cathode wiring 80 Correlation insulating film 82E Emitter Pad 82W interconnect wiring 83E Emitter protrusion electrode 84 Solder 86 Interlayer insulating film 87 Protective film 87A aperture 100 capacitors 100L lower electrode 100U upper electrode 110 Resistor element 110R high resistance part 110W end connection wiring 120 Inductor 120L lower layer 120U top layer 200 motherboard 201 Peeling layer 202 Device formation layer 204 Connecting support

Claims

1. A support substrate; an adhesive layer including a first metal region disposed on at least a portion of an upper surface of the support substrate; an underlayer disposed on the adhesion layer and including a subcollector region made of a conductive semiconductor material electrically connected to the first metal region; a first transistor including a collector layer disposed above the sub-collector region and electrically connected to the sub-collector region, a base layer disposed above the collector layer, and an emitter layer disposed above the base layer; a collector electrode disposed on the sub-collector region, outside the first transistor in a plan view, and at a position overlapping the first metal region, the collector electrode being electrically connected to the sub-collector region; Equipped with the adhesion layer further includes at least one second metal region electrically isolated from the first metal region; The semiconductor device further comprises an insulating region made of oxide or nitride, the insulating region being disposed between the first metal region and the second metal region in a plan view.

2. 2. The semiconductor device according to claim 1, wherein the first metal region includes at least one metal selected from the group consisting of Au, Ag, Pt, Cu, Al, W, Ti, and Ta.

3. 3. The semiconductor device according to claim 1, wherein the first metal region includes a first lower metal region on the side of the support substrate and a first upper metal region on the side of the base layer, and the first lower metal region and the first upper metal region are bonded together.

4. 4. The semiconductor device according to claim 1, wherein the support substrate includes a semiconductor material having a thermal conductivity higher than that of any of the semiconductor materials forming the collector layer, the base layer, and the emitter layer of the first transistor and the semiconductor material forming the sub-collector region.

5. the underlayer further includes an insulating element isolation region outside the sub-collector region in a plan view, 5. The semiconductor device according to claim 1, further comprising a passive element disposed on the element isolation region at a position not overlapping the first metal region and the second metal region in a plan view.

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