Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device and a method of manufacturing the same capable of reducing electric resistance of a gate electrode.SOLUTION: A semiconductor device has: a substrate; a semiconductor layer provided on the substrate; an insulating layer provided on the semiconductor layer, being formed with a first opening; a gate electrode provided on the insulating layer in contact with the semiconductor layer via the first opening; and source and drain electrodes in ohmic contact with the semiconductor layer. The gate electrode has: a crystalline control film provided on the insulating layer, having a second opening formed so that its inner wall is continuous to an inner wall of the first opening toward the substrate in a plan view from a direction perpendicular to an upper surface of the substrate; a first metal film provided on the crystalline control film in Schottky contact with the semiconductor layer via the respective continuous inner walls of the second and first openings; and a second metal film provided on the first metal film, having an electric resistance lower than that of the first metal film.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] There is a semiconductor device in which a gate electrode is in Schottky contact with a semiconductor layer. In this semiconductor device, an insulating layer is formed on the semiconductor layer to reduce electric field concentration near the gate electrode, and a part of the gate electrode is provided on the insulating layer (Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-207086 [Patent Document 2] Japanese Patent Application Publication No. 2019-216188 Summary of the Invention [Problem to be solved by the invention]

[0004] Although the semiconductor devices described in Patent Documents 1 and 2 achieve the intended purpose, it is desirable to reduce the resistance of the gate electrode in order to obtain higher characteristics.

[0005] An object of the present disclosure is to provide a semiconductor device and a method for manufacturing the semiconductor device that can reduce the electrical resistance of the gate electrode. [Means for solving the problem]

[0006] a first metal film provided on the crystallinity control film and making Schottky contact with the semiconductor layer through the inner walls of the second opening and the first opening; and a second metal film provided on the first metal film and having a lower electrical resistance than the first metal film. The semiconductor layer includes a nitride semiconductor layer, the first metal film is a Ni film, and the atomic arrangement at the interface between the crystallinity control film and the first metal film is hexagonally symmetric. do. [Effects of the Invention]

[0007] According to the present disclosure, the electrical resistance of the gate electrode can be reduced. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view showing a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is an enlarged cross-sectional view of the gate electrode. [Figure 3] FIG. 3 is a cross-sectional view (part 1) illustrating the method for manufacturing a semiconductor device according to the embodiment. [Figure 4] FIG. 4 is a cross-sectional view (part 2) showing the method for manufacturing the semiconductor device according to the embodiment. [Figure 5] FIG. 5 is a cross-sectional view (part 3) illustrating the method for manufacturing a semiconductor device according to the embodiment. [Figure 6] FIG. 6 is a cross-sectional view (part 4) showing the method for manufacturing a semiconductor device according to the embodiment. [Figure 7] FIG. 7 is a cross-sectional view (part 5) illustrating the method for manufacturing a semiconductor device according to the embodiment. [Figure 8] FIG. 8 is a cross-sectional view (part 6) showing the method for manufacturing a semiconductor device according to the embodiment. [Figure 9] FIG. 9 is a cross-sectional view (part 7) illustrating the method for manufacturing a semiconductor device according to the embodiment. [Figure 10] FIG. 10 is a cross-sectional view (part 8) showing the method for manufacturing a semiconductor device according to the embodiment. [Figure 11] FIG. 11 is a ninth cross-sectional view illustrating the method for manufacturing a semiconductor device according to the embodiment. [Figure 12] FIG. 12 is a cross-sectional view (part 10) showing the method for manufacturing the semiconductor device according to the embodiment. [Figure 13] FIG. 13 is a cross-sectional view (part 11) illustrating the method for manufacturing a semiconductor device according to the embodiment. [Figure 14] FIG. 14 is a twelfth cross-sectional view showing the method for manufacturing a semiconductor device according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described.

[0010] [1] A semiconductor device according to one embodiment of the present disclosure includes a substrate, a semiconductor layer provided on the substrate, an insulating layer provided on the semiconductor layer and having a first opening formed therein, a gate electrode provided on the insulating layer and in contact with the semiconductor layer through the first opening, and a source electrode and a drain electrode in ohmic contact with the semiconductor layer, wherein the gate electrode includes a crystallinity control film provided on the insulating layer and having a second opening formed facing the substrate in a plan view perpendicular to an upper surface of the substrate, the second opening having an inner wall continuous with an inner wall of the first opening, a first metal film provided on the crystallinity control film and in Schottky contact with the semiconductor layer through the inner walls of the second opening and the first opening, and a second metal film provided on the first metal film and having lower electrical resistance than the first metal film.

[0011] A first metal film is formed on a crystallinity control film. Therefore, the crystallinity of the first metal film is improved compared to when the first metal film is formed on an insulating layer so as to be in contact with the insulating layer. Since the crystallinity of the second metal film is affected by the crystallinity of the first metal film, the crystallinity of the second metal film is also improved. Therefore, the electrical resistance of the gate electrode can be reduced. By reducing the gate electrode, loss of signals input to the gate electrode can be reduced, and degradation of high-frequency gain can be reduced. This can improve the characteristics and reliability of the semiconductor device.

[0012] [2] In [1], the semiconductor layer may include a nitride semiconductor layer, the first metal film may be a Ni film, and the atomic arrangement of the crystallinity control film at the interface with the first metal film may be hexagonally symmetric. In this case, the crystallinity of the Ni film may be easily improved.

[0013] [3] In [1] or [2], the crystallinity control film may include a ZnO film, a GaN film, a Ti film, a TiN film, an Al film, an AlSiCu film, or an AlN film. In this case, the crystallinity of the Ni film is easily improved.

[0014] [4] In any of [1] to [3], the gate electrode may have, in a plan view perpendicular to the upper surface of the substrate, a first region overlapping the first opening, a second region extending horizontally from the first region on the source electrode side, and a third region extending horizontally from the first region on the drain electrode side, and the crystallinity control film may be provided in at least a portion of the second region and a portion of the third region. In this case, electric field concentration near the gate electrode is easily alleviated. Furthermore, deterioration of the crystallinity of the first metal film and the second metal film in the second region and the third region can be suppressed.

[0015] [5] In [4], the half-width of the electron diffraction pattern of the second metal film in the second region and the half-width of the electron diffraction pattern of the second metal film in the third region may be 45 times or less than the half-width of the electron diffraction pattern of the second metal film in the first region. In this case, the electrical resistance of the gate electrode is particularly likely to be reduced.

[0016] [6] In [4] or [5], the average crystal grain size of the second metal film in the second region and the average crystal grain size of the second metal film in the third region may be 60% or more of the average crystal grain size of the second metal film in the first region, which makes it particularly easy to reduce the electrical resistance of the gate electrode.

[0017] [7] In any of [1] to [6], the thickness of the crystallinity control film may be 10 nm or more and 30 nm or less. In this case, side etching is suppressed during etching when the crystallinity control film is formed, and the crystallinity of the first metal film is likely to be improved.

[0018] [8] In any of [1] to [7], a portion of the gate electrode above an upper surface of the insulating layer may have a tapered shape that becomes wider toward the insulating layer in a cross-sectional view perpendicular to the direction in which the source electrode and the drain electrode are arranged and parallel to the upper surface of the substrate. When the gate electrode is formed by a deposition method using a resist mask, the gate electrode is likely to have such a shape.

[0019] [9] In any of [1] to [8], the insulating layer may be an amorphous layer, which makes it easier to suppress leakage between the gate electrode and the semiconductor layer.

[0020]

[10] A semiconductor device according to another aspect of the present disclosure includes a substrate, a semiconductor layer provided on the substrate, an insulating layer provided on the semiconductor layer and having a first opening formed therein, a gate electrode provided on the insulating layer and in contact with the semiconductor layer through the first opening, and source and drain electrodes in ohmic contact with the semiconductor layer, wherein the gate electrode includes: a ZnO film provided on the insulating layer and having a second opening formed so that its inner wall is continuous with an inner wall of the first opening; a Ni film provided on the ZnO film and in Schottky contact with the semiconductor layer through the inner walls where the second opening and the first opening are continuous with each other; and an Au film provided on the Ni film and having lower electrical resistance than the Ni film.

[0021] Because the Ni film is formed on the ZnO film, the crystallinity of the Ni film is improved compared to when the Ni film is formed on the insulating layer so as to be in contact with the insulating layer. The crystallinity of the Au film is affected by the crystallinity of the Ni film, so the crystallinity of the Au film is also improved. Therefore, the electrical resistance of the gate electrode can be reduced. By reducing the gate electrode, the loss of the signal input to the gate electrode can be reduced, and the deterioration of high-frequency gain can be reduced. This can improve the characteristics and reliability of the semiconductor device.

[0022]

[11] A method for manufacturing a semiconductor device according to another aspect of the present disclosure includes the steps of: forming a semiconductor layer on a substrate; forming source and drain electrodes in ohmic contact with the semiconductor layer; forming an insulating layer on the semiconductor layer; forming a crystallinity control film on the insulating layer; forming a second opening in the crystallinity control film; forming a first opening in the insulating layer such that an inner wall of the second opening is continuous with the inner wall of the first opening; forming a resist mask having a third opening having an opening width larger than the opening widths of the second opening and the first opening; forming a first metal film on the crystallinity control film through the third opening, such that the second opening and the first opening are in Schottky contact with the semiconductor layer through the inner walls of each other; forming a second metal film on the first metal film through the third opening, the second metal film having a lower electrical resistance than the first metal film; and removing the resist mask.

[0023] Because the first metal film is formed on the crystallinity control film, the crystallinity of the first metal film is improved compared to when the first metal film is formed on the insulating layer so as to be in contact with the insulating layer. The crystallinity of the second metal film is affected by the crystallinity of the first metal film, so the crystallinity of the second metal film is also improved. Therefore, the electrical resistance of the gate electrode can be reduced. By reducing the gate electrode, loss of signals input to the gate electrode can be reduced, and degradation of high-frequency gain can be reduced. This improves the characteristics and reliability of the semiconductor device.

[0024]

[12] In

[11] , in the step of forming the crystallinity control film, the temperature of the substrate may be 150° C. or higher and 500° C. or lower.

[0025]

[13] In the configuration

[11] or

[12] , the first metal film and the second metal film may be formed by a vapor deposition method.

[0026]

[14] In any of

[11] to

[13] , the temperature of the substrate in the step of forming the first metal film and the step of forming the second metal film may be 80° C. or less.

[0027] [Details of the embodiments of the present disclosure] Hereinafter, embodiments of the present disclosure will be described in detail, but the present disclosure is not limited thereto. In this specification and drawings, components having substantially the same functional configurations may be designated by the same reference numerals to avoid redundant description.

[0028] 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure, which includes a high electron mobility transistor (HEMT) using a nitride semiconductor.

[0029] The semiconductor device 1 according to the embodiment includes a substrate 10 and a semiconductor laminate 20 including multiple nitride semiconductor layers and disposed on the substrate 10. The substrate 10 is, for example, a SiC substrate having a (0001) plane, and the stacking direction of the semiconductor laminate 20 is, for example, the

[0001] direction. The semiconductor laminate 20 includes, in order from the substrate 10 side, a nucleation layer 12, a channel layer 14, a barrier layer 16, and a cap layer 18. The nucleation layer 12 functions as a seed layer for the channel layer 14. For example, the nucleation layer 12 is an AlN layer, and the thickness of the nucleation layer 12 is 5 nm to 20 nm. The channel layer 14 is epitaxially grown on the nucleation layer 12 and functions as an electron transit layer. For example, the channel layer 14 is an undoped GaN layer, and the thickness of the channel layer 14 is 500 nm. The semiconductor laminate 20 is an example of a semiconductor layer.

[0030] The barrier layer 16 is epitaxially grown on the channel layer 14 and functions as an electron supply layer. For example, the barrier layer 16 is an AlGaN layer, an InAlN layer, or an InAlGaN layer, and has a thickness of 5 nm to 30 nm. The band gap of the barrier layer 16 is larger than the band gap of the channel layer 14. When the barrier layer 16 is an AlGaN layer, the Al composition of the barrier layer 16 is, for example, 0.15 to 0.35. The conductivity type of the barrier layer 16 may be n-type, or the barrier layer 16 may be undoped. The barrier layer 16 and the channel layer 14 may be in contact with each other, or a spacer layer (not shown) may be interposed between the barrier layer 16 and the channel layer 14. Strain occurs in the barrier layer 16 and the channel layer 14 due to the difference in lattice constants between them. This strain generates a two-dimensional electron gas (2DEG) due to piezoelectric charges in a region near the interface between the barrier layer 16 and the channel layer 14 on the channel layer 14 side, forming a channel region.

[0031] The cap layer 18 is epitaxially grown on the barrier layer 16. For example, the cap layer 18 is a GaN layer, and the thickness of the cap layer 18 is 5 nm. For example, the conductivity type of the cap layer 18 is n-type.

[0032] The semiconductor device further includes a source electrode 22 and a drain electrode 24. The source electrode 22 and the drain electrode 24 are aligned along the upper surface of the substrate 10. The source electrode 22 and the drain electrode 24 are provided on the cap layer 18 and form ohmic contact with the semiconductor laminate 20. The source electrode 22 and the drain electrode 24 are formed by heat treating (alloying) a tantalum (Ta) layer, an aluminum (Al) layer, and a Ta layer, which are provided in this order from the semiconductor laminate 20 side. A Ti layer may be provided instead of the Ta layer.

[0033] The semiconductor device 1 further includes a SiN passivation film 26. For example, the thickness of the SiN passivation film 26 is 20 nm or more and 100 nm or less. The SiN passivation film 26 is an amorphous film. The SiN passivation film 26 is provided on the source electrode 22, the drain electrode 24, and the cap layer 18, and covers the source electrode 22, the drain electrode 24, and the cap layer 18. An opening 26G is formed in the SiN passivation film 26, and the cap layer 18 is exposed from the SiN passivation film 26 through the opening 26G. The SiN passivation film 26 is an example of an insulating layer. The opening 26G is an example of a first opening.

[0034] The semiconductor device 1 further includes a gate electrode 28. The gate electrode 28 is provided on the SiN passivation film 26 between the source electrode 22 and the drain electrode 24. The gate electrode 28 will now be described in detail. Figure 2 is an enlarged cross-sectional view of the gate electrode 28.

[0035] The gate electrode 28 covers the opening 26G and is in contact with the semiconductor laminate portion 20 through the opening 26G. The gate electrode 28 has a zinc oxide (ZnO) film 52, a nickel (Ni) film 54, and a gold (Au) film 56.

[0036] The ZnO film 52 is provided on the SiN passivation film 26, and an opening 52G is formed in the ZnO film 52. The inner wall portions of the opening 52G and the opening 26G are smoothly continuous from the opening 52G toward the opening 26G in a plan view perpendicular to the upper surface of the substrate. In other words, the inner wall of the opening 52G is formed so as to be continuous with the inner wall of the opening 26G. For example, the thickness of the ZnO film 52 is 10 nm or more and 30 nm or less. The ZnO film 52 is an example of a crystallinity control film.

[0037] The Ni film 54 is provided on the ZnO film 52 and is in Schottky contact with the semiconductor laminate 20 through the openings 52G and 26G. The Ni film 54 is in contact with the ZnO film 52. The Ni film 54 covers the openings 52G and 26G. The Ni film 54 extends from the upper surface of the semiconductor laminate 20 in the opening 26G, over the adjacent inner wall surfaces of the openings 26G and 52G, and onto the ZnO film 52. For example, the thickness of the Ni film 54 is 1 nm or more and 200 nm or less. The Ni film 54 is an example of a first metal film.

[0038] The Au film 56 is provided on the Ni film 54 from inside the openings 26G and 52G to above the SiN passivation film 26. The Au film 56 is in contact with the Ni film 54. For example, the thickness of the Au film is 300 nm or more and 800 nm or less. The electrical resistance of the Au film 56 is lower than the electrical resistance of the Ni film 54. The Au film 56 is an example of a second metal film.

[0039] In a plan view from a direction perpendicular to the upper surface of the substrate, the gate electrode 28 has a first region 62 overlapping the opening 26G, a second region 64 extending horizontally from the first region 62 on the source electrode 22 side, and a third region 66 extending horizontally from the first region 62 on the drain electrode 24 side. The second region 64 and the third region 66 extend over the SiN passivation film 26. A pair of side surfaces 28A, 28B of the gate electrode 28 on the SiN passivation film 26 are inclined with respect to the upper surface of the SiN passivation film 26, and become closer to each other as they move away from the semiconductor laminate portion 20. Therefore, the portion of the gate electrode 28 above the upper surface of the SiN passivation film 26 is generally trapezoidal. That is, the portion of the gate electrode 28 above the upper surface of the SiN passivation film 26 has a tapered shape that becomes wider as it approaches the SiN passivation film 26, when viewed in a cross-sectional view perpendicular to the direction in which the source electrode 22 and the drain electrode 24 are arranged and parallel to the upper surface of the substrate 10. A pair of side surfaces 28A, 28B of the gate electrode 28 are mainly composed of the Au film 56. The side surface 26A is the side surface on the source electrode 22 side, and the side surface 26B is the side surface on the drain electrode 24 side.

[0040] The semiconductor device 1 further includes an insulating layer 30. The insulating layer 30 covers the gate electrode 28. The insulating layer 30 is made of an insulating material containing Si, such as a SiN layer, a SiO2 layer, or a SiON layer. For example, the insulating layer 30 has a thickness of 20 nm or more and 400 nm or less. An opening 32 and an opening 34 are formed in the SiN passivation film 26 and the insulating layer 30. The source electrode 22 is exposed from the opening 32, and the drain electrode 24 is exposed from the opening 34. A wiring (not shown) connected to the source electrode 22 is provided in the opening 32, and a wiring (not shown) connected to the drain electrode 24 is provided in the opening 34.

[0041] Here, a method for manufacturing the semiconductor device 1 according to the embodiment will be described. Figures 3 to 14 are cross-sectional views showing a method for manufacturing the semiconductor device 1 according to the embodiment.

[0042] First, as shown in FIG. 3, a semiconductor stack 20 including multiple nitride semiconductor layers is formed on a substrate 10 by metal organic chemical vapor deposition (MOCVD). Specifically, first, a nucleation layer 12 is grown on the substrate 10. When the nucleation layer 12 is an AlN layer, for example, the source gases are TMA (trimethylaluminum) and NH3 (ammonia), and the temperature of the substrate 10 when forming the nucleation layer 12 is 1100°C. Next, a channel layer 14 is grown on the nucleation layer 12. When the channel layer 14 is a GaN layer, for example, the source gases are TMG (trimethylgallium) and NH3, and the temperature of the substrate 10 when forming the channel layer 14 is 1050°C. Next, a barrier layer 16 is grown on the channel layer 14. When the barrier layer 16 is an AlGaN layer, for example, the source gases are TMA, TMG, and NH3, and the temperature of the substrate 10 when forming the barrier layer 16 is 1050°C. Next, the cap layer 18 is grown on the barrier layer 16. When the cap layer 18 is a GaN layer, for example, the source gases are TMG and NH3, and the temperature of the substrate 10 when the cap layer 18 is formed is 1050°C.

[0043] 4, lithography and lift-off techniques are used to form the source electrode 22 and the drain electrode 24 by vapor deposition on the cap layer 18. After that, alloying is performed by heat treatment at a temperature of 500°C or higher and 600°C or lower.

[0044] 5, a SiN passivation film 26 is formed to cover the source electrode 22, the drain electrode 24, and the semiconductor laminate portion 20. The SiN passivation film 26 can be formed by, for example, plasma CVD or sputtering. For example, when the SiN passivation film 26 is formed by plasma CVD, the temperature of the substrate 10 is set to 250°C or higher and 350°C or lower.

[0045] Next, as shown in FIG. 6, a ZnO film 52 is formed on the SiN passivation film 26. The ZnO film 52 can be formed by, for example, sputtering, plasma CVD, or atomic layer deposition (ALD). The temperature (growth temperature) of the substrate 10 when forming the ZnO film 52 is, for example, 150°C or higher and 500°C or lower. Setting the growth temperature to 150°C or higher and 500°C or lower makes it easier to improve the c-axis orientation of the ZnO film 52. The growth temperature is preferably 200°C or higher and 450°C or lower, and more preferably 250°C or higher and 400°C or lower.

[0046] 7, a resist mask 72 having openings 72A in regions where the openings 26G are to be formed is formed on the ZnO film 52. The resist mask 72 can be formed by, for example, applying, exposing, and developing a resist.

[0047] 8, the portion of the ZnO film 52 exposed through the opening 72A is etched to form an opening 52G in the ZnO film 52. The ZnO film 52 is preferably etched by anisotropic dry etching using a chlorine-based gas. Although side etching may occur, wet etching using HCl, HNO, CHCOOH, or the like may also be performed.

[0048] The ZnO film 52 may be etched by the developer used to form the resist mask 72, such as tetramethylammonium hydroxide (TMAH).

[0049] 9, the portions of the SiN passivation film 26 exposed from the opening 72A and the opening 52G are etched to form an opening 26G in the SiN passivation film 26. The opening 26G is formed so that its inner wall is continuous with the inner wall of the opening 52G. The etching of the SiN passivation film 26 is preferably anisotropic dry etching using a fluorine-based gas.

[0050] Next, as shown in FIG. 10 , the resist mask 72 is removed. Next, a resist mask 74 having an opening 74A and a resist mask 76 having an opening 76A are formed on the ZnO film 52. In the cross-sectional shape shown in FIG. 10 , the horizontal opening width of the opening 76A is larger than the horizontal opening widths of the openings 52G and 26G. The horizontal opening width of the opening 74A is also larger than the horizontal opening width of the opening 76A. To form the resist masks 74 and 76, a resist for the resist mask 74 is applied, and then a resist for the resist mask 76 is applied. Next, the opening 76A is formed in the resist for the resist mask 76 so that its opening width is larger than the opening widths of the openings 52G and 26G. Then, the opening 74A is formed in the resist for the resist mask 74 so that its opening width is larger than the opening width of the opening 76A. The resist mask 74 and the resist mask 76 are included in a resist mask 78, and the opening 74A and the opening 76A are included in an opening 78A. The opening 78A is an example of a third opening.

[0051] Next, as shown in FIG. 11 , a Ni film 54 and an Au film 56 are formed in this order through the openings 76A and 74A by vapor deposition. To avoid deterioration of the resist masks 76 and 74, the temperature of the substrate 10 during the formation of the Ni film 54 and the Au film 56 is preferably 80°C or less, and more preferably 70°C or less. The Ni film 54 is formed on the ZnO film 52 and makes Schottky contact with the semiconductor laminate 20 through the openings 52G and 26G. The Au film 56 is formed on the Ni film 54 from inside the openings 26G and 52G to above the SiN passivation film 26. When the Ni film 54 is formed, a Ni film 54A is formed on the resist mask 76, and when the Au film 56 is formed, an Au film 56A is formed on the Ni film 54A.

[0052] 12, the resist mask 76 and the resist mask 74 are removed. The Ni film 54A and the Au film 56A are also removed when the resist mask 76 and the resist mask 74 are removed. In other words, lift-off is performed.

[0053] Next, as shown in FIG. 13 , the portions of the ZnO film 52 exposed from the Au film 56 and the Ni film 54 are removed. The ZnO film 52 is removed by, for example, wet etching. A diluted solution of, for example, hydrochloric acid or sulfuric acid can be used to remove the ZnO film 52. As a result, the gate electrode 28 is formed, including the ZnO film 52, the Ni film 54, and the Au film 56. Because the Ni film 54 and the Au film 56 are formed using the resist masks 74 and 76, the portion of the gate electrode 28 above the top surface of the SiN passivation film 26 has a substantially trapezoidal shape. That is, the portion of the gate electrode 28 above the top surface of the SiN passivation film 26 has a tapered shape that becomes wider as it approaches the SiN passivation film 26, when viewed in a cross-sectional view perpendicular to the direction in which the source electrode 22 and the drain electrode 24 are arranged and parallel to the top surface of the substrate.

[0054] 14, an insulating layer 30 is formed to cover the gate electrode 28 and the SiN passivation film 26. The insulating layer 30 can be formed by, for example, plasma CVD or sputtering. The temperature of the substrate 10 when forming the insulating layer 30 is, for example, 250°C or higher and 350°C or lower. Next, an opening 32 and an opening 34 are formed in the insulating layer 30 and the SiN passivation film 26. The source electrode 22 is exposed from the opening 32, and the drain electrode 24 is exposed from the opening 34.

[0055] In this manner, the semiconductor device 1 according to the embodiment can be manufactured.

[0056] In this embodiment, a Ni film 54 that makes Schottky contact with the semiconductor laminate 20 is formed on the ZnO film 52, which is a crystallinity control film. Therefore, the crystallinity of the Ni film 54 is improved compared to when the Ni film 54 is formed on the SiN passivation film 26 so as to be in contact with the SiN passivation film 26. Furthermore, the crystallinity of the Au film 56 is affected by the crystallinity of the Ni film 54. Therefore, according to this embodiment, the crystallinity of the Au film 56 is also improved compared to when the Ni film 54 is formed on the SiN passivation film 26 so as to be in contact with the SiN passivation film 26. Therefore, according to this embodiment, the electrical resistance of the gate electrode 28 can be reduced. Reducing the gate electrode 28 reduces loss of signals input to the gate electrode 28 and reduces degradation of high-frequency gain. This improves the characteristics and reliability of the semiconductor device 1.

[0057] In this embodiment, the semiconductor laminate 20 includes a nitride semiconductor layer, and the Ni film 54 is in Schottky contact with the nitride semiconductor layer. The atomic arrangement of the Ni film 54 at the interface with the ZnO film 52 is six-fold symmetric, and the atomic arrangement of the ZnO film 52 at the interface with the Ni film 54 is six-fold symmetric. Therefore, the crystallinity of the Ni film 54 can be easily improved.

[0058] The ZnO film serving as the crystallinity control film may or may not be doped with impurities. When doped with impurities, the concentration is, for example, 1 atomic % or more and 10 atomic % or less. Examples of impurities doped into the ZnO film include B, Al, Ga, and In. The crystallinity control film is not limited to a ZnO film, and may include a GaN film, a Ti film, a TiN film, an Al film, an AlSiCu film, or an AlN film. The atomic arrangement of these films at the interface with the first metal film also has six-fold symmetry. The GaN film may or may not be doped with impurities. Examples of impurities doped into the GaN film include Si and Ge.

[0059] Since the gate electrode 28 includes the first region 62, the second region 64, and the third region 66, it is possible to alleviate electric field concentration in the vicinity of the gate electrode 28. Furthermore, since the ZnO film 52 is provided in the second region 64 and the third region 66, it is possible to suppress deterioration in the crystallinity of the Ni film 54 and the Au film 56 in the second region 64 and the third region 66.

[0060] Since the SiN passivation film 26 is an amorphous film, leakage between the gate electrode 28 and the semiconductor laminate portion 20 can be easily suppressed.

[0061] A barrier metal film such as a Pd film, a Pt film, or a Ru film may be provided between the Ni film 54 and the Au film 56. The thickness of the barrier metal film is, for example, 5 nm to 100 nm. Also, a Ta film, a TaN film, a Hf film, a HfN film, a Zr film, a ZrN film, a W film, a WN film, or the like may be provided on the Au film 56.

[0062] In the present disclosure, the half-width of the electron diffraction pattern of the second metal film in the second region and the half-width of the electron diffraction pattern of the second metal film in the third region are preferably 45 times or less, more preferably 30 times or less, and even more preferably 20 times or less, of the half-width of the electron diffraction pattern of the second metal film in the first region. The smaller the half-width of the electron diffraction pattern of the second metal film in the second region and the half-width of the electron diffraction pattern of the second metal film in the third region, the easier it is to reduce the electrical resistance of the gate electrode.

[0063] The half-width of the electron diffraction pattern of the second metal film can be measured as follows. A focused ion beam (FIB) is used to thin the cross section of the gate electrode 28, exposing the cross section. The thickness of the thin section is preferably approximately 50 nm to 200 nm. A transmission electron microscope (TEM) is used to irradiate an electron beam perpendicular to the cross section of the gate electrode 28. Because the second metal film is crystalline, the electron beam passing through the sample (thin section) constructively interacts in a specific direction corresponding to the periodicity of the crystal, forming a spot-like image on the detector, resulting in an electron diffraction pattern. The intensity profile of the 111 diffraction point or -1-1-1 diffraction point is extracted from the electron diffraction pattern, and its half-width is measured.

[0064] In the first region, the first metal film is in contact with the nitride semiconductor film, and in the second and third regions, a SiN passivation film 26 is present between the first metal film and the nitride semiconductor film. By obtaining electron beam diffraction patterns and measuring the half-widths for each of the second metal film in the first region, the second metal film in the second region, and the second metal film in the third region, the (111) orientation in the regions with different underlying layers can be quantified and compared.

[0065] In the present disclosure, the average crystal grain size of the second metal film in the second region and the average crystal grain size of the second metal film in the third region are preferably 60% or more, more preferably 70% or more, and even more preferably 80% or more of the average crystal grain size of the second metal film in the first region. The larger the average crystal grain size of the second metal film in the second region and the average crystal grain size of the second metal film in the third region, the more likely it is that interdiffusion between the first and second metal films will be suppressed, and the easier it will be to reduce the electrical resistance of the gate electrode.

[0066] The average crystal grain size of the second metal film can be measured using, for example, an atomic force microscope.

[0067] In the present disclosure, the thickness of the crystallinity control film is preferably 10 nm or more and 30 nm or less, and more preferably 15 nm or more and 25 nm or less. If the crystallinity control film is excessively thin, the crystallinity of the first metal film may not be improved. Furthermore, if the crystallinity control film is excessively thick, side etching may occur during etching of the crystallinity control film.

[0068] Although the embodiments have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0069] 1: Semiconductor device 10: Circuit board 12: Nucleation layer 14: Channel layer 16: Barrier layer 18: Cap layer 20: Semiconductor laminated section 22: Source electrode 24: Drain electrode 26: SiN passivation film 26G:Aperture 28: Gate electrode 28A, 28B: Side 30: Insulating layer 32, 34: Aperture 52:ZnO film 52G:Aperture 54, 54A: Ni film 56, 56A: Au film 62:First area 64:Second area 66: Third area 72, 74, 76, 78: Resist mask 72A, 74A, 76A, 78A: Opening

Claims

1. A substrate; a semiconductor layer provided on the substrate; an insulating layer provided on the semiconductor layer and having a first opening; a gate electrode provided on the insulating layer and in contact with the semiconductor layer through the first opening; a source electrode and a drain electrode in ohmic contact with the semiconductor layer; and The gate electrode is a crystallinity control film provided on the insulating layer, the crystallinity control film including a second opening formed such that its inner wall is continuous with the inner wall of the first opening toward the substrate in a plan view from a direction perpendicular to the upper surface of the substrate; a first metal film provided on the crystallinity control film and making Schottky contact with the semiconductor layer through the continuous inner walls of the second opening and the first opening; a second metal film provided on the first metal film and having a lower electrical resistance than the first metal film; and the semiconductor layer includes a nitride semiconductor layer, the first metal film is a Ni film, The semiconductor device, wherein the atomic arrangement at the interface between the crystallinity control film and the first metal film is six-fold symmetric.

2. A substrate, a semiconductor layer provided on the substrate; an insulating layer provided on the semiconductor layer and having a first opening; a gate electrode provided on the insulating layer and in contact with the semiconductor layer through the first opening; a source electrode and a drain electrode in ohmic contact with the semiconductor layer; and The gate electrode is a crystallinity control film provided on the insulating layer, the crystallinity control film including a second opening formed such that its inner wall is continuous with the inner wall of the first opening toward the substrate in a plan view from a direction perpendicular to the upper surface of the substrate; a first metal film provided on the crystallinity control film and making Schottky contact with the semiconductor layer through the continuous inner walls of the second opening and the first opening; a second metal film provided on the first metal film and having a lower electrical resistance than the first metal film; and The semiconductor device, wherein the crystallinity control film includes a ZnO film, a GaN film, a Ti film, a TiN film, an Al film, an AlSiCu film, or an AlN film.

3. The gate electrode has, in a plan view from a direction perpendicular to an upper surface of the substrate, a first region overlapping the first opening; a second region that is connected to the first region in a horizontal direction on the source electrode side; a third region that is connected to the first region in a horizontal direction on the drain electrode side; and 3. The semiconductor device according to claim 1, wherein the crystallinity control film is provided in at least a part of the second region and a part of the third region.

4. 4. The semiconductor device according to claim 3, wherein the half-width of the electron beam diffraction pattern of the second metal film in the second region and the half-width of the electron beam diffraction pattern of the second metal film in the third region are 45 times or less than the half-width of the electron beam diffraction pattern of the second metal film in the first region.

5. 5. The semiconductor device according to claim 3, wherein the average crystal grain size of the second metal film in the second region and the average crystal grain size of the second metal film in the third region are 60% or more of the average crystal grain size of the second metal film in the first region.

6. 6. The semiconductor device according to claim 1, wherein the crystallinity control film has a thickness of 10 nm or more and 30 nm or less.

7. 7. The semiconductor device according to claim 1, wherein a portion of the gate electrode above an upper surface of the insulating layer has a tapered shape that becomes wider as it approaches the insulating layer when viewed in a cross-sectional view perpendicular to a direction in which the source electrode and the drain electrode are arranged and parallel to an upper surface of the substrate.

8. 8. The semiconductor device according to claim 1, wherein the insulating layer is an amorphous layer.

9. A substrate; a semiconductor layer provided on the substrate; an insulating layer provided on the semiconductor layer and having a first opening; a gate electrode provided on the insulating layer and in contact with the semiconductor layer through the first opening; a source electrode and a drain electrode in ohmic contact with the semiconductor layer; and The gate electrode is a ZnO film provided on the insulating layer, the ZnO film having a second opening formed so that its inner wall is continuous with the inner wall of the first opening; a Ni film provided on the ZnO film and in Schottky contact with the semiconductor layer through inner walls of the second opening and the first opening that are connected to each other; an Au film provided on the Ni film and having a lower electrical resistance than the Ni film; A semiconductor device having:

10. forming a semiconductor layer on a substrate; forming a source electrode and a drain electrode in ohmic contact with the semiconductor layer; forming an insulating layer on the semiconductor layer; forming a crystallinity control film on the insulating layer; forming a second opening in the crystallinity control film; forming a first opening in the insulating layer such that an inner wall of the second opening is continuous with the first opening; forming a resist mask having a third opening having an opening width larger than the second opening and the first opening; forming a first metal film on the crystallinity control film through the third opening, the first metal film being in Schottky contact with the semiconductor layer through the inner walls of the second opening and the first opening; forming a second metal film having a lower electrical resistance than the first metal film on the first metal film through the third opening; removing the resist mask; and The method for manufacturing a semiconductor device, wherein the crystallinity control film includes a ZnO film, a GaN film, a Ti film, a TiN film, an Al film, an AlSiCu film, or an AlN film.

11. 11. The method for manufacturing a semiconductor device according to claim 10, wherein the temperature of the substrate is 150[deg.] C. or more and 500[deg.] C. or less in the step of forming the crystallinity control film.

12. The method for manufacturing a semiconductor device according to claim 10 or 11, wherein the first metal film and the second metal film are formed by a vapor deposition method.

13. 13. The method for manufacturing a semiconductor device according to claim 10, wherein the temperature of the substrate in the step of forming the first metal film and the step of forming the second metal film is 80[deg.] C. or less.

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