Imaging device

Abstract

To provide an imaging apparatus with a stacked structure that can be easily fabricated.SOLUTION: An imaging apparatus has a signal processing circuit, a storage device, and an image sensor. The imaging apparatus has a stacked structure, in which the storage device is provided above the signal processing circuit and the image sensor is provided above the storage device. The signal processing circuit has a transistor formed on a first semiconductor substrate, the storage device has a transistor having a metal oxide in a channel forming region, and the image sensor has a transistor formed on a second semiconductor substrate.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] 1. Field of the Invention An embodiment of the present invention relates to an imaging device, and more particularly to an imaging device having a layered structure.

[0002] Note that one aspect of the present invention is not limited to the above-mentioned technical fields. The technical fields of the invention disclosed in this specification relate to products, methods, or manufacturing methods. Alternatively, one aspect of the present invention relates to processes, machines, manufactures, or compositions of matter. [Background technology]

[0003] MOS image sensors, such as CMOS (Complementary Metal Oxide Semiconductor), are known as imaging devices widely used in electronic devices such as digital video cameras, digital cameras, and smartphones.

[0004] Furthermore, in recent years, a stacked structure has been put to practical use in imaging devices, in which multiple semiconductor chips with different functions are stacked and electrically connected. By adopting a stacked structure, the manufacturing method and materials used for each semiconductor chip can be adapted to the function of each semiconductor chip, making it easy to realize high performance imaging devices and also enabling electronic devices equipped with imaging devices to be made smaller and lighter.

[0005] Non-Patent Document 1 shows an example of an imaging device in which a signal processing circuit, a storage device, and a MOS image sensor are stacked. Non-Patent Document 1 states that by adopting a DRAM (Dynamic Random Access Memory) as the storage device and storing captured image data in the DRAM, high-speed imaging that exceeds the data transfer speed with an electronic device equipped with the imaging device is achieved.

[0006] While silicon-based semiconductor materials are widely known as semiconductors applicable to transistors, oxide semiconductors are also attracting attention. Oxide semiconductors include not only oxides of single-component metals such as indium oxide and zinc oxide, but also oxides of multi-component metals. Among multi-component metal oxides, research on In-Ga-Zn oxide (hereinafter also referred to as IGZO) has been particularly active.

[0007] Research on IGZO has revealed that oxide semiconductors have a c-axis aligned crystalline (CAAC) structure and a nanocrystalline (nc) structure, which are neither single crystal nor amorphous (see Non-Patent Documents 2 to 4). Non-Patent Documents 2 and 3 also disclose techniques for fabricating transistors using oxide semiconductors with a CAAC structure. Furthermore, Non-Patent Documents 5 and 6 show that even oxide semiconductors with lower crystallinity than the CAAC structure and the nc structure have minute crystals.

[0008] Furthermore, a transistor using an oxide semiconductor has an extremely low off-state current (see Non-Patent Document 7), and LSIs and displays utilizing this characteristic have been reported (see Non-Patent Documents 8 and 9).

[0009] Furthermore, DRAMs in which transistors using oxide semiconductors are applied to DRAM cells have been proposed (for example, Patent Document 1 and Non-Patent Document 10). Transistors using oxide semiconductors have an extremely small leakage current (off-state current) in an off state, and therefore, memories with a long refresh period and low power consumption can be manufactured. In this specification and the like, DRAMs in which transistors using oxide semiconductors are applied to DRAM cells are referred to as "oxide semiconductor DRAMs" or "DOSRAMs (registered trademark, Dynamic Oxide Semiconductor Random Access Memory)." [Prior art documents] [Patent documents]

[0010]

Patent Document 1

Non-licensed literature

[0011] [Non-licensed document 1] Tsutomu.Haruta et al., "A 1 / 2.3inch 20Mpixel 3-Layer Stacked CMOS Image Sensor with DRAM", IEEE ISSCC Dig.Tech.Papers, 2017, pp.76-78. [Non-licensed document 2] S.Yamazaki et al., "SID Symposium Digest of Technical Papers", 2012, volume 43, issue 1, p.183-186 [Non-licensed document 3] S.Yamazaki et al., "Japanese Journal of Applied Physics", 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10

Non-licensed Document 4

Non-licensed Document 5

Non-licensed Document 6

Non-licensed Document 7

[0012] In Non-Patent Document 1, a signal processing circuit, a memory device, and a MOS image sensor are each fabricated on separate semiconductor chips, which are then stacked in three layers and electrically connected. Here, the surfaces on which the signal processing circuit, memory device, and MOS image sensor are formed are referred to as the top surfaces of the semiconductor chips. Specifically, the top surface of the semiconductor chip in the second layer (memory device) is bonded to the top surface of the semiconductor chip in the first layer (signal processing circuit), and the semiconductor chip in the second layer is thinned. Furthermore, the top surface of the semiconductor chip in the third layer (MOS image sensor) is bonded to the semiconductor chip in the second layer, and the semiconductor chip in the third layer is thinned. In this way, an imaging device is fabricated that incorporates a so-called "back-illuminated" MOS image sensor that detects light incident from the bottom surface (thinned surface) of the semiconductor chip in the third layer.

[0013] However, this manufacturing method is difficult because it requires two bonding processes and two thinning processes, and also requires electrical connections to be made through the silicon substrate of the second-layer semiconductor chip. Therefore, it is not easy to increase the number of stacked layers in the memory device and increase memory capacity. Furthermore, bonding semiconductor chips together creates the problem of heat generation, and the DRAM used as a memory device also has the problem of being relatively heat-resistant.

[0014] An object of one embodiment of the present invention is to provide a stacked imaging device that can be easily manufactured, a stacked imaging device whose storage capacity can be easily increased, or a stacked imaging device that is heat-resistant and has a highly reliable storage device.

[0015] Another object of one embodiment of the present invention is to provide a novel imaging device.Another object of one embodiment of the present invention is to provide an electronic device including the novel imaging device.

[0016] It should be noted that one embodiment of the present invention does not necessarily have to solve all of the above problems, but may solve at least one of the problems. Furthermore, the description of the above problems does not preclude the existence of other problems. Problems other than these will become apparent from the description in the specification, claims, drawings, etc., and other problems can be extracted from the description in the specification, claims, drawings, etc. [Means for solving the problem]

[0017] One embodiment of the present invention is an imaging device including a first layer, a second layer above the first layer, and a third layer above the second layer. The first layer includes a signal processing circuit, the second layer includes a memory device, and the third layer includes an image sensor. The signal processing circuit includes a transistor formed over a first semiconductor substrate, the memory device includes a transistor including a metal oxide in a channel formation region, and the image sensor includes a transistor formed over the second semiconductor substrate.

[0018] Another embodiment of the present invention is an imaging device including a first layer, a second layer above the first layer, and a third layer above the second layer. The first layer includes a signal processing circuit, the second layer includes a memory device, and the third layer includes an image sensor. The memory device includes a plurality of memory cells, each including a transistor and a capacitor, wherein one of a source and a drain of the transistor is electrically connected to one electrode of the capacitor, and the transistor includes a metal oxide in a channel formation region. The signal processing circuit includes a transistor formed over a first semiconductor substrate, and the image sensor includes a transistor formed over a second semiconductor substrate.

[0019] In the above embodiment, the signal processing circuit may have a function of controlling the operations of the storage device and the image sensor.

[0020] In the above-described embodiment, at least one of the signal processing circuit and the image sensor may have an analog-to-digital conversion circuit, and the analog-to-digital conversion circuit may have a function of converting image data generated by the image sensor into a digital signal.

[0021] In the above embodiments, the storage device may have a function of storing a digital signal. [Effects of the Invention]

[0022] According to one embodiment of the present invention, it is possible to provide a stacked imaging device that can be easily manufactured, a stacked imaging device whose storage capacity can be easily increased, or a stacked imaging device that is heat-resistant and has a highly reliable storage device.

[0023] Alternatively, it is possible to provide a stacked-type imaging device with reduced cost, or a stacked-type imaging device with reduced refresh frequency and low power consumption.

[0024] According to one embodiment of the present invention, a novel imaging device can be provided. Alternatively, according to one embodiment of the present invention, an electronic device including the novel imaging device can be provided.

[0025] Note that the description of these effects does not preclude the existence of other effects. Furthermore, one embodiment of the present invention does not necessarily have all of these effects. Effects other than these will become apparent from the description in the specification, claims, drawings, etc., and other effects can be extracted from the description in the specification, claims, drawings, etc. [Brief explanation of the drawings]

[0026] [Figure 1] 1A and 1B are perspective views showing an example of the configuration of an imaging device. [Figure 2] (A, B, C) Circuit diagrams showing an example of the configuration of a memory cell, and (D) Circuit diagram showing an example of the configuration of a pixel. [Figure 3] FIG. 1 is a perspective view showing an example of the configuration of an imaging apparatus. [Figure 4] 2 is a cross-sectional view showing an example of the configuration of a layer 100 and a layer 200. FIG. [Figure 5] 1A, 1B, and 1C are cross-sectional views showing examples of transistor configurations. [Figure 6] FIG. 1 is a cross-sectional view showing an example of the configuration of an imaging apparatus. [Figure 7] FIG. 1 is a cross-sectional view showing an example of the configuration of an imaging apparatus. [Figure 8] 1A and 1B are cross-sectional views showing examples of transistor configurations. [Figure 9] 1A is a top view illustrating a structural example of a transistor, and FIG. 1B is a perspective view illustrating the structural example of a transistor. [Figure 10] 1A and 1B are cross-sectional views showing examples of transistor configurations. [Figure 11] (A, C) Cross-section of the transistor, (B, D) Electrical characteristics of the transistor. [Figure 12] (A, B, C, D) Diagrams showing examples of the configuration of electronic devices. [Figure 13] 1A and 1B are diagrams illustrating examples of the configuration of electronic devices. [Figure 14] (A, B) Shmoo plots. [Figure 15] FIG. [Figure 16] (A, B, C) Diagram showing power consumption estimation. DETAILED DESCRIPTION OF THE INVENTION

[0027] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different forms and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0028] In addition, the following multiple embodiments can be combined as appropriate. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined with each other as appropriate.

[0029] In addition, in the drawings, etc., the size, layer thickness, region, etc. may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings.

[0030] In addition, in drawings, etc., identical elements or elements having similar functions, elements made of the same material, or elements formed at the same time may be given the same symbol, and repeated explanations may be omitted.

[0031] Furthermore, in this specification and the like, the terms "film" and "layer" can be interchangeable. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0032] Furthermore, in this specification and the like, terms indicating arrangement such as "above" and "below" do not limit the positional relationship of components to "directly above" or "directly below." For example, the expression "gate electrode on a gate insulating layer" does not exclude other components between the gate insulating layer and the gate electrode.

[0033] In addition, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components and do not imply any numerical limitation.

[0034] In addition, in this specification, "electrically connected" includes connection via "something that has some kind of electrical action." Here, "something that has some kind of electrical action" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical action" includes electrodes and wiring, as well as switching elements such as transistors, resistive elements, inductors, capacitive elements, and other elements with various functions.

[0035] Furthermore, in this specification and the like, the term "voltage" often refers to the potential difference between a certain potential and a reference potential (for example, ground potential). Therefore, the terms "voltage" and "potential difference" can be used interchangeably.

[0036] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A channel formation region is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and a current can flow between the source and the drain through the channel formation region. In this specification and the like, the channel formation region refers to a region through which a current mainly flows.

[0037] Furthermore, the functions of the source and drain may be interchanged when transistors of different polarities are used, when the direction of current flow changes during circuit operation, etc. For this reason, the terms source and drain may be used interchangeably in this specification and the like.

[0038] In this specification and the like, unless otherwise specified, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the gate voltage Vgs relative to the source is lower than the threshold voltage Vth for an n-channel transistor, and a state in which the gate voltage Vgs relative to the source is higher than the threshold voltage Vth for a p-channel transistor. In other words, the off-state current of an n-channel transistor may be referred to as the drain current when the gate voltage Vgs relative to the source is lower than the threshold voltage Vth.

[0039] In the above description of off-state current, the drain may be read as the source. In other words, the off-state current may refer to the source current when a transistor is in an off state. The off-state current may also be referred to as leakage current, which has the same meaning as the off-state current. In this specification and the like, the off-state current may also refer to the current that flows between the source and drain when a transistor is in an off state.

[0040] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as "oxide semiconductors"). For example, when a metal oxide is used in a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide has at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Hereinafter, a transistor having a metal oxide in a channel formation region is also referred to as an "oxide semiconductor transistor" or an "OS transistor." The above-mentioned "transistor using an oxide semiconductor" is also a transistor having a metal oxide in a channel formation region.

[0041] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides. Details of metal oxides will be described later.

[0042] (Embodiment 1) In this embodiment, a configuration example of an imaging device according to one embodiment of the present invention will be described. The imaging device according to one embodiment of the present invention has a structure in which a layer having a transistor formed on a semiconductor substrate and a layer having an OS transistor are stacked, and further a layer having a transistor and a photodiode formed on the semiconductor substrate are bonded and stacked.

[0043] <Configuration example of imaging device> FIG. 1A is a perspective view showing an example of the configuration of an imaging device 10 according to an embodiment of the present invention.

[0044] The imaging device 10 has a layer 100, a layer 200, and a layer 300. As shown in Fig. 1(A), the imaging device 10 has a structure in which the layer 200 is stacked on the layer 100, and the layer 300 is stacked on the layer 200. An interlayer insulating layer can be provided between the layer 100 and the layer 200.

[0045] FIG. 1B is a perspective view for explaining the configuration example of the imaging device 10 in a more easily understandable manner.

[0046] Layers 100, 200, and 300 each have a device or circuit that can function by utilizing the semiconductor properties, with layer 100 having a signal processing circuit 110, layer 200 having a memory device 210, and layer 300 having an image sensor 310.

[0047] <Signal Processing Circuit 110> The signal processing circuit 110 has functions such as controlling the operation of the memory device 210 and the image sensor 310, processing image data generated by the image sensor 310, and transmitting and receiving data, control signals, etc. to and from an electronic device equipped with the imaging device 10.

[0048] Specifically, for example, the signal processing circuit 110 includes a control circuit 111, a control circuit 112, an image processing circuit 113, and an input / output circuit 114 (see FIG. 1B).

[0049] The control circuit 111 has a function of supplying data to be written to the storage device 210, an address signal that specifies an address in the storage device 210 that reads and writes data, a control signal for controlling the operation of the storage device 210, etc. The control circuit 111 also has a function of receiving data that has been read from the storage device 210.

[0050] The control circuit 112 has a function of receiving image data generated by the image sensor 310 and a function of supplying control signals and the like for controlling the operation of the image sensor 310. The control circuit 112 may have an analog-digital converter (ADC).

[0051] The image processing circuit 113 has functions to perform, for example, gamma correction, dimming processing, color adjustment processing, noise removal, distortion correction, video codec, etc. on the image data generated by the image sensor 310. The image processing circuit 113 may also have functions to perform face detection, automatic scene recognition, and high dynamic range rendering (HDR).

[0052] Here, automatic scene recognition refers to recognizing a scene such as the external environment and automatically adjusting exposure, focus, flash, etc. The image processing circuit 113 does not need to perform all of the above processing, and can select or omit some as needed.

[0053] The input / output circuit 114 has a function of transmitting and receiving data, control signals, etc. to and from an electronic device equipped with the imaging device 10. The input / output circuit 114 uses an interface such as LVDS (Low-Voltage Differential Signaling), MIPI (Mobile Industry Processor Interface), or SPI (Serial Peripheral Interface), for example.

[0054] In addition, the signal processing circuit 110 may have a bus line 115, a power supply circuit 116, etc. In FIG. 1B, the control circuit 111, the control circuit 112, the image processing circuit 113, and the input / output circuit 114 are connected via the bus line 115.

[0055] The signal processing circuit 110 is configured using transistors formed on a semiconductor substrate SUB1. The semiconductor substrate SUB1 is not particularly limited as long as it is possible to form a channel region of the transistor. For example, a single crystal silicon substrate, a single crystal germanium substrate, a compound semiconductor substrate (such as a SiC substrate or a GaN substrate), or an SOI (Silicon on Insulator) substrate can be used.

[0056] Alternatively, the SOI substrate may be a SIMOX (Separation by Implanted Oxygen) substrate formed by implanting oxygen ions into a mirror-polished wafer and then heating it at a high temperature to form an oxide layer to a certain depth from the surface and eliminate defects that have occurred in the surface layer, or an SOI substrate formed using the Smart Cut method or the ELTRAN (registered trademark: Epitaxial Layer Transfer) method, which cleaves a semiconductor substrate by utilizing the growth of microvoids formed by hydrogen ion implantation through heat treatment. A transistor formed using a single crystal substrate has a single crystal semiconductor in the channel formation region.

[0057] In this embodiment, as an example, a case will be described in which a single crystal silicon substrate is used as the semiconductor substrate SUB1. Hereinafter, a transistor formed on a single crystal silicon substrate will be referred to as a Si transistor.

[0058] <Storage device 210> The memory device 210 is connected to the control circuit 111 via wiring CL that connects the layer 100 and the layer 200. The wiring CL is formed by a conductor formed in a contact hole between the layer 100 and the layer 200. Input and output of data and signals between the memory device 210 and the control circuit 111 is performed via the wiring CL.

[0059] The memory device 210 provided on the layer 200 has a cell array 211, a driving circuit 221, and a driving circuit 222. The cell array 211 is made up of a plurality of memory cells 212 arranged in a matrix.

[0060] The memory cell 212 has a function of storing data. The memory cell 212 may have a function of storing binary data (high level and low level), or may have a function of storing multi-level data having four or more levels. The memory cell 212 may also have a function of storing analog data.

[0061] The driver circuit 221 has a function of selecting the memory cell 212. Specifically, the driver circuit 221 has a function of supplying a signal for selecting the memory cell 212 to which data is written or read (hereinafter also referred to as a selection signal) to a wiring connected to the memory cell 212.

[0062] The driver circuit 222 has a function of writing data to the memory cell 212 and a function of reading the data stored in the memory cell 212. Specifically, the driver circuit 222 has a function of supplying a potential (hereinafter also referred to as a write potential) corresponding to data stored in the memory cell 212 to a wiring connected to the memory cell 212 to which data is written. The driver circuit 222 also has a function of reading a potential (hereinafter also referred to as a read potential) corresponding to data stored in the memory cell 212 and outputting it to the control circuit 111 through a wiring CL.

[0063] Address signals, clock signals, timing signals, etc. are input to the drive circuit 221 from the control circuit 111 provided on the layer 100 via wiring CL. The drive circuit 221 then generates a selection signal using these signals. The timing at which the selection signal is output from the drive circuit 221 is controlled by the timing signal input from the control circuit 111.

[0064] Furthermore, the control circuit 111 provided in the layer 100 supplies the driver circuit 222 with an address signal, a clock signal, a timing signal, data to be written to the memory cell 212, and the like via wiring CL. The driver circuit 222 generates a write potential using these signals. The timing at which the driver circuit 222 outputs the write potential is controlled by the timing signal input from the control circuit 111.

[0065] Note that in FIG. 1B, the wiring CL connected to the driver circuit 221 and the driver circuit 222 is illustrated as one wiring.

[0066] The memory cell 212, the driver circuit 221, and the driver circuit 222 are each composed of an OS transistor. Since the band gap of an oxide semiconductor is 2.5 eV or more, preferably 3.0 eV or more, the OS transistor has a small leakage current due to thermal excitation and an extremely small off-state current. Note that the off-state current refers to a current that flows between the source and drain of a transistor when it is off.

[0067] The oxide semiconductor used in the channel formation region of a transistor is preferably an oxide semiconductor containing at least one of indium (In) and zinc (Zn). A typical example of such an oxide semiconductor is an In-M-Zn oxide (wherein the element M is, for example, Al, Ga, Y, or Sn). By reducing impurities such as moisture and hydrogen that serve as electron donors (donors) and also reducing oxygen vacancies, the oxide semiconductor can be made i-type (intrinsic) or substantially i-type. Such an oxide semiconductor can be called a highly purified oxide semiconductor. Details of the OS transistor will be described in Embodiment 3.

[0068] Because the off-state current of an OS transistor is extremely small, it is suitable as a transistor for use in the memory cell 212. The off-state current of the OS transistor per 1 μm of channel width can be, for example, 100 zA / μm or less, 10 zA / μm or less, 1 zA / μm or less, or 10 yA / μm or less. By using an OS transistor for the memory cell 212, data stored in the memory cell 212 can be retained for a long period of time.

[0069] By using an OS transistor for the memory cell 212, the refresh frequency of the memory cell 212 can be reduced. Alternatively, the refresh operation of the memory cell 212 can be eliminated. Furthermore, by reducing the refresh frequency of the memory cell 212, the power consumption of the memory device 210 can be reduced. Alternatively, by eliminating the refresh operation of the memory cell 212, the circuitry required for the refresh operation can be reduced.

[0070] Furthermore, since the leakage current of the OS transistor is extremely small, multilevel data or analog data can be stored in the memory cell 212. Furthermore, since the off-state current of the OS transistor is unlikely to increase even at high temperatures, data stored in the memory cell 212 is unlikely to be lost even at high temperatures caused by heat generation from the signal processing circuit 110 or the image sensor 310. Use of the OS transistor can improve the reliability of the memory device 210.

[0071] 2A is a circuit diagram illustrating a configuration example of a memory cell 212 using an OS transistor. The memory cell 212 illustrated in FIG. 2A includes a transistor 213 and a capacitor 214. Note that the symbol "OS" in the drawing indicates an OS transistor.

[0072] The gate of the transistor 213 is connected to a node a1, one of the source or the drain is connected to one electrode of the capacitor 214, and the other of the source or the drain is connected to a node a2. The other electrode of the capacitor 214 is connected to a node a3 to which a constant potential (for example, a low power supply potential) is supplied. The node a1 is connected to the driver circuit 221 in FIG. 1B, and the node a2 is connected to the driver circuit 222 in FIG. 1B. The node connected to the one of the source or the drain of the transistor 213 and one electrode of the capacitor 214 is referred to as a node N1.

[0073] When writing data to the memory cell 212, a write potential is supplied to the node a2. Then, a selection signal (high-level potential) is supplied to the node a1 to turn on the transistor 213. As a result, the write potential is written to the node N1. After that, a low-level potential is supplied to the node a1 to turn off the transistor 213. As a result, the node N1 is brought into a floating state, and the write potential is held.

[0074] When reading data stored in the memory cell 212, the potential of the node N1 becomes a read potential. By supplying a selection signal (high-level potential) to the node a1, the transistor 213 is turned on. As a result, the potential of the node a2 is determined according to the potential of the node N1. In this way, the data stored in the memory cell 212 is read.

[0075] Since the transistor 213 is an OS transistor, the potential of the node N1 is held for a long period of time. This reduces the frequency of data refresh, leading to reduced power consumption. In this specification and elsewhere, the memory device 210 in which the memory cell 212 is configured using the circuit shown in FIG. 2A is referred to as a DOSRAM.

[0076] A transistor having a back gate may be used for the memory cell 212. Fig. 2B shows a configuration example of the memory cell 212 using a transistor 215 having a back gate. The memory cell 212 shown in Fig. 2B includes a transistor 215 and a capacitor 214.

[0077] The back gate of the transistor 215 is connected to the node a4. The threshold voltage of the transistor 215 can be increased or decreased by applying any potential to the node a4. For example, the threshold voltage can be increased and the off-state current can be reduced by applying a negative potential (a potential lower than that of the node a2 and the node N1) to the back gate.

[0078] 2C, the back gate of the transistor 215 may be connected to the node a1. By connecting the back gate of the transistor 215 to the node a1, the current flowing through the transistor 215 can be increased when the transistor 215 is in a conductive state. Note that in FIGS. 2B and 2C, the description of parts other than the back gate is omitted because they are the same as those in FIG. 2A.

[0079] 1B, the driver circuit 221 and the driver circuit 222 are also configured with OS transistors, similar to the memory cell 212. That is, the memory cell 212, the driver circuit 221, and the driver circuit 222 do not include Si transistors but are configured with n-channel OS transistors. Such a circuit configured with transistors of the same conductivity type is also referred to as a unipolar circuit hereinafter. That is, the layer 200 includes a memory device 210 configured with a unipolar circuit using OS transistors.

[0080] The control circuit 111 that controls the memory device 210 is provided in the layer 100 and can be configured by a CMOS circuit using Si transistors, etc. This allows the configuration of a high-speed, high-performance control circuit 111, which can be used to operate the memory device 210.

[0081] Although the above description has been given of a configuration in which an OS transistor is used in the circuit provided in the layer 200, a transistor in which a channel region is formed in a film containing a semiconductor material other than an oxide semiconductor can also be used. Examples of such a transistor include a transistor in which an amorphous silicon film, a microcrystalline silicon film, a polycrystalline silicon film, a single-crystal silicon film, an amorphous germanium film, a microcrystalline germanium film, a polycrystalline germanium film, or a single-crystal germanium film is used as a semiconductor layer.

[0082] <Image Sensor 310> The image sensor 310 is configured using transistors formed on a semiconductor substrate SUB2. The semiconductor substrate SUB2 is not particularly limited as long as it is capable of forming a channel region of the transistor. A description of the semiconductor substrate SUB2 will be omitted as it is similar to the semiconductor substrate SUB1. In addition, in this embodiment, as an example, a case will be described in which a single crystal silicon substrate is used for the semiconductor substrate SUB2.

[0083] The image sensor 310 is connected to the control circuit 112 by electrical connections between the wiring CL connecting the layer 100 and the layer 200, the conductor 201 provided on the top surface of the layer 200, and the conductor 301 provided on the top surface of the layer 300. Input and output of data and signals between the image sensor 310 and the control circuit 112 is performed via the wiring CL, the conductor 201, and the conductor 301.

[0084] Here, the surface of layer 200 is the surface on which memory device 210 is formed, and the surface of layer 300 is the surface on which image sensor 310 is formed. In other words, layer 300 is stacked on layer 200 so that the surface on which image sensor 310 is formed is in contact with the surface on which memory device 210 is formed.

[0085] The image sensor 310 includes a pixel array 311, a driving circuit 321, and a driving circuit 322. The pixel array 311 is made up of a plurality of pixels 312 arranged in a matrix.

[0086] The pixels 312 have a function of converting the intensity of light into an electric signal. The electric signals obtained by the plurality of pixels 312 are read out by the drive circuit 322 and output from the image sensor 310 to the control circuit 112 as image data.

[0087] Here, the layer 300 is stacked so that the surface on which the image sensor 310 is formed and the surface on which the memory device 210 is formed are in contact with each other, and therefore, the light 20 is incident on the surface of the layer 300 on which the image sensor 310 is not formed (see FIG. 1(B)). Therefore, the layer 300 is thinned to an extent that light can pass through.

[0088] The driver circuit 321 has a function of selecting the pixel 312. Specifically, the driver circuit 321 has a function of supplying a selection signal for selecting the pixel 312 from which data is to be read to a wiring connected to the pixel 312.

[0089] The drive circuit 322 has a function of reading out electrical signals from the pixels 312. The drive circuit 322 may have a function of performing noise removal, analog-to-digital conversion, etc. on the read-out electrical signals. For example, the drive circuit 322 may have a CDS (Correlated Double Sampling) circuit as a circuit for removing noise, and a column-parallel analog-to-digital conversion circuit as a circuit for performing analog-to-digital conversion.

[0090] The analog-to-digital conversion circuit may be included in either the driver circuit 322 or the control circuit 112 provided in the layer 100. Alternatively, the analog-to-digital conversion circuit may be included in both the driver circuit 322 and the control circuit 112. By including the analog-to-digital conversion circuit, the image data generated by the image sensor 310 can be processed as a digital signal.

[0091] A clock signal, a timing signal, and the like are input from the control circuit 112 provided on the layer 100 to the drive circuit 321 via the wiring CL, the conductor 201, and the conductor 301. The drive circuit 321 then generates a selection signal using these signals. The timing at which the selection signal is output from the drive circuit 321 is controlled by the timing signal input from the control circuit 112.

[0092] The driver circuit 322 also has a function of outputting, as image data, the electrical signals read from the pixels 312. The driver circuit 322 outputs the image data to the control circuit 112 through the conductors 301, 201, and the wirings CL.

[0093] Note that in FIG. 1B, the wiring CL connected to the driver circuit 321 and the driver circuit 322 is illustrated as one wire, and the conductor 201 and the conductor 301 are illustrated as one wire.

[0094] <Pixel 312> 2D is a circuit diagram illustrating a configuration example of the pixel 312. The pixel 312 illustrated in FIG.

[0095] The photoelectric conversion element 313 may be, for example, a pn junction photodiode using a p-type silicon semiconductor and an n-type silicon semiconductor. Alternatively, it may be a pin-type photodiode in which an i-type silicon semiconductor layer is provided between a p-type silicon semiconductor and an n-type silicon semiconductor. Alternatively, a pin-type diode element using an amorphous silicon film or a microcrystalline silicon film, a diode-connected transistor, a variable resistor utilizing the photoelectric effect, or the like may be formed using silicon, germanium, selenium, or the like.

[0096] Furthermore, a material capable of absorbing radiation and generating electric charges may be used as the photoelectric conversion element 313. Examples of materials capable of absorbing radiation and generating electric charges include lead iodide, mercury iodide, gallium arsenide, CdTe, and CdZn.

[0097] One of the source and drain of the transistor 314 is electrically connected to the cathode of the photoelectric conversion element 313, and the other is electrically connected to a node 331 (charge storage portion). The anode of the photoelectric conversion element 313 is electrically connected to a wiring 334.

[0098] One of a source or a drain of the transistor 315 is electrically connected to a node 331, and the other is electrically connected to a wiring 332. A gate of the transistor 316 is electrically connected to the node 331, one of a source or a drain is electrically connected to a wiring 333, and the other is electrically connected to one of a source or a drain of the transistor 317. The other of the source or the drain of the transistor 317 is electrically connected to a wiring 332. One electrode of the capacitor 318 is electrically connected to the node 331, and the other electrode is electrically connected to a wiring 334.

[0099] The transistor 314 functions as a transfer transistor. A transfer signal TX is supplied to the gate of the transistor 314. The transistor 315 functions as a reset transistor. A reset signal RST is supplied to the gate of the transistor 315. The transistor 316 functions as an amplifying transistor. The transistor 317 functions as a selection transistor. A selection signal SEL is supplied to the gate of the transistor 317.

[0100] A high power supply potential VDD is supplied to the wiring 332, and a low power supply potential VSS is supplied to the wiring 334. In this specification, the high power supply potential refers to a power supply potential that is higher than the low power supply potential. The low power supply potential refers to a power supply potential that is lower than the high power supply potential.

[0101] Next, the operation of the pixel 312 shown in FIG. 2(D) will be described.

[0102] First, the transistor 315 is turned on to supply VDD to the node 331 (reset operation). After that, when the transistor 315 is turned off, the node 331 is held at VDD.

[0103] Next, when the transistor 314 is turned on, the potential of the node 331 changes (accumulation operation) in accordance with the amount of light received by the photoelectric conversion element 313. After that, when the transistor 314 is turned off, the potential of the node 331 is held.

[0104] When the transistor 317 is turned on, a potential corresponding to the potential of the node 331 is output from the wiring 333 (selection operation). By detecting the potential of the wiring 333, the amount of light received by the photoelectric conversion element 313 can be known.

[0105] The above operation is performed for all pixels 312 in the pixel array 311, and the drive circuit 322 reads out the electrical signals, allowing the image sensor 310 to generate image data.

[0106] Note that the above-described configuration of the pixel 312 is an example, and some circuits, some transistors, or some capacitors may not be included. Alternatively, circuits, transistors, or capacitors not included in the configuration of the pixel 312 may be included. Alternatively, some power supply potentials may be different.

[0107] <Imaging device 10> As described above, the imaging device 10 has a structure in which the layer 200 is stacked on the layer 100, and the layer 300 is stacked on the layer 200, and includes a signal processing circuit 110, a memory device 210, and an image sensor 310. The imaging device 10 can perform various image processing such as analog-to-digital conversion and noise removal on the image data generated by the image sensor 310, and then output the data to an electronic device incorporating the imaging device 10. This allows for the electronic device incorporating the imaging device 10 to be made smaller and lighter.

[0108] In addition, the imaging device 10 has a memory device 210 made up of OS transistors, and by storing captured image data in the memory device 210, high-speed imaging can be performed that exceeds the speed (data transfer rate) at which the input / output circuit 114 sends and receives data between the imaging device 10 and an electronic device equipped with the imaging device 10.

[0109] Furthermore, because the OS transistor can be formed over the layer 100, the number of bonding steps and thinning steps can be reduced compared to the manufacturing method of an imaging device described in Non-Patent Document 1. The imaging device 10 may include a plurality of layers 200. FIG. 3 shows an example in which the imaging device 10 includes two layers 200. The imaging device 15 shown in FIG. 3 includes a layer 100, a layer 200a, a layer 200, and a layer 300. The layer 200a is similar to the layer 200 except that it does not include the conductor 201, and therefore a description of the layer 200a will be omitted. However, the storage capacity of the imaging device 10 can be easily increased by increasing the number of layers 200.

[0110] Furthermore, since the OS transistors constituting the memory device 210 have an extremely small leakage current, data stored in the memory cells 212 can be retained for a long period of time. This reduces the frequency of refreshing the memory cells 212 or eliminates the need for refresh operations, thereby reducing the power consumption of the memory device 210. Furthermore, since the off-state current of the OS transistors is unlikely to increase even at high temperatures, data stored in the memory cells 212 is unlikely to be lost even at high temperatures. In other words, the reliability of the memory device 210 can be improved.

[0111] Note that this embodiment mode can be implemented in appropriate combination with other embodiment modes described in this specification.

[0112] (Embodiment 2) In this embodiment, an example of the cross-sectional configuration of the imaging device 10 described in the above embodiment will be described.

[0113] Note that the signal processing circuit 110 is configured using transistors formed on the semiconductor substrate SUB1, and the image sensor 310 is configured using transistors formed on the semiconductor substrate SUB2, so the layers 100 and 300 are configured using transistors formed on different semiconductor substrates. Also, the memory device 210 is configured using OS transistors, and the layer 200 is formed on the layer 100, so the layer 200 is configured above the semiconductor substrate SUB1.

[0114] 4 and 5 show examples of the cross-sectional configuration of the layer 100 and the layer 200, and FIG. 6 shows an example of the cross-sectional configuration of the layer 300.

[0115] <Layer 100 and Layer 200> 4 includes a transistor 400a, a transistor 400b, a transistor 500, and a capacitor 600. Fig. 5A is a cross-sectional view of the transistor 500 in the channel length direction, Fig. 5B is a cross-sectional view of the transistor 500 in the channel width direction, and Fig. 5C is a cross-sectional view of the transistor 400a in the channel width direction.

[0116] The transistor 500 is a transistor including a metal oxide in a channel formation region. Because the off-state current of the transistor 500 is extremely low, stored data can be retained for a long time when used in the memory cell 212. That is, refresh operations are performed less frequently or are not required, and therefore, the power consumption of the memory device 210 can be reduced.

[0117] As shown in FIG. 4, the transistor 500 is provided above the transistor 400a and the transistor 400b, and the capacitor 600 is provided above the transistor 500.

[0118] The transistor 400a is provided on a semiconductor substrate 411 and includes a conductor 416, an insulator 415, a semiconductor region 413 made of part of the semiconductor substrate 411, and low-resistance regions 414a and 414b functioning as source and drain regions. Similarly, the transistor 400b is provided on the semiconductor substrate 411 and includes a conductor 416, an insulator 415, a semiconductor region 417 made of part of the semiconductor substrate 411, and low-resistance regions 418a and 418b functioning as source and drain regions. The semiconductor substrate 411 corresponds to the semiconductor substrate SUB1 in the first embodiment.

[0119] As shown in the cross-sectional view of the transistor 400a in the channel width direction in FIG. 5C, the top surface and the side surface in the channel width direction of the semiconductor region 413 are covered with the conductor 416 via the insulator 415. As described above, the transistors 400a and 400b are fin-type transistors. By configuring the transistors 400a and 400b as fin-type transistors, the effective channel width can be increased, and the on-state characteristics of the transistors can be improved. Furthermore, the contribution of the electric field of the gate electrode can be increased, and therefore the off-state characteristics of the transistors 400a and 400b can be improved.

[0120] In this embodiment, as an example, an n-type single crystal silicon substrate is used as the semiconductor substrate 411. The semiconductor region 417 is a part of a p-type semiconductor well provided in a part of the semiconductor substrate 411. That is, the transistor 400a functions as a p-channel transistor, and the transistor 400b functions as an n-channel transistor.

[0121] The semiconductor substrate 411 may be formed of a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. Alternatively, the semiconductor substrate 411 may be configured using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing. Alternatively, the transistor 400 may be configured as a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs, or the like.

[0122] Low-resistance region 414a, low-resistance region 414b, and semiconductor region 417 contain an element that imparts p-type conductivity, such as boron, in addition to the semiconductor material used in semiconductor region 413. Low-resistance region 418a and low-resistance region 418b contain an element that imparts n-type conductivity, such as arsenic or phosphorus, in addition to the semiconductor material used in semiconductor region 417.

[0123] The conductor 416 functioning as the gate electrode can be made of a conductive material such as a semiconductor material, metal material, alloy material, or metal oxide material, such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0124] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by changing the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride as the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum stacked on the conductor, and tungsten is particularly preferable in terms of heat resistance.

[0125] 4 is an example, and the transistors 400a and 400b are not limited to the structures shown in FIG. 4. Appropriate transistors may be used depending on the circuit configuration and driving method. For example, like the transistor 500, the transistors 400a and 400b may be formed using an oxide semiconductor.

[0126] An insulator 420, an insulator 422, an insulator 424, and an insulator 426 are stacked in this order to cover the transistor 400a and the transistor 400b.

[0127] The insulators 420, 422, 424, and 426 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like.

[0128] The insulator 422 may function as a planarization film that flattens steps caused by the transistor 400a or the like provided thereunder. For example, the top surface of the insulator 422 may be planarized by planarization treatment such as chemical mechanical polishing (CMP) to improve the planarity.

[0129] The insulator 424 is preferably a film having a barrier property that prevents hydrogen and impurities from diffusing from the semiconductor substrate 411, the transistor 400a, or the like to a region where the transistor 500 is provided. For example, silicon nitride formed by a CVD method can be used as an example of a film having a barrier property against hydrogen.

[0130] The characteristics of a semiconductor element including an oxide semiconductor, such as the transistor 500, may be degraded due to diffusion of hydrogen into the semiconductor element. Therefore, a film that suppresses hydrogen diffusion is preferably used between the transistor 500 and the transistors 400a and 400b. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0131] The amount of desorbed hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS) etc. For example, the amount of desorbed hydrogen from the insulator 424 is calculated by TDS analysis as follows: when the surface temperature of the film is in the range of 50°C to 500°C, the amount of desorbed hydrogen converted into hydrogen atoms is 10 x 10 per area of ​​the insulator 424. 15 atoms / cm 2 Less than or equal to 5 x 10 15 atoms / cm 2 The following is fine.

[0132] Note that the insulator 426 preferably has a lower dielectric constant than the insulator 424. For example, the relative dielectric constant of the insulator 426 is preferably less than 4, more preferably less than 3. For example, the relative dielectric constant of the insulator 426 is preferably 0.7 times or less, more preferably 0.6 times or less, the relative dielectric constant of the insulator 424. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced.

[0133] A conductor 428, a conductor 430, and the like which connect to the capacitor 600 or the transistor 500 are embedded in the insulator 420, the insulator 422, the insulator 424, and the insulator 426. Note that the conductor 428 and the conductor 430 function as a plug or a wiring.

[0134] Here, for conductors that function as plugs or wiring, the same symbol may be used to refer to multiple structures. Furthermore, in this specification and the like, the wiring and the plug connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0135] The materials for each plug and wiring (such as the conductor 428 and the conductor 430) can be a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material, and can be used in a single layer or a laminated layer. High-melting-point materials such as tungsten and molybdenum, which have both heat resistance and conductivity, are preferably used, and tungsten is preferred. Alternatively, they are preferably formed from a low-resistance conductive material such as aluminum or copper. The use of a low-resistance conductive material can reduce the wiring resistance.

[0136] A wiring layer may be provided over the insulator 426 and the conductor 430. For example, in FIG. 4, the insulator 450, the insulator 452, and the insulator 454 are stacked in this order. The conductor 456 is formed over the insulator 450, the insulator 452, and the insulator 454. The conductor 456 functions as a plug or wiring connected to the transistor 400a or the like. Note that the conductor 456 can be formed using a material similar to that of the conductor 428 and the conductor 430.

[0137] Note that, for example, the insulator 450 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 424. The conductor 456 preferably includes a conductor having a barrier property against hydrogen. In this case, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 450 having a barrier property against hydrogen. With this structure, the transistors 400a and 400b can be separated from the transistor 500 by a barrier layer, and diffusion of hydrogen from the transistors 400a and 400b to the transistor 500 can be suppressed.

[0138] For example, tantalum nitride may be used as a conductor having a barrier property against hydrogen. Furthermore, by stacking tantalum nitride and highly conductive tungsten, the diffusion of hydrogen from the transistors 400a and 400b can be suppressed while maintaining the conductivity of the wiring. In this case, a structure in which the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 450 having a barrier property against hydrogen is preferable.

[0139] A wiring layer may be provided over the insulator 454 and the conductor 456. For example, in FIG. 4, an insulator 460, an insulator 462, and an insulator 464 are stacked in this order. A conductor 466 is formed in the insulator 460, the insulator 462, and the insulator 464. The conductor 466 functions as a plug or a wiring. The conductor 466 can be formed using a material similar to that of the conductors 428 and 430.

[0140] Note that, for example, the insulator 460 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 424. The conductor 466 preferably includes a conductor having a barrier property against hydrogen. In this case, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 460 having a barrier property against hydrogen. With this structure, the transistors 400a and 400b can be separated from the transistor 500 by a barrier layer, and diffusion of hydrogen from the transistors 400a and 400b to the transistor 500 can be suppressed.

[0141] Although the above describes a wiring layer including the conductor 456 and a wiring layer including the conductor 466, the cross-sectional structures of the layer 100 and the layer 200 are not limited to this. There may be one wiring layer similar to the wiring layer including the conductor 456, or there may be three or more wiring layers similar to the wiring layer including the conductor 456.

[0142] Here, the gate of the transistor 400a is electrically connected to one of the source and the drain of the transistor 500 through a conductor 428, a conductor 430, a conductor 456, a conductor 466, etc. This series of wirings corresponds to the wiring CL in the first embodiment.

[0143] An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are stacked in this order over the insulator 464. Any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 is preferably made using a substance that has a barrier property against oxygen and hydrogen.

[0144] For example, the insulator 510 and the insulator 514 are preferably films having barrier properties that prevent hydrogen and impurities from diffusing from the semiconductor substrate 411 or the region where the transistors 400a and 400b are provided to the region where the transistor 500 is provided. Therefore, a material similar to that of the insulator 424 can be used.

[0145] As a film having a barrier property against hydrogen, for example, the insulators 510 and 514 are preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0146] In particular, aluminum oxide has a high blocking effect against both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0147] For example, the insulators 512 and 516 can be formed using a material similar to that of the insulator 420. Using a material with a relatively low dielectric constant for the insulators can reduce parasitic capacitance between wirings. For example, the insulators 512 and 516 can be formed using a silicon oxide film, a silicon oxynitride film, or the like.

[0148] A conductor 518 and a conductor that constitutes the transistor 500 (the conductor 503 (see FIG. 5A)) are embedded in the insulators 510, 512, 514, and 516. The conductor 518 functions as a plug or a wiring that connects to the capacitor 600 or the transistor 400a. The conductor 518 can be formed using a material similar to that of the conductors 428 and 430.

[0149] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor that has a barrier property against oxygen, hydrogen, and water. With this structure, the transistor 400a and the transistor 400b can be separated from the transistor 500 by a layer that has a barrier property against oxygen, hydrogen, and water, and diffusion of hydrogen and the like from the transistor 400a and the transistor 400b to the transistor 500 can be suppressed.

[0150] Above the insulator 516 is the transistor 500 .

[0151] As shown in FIGS. 5A and 5B, the transistor 500 includes a conductor 503 disposed so as to be embedded in an insulator 514 and an insulator 516, an insulator 520 disposed on the insulator 516 and the conductor 503, an insulator 522 disposed on the insulator 520, an insulator 524 disposed on the insulator 522, an oxide 530a disposed on the insulator 524, an oxide 530b disposed on the oxide 530a, and conductors 542a and 542b disposed apart from each other on the oxide 530b. and conductor 542b, an insulator 580 disposed on conductor 542a and conductor 542b and having an opening formed thereon overlapping between conductor 542a and conductor 542b, a conductor 560 disposed in the opening, an insulator 550 disposed among oxide 530b, conductor 542a, conductor 542b, and insulator 580, and conductor 560, and an oxide 530c disposed among oxide 530b, conductor 542a, conductor 542b, insulator 580, and insulator 550.

[0152] 5(A) and 5(B), it is preferable that an insulator 544 be disposed between the oxide 530a, the oxide 530b, the conductor 542a, and the conductor 542b and the insulator 580. It is preferable that the conductor 560 include a conductor 560a provided inside the insulator 550 and a conductor 560b provided so as to be embedded inside the conductor 560a, as shown in FIGS. 5(A) and 5(B). It is preferable that an insulator 574 be disposed over the insulator 580, the conductor 560, and the insulator 550.

[0153] In the following, the oxide 530a, the oxide 530b, and the oxide 530c may be collectively referred to as the oxide 530. The conductor 542a and the conductor 542b may be collectively referred to as the conductor 542.

[0154] Although the transistor 500 has a three-layer structure of oxide 530a, oxide 530b, and oxide 530c in and around the channel formation region, the present invention is not limited to this structure. For example, the transistor may have a single layer of oxide 530b, a two-layer structure of oxide 530b and oxide 530a, a two-layer structure of oxide 530b and oxide 530c, or a stacked structure of four or more layers. Although the transistor 500 has a two-layer structure, the present invention is not limited to this structure. For example, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers. The transistor 500 shown in FIGS. 4, 5A, and 5B is merely an example, and the transistor may have any structure suitable for the circuit configuration and driving method.

[0155] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and 542b function as the source and drain electrodes, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. The arrangements of the conductors 560, 542a, and 542b are selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be positioned between the source and drain electrodes in a self-aligned manner. Therefore, the conductor 560 can be formed without providing an alignment margin, thereby reducing the area occupied by the transistor 500. This allows, for example, miniaturization and high integration of the memory device 210 provided in the layer 200.

[0156] Furthermore, since the conductor 560 is formed in a self-aligned manner in the region between the conductor 542a and the conductor 542b, the conductor 560 does not have a region that overlaps with the conductor 542a or the conductor 542b. This reduces the parasitic capacitance formed between the conductor 560 and the conductor 542a and between the conductor 560 and the conductor 542b. This improves the switching speed of the transistor 500 and provides high frequency characteristics.

[0157] The conductor 560 may function as a first gate (also referred to as a top gate) electrode. The conductor 503 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, applying a negative potential to the conductor 503 can increase the threshold voltage of the transistor 500 above 0 V and reduce the off-state current. Therefore, applying a negative potential to the conductor 503 can reduce the drain current when the potential applied to the conductor 560 is 0 V compared to when a negative potential is not applied.

[0158] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. In this way, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected, and a channel formation region formed in the oxide 530 can be covered. In this specification and the like, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first gate electrode and the second gate electrode is called a surrounded channel (S-channel) structure.

[0159] Conductor 503 has the same configuration as conductor 518, with conductor 503a being formed in contact with the inner walls of the openings of insulators 514 and 516, and conductor 503b being formed further inside.

[0160] Insulator 520, insulator 522, insulator 524, and insulator 550 function as gate insulators.

[0161] Here, the insulator 524 in contact with the oxide 530 preferably contains more oxygen than the oxygen required for the stoichiometric composition. That is, an excess oxygen region is preferably formed in the insulator 524. By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen vacancies in the oxide 530 can be reduced and the reliability of the transistor 500 can be improved.

[0162] Specifically, it is preferable to use an oxide that releases a portion of oxygen when heated as an insulator having an excess oxygen region. The oxide that releases oxygen when heated is an oxide that releases oxygen in terms of oxygen atoms when measured by thermal desorption spectroscopy (TDS analysis) in an amount of 1.0 x 10 18 atoms / cm 3 or more, preferably 1.0 × 10 19 atoms / cm 3 More preferably, 2.0 × 10 19 atoms / cm 3 or more, or 3.0 x 10 20 atoms / cm 3 The oxide film is one having the above properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0163] When the insulator 524 has an excess oxygen region, the insulator 522 preferably has a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (preferably making the oxygen less permeable).

[0164] The insulator 522 preferably has a function of suppressing diffusion of oxygen and impurities, which prevents oxygen contained in the oxide 530 from diffusing toward the insulator 520. Furthermore, reaction of the conductor 503 with oxygen contained in the insulator 524 or the oxide 530 can be suppressed.

[0165] The insulator 522 is preferably a single-layer or multi-layer insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, thinning the gate insulator can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulator allows for a reduction in the gate potential during transistor operation while maintaining the physical film thickness.

[0166] In particular, an insulator containing an oxide of one or both of aluminum and hafnium, which is an insulating material that has the function of suppressing the diffusion of impurities and oxygen (i.e., is difficult for oxygen to permeate), is preferably used. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator containing an oxide of one or both of aluminum and hafnium. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses oxygen release from the oxide 530 and the intrusion of impurities such as hydrogen into the oxide 530 from the periphery of the transistor 500.

[0167] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0168] Furthermore, the insulator 520 is preferably thermally stable. For example, silicon oxide and silicon oxynitride are thermally stable, and therefore, by combining them with a high-k material insulator, a thermally stable layered structure with a high dielectric constant can be obtained.

[0169] The insulators 520, 522, and 524 may have a stacked structure of four or more layers. In this case, the stacked structures are not limited to those made of the same material, and may be those made of different materials.

[0170] In the transistor 500, a metal oxide functioning as an oxide semiconductor is preferably used for the oxide 530 including the channel formation region. For example, a metal oxide such as In-M-Zn oxide (wherein the element M is one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used for the oxide 530. Alternatively, an In-Ga oxide or an In-Zn oxide may be used for the oxide 530.

[0171] The metal oxide that functions as a channel formation region in the oxide 530 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0172] The oxide 530 has the oxide 530a below the oxide 530b, which can prevent impurities from diffusing from structures formed below the oxide 530a to the oxide 530b. Also, the oxide 530 has the oxide 530c on the oxide 530b, which can prevent impurities from diffusing from structures formed above the oxide 530c to the oxide 530b.

[0173] The oxide 530 preferably has a layered structure made up of oxides with different atomic ratios of metal atoms. Specifically, the atomic ratio of the element M among the constituent elements in the metal oxide used for the oxide 530a is preferably greater than the atomic ratio of the element M among the constituent elements in the metal oxide used for the oxide 530b. The atomic ratio of the element M to In in the metal oxide used for the oxide 530a is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. The atomic ratio of In to M in the metal oxide used for the oxide 530b is preferably greater than the atomic ratio of In to M in the metal oxide used for the oxide 530a. The oxide 530c can be made up of the same metal oxide that can be used for the oxide 530a or the oxide 530b.

[0174] The oxides 530a and 530c preferably have a conduction band minimum energy higher than that of the oxide 530b, and the oxides 530a and 530c preferably have a lower electron affinity than that of the oxide 530b.

[0175] Here, the energy level of the conduction band minimum changes smoothly at the junction between the oxides 530a, 530b, and 530c. In other words, the energy level of the conduction band minimum at the junction between the oxides 530a, 530b, and 530c changes continuously or forms a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxides 530a and 530b and at the interface between the oxides 530b and 530c.

[0176] Specifically, when the oxides 530a and 530b, and the oxides 530b and 530c, contain a common element (main component) other than oxygen, a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, the oxides 530a and 530c may be made of an In-Ga-Zn oxide, a Ga-Zn oxide, or a gallium oxide.

[0177] In this case, the oxide 530b serves as the main carrier path. By configuring the oxide 530a and the oxide 530c as described above, the defect state density at the interface between the oxide 530a and the oxide 530b and at the interface between the oxide 530b and the oxide 530c can be reduced. This reduces the effect of interface scattering on carrier conduction, allowing the transistor 500 to obtain a high on-state current.

[0178] Conductor 542 (conductor 542a and conductor 542b) functioning as a source electrode and a drain electrode is provided on oxide 530b. Conductor 542 is preferably made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing any of the above metal elements or an alloy combining any of the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel is preferably used. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain their conductivity even when they absorb oxygen.

[0179] 5A, a region 543 (regions 543a and 543b) may be formed as a low-resistance region at and near the interface between the oxide 530 and the conductor 542. In this case, the region 543a functions as one of a source region and a drain region, and the region 543b functions as the other of the source region and the drain region. A channel formation region is formed in a region sandwiched between the regions 543a and 543b.

[0180] Providing the conductor 542 so as to be in contact with the oxide 530 may reduce the oxygen concentration in the region 543. Also, a metal compound layer containing the metal contained in the conductor 542 and components of the oxide 530 may be formed in the region 543. In such a case, the carrier density in the region 543 increases, and the region 543 becomes a low-resistance region.

[0181] The insulator 544 is provided to cover the conductor 542 and suppresses oxidation of the conductor 542. In this case, the insulator 544 may be provided to cover the side surface of the oxide 530 and to be in contact with the insulator 524.

[0182] The insulator 544 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, or the like.

[0183] In particular, it is preferable to use, as the insulator 544, an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). Hafnium aluminate is particularly preferable because it has higher heat resistance than hafnium oxide film. Therefore, it is less likely to crystallize during heat treatment in a later process. Note that if the conductor 542 is made of a material that is resistant to oxidation or does not significantly decrease in conductivity even when it absorbs oxygen, the insulator 544 is not an essential component. It can be designed appropriately depending on the desired transistor characteristics.

[0184] The insulator 550 functions as a gate insulator. The insulator 550 is preferably disposed in contact with the inside (top and side surfaces) of the oxide 530c. The insulator 550 is preferably formed using an insulator that releases oxygen when heated. For example, in thermal desorption spectroscopy (TDS analysis), the amount of released oxygen, converted into oxygen atoms, is 1.0×10 18 atoms / cm 3 or more, preferably 1.0 × 10 19 atoms / cm 3 More preferably, 2.0 × 10 19 atoms / cm 3 or more, or 3.0 x 10 20 atoms / cm 3 The oxide film is as described above. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower.

[0185] Specifically, it is possible to use silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having vacancies, etc. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0186] By providing the insulator 550, which releases oxygen upon heating, in contact with the top surface of the oxide 530c, oxygen can be effectively supplied from the insulator 550 to the channel formation region of the oxide 530b through the oxide 530c. Similarly to the insulator 524, the insulator 550 preferably has a low concentration of impurities such as water or hydrogen. The thickness of the insulator 550 is preferably 1 nm to 20 nm.

[0187] Furthermore, a metal oxide may be provided between the insulator 550 and the conductor 560 to efficiently supply excess oxygen contained in the insulator 550 to the oxide 530. The metal oxide preferably suppresses oxygen diffusion from the insulator 550 to the conductor 560. By providing a metal oxide that suppresses oxygen diffusion, the diffusion of excess oxygen from the insulator 550 to the conductor 560 is suppressed. In other words, a decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed. Furthermore, oxidation of the conductor 560 due to excess oxygen can be suppressed. As the metal oxide, a material that can be used for the insulator 544 may be used.

[0188] The conductor 560 functioning as the first gate electrode is shown as a two-layer structure in FIGS. 5A and 5B, but may be a single-layer structure or a stacked structure of three or more layers.

[0189] Conductor 560a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), and copper atoms. Alternatively, conductive material that has the function of suppressing the diffusion of oxygen (e.g., oxygen atoms, oxygen molecules, etc.) is preferably used. Conductor 560a has the function of suppressing the diffusion of oxygen, which can suppress the oxidation of conductor 560b due to oxygen contained in insulator 550, thereby preventing a decrease in conductivity. As a conductive material that has the function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used.

[0190] The conductor 560b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Because the conductor 560b also functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 560b may have a layered structure, such as a layered structure of titanium, titanium nitride, and the above-mentioned conductive material.

[0191] The insulator 580 is provided on the conductor 542 with the insulator 544 interposed therebetween. The insulator 580 preferably has an excess oxygen region. For example, the insulator 580 preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, or a resin. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Silicon oxide and silicon oxide having voids are particularly preferred because they allow for easy formation of an excess oxygen region in a later step.

[0192] The insulator 580 preferably has an excess oxygen region. By providing the insulator 580, from which oxygen is released by heating, in contact with the oxide 530c, oxygen in the insulator 580 can be efficiently supplied to the oxide 530 through the oxide 530c. Note that the concentration of impurities such as water or hydrogen in the insulator 580 is preferably reduced.

[0193] The opening of the insulator 580 is formed to overlap the region between the conductor 542a and the conductor 542b, so that the conductor 560 is formed to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.

[0194] When miniaturizing semiconductor devices, it is necessary to shorten the gate length, but it is also necessary to prevent the conductivity of the conductor 560 from decreasing. If the film thickness of the conductor 560 is increased to achieve this, the conductor 560 may have a shape with a high aspect ratio. In this embodiment, the conductor 560 is provided so as to be embedded in the opening of the insulator 580. Therefore, even if the conductor 560 has a shape with a high aspect ratio, the conductor 560 can be formed without collapsing during the process.

[0195] The insulator 574 is preferably provided in contact with the top surface of the insulator 580, the top surface of the conductor 560, and the top surface of the insulator 550. By forming the insulator 574 by a sputtering method, excess oxygen regions can be provided in the insulator 550 and the insulator 580. This allows oxygen to be supplied from the excess oxygen regions into the oxide 530.

[0196] For example, the insulator 574 can be a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like.

[0197] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even when it is a thin film with a thickness of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by sputtering can function as both an oxygen source and a barrier film against impurities such as hydrogen.

[0198] An insulator 581 functioning as an interlayer film is preferably provided over the insulator 574. Like the insulator 524, the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen.

[0199] Furthermore, conductors 540a and 540b are arranged in openings formed in insulators 581, 574, 580, and 544. Conductor 540a and 540b are arranged opposite each other with conductor 560 interposed therebetween. Conductor 540a and 540b have the same configuration as conductors 546 and 548, which will be described later.

[0200] An insulator 582 is provided over the insulator 581. The insulator 582 is preferably formed using a substance that has a barrier property against oxygen and hydrogen. Therefore, the insulator 582 can be formed using a material similar to that of the insulator 514. For example, the insulator 582 is preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0201] In particular, aluminum oxide has a high blocking effect against both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Aluminum oxide can also suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0202] An insulator 586 is provided over the insulator 582. The insulator 586 can be formed using a material similar to that of the insulator 420. When a material with a relatively low dielectric constant is used for the insulator, parasitic capacitance between wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 586.

[0203] Furthermore, conductors 546 and 548 are embedded in insulators 520, 522, 524, 544, 580, 574, 581, 582, and 586.

[0204] The conductor 546 and the conductor 548 function as a plug or a wiring that connects to the capacitor 600, the transistor 500, or the transistor 400a and the transistor 400b. The conductor 546 and the conductor 548 can be formed using a material similar to that of the conductor 428 and the conductor 430.

[0205] Subsequently, a capacitor 600 is provided above the transistor 500. The capacitor 600 includes a conductor 610, a conductor 620, and an insulator 630.

[0206] A conductor 612 may be provided over the conductor 546 and the conductor 548. The conductor 612 functions as a plug or wiring connected to the transistor 500. The conductor 610 functions as an electrode of the capacitor 600. Note that the conductor 612 and the conductor 610 can be formed at the same time.

[0207] A metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing any of the above elements (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film), etc. can be used for the conductor 612 and the conductor 610. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide with silicon oxide added can also be used.

[0208] 4, the conductor 612 and the conductor 610 are shown to have a single-layer structure, but are not limited to this configuration and may have a laminated structure of two or more layers. For example, a conductor having barrier properties and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having barrier properties and a conductor having high conductivity.

[0209] The conductor 620 is provided so as to overlap with the conductor 610 with the insulator 630 interposed therebetween. Note that the conductor 620 can be made of a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is particularly preferable. Furthermore, when the conductor 620 is formed simultaneously with other structures such as a conductor, a low-resistance metal material such as Cu (copper) or Al (aluminum) can be used.

[0210] An insulator 650 is provided over the conductor 620 and the insulator 630. The insulator 650 can be provided using a material similar to that of the insulator 420. The insulator 650 may also function as a planarizing film that covers the uneven shape underneath.

[0211] Furthermore, a conductor 646 and a conductor 648 are embedded in the insulator 650. The conductor 646 and the conductor 648 function as plugs connecting to the transistor 500, the transistor 400a, the transistor 400b, etc. The conductor 646 and the conductor 648 can be formed using a material similar to that of the conductor 428 and the conductor 430.

[0212] A conductor 660 is provided on the conductor 646 and the conductor 648. The conductor 660 can be provided using a material similar to that of the conductors 612 and 610. The conductor 660 corresponds to the conductor 201 in the first embodiment. That is, electrical connection with the layer 300 can be ensured via the conductor 660.

[0213] Note that a layer including elements similar to the transistor 500 and the capacitor 600 may be provided over the transistor 500 and the capacitor 600. By providing a plurality of layers including the transistor 500 and the capacitor 600, the storage capacity of the memory device 210 can be increased.

[0214] By using the above structure, in the layer 200 including the transistor including an oxide semiconductor, fluctuation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a memory device 210 with reduced power consumption can be provided. Alternatively, miniaturization or high integration can be achieved in the memory device 210 including a transistor including an oxide semiconductor.

[0215] <layer 300> Fig. 6 shows an example of a cross-sectional configuration of the layer 300. The example of the cross-sectional configuration of the layer 300 shown in Fig. 6 includes a transistor 700a and a pn junction photodiode 700c. The photodiode 700c functions as the photoelectric conversion element 313 in the first embodiment.

[0216] The transistor 700a is provided over a semiconductor substrate 711 and includes a conductor 716, an insulator 715, a semiconductor region 713 formed of part of the semiconductor substrate 711, and low-resistance regions 714a and 714b functioning as source and drain regions. The semiconductor substrate 711 corresponds to the semiconductor substrate SUB2 in the first embodiment.

[0217] In this embodiment, an n-type single crystal silicon substrate is used as the semiconductor substrate 711, for example. A part of the semiconductor substrate 711 functions as an n-type semiconductor for the photodiode 700c, and a p-type semiconductor region 718 provided in the semiconductor substrate 711 functions as a p-type semiconductor for the photodiode 700c. The transistor 700a functions as a p-channel transistor. Although an n-channel transistor is not shown in FIG. 6, it can be manufactured in the same manner as the above-described transistor 400b.

[0218] Low resistance region 714a, low resistance region 714b, and p-type semiconductor region 718 contain the semiconductor material applied to semiconductor region 713 plus an element that imparts p-type conductivity, such as boron.

[0219] The conductor 716 functioning as the gate electrode can be made of a conductive material such as a semiconductor material such as silicon containing an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron, a metal material, an alloy material, or a metal oxide material.

[0220] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by changing the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride as the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum stacked on the conductor, and tungsten is particularly preferable in terms of heat resistance.

[0221] An insulator 720, an insulator 722, an insulator 724, and an insulator 726 are stacked in this order to cover the transistor 700a and the photodiode 700c.

[0222] The insulators 720, 722, 724, and 726 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like.

[0223] The insulator 722 may function as a planarizing film to planarize steps caused by the transistor 700a or the like provided thereunder. For example, the top surface of the insulator 722 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve the planarity. The CMP process reduces the unevenness of the sample surface and improves the coverage of an insulating layer or a conductive layer to be formed later. Alternatively, the insulator 722 may be made of a low-k material, a siloxane-based resin, PSG (phosphorus glass), BPSG (borophosphorus glass), or the like.

[0224] Furthermore, a conductor 728, a conductor 730, and the like are embedded in the insulator 720, the insulator 722, the insulator 724, and the insulator 726. Note that the conductor 728 and the conductor 730 function as plugs or wirings.

[0225] The materials for each plug and wiring (such as the conductor 728 and the conductor 730) can be a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material, and can be used in a single layer or a stacked layer. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferred. Alternatively, it is preferable to form the plug and wiring from a low-resistance conductive material such as aluminum or copper. Using a low-resistance conductive material can reduce the wiring resistance.

[0226] A wiring layer may be provided over the insulator 726 and the conductor 730. For example, in FIG. 6, the insulator 750, the insulator 752, and the insulator 754 are stacked in this order. The conductor 756 is formed over the insulator 750, the insulator 752, and the insulator 754. The conductor 756 functions as a plug or wiring connected to the transistor 700a or the like. The conductor 756 can be formed using a material similar to that of the conductor 728 and the conductor 730. The insulator 750, the insulator 752, and the insulator 754 can be formed using a material similar to that of the insulator 720 or the like.

[0227] A wiring layer may be provided over the insulator 754 and the conductor 756. For example, in FIG. 6, insulator 760, insulator 762, and insulator 764 are stacked in this order. A conductor 766 is formed in the insulators 760, 762, and 764. The conductor 766 functions as a plug or a wiring. The conductor 766 can be formed using a material similar to that of the conductors 728 and 730. The insulators 760, 762, and 764 can be formed using a material similar to that of the insulator 720, etc.

[0228] Although the above describes a wiring layer including the conductor 756 and a wiring layer including the conductor 766, the cross-sectional structure of the layer 300 is not limited to this. There may be one wiring layer similar to the wiring layer including the conductor 756, or there may be three or more wiring layers similar to the wiring layer including the conductor 756.

[0229] A conductor 770 is provided over the conductor 766. The conductor 770 can be provided using a material similar to that of the conductors 728 and 730. The conductor 770 corresponds to the conductor 301 in Embodiment 1. That is, electrical connection between the layer 100 and the layer 200 can be ensured through the conductor 770.

[0230] <Imaging device 10> The imaging device 10 is configured by bonding together the above-described layers 100 and 200, and the layer 300. An example of the cross-sectional configuration of the imaging device 10 is shown in FIG.

[0231] The imaging device 10 is configured by bonding together a surface of the semiconductor substrate 411 on which the transistor 400a, the transistor 400b, the transistor 500, the capacitor 600, and the like are provided in the layer 100 and the layer 200, and a surface of the layer 300 on which the transistor 700a, the photodiode 700c, and the like are provided. Note that the imaging device 10 shown in FIG. 7 differs from FIGS. 4 and 6 in that some reference numerals, a layer including the conductor 466, and a layer including the conductor 756 are omitted, and some figures are shown at different scales.

[0232] 7, the layer 100 and the layer 200 are bonded to the layer 300, and the conductor 660 and the conductor 770 are electrically connected to each other. After the layer 100 and the layer 200 are bonded to the layer 300, the semiconductor substrate 711 of the layer 300 is thinned to form the imaging device 10.

[0233] The photodiode 700c captures light transmitted through the semiconductor substrate 711 and converts it into an electrical signal. The electrical signal converted by the photodiode 700c is converted into a digital signal by the signal processing circuit 110 or an analog-to-digital conversion circuit included in the image sensor 310. The electrical signal converted by the photodiode 700c is transmitted to the signal processing circuit 110 via the conductor 770 and the conductor 660.

[0234] <Transistor configuration example 1> 4 and 5 illustrate a configuration example in which the conductor 542 functioning as a source electrode or a drain electrode is formed in contact with the oxide 530. However, the configuration of the OS transistor is not limited to this. For example, a configuration in which the conductor 542 is not provided and the oxide 530b is selectively made low-resistance by reducing the resistance of the oxide 530 can be used in which the source region or the drain region is provided in the oxide 530b. An example of such a transistor configuration is shown in FIG.

[0235] 8A is a cross-sectional view of the transistor 500A in the channel length direction, and FIG. 8B is a cross-sectional view of the transistor 500A in the channel width direction. Note that the transistor 500A shown in FIG. 8 is a modified example of the transistor 500 shown in FIG. 5. Therefore, to avoid repetition of description, differences from the transistor 500 will be mainly described.

[0236] In the transistor 500A, similarly to the transistor 500, a metal oxide functioning as an oxide semiconductor can be used for the oxide 530 including the channel formation region.

[0237] The oxide 530 may have an increased carrier density and a lower resistance when doped with an element that forms oxygen vacancies or an element that bonds with oxygen vacancies. Typical elements that lower the resistance of the oxide 530 include boron and phosphorus. Other elements that may be used include hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, and rare gases. Typical examples of rare gases include helium, neon, argon, krypton, and xenon.

[0238] The concentrations of the above elements may be measured using secondary ion mass spectrometry (SIMS) or the like.

[0239] Boron and phosphorus are particularly preferred because they allow the use of equipment from manufacturing lines for amorphous silicon or low-temperature polysilicon, and existing facilities can be repurposed, thereby reducing capital investment.

[0240] 8, the region 543 (region 543a and region 543b) is a region where the above-mentioned element is added to the oxide 530b. The region 543 can be formed by using a dummy gate, for example.

[0241] For example, a dummy gate may be provided on the oxide 530b, and an element that reduces the resistance of the oxide 530b may be added using the dummy gate as a mask. That is, the element is added to a region of the oxide 530b that does not overlap with the dummy gate, forming a region 543. The element may be added by ion implantation, which adds an ionized source gas after mass separation, ion doping, which adds an ionized source gas without mass separation, or plasma immersion ion implantation.

[0242] Subsequently, an insulating film to be the insulator 544 and an insulating film to be the insulator 545 may be formed on the oxide 530b and the dummy gate. By stacking the insulating film to be the insulator 544 and the insulating film to be the insulator 545, a region can be formed in which the region 543 overlaps with the oxide 530c and the insulator 550.

[0243] Specifically, an insulating film to be the insulator 580 is formed on an insulating film to be the insulator 545, and then a chemical mechanical polishing (CMP) process is performed on the insulating film to be the insulator 580 to remove a portion of the insulating film to be the insulator 580 and expose the dummy gate. Subsequently, when removing the dummy gate, a portion of the insulator 544 in contact with the dummy gate may also be removed. Therefore, the insulators 545 and 544 are exposed on the side surfaces of the opening formed in the insulator 580, and a portion of the region 543 formed in the oxide 530b is exposed on the bottom surface of the opening. Next, an oxide film to be the oxide 530c, an insulating film to be the insulator 550, and a conductive film to be the conductor 560 are sequentially formed in the opening. Then, by performing a CMP process or the like until the insulator 580 is exposed, the oxide film to be the oxide 530c, the insulating film to be the insulator 550, and the conductive film to be the conductor 560 are partially removed, thereby forming the transistor shown in FIG. 8 .

[0244] Note that the insulators 544 and 545 are not essential components and may be appropriately designed depending on desired transistor characteristics.

[0245] The transistor shown in FIG. 8 can be an existing device and does not include the conductor 542, which contributes to cost reduction.

[0246] <Transistor configuration example 2> 4 and 5 illustrate a configuration example in which the conductor 560 functioning as a gate is formed inside the opening of the insulator 580. However, the configuration of the OS transistor is not limited to this. For example, a configuration in which the insulator is provided above the conductor may also be used. Configuration examples of such a transistor are shown in FIGS. 9 and 10.

[0247] Fig. 9A is a top view of the transistor, and Fig. 9B is a perspective view of the transistor. Fig. 10A shows a cross-sectional view taken along X1-X2 in Fig. 9A, and Fig. 10B shows a cross-sectional view taken along Y1-Y2 in Fig. 9A.

[0248] 9 and 10 includes a conductor BGE functioning as a back gate, an insulator BGI functioning as a gate insulating film, an oxide semiconductor S, an insulator FGI functioning as a gate insulating film, a conductor FGE functioning as a front gate, and a conductor WE functioning as wiring. The conductor PE functions as a plug for connecting the conductor WE to the oxide S, the conductor BGE, or the conductor FGE. Here, an example is shown in which the oxide semiconductor S is composed of three layers of oxides S1, S2, and S3.

[0249] <Transistor electrical characteristics> Next, the electrical characteristics of an OS transistor are described. A transistor having a first gate and a second gate will be described below as an example. The threshold voltage of a transistor having a first gate and a second gate can be controlled by applying different potentials to the first gate and the second gate. For example, applying a negative potential to the second gate can increase the threshold voltage of the transistor above 0 V, thereby reducing the off-state current. That is, applying a negative potential to the second gate can reduce the drain current when the potential applied to the first electrode is 0 V.

[0250] Furthermore, when an impurity such as hydrogen is added to an oxide semiconductor, the carrier density may increase. For example, when hydrogen is added to an oxide semiconductor, it may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, the carrier density increases. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons, which serve as carriers. In other words, an oxide semiconductor doped with an impurity such as hydrogen becomes n-type and has low resistance.

[0251] Therefore, the resistance of the oxide semiconductor can be selectively reduced. That is, the oxide semiconductor can be provided with a region having a low carrier density and functioning as a semiconductor that functions as a channel formation region, and a region having a high carrier density and reduced resistance that functions as a source region or a drain region.

[0252] Here, when different potentials are applied to the first gate and the second gate, the influence of the configuration of the low-resistance region and the high-resistance region provided in the oxide semiconductor on the electrical characteristics of the transistor is evaluated.

[0253] [Transistor structure] 11A and 11C are cross-sectional views of a transistor used to evaluate its electrical characteristics, with some elements omitted for clarity.

[0254] 11A and 11C includes a conductor TGE functioning as a first gate, an insulator TGI functioning as a first gate insulating film, an insulator SW functioning as a sidewall provided on a side surface of the first gate, an oxide semiconductor S, a conductor BGE functioning as a second gate, and an insulator BGI functioning as a second gate insulator. The insulator BGI has a three-layer structure including a first layer in contact with the conductor BGE, a second layer on the first layer, and a third layer on the second layer. The third layer is in contact with the oxide semiconductor S.

[0255] Here, the oxide semiconductor S included in the transistor illustrated in FIG. + On the other hand, the oxide semiconductor S included in the transistor in FIG. + region, an i region overlapping with the conductor TGE, and n + n between area and i area - The region has:

[0256] In addition, n +The i-region functions as a source region or a drain region, and is a region with high carrier density and low resistance. The n-region functions as a channel formation region. + This is a high-resistivity region with a lower carrier density than the n - The area is n + The carrier density is lower than that of the i-region, but higher than that of the n-region.

[0257] Although not shown, the n + The region is in contact with the S / D electrode that functions as the source or drain.

[0258] [Electrical characteristics evaluation results] The Id-Vg characteristics of the transistor illustrated in FIG. 11A and the transistor illustrated in FIG. 11C were calculated to evaluate the electrical characteristics of the transistor.

[0259] Here, the amount of change in threshold voltage (hereinafter also referred to as Vsh) of a transistor (hereinafter also referred to as ΔVsh) was used as an indicator of the electrical characteristics of the transistor. Note that Vsh is defined as Id=1.0×10 -12 It is defined as the value of Vg at [A].

[0260] The Id-Vg characteristics are the fluctuation characteristics of the current between the source and drain (hereinafter also referred to as the drain current (Id)) when the potential (hereinafter also referred to as the gate potential (Vg)) applied to the conductor TGE functioning as the first gate of the transistor is changed from a first value to a second value.

[0261] Here, the potential between the source and drain (hereinafter also referred to as the drain potential Vd) was set to +0.1 V, and the change in the drain current (Id) was evaluated when the potential between the source and the conductor TGE functioning as the first gate was changed from -1 V to +4 V.

[0262] The calculations were performed using the Silvaco device simulator ATLAS. Table 1 shows the parameters used in the calculations. Eg is the energy gap, Nc is the effective density of states in the conduction band, and Nv is the effective density of states in the valence band.

[0263] [Table 1]

[0264] The transistor shown in FIG. 11(A) has one n + The area is 700 nm, and - The region was set to 0 nm. The transistor shown in FIG. 11(C) has n + The region is set to 655 nm, and n - The region was set to 45 nm. In the transistor shown in Figure 11(A) and the transistor shown in Figure 11(C), the second gate was larger than the i-region. In this evaluation, the potential of the conductor BGE functioning as the second gate (hereinafter also referred to as back-gate potential (Vbg)) was set to 0.00 V, -3.00 V, or -6.00 V.

[0265] Figure 11B shows the calculated Id-Vg characteristics of the transistor shown in Figure 11A. When the back-gate potential was set to -3.00 V, the threshold voltage of the transistor (ΔVsh) changed by +1.2 V compared to when the back-gate potential was set to 0.00 V. When the back-gate potential was set to -6.00 V, the threshold voltage of the transistor (ΔVsh) changed by +2.3 V compared to when the back-gate potential was set to 0.00 V. That is, when the back-gate potential was set to -6.00 V, the threshold voltage of the transistor (ΔVsh) changed by +1.1 V compared to when the back-gate potential was set to -3.00 V. Therefore, increasing the potential of the conductor BGE functioning as the second gate hardly changed the threshold voltage of the transistor. Furthermore, increasing the back-gate potential did not change the rise characteristics.

[0266] Figure 11(D) shows the calculated Id-Vg characteristics of the transistor shown in Figure 11(C). When the back-gate potential was -3.00 V, the threshold voltage of the transistor (ΔVsh) changed by +1.2 V compared to when the back-gate potential was 0.00 V. When the back-gate potential was -6.00 V, the threshold voltage of the transistor (ΔVsh) changed by +3.5 V compared to when the back-gate potential was 0.00 V. That is, when the back-gate potential was -6.00 V, the threshold voltage of the transistor (ΔVsh) changed by +2.3 V compared to when the back-gate potential was -3.00 V. Therefore, the higher the potential of the conductor BGE functioning as the second gate, the larger the change in the threshold voltage of the transistor. On the other hand, the rise characteristics deteriorated as the back-gate potential increased.

[0267] 11C, the amount of change in the threshold voltage of the transistor increases as the potential of the conductor BGE functioning as the second gate increases. On the other hand, the amount of change in the threshold voltage of the transistor shown in FIG. 11A did not change even when the potential of the conductor BGE functioning as the second gate increased.

[0268] Note that this embodiment mode can be implemented in appropriate combination with other embodiment modes described in this specification.

[0269] (Embodiment 3) In this embodiment, a structure of a metal oxide that can be used for the OS transistor described in the above embodiment will be described.

[0270] <Metal oxide composition> In this specification, etc., they may be referred to as CAAC (c-axis aligned crystal) and CAC (Cloud-Aligned Composite). CAAC represents an example of a crystal structure, and CAC represents an example of a function or material configuration.

[0271] CAC-OS or CAC-metal oxide has a conductive function in part of the material and an insulating function in part of the material, and functions as a semiconductor as a whole. When CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, the conductive function is a function of allowing electrons (or holes) to flow as carriers, and the insulating function is a function of preventing the flow of electrons as carriers. By making the conductive function and the insulating function act complementarily, a switching function (on / off function) can be imparted to CAC-OS or CAC-metal oxide. By separating the respective functions in CAC-OS or CAC-metal oxide, both functions can be maximized.

[0272] Furthermore, CAC-OS or CAC-metal oxide has conductive regions and insulating regions. The conductive regions have the above-mentioned conductive function, and the insulating regions have the above-mentioned insulating function. In addition, the conductive regions and the insulating regions may be separated at the nanoparticle level in the material. In addition, the conductive regions and the insulating regions may be unevenly distributed in the material. In addition, the conductive regions may be observed as connected in a cloud-like shape with the periphery blurred.

[0273] In addition, in CAC-OS or CAC-metal oxide, the conductive regions and the insulating regions may be dispersed in the material with sizes of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm.

[0274] Furthermore, the CAC-OS or CAC-metal oxide is composed of components with different band gaps. For example, the CAC-OS or CAC-metal oxide is composed of a component with a wide gap due to an insulating region and a component with a narrow gap due to a conductive region. In this configuration, when carriers flow, the carriers mainly flow in the component with the narrow gap. Furthermore, the component with the narrow gap acts complementarily with the component with the wide gap, and carriers also flow in the component with the wide gap in conjunction with the component with the narrow gap. Therefore, when the CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, the transistor can achieve high current driving power in the on state, i.e., a large on-state current, and high field-effect mobility.

[0275] That is, CAC-OS or CAC-metal oxide can also be called a matrix composite or a metal matrix composite.

[0276] <Metal oxide structure> Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors, such as c-axis aligned crystalline oxide semiconductors (CAAC-OS), polycrystalline oxide semiconductors, nanocrystalline oxide semiconductors (nc-OS), amorphous-like oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0277] It is preferable to use a thin film with high crystallinity as the oxide semiconductor used as the semiconductor of a transistor. The use of such a thin film can improve the stability or reliability of the transistor. Examples of such a thin film include a thin film of a single-crystal oxide semiconductor or a thin film of a polycrystalline oxide semiconductor. However, forming a thin film of a single-crystal oxide semiconductor or a polycrystalline oxide semiconductor on a substrate requires a high-temperature or laser heating process. This increases the cost of the manufacturing process and also reduces throughput.

[0278] In 2009, the discovery of In-Ga-Zn oxide with a CAAC structure (referred to as CAAC-IGZO) was reported in Non-Patent Documents 2 and 3. It was reported that CAAC-IGZO has a c-axis orientation, no clearly visible grain boundaries, and can be formed on a substrate at low temperatures. Furthermore, it was reported that transistors using CAAC-IGZO have excellent electrical properties and reliability.

[0279] In 2013, an In-Ga-Zn oxide (called nc-IGZO) with an nc structure was discovered (see Non-Patent Document 4). It was reported that nc-IGZO has periodic atomic arrangement in minute regions (for example, regions of 1 nm to 3 nm), and no regularity in the crystal orientation is observed between different regions.

[0280] Non-Patent Documents 5 and 6 show the changes in average crystal size due to electron beam irradiation in thin films of the above-mentioned CAAC-IGZO, nc-IGZO, and low-crystalline IGZO. Crystalline IGZO of approximately 1 nm was observed in the low-crystalline IGZO thin film even before electron beam irradiation. Therefore, it was reported that the presence of a completely amorphous structure could not be confirmed in IGZO. Furthermore, compared with low-crystalline IGZO thin films, CAAC-IGZO thin films and nc-IGZO thin films have been shown to be more stable against electron beam irradiation. Therefore, it is preferable to use CAAC-IGZO thin films or nc-IGZO thin films as semiconductors for transistors.

[0281] CAAC-OS has a c-axis orientation and a distorted crystal structure in which multiple nanocrystals are connected in the ab-plane direction. The distorted crystal structure refers to the change in the lattice orientation between regions with a uniform lattice arrangement and regions with a different uniform lattice arrangement in the regions where multiple nanocrystals are connected.

[0282] Nanocrystals are basically hexagonal, but not necessarily regular hexagons; they can also have non-regular hexagonal shapes. Furthermore, the lattice arrangements of CAAC-OSs can be pentagonal, heptagonal, or other shapes due to distortion. In CAAC-OSs, no clear grain boundaries are observed even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because CAAC-OSs can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by the substitution of metal elements.

[0283] CAAC-OS also tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing the element M, zinc, and oxygen (hereinafter referred to as an (M,Zn) layer) are stacked. Note that indium and the element M are mutually substituted, and when the element M in an (M,Zn) layer is substituted with indium, it can also be expressed as an (In,M,Zn) layer. When the indium in an In layer is substituted with the element M, it can also be expressed as an (In,M) layer.

[0284] CAAC-OS is an oxide semiconductor with high crystallinity. On the other hand, because no clear grain boundaries are observed in CAAC-OS, it can be said that a decrease in electron mobility due to grain boundaries is unlikely to occur. Furthermore, because the crystallinity of oxide semiconductors can be reduced by the inclusion of impurities or the generation of defects, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, CAAC-OS is stable even under high temperatures (so-called thermal budgets) during the manufacturing process. Therefore, using CAAC-OS for OS transistors can increase the flexibility of the manufacturing process.

[0285] The nc-OS has periodic atomic arrangement in a small region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor.

[0286] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS.

[0287] Oxide semiconductors have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

[0288] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0289] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0290] Furthermore, the transistor including the oxide semiconductor has an extremely small leakage current in an off-state. Specifically, the off-state current per 1 μm of the channel width of the transistor is yA / μm (10 -24 Non-Patent Document 7 shows that the leakage current is on the order of A / μm. For example, a low-power-consumption CPU that utilizes the low leakage current characteristics of transistors using oxide semiconductors has been disclosed (see Non-Patent Document 8).

[0291] Furthermore, the application of oxide semiconductor transistors to display devices has been reported, taking advantage of their low leakage current (see Non-Patent Document 9). Display devices change the displayed image several tens of times per second. The number of image changes per second is called the refresh rate. The refresh rate is also sometimes called the drive frequency. Such high-speed screen changes, which are difficult for the human eye to perceive, are thought to cause eye fatigue. Therefore, it has been proposed to reduce the refresh rate of display devices to reduce the number of times the image is rewritten. Furthermore, driving at a reduced refresh rate can reduce the power consumption of display devices. This driving method is called idling stop (IDS) driving.

[0292] Furthermore, it is preferable to use an oxide semiconductor with low carrier density for the transistor. In order to reduce the carrier density of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high-purity intrinsic or substantially high-purity intrinsic. For example, an oxide semiconductor having a carrier density of 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 less than 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 That's all there is to it.

[0293] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0294] In addition, charges trapped in the trap states of an oxide semiconductor take a long time to dissipate and may behave like fixed charges. Therefore, a transistor having a channel region formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0295] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0296] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0297] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentrations of silicon or carbon in the oxide semiconductor and those near the interface with the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are calculated as follows: 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0298] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect states may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. For this reason, it is preferable to reduce the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor. Specifically, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is preferably reduced to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0299] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier density increases, and the oxide semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Therefore, it is preferable that nitrogen be reduced as much as possible in the oxide semiconductor. For example, the nitrogen concentration in the oxide semiconductor is 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 The following applies.

[0300] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in an oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Less than.

[0301] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0302] The discovery of the CAAC structure and the nc structure has contributed to improving the electrical characteristics and reliability of transistors using oxide semiconductors with the CAAC structure or the nc structure, as well as reducing the cost and increasing the throughput of the manufacturing process. Furthermore, research into the application of the transistor to display devices and LSIs is ongoing, taking advantage of the low leakage current of the transistor.

[0303] Note that this embodiment mode can be implemented in appropriate combination with other embodiment modes described in this specification.

[0304] (Fourth embodiment) In this embodiment, an example of an electronic device incorporating the imaging device 10 described in the above embodiment will be described.

[0305] FIG. 12A shows a surveillance camera, which includes a housing 951, a lens 952, a support portion 953, and the like. The imaging device according to one embodiment of the present invention can be provided as one of the components for acquiring an image in the surveillance camera. This allows the surveillance camera to be made smaller and lighter. Furthermore, a surveillance camera with high reliability even in a high-temperature environment can be provided. Note that the term "surveillance camera" is a common name and does not limit the application. For example, a device having a function as a surveillance camera is also called a camera or a video camera.

[0306] FIG. 12B shows a video camera including a first housing 971, a second housing 972, a display unit 973, operation buttons 974, a lens 975, a connection unit 976, and the like. The operation buttons 974 and the lens 975 are provided in the first housing 971, and the display unit 973 is provided in the second housing 972. The imaging device according to one embodiment of the present invention can be provided as one of the components for acquiring an image in the video camera. This allows the video camera to be made smaller and lighter. Furthermore, a video camera capable of long-term imaging with reduced power consumption can be provided. Furthermore, a video camera capable of high-speed imaging can be provided.

[0307] 12C shows a digital camera including a housing 961, a shutter button 962, a microphone 963, a light-emitting unit 967, a lens 965, and the like. The imaging device according to one embodiment of the present invention can be provided as one of the components for acquiring an image in the digital camera. This allows the digital camera to be made smaller and lighter. Furthermore, a digital camera capable of high-speed imaging can be provided.

[0308] FIG. 12D shows a mobile phone (smartphone), which includes a housing 981, a display portion 982, a microphone 987, a speaker 984, a camera 989, an input / output terminal 986, operation buttons 985, and the like. The display portion 982 has a touch panel function, allowing input and output of information. The mobile phone can be provided with an imaging device according to one embodiment of the present invention as one of components for acquiring an image. This allows the mobile phone to be made smaller and lighter. Furthermore, a mobile phone capable of high-speed imaging can be provided. Furthermore, a mobile phone with reduced power consumption during imaging operation can be provided.

[0309] 13 includes a computing device 910, an illuminance sensor 901, a microphone 902, an upper camera 903, a speaker 904, a display 905, a lower camera 906, an obstacle sensor 907, and a movement mechanism 908. The upper camera 903 and the lower camera 906 have the function of capturing images of the surroundings of the robot 900. The obstacle sensor 907 can detect the presence or absence of obstacles in the direction of travel when the robot 900 moves forward using the movement mechanism 908. The robot 900 can recognize the surrounding environment and move safely using the upper camera 903, the lower camera 906, and the obstacle sensor 907.

[0310] In the robot 900, the upper camera 903 and the lower camera 906 can be equipped with an imaging device according to an embodiment of the present invention as one of the components for acquiring images. This allows the robot to be made smaller and lighter. Furthermore, it is possible to provide a highly reliable robot that can move safely even in high-temperature environments.

[0311] Note that the electronic devices, functions, effects, and the like described in this embodiment can be appropriately combined with those of other electronic devices. This embodiment can also be implemented in appropriate combination with other embodiments described in this specification. [Example]

[0312] In this example, we fabricated a prototype DRAM (DOSRAM) in which oxide semiconductor transistors were used as memory cells, and confirmed that the prototype DOSRAM can retain stored data for 100,000 seconds. Furthermore, by reducing the refresh frequency, it is estimated that power consumption can be reduced by up to 50% compared to conventional DRAM.

[0313] The specifications of the prototype DOSRAM are shown in Table 2. This DOSRAM uses a 60nm OSFET process for the memory cells, and uses oxide semiconductor transistors. The driver circuits, which have functions such as selecting memory cells, writing data to memory cells, and reading data stored in memory cells, use a 65nm CMOS process and use Si transistors.

[0314] [Table 2]

[0315] Figure 14(A) shows the Shmoo plot at 25°C, and Figure 14(B) shows the Shmoo plot at 85°C. It can be seen that operation is possible with a cycle time of 10 ns at a supply voltage of 1.2 V and in the temperature range from 25°C to 85°C. This falls within the specifications of conventional DRAM, and therefore compatibility with conventional DRAM is considered to be maintained.

[0316] Figure 15 shows the memory retention characteristics at 85°C. 5 Even after 10 seconds, the device showed excellent data retention characteristics with a rate of correct bit of 99.97%.

[0317] Figure 16 shows the results of estimating power consumption (Power Consumption Ratio) for DRAM, DOSRAM, and DOSRAM with power gating. In Figure 16, it is assumed that oxide semiconductor transistors have been miniaturized to achieve the same cell size and memory capacity as DRAM. Figure 16(A) shows the cases where the number of I / Os is multiplied by 4, Figure 16(B) shows the cases where the number of I / Os is multiplied by 8, and Figure 16(C) shows the cases where the number of I / Os is multiplied by 16, and the memory capacities are 4 Gbit, 8 Gbit, and 16 Gbit, respectively.

[0318] DOSRAM does not require refresh operations, so the power required for refresh operations can be reduced. Furthermore, standby power can also be reduced by using power gating. On the other hand, the percentage of power required for refresh operations in total power increases as the memory density increases and the number of I / Os decreases. As a result, it is estimated that total power can be reduced by up to 50% (see Figure 16(A)). For the calculations, Micron's "Micron DDR4 SDRAM System-Power Calculator" was used. [Explanation of symbols]

[0319] a1: node, a2: node, a3: node, a4: node, N1: node, S: oxide, S1: oxide, SUB1: semiconductor substrate, SUB2: semiconductor substrate, 10: imaging device, 15: imaging device, 20: light, 100: layer, 110: signal processing circuit, 111: control circuit, 112: control circuit, 113: image processing circuit, 114: input / output circuit, 115: bus line, 116: power supply circuit, 200: layer, 200a: layer, 201: conductor, 210: memory device, 211: cell array, 212: memory cell, 213: transistor, 214: capacitance element, 215: transistor, 2 21: driving circuit, 222: driving circuit, 300: layer, 301: conductor, 310: image sensor, 311: pixel array, 312: pixel, 313: photoelectric conversion element, 314: transistor, 315: transistor, 316: transistor, 317: transistor, 318: capacitance element, 321: driving circuit, 322: driving circuit, 331: node, 332: wiring, 333: wiring, 334: wiring, 400: transistor, 400a: transistor, 400b: transistor, 411: semiconductor substrate, 413: semiconductor region, 414a: low resistance region, 414b: low resistance region, 4 15: insulator, 416: conductor, 417: semiconductor region, 418a: low resistance region, 418b: low resistance region, 420: insulator, 422: insulator, 424: insulator, 426: insulator, 428: conductor, 430: conductor, 450: insulator, 452: insulator, 454: insulator, 456: conductor, 460: insulator, 462: insulator, 464: insulator, 466: conductor, 500: transistor, 500A: transistor, 503: conductor, 503a: conductor, 503b: conductor, 510: insulator, 512: insulator, 514: insulator, 516: insulator, 518: conductor, 520: insulator, 522: insulator, 524: insulator, 530: oxide, 530a: oxide, 530b: oxide, 530c: oxide, 540a: conductor, 540b: conductor, 542: conductor, 542a: conductor, 542b: conductor, 543: region, 543a: region, 543b: region, 544: insulator, 545: insulator, 546: conductor, 548: conductor, 550: insulator, 560: conductor, 560a: conductor, 560b: conductor, 574: insulator, 580: insulator, 581: insulator, 582: insulator, 586: insulator, 600: capacitance element, 610: conductor,612: conductor, 620: conductor, 630: insulator, 646: conductor, 648: conductor, 650: insulator, 660: conductor, 700a: transistor, 700c: photodiode, 711: semiconductor substrate, 713: semiconductor region, 714a: low resistance region, 714b: low resistance region, 715: insulator, 716: conductor, 718: p-type semiconductor region, 720: insulator, 722: insulator, 724: insulator, 726: insulator, 728: conductor, 730: conductor, 750: insulator, 752: insulator, 754: insulator, 756: conductor, 760: insulator, 762: insulator, 764: insulator, 766: conductor, 770: conductor, 900: robot, 901: illuminance sensor, 902: microphone, 903: upper camera, 904: speaker, 905: display, 906: lower camera, 907: obstacle sensor, 908: movement mechanism, 910: computing device, 951: housing, 952: lens, 953: support part, 961: housing, 962: shutter button, 963: microphone, 965: lens, 967: light emitting part, 971: housing, 972: housing, 973: display part, 974: button, 975: lens, 976: connection part, 981: housing, 982: display part, 984: speaker, 985: button, 986: input / output terminal, 987: microphone, 989: camera,

Claims

[Claim 1] a first layer; and a second layer above the first layer; a third layer above the second layer; and a fourth layer above the third layer, the first layer has a signal processing circuit; the second layer having a first stacked plurality of plugs and a first memory device; the third layer having a second stacked plurality of plugs and a second memory device; the fourth layer has an image sensor; the signal processing circuit has a first transistor formed on a first semiconductor substrate; the first memory device includes a first memory cell, a driver circuit having a function of selecting the first memory cell, and a driver circuit having a function of writing data to the first memory cell; the first memory device includes a second transistor including a metal oxide in a channel formation region; the second memory device includes a second memory cell, a driver circuit having a function of selecting the second memory cell, and a driver circuit having a function of writing data to the second memory cell; the second memory device includes a third transistor including a metal oxide in a channel formation region; the image sensor has a fourth transistor formed on a second semiconductor substrate; the first transistor is disposed on a first surface side of the first semiconductor substrate; the fourth transistor is disposed on a first surface side of the second semiconductor substrate, the first stacked plurality of plugs are provided to penetrate the second layer; the second stacked plurality of plugs are provided to penetrate the third layer; the first plurality of stacked plugs have an area overlapping with the second plurality of stacked plugs; the second memory device is electrically connected to the signal processing circuit via the second plurality of stacked plugs and the first plurality of stacked plugs; an imaging device, wherein the first semiconductor substrate and the second semiconductor substrate are bonded together so that a first surface of the first semiconductor substrate faces a first surface of the second semiconductor substrate;

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