Transistor channel with vertically stacked nanosheets connected by a fin-shaped bridge region

Abstract

To provide methods for forming a novel field effect transistor (FET) that includes a center fin region and one or more vertically stacked nanosheets.SOLUTION: A method for forming a non-planar channel region having a first semiconductor layer, a second semiconductor layer, and a fin-shaped bridge layer between the first semiconductor layer and the second semiconductor layer. Forming the non-planar channel region includes forming a nanosheet stack over a substrate, forming a trench by removing a portion of the nanosheet stack, and forming the second semiconductor layer in the trench. Outer surfaces of the first semiconductor layer, the second semiconductor layer and the fin-shaped bridge region define an effective channel width of the non-planar channel region.SELECTED DRAWING: Figure 36

Description

[Technical Field]

[0001] The present invention relates generally to methods for fabricating semiconductor devices and the resulting structures, and more particularly to methods for fabricating novel field-effect transistor (FET) architectures configured to include non-planar channels having vertically stacked nanosheets connected to one another by fin-shaped bridge regions. This novel FET and non-planar channel structure is identified herein as an X-FET device / structure. [Background technology]

[0002] Conventional metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication techniques involve a process flow for constructing a planar field-effect transistor (FET). A planar FET includes a substrate (also called a silicon slab), a gate formed on top of the substrate, source and drain regions formed on either side of the gate, and a channel region near the surface of the substrate below the gate. The channel region electrically connects the source region to the drain region, and the gate controls the current flow in the channel. The gate voltage controls whether the path from drain to source is an open circuit ("off") or a resistive path ("on").

[0003] In recent years, research has focused on developing nonplanar transistor structures to achieve greater device density, higher power efficiency, and certain enhanced performance than lateral devices. For example, in nonplanar transistor structures known as nanosheet-type field-effect transistors (NSFETs), a gate stack wraps around the entire periphery of each nanosheet. These nonplanar structures can provide more complete depletion of the channel region compared to some planar devices, reducing short-channel effects due to a steeper subthreshold swing (SS) and smaller drain-induced barrier lowering (DIBL). The wraparound gate structure and source / drain contacts used in NSFETs (sometimes called gate-all-around (GAA) transistors) can also enable better management of leakage current and parasitic capacitance in the active region, even at increased drive currents. Summary of the Invention

[0004] Embodiments of the present invention are directed to methods for forming a semiconductor device. A non-limiting example of this method includes forming a non-planar channel region having a first semiconductor layer, a second semiconductor layer, and a fin-shaped bridge layer between the first and second semiconductor layers. Forming the non-planar channel region can include forming a nanosheet stack on a substrate, forming a trench by removing portions of the nanosheet stack, and forming a third semiconductor layer in the trench. The outer surfaces of the first semiconductor layer, the second semiconductor layer, and the fin-shaped bridge region define an effective channel width of the non-planar channel region.

[0005]

[0006] Embodiments of the present invention are directed to a method for forming a semiconductor device. A non-limiting example of this method includes forming a semiconductor layer on a substrate. Next to the semiconductor layer, a stack of alternating oxide and nitride layers is formed, and the oxide layer is removed to expose sidewalls of the semiconductor layer. The method further includes recessing the exposed sidewalls of the semiconductor layer to define a vertical portion and one or more horizontal portions of the semiconductor layer.

[0006]

[0003] Embodiments of the present invention are directed to methods for forming a semiconductor device. A non-limiting example of this method includes forming a nanosheet stack on a substrate. The nanosheet stack includes a first semiconductor layer and a second semiconductor layer. The second semiconductor layer includes a first material. The method further includes recessing sidewalls of the second semiconductor layer and annealing at a temperature operable to uniformly diffuse the first material into the first semiconductor layer and the second semiconductor layer.

[0007]

[0006] Embodiments of the present invention are directed to a method for forming a semiconductor device. A non-limiting example of this method includes forming a stack of alternating semiconductor and doped semiconductor layers over a substrate. The doped semiconductor layer includes a dopant. The method further includes recessing sidewalls of the doped semiconductor layer and annealing at a temperature operable to uniformly diffuse the dopant into the semiconductor and doped semiconductor layers.

[0008] An embodiment of the present invention is directed to a semiconductor structure. A non-limiting example of this structure includes a channel region above a substrate. The channel region includes a vertical fin and one or a plurality of vertically stacked nanosheets. Each of the one or a plurality of vertically stacked nanosheets extends from a sidewall of the vertical fin. A gate is formed above the channel region. The gate is in contact with the sidewall of the vertical fin and the top and bottom surfaces of each of the one or a plurality of vertically stacked nanosheets.

[0009] An embodiment of the present invention is directed to a method for forming a semiconductor device. A non-limiting example of this method includes forming a nanosheet stack on a substrate. The nanosheet stack includes one or more first semiconductor layers and one or more first sacrificial layers. Removing portions of the one or more first semiconductor layers and the one or more first sacrificial layers forms a trench. The trench exposes a surface of a bottommost one of the one or more first sacrificial layers. The method further includes filling the trench with one or more second semiconductor layers and one or more second sacrificial layers such that each of the one or more second semiconductor layers contacts a sidewall of one of the one or more first semiconductor layers.

[0010] An embodiment of the present invention is directed to a method for forming a semiconductor device. A non-limiting example of this method includes forming a first channel region on a substrate. The first channel region includes a first vertical fin and a first nanosheet extending from a sidewall of the first vertical fin. A second channel region is formed on the first channel region. The second channel region includes a second vertical fin and a second nanosheet extending from a sidewall of the second vertical fin. A gate is formed on the first channel region and the second channel region. The gate contacts a top surface of the first channel region and a bottom surface of the second channel region.

[0011]

[0003] Embodiments of the present invention are directed to a semiconductor structure. A non-limiting example of the structure includes a first channel region above a substrate. The first channel region includes a first vertical fin and a first nanosheet extending from a sidewall of the first vertical fin. The structure further includes a second channel region above the first channel region. The second channel region includes a second vertical fin and a second nanosheet extending from a sidewall of the second vertical fin. A gate surrounds the first channel region and the second channel region. The gate is in contact with a top surface of the first channel region and a bottom surface of the second channel region.

[0012] Additional technical features and advantages are realized through the techniques of the present invention. Embodiments and aspects of the present invention are described in detail herein and are considered part of the claimed subject matter. For a fuller understanding, please refer to the following detailed description and drawings.

[0013] The particulars of the proprietary rights set forth herein are particularly pointed out and distinctly claimed in the claims at the end of the specification. The above and other features and advantages of embodiments of the present invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings. 2A-15B show cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. 16A-19C show cross-sectional views of a GaAs X-FET semiconductor structure after processing operations according to one or more embodiments of the present invention. 20-28 show cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. 29A-31B show cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. 32A-35B show cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Brief explanation of the drawings]

[0014] [Figure 1A] FIG. 2 illustrates the effective channel width of an X-FET structure according to one or more embodiments of the present invention. [Figure 1B] FIG. 2 illustrates the effective channel width of a gate-all-around (GAA) X-FET structure according to one or more embodiments of the present invention. [Figure 2A] 1 is a top view of an X-FET semiconductor structure after processing operations according to one or more embodiments of the present invention. [Figure 2B] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 2C] 2B is a cross-sectional view of the X-FET semiconductor structure of FIG. 2A after processing operations according to one or more embodiments of the present invention. [Figure 3A] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 3B] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 4A] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 4B] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 5A] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 5B] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 6A] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 6B] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 7A] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 7B] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 8A] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 8B] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 9A] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 9B]1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 10A] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 10B] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 11A] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 11B] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 12A] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 12B] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 13A] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 13B] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 14A] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 14B] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 15A] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 15B] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 16A] 1A-1C are cross-sectional views of a GAA X-FET semiconductor structure after processing operations according to one or more embodiments of the present invention. [Figure 16B]1A-1C are cross-sectional views of a GAA X-FET semiconductor structure after processing operations according to one or more embodiments of the present invention. [Figure 17A] 1A-1C are cross-sectional views of a GAA X-FET semiconductor structure after processing operations according to one or more embodiments of the present invention. [Figure 17B] 1A-1C are cross-sectional views of a GAA X-FET semiconductor structure after processing operations according to one or more embodiments of the present invention. [Figure 18A] 1A-1C are cross-sectional views of a GAA X-FET semiconductor structure after processing operations according to one or more embodiments of the present invention. [Figure 18B] 1A-1C are cross-sectional views of a GAA X-FET semiconductor structure after processing operations according to one or more embodiments of the present invention. [Figure 19A] 1A-1C are cross-sectional views of a GAA X-FET semiconductor structure after processing operations according to one or more embodiments of the present invention. [Figure 19B] 1A-1C are cross-sectional views of a GAA X-FET semiconductor structure after processing operations according to one or more embodiments of the present invention. [Figure 19C] 1A-1C are cross-sectional views of a GAA X-FET semiconductor structure after processing operations according to one or more embodiments of the present invention. [Figure 20] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 21] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 22] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 23] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 24] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 25] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 26] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 27] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 28] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 29A] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 29B] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 30A] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 30B] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 31A] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 31B] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 32A] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 32B] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 33A] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 33B] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 34A] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 34B]1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 35A] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 35B] 1A-1C are cross-sectional views of X-FET semiconductor structures after processing operations according to one or more embodiments of the present invention. [Figure 36] 1 is a flow chart illustrating a method according to one or more embodiments of the present invention. [Figure 37] 1 is a flow chart illustrating a method according to one or more embodiments of the present invention. [Figure 38] 1 is a flow chart illustrating a method according to one or more embodiments of the present invention. [Figure 39] 1 is a flow chart illustrating a method according to one or more embodiments of the present invention. [Figure 40] 1 is a flow chart illustrating a method according to one or more embodiments of the present invention. [Figure 41] 1 is a flow chart illustrating a method according to one or more embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0015] The diagrams shown herein are for illustrative purposes. There may be many variations to the diagrams and the operations depicted therein without departing from the spirit of the invention. For example, operations may be performed in a different order, or operations may be added, deleted, or modified.

[0016] In the accompanying figures and the following detailed description of the described embodiments of the invention, various elements shown in the figures will bear two- or three-digit reference numbers. With few exceptions, the left-most digit of each reference number corresponds to the figure in which the element is first shown.

[0017] Although exemplary embodiments of the present invention are described with reference to particular transistor structures, it should be understood in advance that embodiments of the present invention are not limited to only the particular transistor structures or materials described herein. Rather, embodiments of the present invention may be practiced with any other type of transistor structure or material, now known or later developed.

[0018] For the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) manufacturing may or may not be described in detail herein. Furthermore, various operations and process steps described herein may be incorporated into a more comprehensive procedure or process having additional steps or additional functionality not described in detail herein. In particular, the various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known, and therefore, for the sake of brevity, many conventional steps are only briefly mentioned herein or omitted entirely without providing details of the well-known processes.

[0019] We now review technology more clearly related to aspects of the present invention. Metal-oxide-semiconductor field-effect transistors (MOSFETs) are used to amplify or switch electronic signals. MOSFETs have a source, a drain, and a metal-oxide gate electrode. The metal gate portion of the metal-oxide gate electrode is electrically insulated from the main semiconductor n-channel or p-channel by the oxide portion of the metal-oxide gate electrode. The oxide portion of the gate electrode can be implemented as a thin layer of insulating material, such as silicon dioxide or glass, which gives the MOSFET a relatively high input resistance. The gate voltage controls whether the current path from source to drain is open ("off") or a resistive path ("on"). n-type field-effect transistors (NFETs) and p-type field-effect transistors (PFETs) are two complementary types of MOSFETs. NFETs have n-type doped source and drain junctions and use electrons as current carriers. PFETs have p-type doped source and drain junctions and use holes as current carriers. Complementary Metal Oxide Semiconductor (CMOS) is a technology that implements logic functions using complementary, symmetrical MOSFET pairs consisting of a p-type MOSFET and an n-type MOSFET.

[0020] As previously discussed herein, conventional MOSFET fabrication techniques include process flows for building planar and non-planar transistor structures. One objective in designing a non-planar transistor structure is to achieve an effective channel width (W) for a given device footprint within the constraints of the current processing node (e.g., the width of the device processing window, sometimes denoted as RX). effThe effective channel width of a transistor can be defined as the total width of the transistor's channel in contact with the transistor's gate. Therefore, the larger the effective channel width, the more drive current the transistor can deliver. For comparison, the effective channel width of a 50-nm-wide planar transistor is simply the width of the gate (e.g., 50 nm). NSFETs were developed to increase the effective channel width for a given footprint while simultaneously improving electrostatic control of the channel. Continuing the example above, a 50-nm-tall three-nanosheet stack with a 15-nm nanosheet width and a 5-nm nanosheet thickness provides an effective channel width of 120 nm. Increasing the effective channel width increases the effective depletion region in the channel, which allows the device to deliver a larger drive current at a given gate voltage. This can increase device performance and enable further device scaling. Consequently, there is significant interest in further improving the effective channel width for a given device footprint.

[0021] However, there are challenges associated with increasing the effective channel width of transistors beyond the 20 nm node. For example, nanosheet-based SRAM devices require narrow sheet devices (in the 10-15 nm range) due to cell scaling requirements. At these dimensions, the effective channel width of the NSFET is significantly reduced, and this device structure loses some of its performance benefits in terms of drive current capability.

[0022] Theoretically, the effective channel width of an NSFET device can be increased by increasing the sheet width or by increasing the number of sheets. Each of these approaches has its drawbacks. For example, process limitations practically limit how large the width of nanosheet devices can be, preventing the sheet width from being increased at will. Conventional processes are currently constrained by an upper limit of approximately 100 nm for sheet width. Furthermore, increasing the sheet width directly translates into an increase in the device footprint. In other words, each transistor occupies more space on the wafer, which is not ideal for scaling.

[0023] Increasing the number of sheets significantly increases the effective channel width for a given device footprint. However, simulations show that the optimal number of sheets for an NSFET is three (which is the result of optimizing both drive current and parasitic capacitance). While it is possible to add a fourth sheet on top of the stack, this integration scheme complicates the fabrication process, in part due to aspect ratio considerations. Furthermore, this device may actually perform worse than a three-sheet device due to the corresponding increase in parasitic capacitance.

[0024] Aspects of the present invention are now reviewed. Embodiments of the present invention address the above-mentioned shortcomings of the prior art by providing a method for fabricating a novel transistor structure, described herein as an X-type field-effect transistor (X-FET), and the resulting structure. Broadly described, the X-FET structure herein comprises a non-planar channel having a set of vertically stacked nanosheets connected to each other by a fin-shaped bridge region. In some embodiments of the present invention, the X-FET is combined with a gate-all-around (GAA) process to further increase the effective channel width and improve the electrostatic characteristics of the device. The resulting hybrid structure has a significantly larger effective channel width (W) than a 3-sheet NSFET for a given RX width (within the same device footprint and without the need to add additional nanosheets to the stack). eff ) are shown. Furthermore, the X-FET and GAA X-FET structures outperform four-sheet NSFETs when R is less than 15 nm and less than 25 nm, respectively, while avoiding the increased fabrication complexity associated with nanosheet stacks with four or more nanosheets. Advantageously, the gate length is maintained comparable to that of an NSFET. As a result, X-FETs and GAA X-FETs offer the same electrostatic benefits as NSFETs, allowing for very short gate lengths, and the increased effective channel width provides higher drive currents (on-currents). Figures 1A and 1B show the W available when using the X-FET (Figure 1A) and GAA X-FET (Figure 1B) structures described herein. eff This shows an increase in

[0025] Aspects of the present invention will now be described in more detail. Figures 2A-15B show various views of an "X-FET" semiconductor structure 200 that results from performing fabrication operations according to one or more embodiments of the present invention.

[0026] For ease of illustration, FIG. 2A shows a top view of an "X-FET" semiconductor structure 200, illustrating three cross sections that will be used in the following discussion. The "X-FET" type semiconductor structure 200 includes a fin having a fin center and a fin edge. The "X-FET" semiconductor structure 200 further includes a gate formed over a channel region of the fin. As shown in FIG. 2A, the fin cross section "X" is taken along the centerline of the gate. The gate cross section "Y" is taken along the fin center. The gate cross section "Z" is taken along the fin edge.

[0027] As shown in FIGS. 2B and 2C, the partially fabricated semiconductor device may include a first sacrificial layer 202 formed on a substrate 204. The first sacrificial layer 202 may be made of any suitable sacrificial material, such as, for example, silicon-germanium. In some embodiments of the present invention, the germanium concentration of the first sacrificial layer 202 is selected to ensure a high etch selectivity relative to any silicon, silicon-germanium, or germanium layer of a subsequently formed gate stack. In other words, the first sacrificial layer 202 may be selectively etched relative to the silicon, silicon-germanium, or germanium of a subsequently formed gate stack. In some embodiments of the present invention, the germanium concentration of the first sacrificial layer 202 is at least 30 percent higher than the germanium concentration of any other silicon-germanium layer of the stack. In some embodiments of the present invention, the first sacrificial layer 202 may include a germanium concentration of 45 to 70 percent, e.g., 50 percent. However, other germanium concentrations are within the contemplated scope of the present invention.

[0028] The first sacrificial layer 202 can have a wide range of thicknesses, for example, from 5 nm to 25 nm or more. In some embodiments of the present invention, the first sacrificial layer 202 is formed to a height of approximately 10 nm. However, other thicknesses are within the contemplated scope of the present invention. The first sacrificial layer 202 can be formed by a variety of methods, for example, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), ultrahigh vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD), metalorganic chemical vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), limited reaction processing CVD (LRPCVD), and molecular beam epitaxy (MBE). In some embodiments of the present invention, the first sacrificial layer 202 can be epitaxially grown from gas or liquid precursors. Epitaxial semiconductor material can be grown using vapor-phase epitaxy (VPE), MBE, liquid-phase epitaxy (LPE), or other suitable processes.

[0029] The terms "epitaxial growth and / or deposition" and "epitaxially formed and / or epitaxially grown" refer to the growth of a semiconductor material (crystalline material) on a deposition surface of another semiconductor material (crystalline material) such that the growing semiconductor material (crystalline overlayer) has substantially the same crystalline properties as the underlying semiconductor material (seed material). In an epitaxial deposition process, chemical reactants supplied by source gases can be controlled and system parameters set so that the adatoms arrive at the deposition surface with sufficient energy to move about the deposition surface of the semiconductor substrate so that they align with the crystalline arrangement and orientation of the atoms at the deposition surface. Thus, epitaxially grown semiconductor material has substantially the same crystalline properties as the deposition surface on which it was formed. For example, epitaxially grown semiconductor material deposited on a {100}-oriented crystal surface will have a {100} orientation. In some embodiments of the present invention, the epitaxial growth process and / or epitaxial deposition process is selective to formation on semiconductor surfaces and generally does not deposit material on other exposed surfaces, such as silicon dioxide or silicon nitride surfaces.

[0030] Substrate 204 may be made of any suitable substrate material, such as, for example, single crystal Si, silicon germanium (silicon germanium), a III-V compound semiconductor, a II-VI compound semiconductor, or a semiconductor-on-insulator (SOI). In some embodiments of the present invention, substrate 204 may be a silicon substrate. In some embodiments of the present invention, substrate 204 includes a buried oxide layer (not shown). This buried oxide layer may be made of any suitable dielectric material, such as, for example, silicon oxide. In some embodiments of the present invention, the buried oxide layer is formed to a thickness of approximately 145 nm. However, other thicknesses are within the contemplated scope of the present invention. Semiconductor structure 200 may be electrically isolated from other regions of substrate 204 by a shallow trench isolation region (see FIG. 7A).

[0031] In some embodiments of the present invention, a stack of one or more alternating semiconductor layers 206 and one or more sacrificial layers 208 is formed on the first sacrificial layer 202. The stack can be formed such that the top and bottom layers of the stack are sacrificial layers 208. For ease of illustration, the stack is shown as having three alternating semiconductor layers 206 and four sacrificial layers 208, but it is understood that the stack can include any number of alternating semiconductor layers 206 and a corresponding number of sacrificial layers 208. For example, the stack can include two alternating semiconductor layers 206 and three sacrificial layers 208. In the final transistor structure, the semiconductor layer 206 functions as the channel region, and the sacrificial layer 208 replaces the portion of the transistor gate structure surrounding the semiconductor / channel layer 206.

[0032] Each semiconductor layer 206 may have a height ranging from 4 nm to 20 nm, for example, from 7 nm to 10 nm. In some embodiments of the present invention, the semiconductor layers 206 have a height of about 9 nm. The semiconductor layers 206 may be made of any suitable semiconductor channel material, such as, for example, single crystal Si, a III-V compound semiconductor, or a II-VI compound semiconductor. In some embodiments of the present invention, the semiconductor layers 206 are made of silicon.

[0033] Each sacrificial layer 208 can have a height ranging from 4 nm to 20 nm, for example, from 8 nm to 15 nm. In some embodiments of the present invention, the sacrificial layers 208 have a height of about 8 nm. In some embodiments of the present invention, the sacrificial layers 208 are made of silicon germanium. In some embodiments of the present invention, the sacrificial layers 208 include a germanium concentration of 15 to 35 percent, for example, 25 percent. However, other germanium concentrations are within the contemplated scope of the present invention.

[0034] The semiconductor layer 206 and the sacrificial layer 208 can be formed by a variety of methods, including, for example, UHVCVD, RTCVD, MOCVD, LPCVD, LRPCVD, and MBE. In some embodiments of the present invention, the semiconductor layer 206 and the sacrificial layer 208 are epitaxially grown from gas or liquid precursors. Epitaxial semiconductor materials can be grown using VPE, MBE, LPE, or other suitable processes. Epitaxial silicon and silicon germanium can be doped (in situ doped) during deposition by adding n-type dopants (e.g., P or As) or p-type dopants (e.g., Ga, B, BF2, or Al). The dopant concentration in the doped regions can be greater than 1×10 19 cm -3 From 2 x 10 21 cm -3 Range up to, or 1×10 20 cm -3 From 1×10 21 cm -3 The range can be between

[0035] In some embodiments of the present invention, the gas source for depositing the epitaxial semiconductor material comprises a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, an epitaxial Si layer can be deposited from a silicon gas source selected from the group consisting of silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane, and combinations thereof. An epitaxial germanium layer can be deposited from a germanium gas source selected from the group consisting of germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. An epitaxial silicon-germanium alloy layer can be formed using a combination of such gas sources. Carrier gases such as hydrogen, nitrogen, helium, and argon can be used. In some embodiments of the present invention, the doped region comprises silicon. In some embodiments of the present invention, the doped region comprises carbon-doped silicon (Si:C). This Si:C layer can be grown in the same chamber used for other epitaxy steps or can be grown in a dedicated Si:C epitaxy chamber. This Si:C can contain carbon in the range of about 0.2 percent to about 3.0 percent.

[0036] 3A and 3B illustrate cross-sectional views of an "X-FET" type semiconductor structure 200 during intermediate operations of a method for fabricating a semiconductor device according to one or more embodiments of the present invention. As shown in FIGS. 3A and 3B, a hard mask 302 may be formed on the top sacrificial layer 208. In some embodiments of the present invention, the hard mask 302 comprises a nitride, such as silicon nitride. In some embodiments of the present invention, the hard mask 302 is formed to a thickness of 40 nm; however, other thicknesses are within the contemplated scope of the present invention. In some embodiments of the present invention, a second hard mask (not shown) may be formed on the hard mask 302 to form a bilayer hard mask. In some embodiments of the present invention, the second hard mask comprises an oxide, such as silicon dioxide.

[0037] In some embodiments of the present invention, portions of the hard mask 302 are removed (e.g., patterned) to selectively pattern the stack of the semiconductor layer 206 and the sacrificial layer 208 relative to the hard mask 302. As shown in FIG. 3A , portions of the semiconductor layer 206 and the sacrificial layer 208 not covered by the patterned hard mask 302 can be removed using wet etching, dry etching, or a combination of sequential wet or dry etching or both. In this manner, the semiconductor layer 206 and the sacrificial layer 208 can be patterned to expose one or more surfaces of the substrate 204. In some embodiments of the present invention, the substrate 204 can be recessed as a result of this patterning process. In some embodiments of the present invention, the stack is patterned into one or more fins having widths ranging from 10 to 50 nm. However, other widths are within the contemplated scope of the present invention. For ease of illustration, the stack is shown as being patterned to form two fins. However, it is understood that the stack can be patterned into any number of parallel fins.

[0038] In some embodiments of the present invention, shallow trench isolation (STI) 304 is formed on substrate 204 to electrically isolate the one or more semiconductor fins. STI 304 can be any suitable dielectric material, such as, for example, silicon oxide, and can be formed using any suitable process. STI 304 can be formed using, for example, CVD, flowable CVD (FCVD), plasma-enhanced CVD (PECVD), UHVCVD, RTCVD, MOCVD, LPCVD, LRPCVD, ALD, physical vapor deposition (PVD), high-density plasma (HDP), chemical solution deposition, spin-on dielectric, or other similar processes. In some embodiments of the present invention, STI 304 is overfilled and then recessed using, for example, a chemical mechanical planarization (CMP) process.

[0039] 4A and 4B show cross-sectional views of an "X-FET" type semiconductor structure 200 during intermediate operations of a method for fabricating a semiconductor device according to one or more embodiments of the present invention. As shown in FIGS. 4A and 4B, the hard mask 302 can be stripped using, for example, a wet etch, a dry etch, or a combination of sequential wet or dry etches or both. In this manner, the sidewalls of the STI 304 can be exposed.

[0040] In some embodiments of the present invention, fin spacers 402 are formed between the exposed sidewalls of the STIs 304 on the topmost one of the sacrificial layers 208. In some embodiments of the present invention, the fin spacers 402 are formed using a conformal deposition process, such as CVD, PECVD, UHVCVD, RTCVD, MOCVD, LPCVD, LRPCVD, ALD, PVD, chemical solution deposition, or other similar process, in combination with a wet or dry etching process. For example, a spacer material may be conformally deposited on the semiconductor structure 200 and selectively removed using RIE to form the fin spacers 402. The fin spacers 402 may be made of any suitable material, such as a low-k dielectric, nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, or SiBCN. In some embodiments of the present invention, the fin spacers 402 comprise silicon nitride. The fin spacers 402 may be formed to a thickness of approximately 5 to 10 nm, e.g., 5 nm. However, other thicknesses are within the contemplated scope of the present invention.

[0041] 5A and 5B show cross-sectional views of an "X-FET" type semiconductor structure 200 during intermediate operations of a method of fabricating a semiconductor device according to one or more embodiments of the present invention. As shown in FIGURES 5A and 5B, portions of the semiconductor layer 206 and the sacrificial layer 208 that are not covered by the fin spacers 402 can be removed using wet etching, dry etching, or sequential wet or dry etching, or a combination of both.

[0042] In some embodiments of the present invention, these portions are removed using reactive ion etching (RIE). In this manner, the semiconductor layer 206 and the sacrificial layer 208 can be patterned to form trenches 502 that expose one or more surfaces of the first sacrificial layer 202. In some embodiments of the present invention, the first sacrificial layer 202 can be recessed as a result of this patterning process. In some embodiments of the present invention, the semiconductor layer 206 and the sacrificial layer 208 are patterned into nanosheets having a width of 5 nm. However, other widths are within the contemplated scope of the present invention.

[0043] 6A and 6B show cross-sectional views of an "X-FET" type semiconductor structure 200 during intermediate operations of a method of fabricating a semiconductor device according to one or more embodiments of the present invention. As shown in FIGS. 6A and 6B, a semiconductor layer 602 is formed within trench 502. In some embodiments of the present invention, semiconductor layer 602 is formed by bottom-up trench epitaxy.

[0044] Semiconductor layer 602 can be formed by a variety of methods. In some embodiments of the present invention, VPE, MBE, LPE, or other suitable processes can be used to grow epitaxial semiconductor material in trench 502. Semiconductor layer 602 can be made of any suitable semiconductor channel material, such as, for example, single crystal Si, a III-V compound semiconductor, or a II-VI compound semiconductor. In some embodiments of the present invention, semiconductor layer 602 is made of the same material as semiconductor layer 206, such as, for example, silicon.

[0045] 7A and 7B show cross-sectional views of the "X-FET" type semiconductor structure 200 during intermediate operations of a method of fabricating a semiconductor device according to one or more embodiments of the present invention. As shown in FIGS. 7A and 7B, the fin spacers 402 can be filled with additional material to form a hard mask 702, or the fin spacers 402 can be replaced by a hard mask 702.

[0046] The hard mask 702 can be formed using CVD, PECVD, UHVCVD, RTCVD, MOCVD, LPCVD, LRPCVD, ALD, PVD, chemical solution deposition, or other similar processes. For example, a dielectric material can be conformally deposited over the semiconductor structure 200. The hard mask 702 can be made of any suitable material, such as a low-k dielectric, nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, or SiBCN. In some embodiments of the present invention, the hard mask 702 comprises silicon nitride. The hard mask 702 can be formed to a thickness of approximately 5 to 50 nm, for example, 10 nm. However, other thicknesses are within the contemplated scope of the present invention.

[0047] In some embodiments of the present invention, the STIs 304 are recessed below the surface of the first sacrificial layer 202. In this manner, the STIs 304 electrically isolate one or more nanosheet stacks. The STIs 304 can be recessed using, for example, chemical oxide removal (COR) or hydrofluoric acid (HF) wet etching. In some embodiments of the present invention, the STIs 304 are recessed selectively relative to the hard mask 702.

[0048] 8A and 8B show cross-sectional views of an "X-FET" type semiconductor structure 200 during intermediate operations of a method of fabricating a semiconductor device according to one or more embodiments of the present invention. As shown in Figures 8A and 8B, the hard mask 702 can be removed using, for example, a wet etch, a dry etch, or a combination of sequential wet or dry etches or both.

[0049] In some embodiments of the present invention, a dielectric liner 802 is formed on the semiconductor structure 200. In some embodiments of the present invention, the dielectric liner 802 is formed using a conformal deposition process, such as CVD, PECVD, UHVCVD, RTCVD, MOCVD, LPCVD, LRPCVD, ALD, PVD, chemical solution deposition, or other similar process. For example, a dielectric material may be conformally deposited on the semiconductor structure 200. The dielectric liner 802 may be made of any suitable material, such as, for example, a low-k dielectric, nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, or SiBCN. In some embodiments of the present invention, the dielectric liner 802 is silicon oxide. The dielectric liner 802 may be formed to a thickness of about 0.2 to 10 nm, for example, 3 nm. However, other thicknesses are within the contemplated scope of the present invention.

[0050] In some embodiments of the present invention, a sacrificial gate 804 is formed on the dielectric liner 802. The sacrificial gate 804 may be made of any suitable material, such as amorphous silicon or polysilicon. The sacrificial gate 804 may be formed using any known method for patterning a sacrificial gate, such as polysilicon filling and wet etching, dry etching, or sequential wet or dry etching or a combination of both.

[0051] In some embodiments of the present invention, a hard mask 806 (also known as a gate hard mask) is formed on the sacrificial gate 804. The hard mask 806 may be made of any suitable material, such as, for example, silicon nitride. In some embodiments of the present invention, a second hard mask 808 may be formed on the hard mask 806 to form a two-layer hard mask. The second hard mask 808 may comprise an oxide, such as, for example, silicon oxide. In some embodiments of the present invention, the sacrificial gate 804 is formed by patterning the hard masks 806 and 808 and removing the uncovered portions of the sacrificial gate 808 with RIE.

[0052] 9A and 9B show cross-sectional views of an "X-FET" type semiconductor structure 200 during intermediate operations of a method for fabricating a semiconductor device according to one or more embodiments of the present invention. As shown in FIG. 9B, portions of the dielectric liner 802 can be removed to expose the surface of the nanosheet stack (e.g., semiconductor layer 602). The dielectric liner 802 can be removed using wet or dry etching. In some embodiments of the present invention, the dielectric liner 802 is removed using an oxide strip process.

[0053] 9A and 9B, first sacrificial layer 202 can be selectively removed relative to sacrificial layer 208. First sacrificial layer 202 can be removed using any suitable process that can selectively remove a germanium layer relative to a less concentrated germanium layer. Exemplary processes known to provide this etch selectivity include HCl vapor phase chemistry and chlorine trifluoride (ClF) etching.

[0054] In some embodiments of the present invention, a spacer material 902 is formed on top of the semiconductor structure 200. In some embodiments of the present invention, for example, in some embodiments having a first sacrificial layer 202 that is subsequently removed, the spacer material 902 is also formed in the cavity left by the removal of the first sacrificial layer 202. In this manner, the spacer material 902 can replace the first sacrificial layer 202 (if present). Replacing the first sacrificial layer 202 in this manner provides a bottom separation between the nanosheet stack and the substrate 204.

[0055] In some embodiments of the present invention, the spacer material 902 is formed using a conformal deposition process, such as CVD, PECVD, UHVCVD, RTCVD, MOCVD, LPCVD, LRPCVD, ALD, PVD, chemical solution deposition, or other similar process. For example, the spacer material 902 may be conformally deposited on the semiconductor structure 200. The spacer material 902 may be made of any suitable material, such as, for example, a low-k dielectric, a nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, or SiBCN. In some embodiments of the present invention, the spacer material 902 comprises SiBCN. The spacer material 902 may be formed or deposited to a thickness of approximately 5 to 15 nm. However, other thicknesses are within the contemplated scope of the present invention.

[0056] 10A and 10B illustrate cross-sectional views of an "X-FET" type semiconductor structure 200 during intermediate operations of a method for fabricating a semiconductor device according to one or more embodiments of the present invention. As shown in FIGS. 10A and 10B, portions of the spacer material 902 can be etched or otherwise patterned to form spacers 1002 (also known as sidewall spacers or gate spacers) on the sidewalls of the sacrificial gate 804. The spacer material 902 can be patterned using, for example, wet or dry etching. In some embodiments of the present invention, the spacer material is selectively removed using RIE to form the sidewall spacers 1002, thus exposing the surface of the nanosheet stack. In some embodiments of the present invention, the exposed portions of the nanosheet stack (e.g., the semiconductor layer 602 and the sacrificial layer 208) are selectively removed relative to the spacer material 902, the first sacrificial layer 202, or both.

[0057] 11A and 11B show cross-sectional views of an "X-FET" type semiconductor structure 200 during intermediate operations of a method for fabricating a semiconductor device according to one or more embodiments of the present invention. As shown in FIGS. 11A and 11B, the sacrificial layer 208 is recessed and replaced with an inner spacer 1102. The sacrificial layer 208 can be recessed using a wet or dry etch. In some embodiments of the present invention, the sacrificial layer 208 is selectively recessed relative to the semiconductor layer 206. For example, a hydrophosphoric acid-based wet etchant or an HCl or ClF gas dry etchant can be used to selectively etch the sacrificial layer 208 made of silicon germanium relative to the semiconductor layer 206 made of silicon. In some embodiments of the present invention, the sacrificial layer 208 is recessed to a depth selected to result in the thickness of the inner spacer 1102 being the same as the thickness of the spacer 1002.

[0058] In some embodiments of the present invention, inner spacers 1102 are formed by conformal deposition (e.g., CVD or ALD) to fill recesses formed in sacrificial layer 208, and a subsequent etch-back process to remove excess material. Inner spacers 1102 may be made of any suitable material, such as, for example, a low-k dielectric, nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, or SiBCN.

[0059] 12A and 12B show cross-sectional views of an "X-FET" type semiconductor structure 200 during intermediate operations of a method for fabricating a semiconductor device according to one or more embodiments of the present invention. As shown in FIGS. 12A and 12B, source / drain (S / D) regions 1202 can be formed on the surface of the bottom isolation layer 902 and on opposite ends of each nanosheet stack. In some embodiments of the present invention, the S / D regions 1202 are epitaxially grown from the exposed ends of the fin / nanosheet stacks (i.e., semiconductor layer 206).

[0060] The S / D regions 1202 can be epitaxially formed by various methods, such as in-situ doped epitaxy, post-epitaxy doping, or implantation and plasma doping. In some embodiments of the present invention, the epitaxial regions are epitaxially grown on the surface of the substrate 204. As previously described herein, the S / D regions 1202 can be epitaxial semiconductor material grown from gas or liquid precursors. The S / D regions 1202 can be doped with n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or gallium). The dopant concentration of the S / D regions 1202 is greater than 1×10 19 cm -3 From 2 x 10 21 cm -3 Range up to, or 1×10 20 cm -3 From 1×10 21 cm -3The range can be between

[0061] 13A and 13B illustrate cross-sectional views of an "X-FET" type semiconductor structure 200 during intermediate operations of a method for fabricating a semiconductor device according to one or more embodiments of the present invention. As shown in FIGS. 13A and 13B, a dielectric layer 1302 is formed between spacers 1002 over S / D regions 1202. Dielectric layer 1302 may be formed using, for example, CVD, FCVD, PECVD, UHVCVD, RTCVD, MOCVD, LPCVD, LRPCVD, ALD, PVD, chemical solution deposition, or other similar processes. Dielectric layer 1302 may be made of any suitable material, such as, for example, a low-k dielectric, a nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, or SiBCN. In some embodiments of the present invention, dielectric layer 1302 is an oxide, such as silicon oxide.

[0062] In some embodiments of the present invention, dielectric layer 1302 is overfilled and then planarized to the top surface of sacrificial gate 804 using, for example, a CMP process. In some embodiments of the present invention, hard mask 806 and second hard mask 808 are removed during this CMP process.

[0063] 14A and 14B illustrate cross-sectional views of an "X-FET" type semiconductor structure 200 during intermediate operations of a method for fabricating a semiconductor device according to one or more embodiments of the present invention. As shown in FIGS. 14A and 14B, during a replacement metal gate (RMG) process, the sacrificial gate 804, dielectric liner 802, and sacrificial layer 208 can be removed and replaced with a conductive gate 1402. The sacrificial gate 804, dielectric liner 802, and sacrificial layer 208 can be removed using known RMG processes. In some embodiments of the present invention, the sacrificial gate 804 is removed using an amorphous silicon or polysilicon pull. In some embodiments of the present invention, the dielectric liner 802 is removed using an oxide etch.

[0064] In some embodiments of the present invention, sacrificial layer 208 is removed selectively relative to semiconductor layer 206, semiconductor layer 602, or both. Sacrificial layer 208 can be removed using a wet etch or a dry etch. In some embodiments of the present invention, a hydrophosphoric acid-based wet etchant or an HCl or ClF gas dry etchant can be used to selectively remove sacrificial layer 208 made of silicon germanium relative to semiconductor layers 206 and 602 made of silicon. In some embodiments of the present invention, sacrificial layer 208 is removed before forming conductive gate 1402.

[0065] The conductive gate 1402 may be, for example, a high-k metal gate (HKMG) formed using a known RMG process. In some embodiments of the present invention, the conductive gate 1402 is a replacement metal gate stack formed between the spacers 1002. The replacement metal gate stack may include a high-k dielectric material, a work function metal stack, and a bulk gate material.

[0066] In some embodiments of the present invention, a high-k dielectric film (not shown) is formed on the exposed surface of the nanosheet stack. This high-k dielectric film can be made of, for example, silicon oxide, silicon nitride, silicon oxynitride, boron nitride, a high-k material, or any combination of these materials. Examples of high-k materials include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The high-k material can further include dopants such as lanthanum and aluminum. In some embodiments of the present invention, the high-k dielectric film can have a thickness of about 0.5 nm to about 4 nm. In some embodiments of the present invention, the high-k dielectric film comprises hafnium oxide and has a thickness of about 1 nm. However, other thicknesses are within the contemplated scope of the present invention.

[0067] In some embodiments of the present invention, one or more work function layers (not shown, sometimes referred to as a work function metal stack) are formed between the high-k dielectric film and the bulk gate material. The work function layer can be made of, for example, aluminum, lanthanum oxide, magnesium oxide, strontium titanate, strontium oxide, titanium nitride, tantalum nitride, hafnium nitride, tungsten nitride, molybdenum nitride, niobium nitride, hafnium silicon nitride, titanium aluminum nitride, tantalum silicon nitride, titanium aluminum carbide, tantalum carbide, and combinations thereof. The work function layer can further modify the work function of the conductive gate 1402, allowing for tuning of the device threshold voltage. The work function layer can be formed to a thickness of approximately 0.5 to 6 nm; however, other thicknesses are within the contemplated scope of the present invention. In some embodiments of the present invention, the work function layers can be formed to different thicknesses. In some embodiments of the present invention, the work function layer comprises a TiN / TiC / TiCAl stack.

[0068] In some embodiments of the present invention, a bulk gate material is deposited over the work function layer. The bulk gate material can include any suitable conductive material, such as a metal (e.g., tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, lead, platinum, tin, silver, gold), a conductive metal compound material (e.g., tantalum nitride, titanium nitride, tantalum carbide, titanium carbide, titanium aluminum carbide, tungsten silicide, tungsten nitride, ruthenium oxide, cobalt silicide, nickel silicide), conductive carbon, graphene, or any suitable combination of these materials. The conductive material can further include a dopant incorporated during or after deposition.

[0069] In some embodiments of the present invention, a gate hard mask 1404 (sometimes referred to as a self-aligned contact cap, or SAC cap) is formed on the surface of the conductive gate 1402. The gate SAC cap 1404 can be made of any suitable material, such as, for example, nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, or SiBCN. In some embodiments of the present invention, the gate SAC cap 1404 comprises silicon nitride. In some embodiments of the present invention, the gate SAC cap 1404 is formed to a thickness of 30 nm. However, other thicknesses are within the contemplated scope of the present invention.

[0070] 14A, conductive gate 1402 can be in contact with the exposed surfaces of semiconductor layer 206 and semiconductor layer 602. In this manner, semiconductor layer 206 and semiconductor layer 602 collectively define an "X-FET" type channel region between S / D regions 1202. This channel region includes a vertical fin (e.g., semiconductor layer 602) and one or more vertically stacked nanosheets (e.g., semiconductor layer 206). In some embodiments of the present invention, conductive gate 1402 is in direct contact with the sidewalls of the vertical fin (notwithstanding any intervening high-k or work function layers) and the top and bottom surfaces of one or more respective nanosheets.

[0071] 15A and 15B illustrate cross-sectional views of an "X-FET" type semiconductor structure 200 during intermediate operations of a method of fabricating a semiconductor device according to one or more embodiments of the present invention. As shown in FIGS. 15A and 15B, trench contacts 1502 may be formed after removing dielectric layer 1302. Trench contacts 1502 may be formed on S / D regions 1202 using known metallization techniques. In some embodiments of the present invention, trench contacts 1502 are formed using an anisotropic self-aligned RIE etch that selectively etches dielectric layer 1302 relative to gate SAC cap 1404 and spacers 1002. It will be understood that contacts (sometimes referred to as S / D contacts) may be formed on the respective source or drain regions, and that contacts (sometimes referred to as gate contacts) may be formed on the surface of conductive gate 1402.

[0072] The trench contact 1502 can comprise any suitable conductive material, such as, for example, a metal (e.g., tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, platinum), a conductive metal compound material (e.g., tantalum nitride, titanium nitride, tantalum carbide, titanium carbide, titanium aluminum carbide, tungsten silicide, tungsten nitride, cobalt silicide, nickel silicide), conductive carbon, or any suitable combination of these materials. The conductive material can further comprise a dopant incorporated during or after deposition. In some embodiments of the present invention, the contact can be copper and can include a barrier metal liner. The barrier metal liner prevents copper from diffusing into or doping the surrounding material, which could degrade the properties of the surrounding material. Examples of barrier metal liners include tantalum nitride and tantalum (TaN / Ta), titanium, titanium nitride, cobalt, ruthenium, and manganese.

[0073] 16A-16C show cross-sectional views of a "GAA X-FET" type semiconductor structure 1600 during intermediate operations of a method of fabricating a semiconductor device according to one or more embodiments of the present invention. As shown in FIGS. 16A and 16B, the partially fabricated semiconductor device can include a first sacrificial layer 1602 formed over a substrate 1604.

[0074] First sacrificial layer 1602 and substrate 1604 may be made of the same materials and in a similar manner as first sacrificial layer 202 and substrate 204, respectively, shown in FIG. 2B. In some embodiments of the present invention, the germanium concentration of first sacrificial layer 1602 is selected to ensure a higher etch selectivity than any silicon, silicon-germanium, or germanium layer in a subsequently formed gate stack. In some embodiments of the present invention, the germanium concentration of first sacrificial layer 1602 is at least 30 percent higher than any other silicon-germanium layer in the stack. In some embodiments of the present invention, first sacrificial layer 1602 may include a germanium concentration of 45 to 70 percent, e.g., 50 percent. However, other germanium concentrations are within the contemplated scope of the present invention.

[0075] In some embodiments of the present invention, a stack of one or more alternating semiconductor layers 1606 and one or more sacrificial layers 1608 is formed on the first sacrificial layer 162. The stack can be formed such that the top and bottom layers of the stack are sacrificial layers. For ease of illustration, a stack is shown having three alternating semiconductor layers and four sacrificial layers, but it is understood that the stack can include any number of alternating semiconductor layers and a corresponding number of sacrificial layers. For example, the stack can include two alternating semiconductor layers and three sacrificial layers. The semiconductor layers 1606 and sacrificial layers 1608 can be made of the same materials and in a similar manner as the semiconductor layers 206 and sacrificial layers 208 shown in FIG. 2B.

[0076] Each semiconductor layer 1606 can have a height ranging from 4 nm to 20 nm, for example, from 7 nm to 10 nm. In some embodiments of the present invention, semiconductor layer 1606 has a height of about 9 nm. Semiconductor layer 1606 can be made of any suitable semiconductor channel material, such as, for example, single crystal Si, a III-V compound semiconductor, or a II-VI compound semiconductor. In some embodiments of the present invention, semiconductor layer 1606 is made of silicon.

[0077] Each sacrificial layer 1608 can have a height ranging from 6 nm to 40 nm, for example, from 8 nm to 20 nm. In some embodiments of the present invention, each sacrificial layer 1608 has the same height. In some embodiments of the present invention, some sacrificial layers 1608 have different heights. For example, in some embodiments of the present invention, the bottom sacrificial layer has a height of about 10 nm, the top sacrificial layer has a height of about 10 nm, and the remaining (e.g., central) sacrificial layers have a height of about 20 nm. In some embodiments of the present invention, sacrificial layer 1608 is made of silicon germanium. In some embodiments of the present invention, sacrificial layer 1608 includes a germanium concentration of 15 to 35 percent, for example, 25 percent. However, other germanium concentrations are within the contemplated scope of the present invention.

[0078] 17A and 17B illustrate cross-sectional views of a "GAA X-FET" type semiconductor structure 1600 during intermediate operations of a method of fabricating a semiconductor device according to one or more embodiments of the present invention. As shown in FIGS. 17A and 17B, an STI 1702 is formed on a substrate 1604 to electrically isolate one or more semiconductor fins. The STI 1702 may be made of similar materials and formed using similar processes as the STI 304 shown in FIG. 3A.

[0079] In some embodiments of the present invention, fin spacers 1704 are formed between exposed sidewalls of STIs 1702 on the topmost one of the sacrificial layers 1608. Fin spacers 1704 may be made of similar materials and formed using similar processes as fin spacers 402 shown in FIG. 4A. Fin spacers 1704 may be formed to a thickness of approximately 5 to 10 nm, e.g., 5 nm. However, other thicknesses are within the contemplated scope of the present invention.

[0080] In some embodiments of the present invention, portions of semiconductor layer 1606 and sacrificial layer 1608 not covered by fin spacer 1704 are removed to form trench 1706. In some embodiments of the present invention, trench 1706 exposes one or more surfaces of bottom sacrificial layer 1608. In some embodiments of the present invention, the bottom one of sacrificial layers 1608 may be recessed as a result of this patterning process. In some embodiments of the present invention, semiconductor layer 1606 and sacrificial layer 1608 are patterned into nanosheets having a width of 5 nm; however, other widths are within the contemplated scope of the present invention.

[0081] 18A and 18B show cross-sectional views of a "GAA X-FET" type semiconductor structure 1600 during intermediate operations of a method of fabricating a semiconductor device according to one or more embodiments of the present invention. As shown in FIGS. 18A and 18B, semiconductor layers 1802 and sacrificial layers 1804 are alternately formed within trench 1706. In some embodiments of the present invention, semiconductor layers 1802 and sacrificial layers 1804 are formed using a bottom-up trench epitaxy process, in which each layer is epitaxially grown sequentially on the preceding layer within the trench.

[0082] Semiconductor layer 1802 and sacrificial layer 1804 may be formed by a variety of methods. In some embodiments of the present invention, VPE, MBE, LPE, or other suitable processes may be used to grow epitaxial semiconductor material in trench 1706. Semiconductor layer 1802 may be made of a material similar to semiconductor layer 1606. Sacrificial layer 1804 may be made of a material similar to sacrificial layer 1608.

[0083] In some embodiments of the present invention, the height of each semiconductor layer 1802 is the same as the width of each corresponding semiconductor layer 1606. In other words, if semiconductor layer 1606 is epitaxially grown to a width of 15 nm, then semiconductor layer 1802 can be epitaxially grown to a height of 15 nm. However, other widths and corresponding thicknesses are within the contemplated scope of the present invention.

[0084] 19A-19C illustrate cross-sectional views of a "GAA X-FET" type semiconductor structure 1600 during intermediate operations of a method of fabricating a semiconductor device according to one or more embodiments of the present invention. The "GAA X-FET" type semiconductor structure 1600 can be completed substantially in a manner similar to the "X-FET" type semiconductor structure 200 shown in FIGS. 2A-15B.

[0085] 19A-19C, the "GAA X-FET" type semiconductor structure 1600 includes a conductive gate 1902, a SAC cap 1904, S / D regions 1906, inner spacers 1908, a gate spacer 1910, a dielectric layer 1912, and contacts 1914. Each of these features may be made of similar materials and in a manner substantially similar to the corresponding features of the "X-FET" type semiconductor structure 200 shown in FIGS.

[0086] As shown in Figure 19A, conductive gate 1902 is applied to the exposed surfaces of semiconductor layer 1606 and semiconductor layer 1802. In this manner, semiconductor layer 1606 and semiconductor layer 1802 collectively define a "GAA X-FET" type channel region between S / D regions 1906. This channel region includes one or more vertical fins (e.g., semiconductor layer 1802) and one or more vertically stacked nanosheets (e.g., semiconductor layer 1606). In some embodiments of the invention, a high-k dielectric (not shown) of conductive gate 1902 is in direct contact with the sidewalls of the vertical fins and the top and bottom surfaces of one or more respective nanosheets.

[0087] 20-28 show cross-sectional views of an "X-FET" type semiconductor structure 2000 during intermediate operations of a method of fabricating a semiconductor device according to one or more embodiments of the present invention. As shown in FIG. 20, the partially fabricated semiconductor device can include a first sacrificial layer 2002 formed over a substrate 2004.

[0088] First sacrificial layer 2002 and substrate 2004 may be made of the same materials and fabricated in the same manner as first sacrificial layer 202 and substrate 204, respectively, shown in FIG. 2B. In some embodiments of the present invention, a semiconductor layer 2006 is formed on first sacrificial layer 2002. Semiconductor layer 2006 may be made of the same materials and fabricated in the same manner as semiconductor layer 206 shown in FIG. 2B. In some embodiments of the present invention, the thickness of semiconductor layer 2006 is greater than the thickness of semiconductor layer 206. This is because semiconductor layer 2006 defines the final thickness (vertical height) of the channel region (shown in FIGS. 29A and 29B). In some embodiments of the present invention, semiconductor layer 2006 is approximately 60 nm thick. However, other thicknesses are within the contemplated scope of the present invention.

[0089] In some embodiments of the present invention, a hard mask 2008 may be formed on semiconductor layer 2006. In some embodiments of the present invention, hard mask 2008 comprises a nitride, such as silicon nitride. In some embodiments of the present invention, hard mask 2008 is formed to a thickness of 40 nm; however, other thicknesses are within the contemplated scope of the present invention. In some embodiments of the present invention, a second hard mask (not shown) may be formed on hard mask 2008 to form a two-layer hard mask. In some embodiments of the present invention, this second hard mask comprises an oxide, such as silicon dioxide.

[0090] In some embodiments of the present invention, portions of hard mask 2008 are removed (e.g., patterned) and semiconductor layer 2006 and first sacrificial layer 2002 are selectively patterned relative to hard mask 2008. As shown in Figure 20, portions of semiconductor layer 2006 and first sacrificial layer 2002 not covered by patterned hard mask 2008 can be removed using wet etching, dry etching, or sequential wet or dry etching or a combination of both.

[0091] In some embodiments of the present invention, the semiconductor layer 2006 and first sacrificial layer 2002 are patterned into one or more fins having widths ranging from 10 to 50 nm. However, other widths are within the contemplated scope of the present invention. For ease of illustration, the stack is shown as being patterned to form two fins. However, it will be understood that the stack can be patterned into any number of parallel fins. In some embodiments of the present invention, the pitch, or end-to-end spacing, between the fins is about 40 nm. However, other spacings are within the contemplated scope of the present invention.

[0092] FIG. 21 illustrates a cross-sectional view of an “X-FET” type semiconductor structure 2000 during an intermediate operation of a method for fabricating a semiconductor device according to one or more embodiments of the present invention. As shown in FIG. 21 , a hard mask 2102 may be formed on the surface of a substrate 2004. The hard mask 2102 may be made of any suitable material, such as, for example, a low-k dielectric, nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, or SiBCN. In some embodiments of the present invention, the hard mask 2102 comprises silicon nitride. The hard mask 2102 may be formed to a thickness of about 20 to 100 nm, e.g., 70 nm. However, other thicknesses are within the contemplated scope of the present invention. In some embodiments of the present invention, the hard mask 2102 is formed to a thickness sufficient to cover the sidewalls of the first sacrificial layer 2002.

[0093] In some embodiments of the present invention, a stack of one or more alternating oxide layers 2104 and one or more nitride layers 2106 is formed over the hard mask 2102. The stack can be formed such that the top and bottom layers of the stack are oxide layers. For ease of illustration, the stack is shown as having four alternating oxide layers and three alternating nitride layers, but it is understood that the stack can include any number of alternating oxide layers and a corresponding number of nitride layers. For example, the stack can include two alternating oxide layers and a single nitride layer. The number of nitride layers 2106 defines the number of fins in the channel region (as shown in FIG. 25).

[0094] Each oxide layer 2104 may have a height in the range of 6 nm to 20 nm, for example, 8 nm to 15 nm. In some embodiments of the invention, oxide layer 2104 has a height of about 8 nm. Oxide layer 2104 may be made of any suitable material, such as, for example, silicon oxide.

[0095] Each nitride layer 2106 may have a height ranging from 4 nm to 12 nm, for example, from 7 nm to 10 nm. In some embodiments of the present invention, nitride layer 2106 has a height of about 9 nm. Nitride layer 2106 may be made of any suitable material, such as, for example, silicon nitride.

[0096] The oxide layer 2104 and nitride layer 2106 can be formed by anisotropic deposition. For example, alternating oxide and nitride dielectric materials can each be deposited over the hard mask 2102 using a HDP deposition+isotropic etchback process cycled (i.e., repeated) “n” times.

[0097] FIG. 22 illustrates a cross-sectional view of an “X-FET” type semiconductor structure 2000 during an intermediate operation of a method for fabricating a semiconductor device according to one or more embodiments of the present invention. As shown in FIG. 22, spacers 2202 are formed on exposed sidewalls of a hard mask 2008 on a topmost one of the oxide layers 2104. In some embodiments of the present invention, the spacers 2202 are formed using a conformal deposition process, such as CVD, PECVD, UHVCVD, RTCVD, MOCVD, LPCVD, LRPCVD, ALD, PVD, chemical solution deposition, or other similar process, in combination with a wet or dry etching process. For example, a spacer material may be conformally deposited on top of the semiconductor structure 2000 and selectively removed using RIE to form the sidewall spacers 2202. The spacers 2202 may be made of any suitable material, such as a low-k dielectric, nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, or SiBCN. In some embodiments of the present invention, the spacers 2202 comprise SiC. Spacers 2202 may be formed to a thickness of approximately 5 to 10 nm, for example 5 nm, although other thicknesses are within the contemplated scope of the present invention.

[0098] FIG. 23 illustrates a cross-sectional view of an “X-FET” type semiconductor structure 2000 during an intermediate operation of a method for fabricating a semiconductor device according to one or more embodiments of the present invention. As shown in FIG. 23 , portions of oxide layer 2104, nitride layer 2106, and hard mask 2102 may be removed. Oxide layer 2104, nitride layer 2106, and hard mask 2102 may be removed using wet etching, dry etching, or a combination of sequential wet or dry etching or both. In some embodiments of the present invention, oxide layer 2104, nitride layer 2106, and hard mask 2102 may be removed using an RIE that stops within hard mask 2102. In other words, hard mask 2102 may be recessed. In this manner, the remaining portions of hard mask 2102 protect substrate 2004 during downstream processing.

[0099] 24 illustrates a cross-sectional view of an "X-FET" type semiconductor structure 2000 during an intermediate operation of a method of fabricating a semiconductor device according to one or more embodiments of the present invention. As shown in FIG. 24, oxide layer 2104 may be removed to expose the sidewalls of semiconductor layer 2006. Oxide layer 2104 may be removed using a wet etch or a dry etch. In some embodiments of the present invention, oxide layer 2104 may be selectively removed relative to nitride layer 2106, semiconductor layer 2006, or spacers 2202, or a combination thereof.

[0100] FIG. 25 illustrates a cross-sectional view of an “X-FET” type semiconductor structure 2000 during an intermediate operation of a method of fabricating a semiconductor device according to one or more embodiments of the present invention. As shown in FIG. 25 , the semiconductor layer 2006 can be recessed laterally to form a recess 2502 that exposes a surface of the first sacrificial layer 2002 and a surface of the hard mask 2008. In this manner, the semiconductor layer 2006 can be recessed to define a vertical portion (e.g., a vertical fin) and one or more horizontal portions (e.g., nanosheets). The semiconductor layer 2006 can be recessed using wet or dry etching. In some embodiments of the present invention, the semiconductor layer 2006 can be recessed selectively relative to the nitride layer 2106 or the spacers 2202, or both. In some embodiments of the present invention, the remaining portions of the hard mask 2102 protect the substrate 2004 from etch-back during this process.

[0101] 26 illustrates a cross-sectional view of an "X-FET" type semiconductor structure 2000 during an intermediate operation of a method of fabricating a semiconductor device according to one or more embodiments of the present invention. As shown in FIG. 26, a sacrificial region 2602 may be formed within the recess 2502. In some embodiments of the present invention, the sacrificial region 2602 partially fills the recess 2502. In some embodiments of the present invention, the sidewalls of the sacrificial region 2602 are coplanar with the sidewalls of the hard mask 2008.

[0102] In some embodiments of the present invention, sacrificial region 2602 is made of silicon germanium. In some embodiments of the present invention, sacrificial region 2602 comprises a germanium concentration of 15 to 45 percent, for example, 25 percent. However, other germanium concentrations are within the contemplated scope of the present invention. In some embodiments of the present invention, sacrificial region 2602 is epitaxially grown on the exposed surface of semiconductor layer 2006. In some embodiments of the present invention, remaining portions of hard mask 2102 protect substrate 2004 from parasitic epitaxial growth during this process.

[0103] 27 illustrates a cross-sectional view of an "X-FET" type semiconductor structure 2000 during an intermediate operation of a method of fabricating a semiconductor device according to one or more embodiments of the present invention. As shown in FIG. 27, the spacers 2202, nitride layer 2106, and hard mask 2102 may be removed. The spacers 2202, nitride layer 2106, and hard mask 2102 may be removed using a wet etch, a dry etch, or a combination of sequential wet or dry etches or both. In some embodiments of the present invention, the spacers 2202, nitride layer 2106, and hard mask 2102 may be removed using an RIE or nitride strip process.

[0104] In some embodiments of the present invention, STIs 2702 are formed on substrate 2004 to electrically isolate one or more semiconductor fins. STIs 2702 can be any suitable dielectric material, such as, for example, silicon oxide, and can be formed using any suitable process. STIs 2702 can be formed using, for example, CVD, FVCD, PECVD, UHVCVD, RTCVD, MOCVD, LPCVD, LRPCVD, ALD, PVD, HDP, chemical solution deposition, spin-on dielectric, or other similar processes. In some embodiments of the present invention, STIs 2702 are overfilled and then recessed using, for example, a chemical mechanical planarization (CMP) process.

[0105] In some embodiments of the present invention, the STIs 2702 are recessed below the surface of the first sacrificial layer 2002. In this manner, the STIs 2702 electrically isolate one or more nanosheet stacks. The STIs 2702 can be recessed using, for example, chemical oxide removal (COR) or hydrofluoric acid (HF) wet etching. In some embodiments of the present invention, the STIs 2702 are recessed selectively relative to the hard mask 2008.

[0106] 28 shows a cross-sectional view of an "X-FET" type semiconductor structure 2000 during an intermediate operation of a method of fabricating a semiconductor device according to one or more embodiments of the present invention. The "X-FET" type semiconductor structure 2000 can be completed substantially in a manner similar to the "X-FET" type semiconductor structure 200 shown in FIGS. 2A-15B.

[0107] 28, the "X-FET" type semiconductor structure 2000 includes a conductive gate 2802 and a gate hard mask 2804. In some embodiments of the present invention, the semiconductor structure 2000 further includes S / D regions, inner spacers, gate spacers, dielectric layers, and contacts (not shown). Each of these features may be made of similar materials and by substantially similar methods as the corresponding features of the "X-FET" type semiconductor structure 200 shown in FIGS. 2A-15B.

[0108] 28, a conductive gate 2802 can be deposited over the exposed surface of semiconductor layer 2006. In this manner, the vertical (e.g., vertical fins) and horizontal (e.g., nanosheets) portions of semiconductor layer 2006 define an "X-FET" type channel region between the S / D regions. In some embodiments of the invention, the high-k dielectric layer of conductive gate 2802 is in direct contact with the sidewalls of the vertical fins and the top and bottom surfaces of one or more respective nanosheets.

[0109] 29A-31B illustrate cross-sectional views of an "X-FET" type semiconductor structure 2900 during intermediate operations of a method of fabricating a semiconductor device according to one or more embodiments of the present invention. As shown in FIGS. 29A and 29B, the partially fabricated semiconductor device can include a buried oxide (BOX) layer 2902 formed over a substrate 2904. The BOX layer 2902 can be formed using known silicon-on-insulator (SOI) processes and can comprise, for example, silicon dioxide or sapphire. The substrate 2904 can be made of the same material and in a similar manner as the substrate 204 shown in FIG. 2B.

[0110] In some embodiments of the present invention, a stack of one or more alternating first semiconductor layers 2906 and one or more second semiconductor layers 2908 is formed on the BOX layer 2902. For ease of illustration, the stack is shown as having three alternating first semiconductor layers 2906 and four alternating second semiconductor layers 2908, but it is understood that the stack can include any number of alternating first semiconductor layers and a corresponding number of alternating second semiconductor layers. The first semiconductor layer 2906 and the second semiconductor layer 2908 can be formed in a manner similar to the semiconductor layer 206 and the sacrificial layer 208 shown in FIG. 2B, respectively. In some embodiments of the present invention, the first semiconductor layer 2906 is made of silicon, and the second semiconductor layer 2908 is made of silicon-germanium.

[0111] Each first semiconductor layer 2906 can have a height ranging from 4 nm to 12 nm, e.g., 7 nm to 10 nm. In some embodiments of the present invention, first semiconductor layer 2906 has a height of about 8 nm. Each second semiconductor layer 2908 can have a height ranging from 6 nm to 40 nm, e.g., 8 nm to 20 nm. In some embodiments of the present invention, each second semiconductor layer 2908 has the same height as first semiconductor layer 2906. In some embodiments of the present invention, second semiconductor layer 2908 includes a germanium concentration of 15 to 35 percent, e.g., 25 percent. However, other germanium concentrations are within the contemplated scope of the present invention.

[0112] In some embodiments of the present invention, a hard mask 2910 may be formed on the topmost one of the second semiconductor layers 2908. In some embodiments of the present invention, the hard mask 2910 comprises a nitride, such as silicon nitride. In some embodiments of the present invention, the hard mask 2910 is formed to a thickness of 40 nm; however, other thicknesses are within the contemplated scope of the present invention. In some embodiments of the present invention, a second hard mask (not shown) may be formed on the hard mask 2910 to form a two-layer hard mask. In some embodiments of the present invention, the second hard mask comprises an oxide, such as silicon dioxide.

[0113] In some embodiments of the present invention, portions of hard mask 2910 are removed (e.g., patterned) and the stack of first semiconductor layer 2906 and second semiconductor layer 2908 is selectively patterned relative to hard mask 2910. Portions of first semiconductor layer 2906 and second semiconductor layer 2908 not covered by patterned hard mask 2910 can be removed using wet etching, dry etching, or sequential wet or dry etching or a combination of both.

[0114] 30A and 30B show cross-sectional views of an "X-FET" type semiconductor structure 2900 during intermediate operations of a method of fabricating a semiconductor device according to one or more embodiments of the present invention. As shown in Figures 30A and 30B, the second semiconductor layer 2908 is recessed to form one or more recesses 3002.

[0115] In some embodiments of the present invention, the second semiconductor layer 2908 is selectively recessed relative to the first semiconductor layer 2906. The second semiconductor layer 2908 can be recessed using any suitable process that can selectively remove a silicon-germanium layer relative to a silicon layer or a silicon-germanium layer having a lower germanium concentration. Exemplary processes known to provide this etch selectivity include hydrophosphoric acid, HCl vapor phase chemistry, and chlorine trifluoride (ClF) etching.

[0116] 31A and 31B show cross-sectional views of an "X-FET" type semiconductor structure 2900 during intermediate operations of a method of fabricating a semiconductor device according to one or more embodiments of the present invention. As shown in FIGURES 31A and 31B, the semiconductor structure 2900 is subjected to an annealing process. This annealing process causes the germanium in the second semiconductor layer 2908 to diffuse uniformly throughout the first semiconductor layer 2906 and the second semiconductor layer 2908.

[0117] The resulting semiconductor layer 3102 comprises silicon germanium with a germanium concentration between 0 and the germanium concentration of the second semiconductor layer 2908 before annealing. For example, if the second semiconductor layer 2908 was SiGe20% (e.g., 20% Ge), the final germanium concentration of the semiconductor layer 3102 would be less than 20%. In some embodiments of the present invention, the semiconductor structure 2900 can be annealed at a temperature of about 950 to 1150 degrees Celsius.

[0118] In some embodiments of the present invention, an "X-FET" type semiconductor structure 2900 can be completed substantially in a manner similar to the "X-FET" type semiconductor structure 200 shown in FIGS. 2A-15B. The "X-FET" type semiconductor structure 2900 can include a conductive gate, a gate SAC cap, S / D regions, inner spacers, gate spacers, a dielectric layer, and contacts (not shown). Each of these features can be made of similar materials and by substantially similar methods as the corresponding features of the "X-FET" type semiconductor structure 200 shown in FIGS. 2A-15B.

[0119] 32A-35B show cross-sectional views of a "junctionless X-FET" type semiconductor structure 3200 during intermediate operations of a method of fabricating a semiconductor device according to one or more embodiments of the present invention. As shown in FIGS. 32A and 32B, the partially fabricated semiconductor device can include a BOX layer 3202 formed on a substrate 3204. BOX layer 3202 and substrate 3204 can be made of the same materials and in a similar manner as BOX layer 2902 and substrate 2904, respectively, shown in FIG. 29A.

[0120] In some embodiments of the present invention, a stack of one or more alternating first semiconductor layers 3206 and one or more second semiconductor layers 3208 is formed on the BOX layer 3202. For ease of illustration, the stack is shown as having three alternating first semiconductor layers 3206 and four alternating second semiconductor layers 3208, but it is understood that the stack can include any number of alternating first semiconductor layers and a corresponding number of second semiconductor layers. In some embodiments of the present invention, the first semiconductor layer 3206 is made of silicon and the second semiconductor layer 3208 is made of doped silicon, such as, for example, boron-doped silicon.

[0121] The second semiconductor layer 3208 can be doped using in situ doped epitaxy, can be doped after epitaxy, or can be doped by implantation and plasma doping. In some embodiments of the present invention, the first semiconductor layer 3206 and the second semiconductor layer 3208 are formed using an epitaxy process in which each layer is epitaxially grown sequentially on the preceding layer.

[0122] Each first semiconductor layer 3206 can have a height in the range of 4 nm to 12 nm, for example, 7 nm to 10 nm. In some embodiments of the present invention, first semiconductor layer 3206 has a height of about 8 nm. Each second semiconductor layer 3208 can have a height in the range of 6 nm to 40 nm, for example, 8 nm to 20 nm. In some embodiments of the present invention, each second semiconductor layer 3208 has the same height as first semiconductor layer 3206. In some embodiments of the present invention, second semiconductor layer 3208 has a height in the range of 10 nm to 12 nm, for example, 7 nm to 10 nm. 13 cm -3 From 10 18 cm -3 However, other boron dopant concentrations are within the contemplated scope of the present invention.

[0123] In some embodiments of the present invention, a hard mask 3210 may be formed on the topmost one of the second semiconductor layers 3208. In some embodiments of the present invention, the hard mask 3210 comprises a nitride, such as silicon nitride. In some embodiments of the present invention, the hard mask 3210 is formed to a thickness of 40 nm; however, other thicknesses are within the contemplated scope of the present invention. In some embodiments of the present invention, a second hard mask (not shown) may be formed on the hard mask 3210 to form a two-layer hard mask. In some embodiments of the present invention, the second hard mask comprises an oxide, such as silicon dioxide.

[0124] In some embodiments of the present invention, portions of the hard mask 3210 are removed (e.g., patterned) and the stack of first semiconductor layer 3206 and second semiconductor layer 3208 is selectively patterned relative to the hard mask 3210. Portions of the first semiconductor layer 3206 and second semiconductor layer 3208 not covered by the patterned hard mask 3210 can be removed using wet etching, dry etching, or sequential wet or dry etching or a combination of both.

[0125] 33A and 33B show cross-sectional views of a "junctionless X-FET" type semiconductor structure 3200 during intermediate operations of a method of fabricating a semiconductor device according to one or more embodiments of the present invention. As shown in FIGURES 33A and 33B, the second semiconductor layer 3208 is recessed to form one or more recesses 3302.

[0126] In some embodiments of the present invention, the second semiconductor layer 3208 is selectively recessed relative to the first semiconductor layer 3206. The second semiconductor layer 3208 can be recessed using any suitable process that can selectively remove doped silicon layers (e.g., boron-doped silicon) relative to silicon layers. Exemplary processes known to provide this etch selectivity include ammonia-based chemistries and tetramethylammonium hydroxide (TMAH or TMAOH) etches.

[0127] 34A and 34B show cross-sectional views of a "junctionless X-FET" type semiconductor structure 3200 during intermediate operations of a method of fabricating a semiconductor device according to one or more embodiments of the present invention. As shown in FIGURES 34A and 34B, the semiconductor structure 3200 is subjected to an annealing process. This annealing process causes the dopant (e.g., boron) in the second semiconductor layer 3208 to diffuse uniformly throughout the first semiconductor layer 3206 and the second semiconductor layer 3208.

[0128] The resulting semiconductor layer 3402 comprises doped silicon having a dopant concentration between 0 and the dopant concentration of the second semiconductor layer 3208 before annealing. For example, if the second semiconductor layer 3208 is 10 15 cm -3 If the silicon was boron doped with silicon having a boron concentration of 10.0, the final boron dopant concentration in semiconductor layer 3402 would be 10.0. 15 cm -3 In some embodiments of the present invention, the semiconductor structure 3200 may be annealed at a temperature of about 950 to 1150 degrees Celsius. At this point, the semiconductor structure 3200 is a junctionless device (sometimes called a junction-free device).

[0129] 35A and 35B show cross-sectional views of a "junctionless X-FET" type semiconductor structure 3200 during intermediate operations of a method of fabricating a semiconductor device according to one or more embodiments of the present invention. If a junctionless device is not desired, the intrinsic silicon channel in semiconductor structure 3200 can be restored, as shown in FIGS. 35A and 35B. In some embodiments of the present invention, semiconductor structure 3200 is subjected to a hydrogen treatment to drive out dopants (e.g., boron) in semiconductor layer 3402.

[0130] In some embodiments of the present invention, several "junctionless X-FET" type semiconductor structures are formed and only a subset of those structures are subjected to hydrogen treatment (e.g., using masking or other isolation techniques). In this manner, several "junctionless X-FET" type semiconductor structures can be formed along with conventional semiconductor structures that have effective junctions.

[0131] In some embodiments of the present invention, the "junctionless X-FET" type semiconductor structure 3200 (or a conventional structure after hydrogen treatment) can be completed substantially in a manner similar to the "X-FET" type semiconductor structure 200 shown in FIGS. 2A-15B. The "junctionless X-FET" type semiconductor structure 3200 can include a conductive gate, a SAC cap, S / D regions, inner spacers, gate spacers, a dielectric layer, and contacts (not shown). Each of these features can be made of similar materials and by substantially similar methods as the corresponding features of the "X-FET" type semiconductor structure 200 shown in FIGS. 2A-15B.

[0132] FIG. 36 shows a flow chart 3600 illustrating a method for forming a semiconductor device according to one or more embodiments of the present invention. The semiconductor device may include a first semiconductor layer, a second semiconductor layer, and a non-planar channel region having a fin-shaped bridge layer between the first and second semiconductor layers (e.g., as shown in FIGS. 15A and 15B). The outer surfaces of the first semiconductor layer, the second semiconductor layer, and the fin-shaped bridge region define an effective channel width of the non-planar channel region. In some embodiments of the present invention, the width of the first semiconductor layer is greater than the width of the fin-shaped bridge region. In some embodiments of the present invention, the width of the second semiconductor layer is greater than the width of the fin-shaped bridge region. In some embodiments of the present invention, the width of the first semiconductor layer is the same as the width of the second semiconductor layer.

[0133] As shown in block 3602, a first sacrificial layer is formed on a substrate. As shown in block 3604, a nanosheet stack is formed on the first sacrificial layer. The nanosheet stack includes a first semiconductor layer and a second sacrificial layer.

[0134] At block 3606, a first fin spacer is formed on a first portion of the nanosheet stack. At block 3608, a second fin spacer is formed on a second portion of the nanosheet stack. As shown in block 3610, a trench is formed by removing a third portion of the nanosheet stack. The trench exposes a surface of the first sacrificial layer. At block 3612, a second semiconductor layer is formed on the surface of the first sacrificial layer in the trench.

[0135] 37 shows a flow chart 3700 illustrating a method for forming a semiconductor device according to one or more embodiments of the present invention. A semiconductor layer is formed on a substrate, as shown in block 3702. At block 3704, a stack of alternating oxide and nitride layers is formed adjacent to the semiconductor layer.

[0136] The oxide layer is removed to expose sidewalls of the semiconductor layer, as shown in block 3706. In block 3708, the exposed sidewalls of the semiconductor layer are recessed to define a vertical portion and one or more horizontal portions of the semiconductor layer.

[0137] 38 shows a flow chart 3800 illustrating a method for forming a semiconductor device according to one or more embodiments of the present invention. As shown in block 3802, a nanosheet stack is formed on a substrate. The nanosheet stack includes a first semiconductor layer and a second semiconductor layer. The second semiconductor layer includes a first material.

[0138] At block 3804, the sidewalls of the second semiconductor layer are recessed. At block 3806, the structure is annealed at a temperature operable to uniformly diffuse the first material into the first semiconductor layer and the second semiconductor layer.

[0139] 39 shows a flow chart 3900 illustrating a method for forming a semiconductor device according to one or more embodiments of the present invention. As shown in block 3902, a stack of alternating semiconductor layers and doped semiconductor layers is formed over a substrate. The doped semiconductor layers include a dopant.

[0140] The sidewalls of the doped semiconductor layer are recessed, as shown in block 3904. In block 3906, the structure is annealed at a temperature operable to uniformly diffuse the dopants into the semiconductor layer and the doped semiconductor layer.

[0141] 40 shows a flow chart 4000 illustrating a method for forming a semiconductor device according to one or more embodiments of the present invention. As shown in block 4002, a nanosheet stack is formed on a substrate. The nanosheet stack includes one or more first semiconductor layers and one or more first sacrificial layers.

[0142] As shown in block 4004, a trench is formed by removing portions of the one or more first semiconductor layers and the one or more first sacrificial layers. The trench exposes a surface of a bottommost sacrificial layer of the one or more first sacrificial layers. At block 4006, the trench is filled with one or more second semiconductor layers and one or more second sacrificial layers such that one or more respective second semiconductor layers contact a sidewall of one of the one or more first semiconductor layers.

[0143] 41 shows a flow chart 4100 illustrating a method for forming a semiconductor device according to one or more embodiments of the present invention. As shown in block 4102, a first channel region is formed over a substrate. The first channel region includes a first vertical fin and a first nanosheet extending from a sidewall of the first vertical fin.

[0144] As shown in block 4104, a second channel region is formed over the first channel region. The second channel region includes a second vertical fin and a second nanosheet extending from a sidewall of the second vertical fin. At block 4106, a gate is formed over the first channel region and the second channel region. The gate contacts a top surface of the first channel region and a bottom surface of the second channel region.

[0145] The methods and resulting structures described herein can be used in the manufacture of IC chips. Manufacturers can distribute the resulting IC chips in raw wafer form (i.e., as a single wafer containing multiple unpackaged chips), as bare die, or in packaged form. When distributed in packaged form, the chips are mounted in single-chip packages (such as plastic carriers with leads attached to a motherboard or other higher-level carrier) or multi-chip packages (such as ceramic carriers with single-sided or double-sided interconnects or embedded interconnects). In either case, the chips are then integrated with other chips, discrete circuit elements, or other signal processing devices, or a combination thereof, as part of either (a) an intermediate product such as a motherboard or (b) a final product. The final product can be any product containing IC chips, ranging from toys and other low-end applications to sophisticated computer products with displays, keyboards or other input devices, and central processing units.

[0146] Various embodiments of the present invention are described herein with reference to the associated figures. Alternate embodiments may be devised without departing from the scope of the present invention. While the following description and drawings illustrate various connections and relationships between elements (e.g., above, below, adjacent, etc.), those skilled in the art will appreciate that many of the relationships described herein are independent of orientation, as the described functionality is maintained even when the orientation is changed. These connections and / or relationships can be direct or indirect, unless otherwise specified, and the present invention is not intended to be limited in this regard. Similarly, the term "coupled" and variations thereof indicate that there is a communication path between two elements and do not imply a direct connection between the elements with no intervening elements / connections between them. All of these variations are considered part of this specification. Thus, coupling of entities can be direct or indirect coupling, and relationship between entities can be direct or indirect. As an example of an indirect positional relationship, references in this specification to forming layer "A" on layer "B" include situations where there are one or more intermediate layers (e.g., layer "C") between layer "A" and layer "B," so long as the relative properties and functions of layer "A" and layer "B" are not substantially altered by the intermediate layers.

[0147] The following definitions and abbreviations are used for the purposes of interpreting the claims and this specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," or "containing," or other variations of these terms, are intended to cover non-exclusive inclusion. For example, a composition, mixture, process, method, article, or device that includes a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent in such composition, mixture, process, method, article, or device.

[0148] Moreover, the word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" are understood to include any integer number greater than or equal to one, i.e., 1, 2, 3, 4, etc. The term "plurality" is understood to include any integer number greater than or equal to two, i.e., 2, 3, 4, 5, etc. The term "connected" can include an indirect "connected" and a direct "connected."

[0149] When reference is made herein to "one embodiment," "an embodiment," "an exemplary embodiment," or the like, it indicates that the described embodiment may include a particular feature, structure, or characteristic, but that all embodiments may or may not include that particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described with respect to one embodiment, it is believed to be within the knowledge of one of ordinary skill in the art to affect such feature, structure, or characteristic with respect to other embodiments, whether or not explicitly stated.

[0150] For purposes of the foregoing description, the terms "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and derivatives of these terms refer to the described structures and methods as oriented in the figures. The terms "overlying," "atop," "on top," "positioned on," or "positioned atop" mean that a first element, such as a first structure, is on a second element, such as a second structure, where there may be an intervening element, such as an interface structure, between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediate conductive, insulating, or semiconducting layer at the interface between the two elements.

[0151] For ease of explanation, spatially relative terms, such as "beneath," "below," "lower," "above," and "upper," are used herein to describe the relationship of one element or feature to another element or feature shown in the figures. These spatially relative terms are understood to encompass various orientations of the device in use or operation, not just the orientation depicted in the figures. For example, if a device in the figures were turned over, an element described as being "below" or "below" another element or feature would then be located "above" that other element or feature. Thus, the term "below" can encompass both an orientation of above and below. The device may also be otherwise oriented (e.g., rotated 90 degrees or at another orientation), and the spatially relative descriptors used herein should be interpreted accordingly.

[0152] The terms "about," "substantially," "approximately," and variations of these terms are intended to include the degree of error associated with the magnitude of the particular quantity, based on the equipment available at the time of filing this application. For example, "about" can include a range of ±8%, 5%, or 2% of a given value.

[0153] The phrase "selective to," such as "selectively to a first element relative to a second element," means that the first element can be etched and the second element can act as an etch stop.

[0154] The term "conformal" (e.g., conformal layer) means that the thickness of the layer is substantially the same on all surfaces, or that the thickness varies by less than 15% of the nominal thickness of the layer.

[0155] The terms "epitaxial growth and / or deposition" and "epitaxially formed and / or epitaxially grown" refer to the growth of a semiconductor material (crystalline material) on a deposition surface of another semiconductor material (crystalline material), where the growing semiconductor material (crystalline overlayer) has substantially the same crystalline properties as the semiconductor material (seed material) on the deposition surface. In an epitaxial deposition process, chemical reactants supplied by source gases can be controlled and system parameters can be set so that the adatoms arrive at the deposition surface with sufficient energy to move around the deposition surface of the semiconductor substrate so that they align with the crystalline arrangement and orientation of the atoms on the deposition surface. Epitaxially grown semiconductor material can have substantially the same crystalline properties as the deposition surface on which it was formed. For example, epitaxially grown semiconductor material deposited on a {100}-oriented crystal surface can have a {100} orientation. In some embodiments of the present invention, the epitaxial growth process and / or epitaxial deposition process may be selective to formation on semiconductor surfaces and may or may not deposit material on exposed surfaces, such as silicon dioxide or silicon nitride surfaces.

[0156] As noted previously herein, for the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) manufacturing may or may not be described in detail herein. However, the Background section provided a more general description of semiconductor device manufacturing processes that may be utilized in practicing one or more embodiments of the present invention. While the specific manufacturing operations used in practicing one or more embodiments of the present invention may be individually known, the described combination of operations and / or resulting structures of the present invention is unique. Thus, the unique combination of operations described in connection with the manufacture of semiconductor devices utilizes a variety of individually known physical and chemical processes performed on semiconductor (e.g., silicon) substrates, some of which are described in the following paragraphs.

[0157] The various processes used to form microchips that are packaged as integrated circuits generally fall into four general categories: film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is the process of growing material on a wafer, coating it with material, or otherwise transferring material onto the wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and the more recent atomic layer deposition (ALD), among others. Removal / etching is the process of removing material from a wafer. Examples include etching processes (wet or dry) and chemical-mechanical planarization (CMP). For example, reactive ion etching (RIE) is a type of dry etching that uses a chemically reactive plasma to remove material, such as a masked pattern of semiconductor material, by bombarding it with ions that remove portions of the material from the exposed surface. This plasma is usually generated under low pressure (vacuum) by an electromagnetic field. Semiconductor doping is the modification of electrical properties through doping, such as doping the source and drain of a transistor, and is typically performed by diffusion, ion implantation, or both. These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). The annealing serves to activate the implanted dopants. Both conductor (e.g., polysilicon, aluminum, copper, etc.) and insulator (e.g., various forms of silicon dioxide and silicon nitride, etc.) films are used to connect and separate transistors and their components. Selective doping of various regions of a semiconductor substrate allows the substrate's conductivity to change with the application of voltage. Fabricating these various component structures allows millions of transistors to be built and wired together to form the complex circuits of modern microelectronic devices. Semiconductor lithography is the creation of three-dimensional relief images or patterns on a substrate that are then transferred to a semiconductor substrate.In semiconductor lithography, patterns are formed using a light-sensitive polymer called photoresist. Lithography and etching pattern transfer steps are repeated many times to build the complex structures that make up transistors and the many wires that connect the millions of transistors in the circuit. Each pattern printed on the wafer is aligned with a previously formed pattern, and conductors, insulators, and selectively doped regions are slowly built up to form the final device.

[0158] The flowcharts and block diagrams in the accompanying figures illustrate possible implementations of methods of manufacture and / or operation according to various embodiments of the present invention. In the flowcharts, various functions / operations of the method are represented by blocks. In some alternative implementations, the functions shown in the blocks may be performed in an order different from that shown in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may be executed in the reverse order, depending on the functionality involved.

[0159] The description of various embodiments of the present invention has been provided for illustrative purposes and is not intended to be exhaustive or to limit the description to only the described embodiments. Many modifications and variations that do not depart from the scope and spirit of the described embodiments will be apparent to those skilled in the art. The terminology used herein has been selected to best explain the principles, practical applications, or technical improvements of the embodiments over commercially available technology, or to enable those skilled in the art to understand the embodiments described herein.

Claims

1. 1. A method for forming a semiconductor device, the method comprising: forming a stack of alternating semiconductor and doped semiconductor layers on a substrate; wherein the doped semiconductor layer comprises a dopant, and the method further comprises: recessing a sidewall of the doped semiconductor layer; and annealing at a temperature operable to uniformly diffuse the dopant into the semiconductor layer and the doped semiconductor layer. Including, The method further comprising removing the dopant from the semiconductor layer and the doped semiconductor layer.

2. The method of claim 1 , wherein removing the dopant comprises hydrogen treatment.

3. The method of claim 1 , wherein the dopant comprises boron.

4. The method of claim 1 , further comprising forming a gate over the semiconductor layer and the doped semiconductor layer.

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