Method for forming dielectric materials with selected polarization for semiconductor devices

Abstract

A dielectric film for a semiconductor device and a method for forming the same. The processing method includes forming a first film of a first dielectric material on a substrate by performing a first plurality of cycles of atomic layer deposition, followed by heat-treating the first film, where the thickness of the first film is less than a threshold thickness required for spontaneous polarization in the first dielectric material. The processing method further includes forming a second film of a second dielectric material on the substrate by performing a second plurality of cycles of atomic layer deposition, followed by heat-treating the second film, where the thickness of the second film is greater than the thickness of the first film, and the second film is a ferroelectric or antiferroelectric. The first and second dielectric materials can include at least one metal oxide, such as zirconium oxide, hafnium oxide, or a stack or mixture thereof.

Description

[Technical Field]

[0001] This application is related to and claims priority to U.S. Provisional Patent Application No. 63 / 063,840, filed August 10, 2020, the entire contents of which are incorporated herein by reference.

[0002] The present invention relates to semiconductor processing and semiconductor devices, and more particularly to substrate processing methods for forming dielectric materials with selected polarization by thin film vapor deposition. [Background technology]

[0003] Dielectric materials are used for CMOS-related applications, including field-effect transistor (FET) and dynamic random access memory (DRAM) devices. Novel methods are needed to form dielectric materials with selected polarizations by thin-film vapor deposition. Summary of the Invention [Means for solving the problem]

[0004]

[0006] Embodiments of the present invention include methods for forming structures of dielectric films on a substrate, including high-k films that may be used as capacitors and memory cells in semiconductor and other devices. According to one embodiment, the method includes forming a first film of a first dielectric material on the substrate by performing first multiple cycles of atomic layer deposition, followed by heat-treating the first film, wherein the thickness of the first film is less than a threshold thickness required for spontaneous polarization in the first dielectric material. The method further includes forming a second film of a second dielectric material on the substrate by performing second multiple cycles of atomic layer deposition, followed by heat-treating the second film, wherein the thickness of the second film is greater than the thickness of the first film, and the second film is a ferroelectric or antiferroelectric.

[0005] According to one embodiment, a semiconductor device includes a first film of a first dielectric material on a substrate, the first film having a thickness less than a threshold thickness required for spontaneous polarization in the first dielectric material, and a second film of a second dielectric material on the substrate, the second film having a thickness greater than the thickness of the first film, the second film being a ferroelectric or an antiferroelectric.

[0006] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present invention and, together with the general description of the invention given above and the detailed description given below, serve to explain the invention. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a flowchart of an exemplary method for fabricating a dielectric film structure, in accordance with one embodiment of the present invention. [Figure 2A] 1 illustrates a cross-sectional view of an exemplary dielectric film structure, in accordance with one embodiment of the present invention. [Figure 2B] 1 illustrates a cross-sectional view of an exemplary dielectric film structure, in accordance with one embodiment of the present invention. [Figure 2C] 1 illustrates a cross-sectional view of an exemplary dielectric film structure, in accordance with one embodiment of the present invention. [Figure 2D] 1 illustrates a cross-sectional view of an exemplary dielectric film structure, in accordance with one embodiment of the present invention. [Figure 2E] 1 illustrates a cross-sectional view of an exemplary dielectric film structure, in accordance with one embodiment of the present invention. [Figure 3] 1 illustrates a cross-sectional view of an exemplary dielectric film structure, in accordance with one embodiment of the present invention. [Figure 4] 1 illustrates a cross-sectional view of an exemplary dielectric film structure, in accordance with one embodiment of the present invention. [Figure 5] 1 illustrates a cross-sectional view of an exemplary dielectric film structure, in accordance with one embodiment of the present invention. [Figure 6A] 1A and 1B illustrate schematic cross-sectional views of exemplary membrane structures for semiconductor devices, according to embodiments of the present invention. [Figure 6B]1A and 1B illustrate schematic cross-sectional views of exemplary membrane structures for semiconductor devices, according to embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0008] This disclosure repeats reference numerals in the various embodiments. This repetition is for the purposes of simplicity and clarity, and repeated reference numerals indicate similar features across the various embodiments unless otherwise stated.

[0009] In one embodiment, as shown generally in FIGS. 1 and 2A-2E, the method in Flowchart 1 includes providing a substrate 200 to a process chamber at 100. In one example, the process chamber may be configured to perform atomic layer deposition (ALD) of a dielectric material on the substrate 200. The substrate 200 may include a semiconductor material, including, for example, silicon, germanium, silicon germanium, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In one example, the substrate 200 may have an epitaxial layer overlying a bulk semiconductor. Furthermore, the substrate 200 may include a semiconductor-on-insulator (SOI) structure. Furthermore, the substrate 200 may include a metal layer.

[0010] Substrate 200 may also include various p-type and / or n-type doped regions achieved by processes such as ion implantation and / or diffusion, which may include n-type wells, p-type wells, lightly doped regions (LDDs), and various channel doping profiles configured to form various integrated circuit (IC) devices, such as complementary metal oxide semiconductor field effect transistors (CMOSFETs), image sensors, and / or light emitting diodes (LEDs).

[0011] The substrate 200 may also include various isolation regions. The isolation regions separate various device regions in the substrate 200. The isolation regions include different structures formed using different processing techniques. For example, the isolation regions may include shallow trench isolation (STI) regions. Forming the STI regions may include etching trenches in the substrate 200 and filling the trenches with an insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. The filled trenches may have a multi-layer structure, such as a thermal oxide liner layer and silicon nitride filling the trenches. Chemical mechanical polishing (CMP) may be performed to polish away excess insulating material and planarize the top surfaces of the isolation features.

[0012] The method further includes forming 110 a first film 220 of a first dielectric material on the substrate 200 by performing a first plurality of cycles of atomic layer deposition (ALD). This is shown schematically in FIG. 2B. According to some embodiments, the first film 220 comprises a high-k material having a dielectric constant greater than that of SiO (k≈4). In the example of a metal oxide, the ALD can include alternating cycles of saturated gas exposure with a metal-containing precursor and an oxidizer, with each cycle including one exposure of the metal-containing precursor followed by one exposure of the oxidizer. Each cycle deposits one or less atomic layers of the metal oxide, and the number of cycles can be selected to precisely control film thickness. Steric hindrance of the ligands in the metal-containing precursor and the oxidizer, as well as a limited number of binding sites, can limit chemisorption on the substrate surface; therefore, film growth per cycle can remain less than one atomic layer.

[0013] According to some embodiments, the first film 220 can include zirconium oxide (ZrO), hafnium oxide (HfO), or a stack or mixture thereof. The HfO may be doped with aluminum (Al), gadolinium (Gd), lanthanum (La), silicon (Si), strontium (Sr), or yttrium (Y) dopants.

[0014] In one example, a first film 220 including ZrO may be deposited by ALD using alternating cycles of gas exposure of a zirconium-containing precursor and an oxidizer. In another example, a first film 220 including a mixture of ZrO and HfO may be deposited using ALD using alternating cycles of gas exposure of a zirconium-containing precursor and an oxidizer, and a hafnium-containing precursor and an oxidizer. In yet another example, a first film 220 including doped HfO may be deposited using ALD using alternating cycles of gas exposure of a hafnium-containing precursor, a dopant gas, and an oxidizer. The dopant concentration may be, for example, between about 0.1 atomic % and about 20 atomic %, between about 0.1 atomic % and about 10 atomic %, or between about 0.1 atomic % and about 1 atomic %.

[0015] Embodiments of the present invention may utilize a wide variety of zirconium (Zr) and hafnium (Hf) precursors for vapor deposition. For example, representative examples include Zr(O t Bu)4 (zirconium tert-butoxide, ZTB), Zr(NEt2)4 (tetrakis(diethylamido)zirconium, TDEAZ), Zr(NMeEt)4 (tetrakis(ethylmethylamido)zirconium, TEMAZ), Zr(NMe2)4 (tetrakis(dimethylamido)zirconium, TDMAZ), Hf(O tExamples of suitable precursors include Hf(Bu)4 (hafnium tert-butoxide, HTB), Hf(NEt2)4 (tetrakis(diethylamido)hafnium, TDEAH), Hf(NEtMe)4 (tetrakis(ethylmethylamido)hafnium, TEMAH), and Hf(NMe2)4 (tetrakis(dimethylamido)hafnium, TDMAH). In some embodiments, tris(dimethylaminocyclopentadienylhafnium (HfCp(NMe2)3), available from Air Liquide as HyALD™, may be used as the hafnium precursor, and tris(dimethylaminocyclopentadienylzirconium (ZrCp(NMe2)3), available from Air Liquide as ZyALD™, may be used as the zirconium precursor. The oxidizer may include an oxygen-containing gas, including plasma-excited O2, water (HO), or ozone (O3).

[0016] The Al, Gd, La, Si, Sr and Y dopant elements can be provided using any dopant gas having sufficient reactivity, thermal stability and volatility.

[0017] Examples of Al precursors include Al2Me6, Al2Et6, [Al(O(sBu))3]4, Al(CH3COCHCOCH3)3, AlBr3, AlI3, Al(O(iPr))3, [Al(NMe2)3]2, Al(iBu)2Cl, Al(iBu)3, Al(iBu)2H, AlEt2Cl, Et3Al2(O(sBu))3, and Al(THD)3.

[0018] Examples of Gd precursors include Gd(N(SiMe3)2)3, ((iPr)Cp)3Gd, Cp3Gd, Gd(THD)3, Gd[OOCCH(C2H5)C4H9]3, Gd(O(iPr))3, and Gd(acac)3.

[0019] Examples of La precursors are La(N(SiMe3)2)3, La(N(iPr)2)3, La(N(tBu)SiMe3)3, La(TMPD)3, ((iPr)Cp) 3La, Cp3La, Cp3La(NCCH3)2, La(Me2NC2H4Cp)3, La(THD)3, La[OOCCH(C2H5)C4H9]3, La(C 11 H 19 O2)3·CH3(OCH2CH2)3OCH3, La(C 11 H 19 O2)3·CH3(OCH2CH2)4OCH3, La(O(iPr))3, La(OEt)3, La(acac)3, La(((tBu)2N)2CMe)3, La (((iPr)2N)2CMe)3, La(((tBu)2N)2C(tBu))3, La(((iPr)2N)2C(tBu))3, and La(FOD)3.

[0020] Examples of silicon precursors include silane (SiH), disilane (SiH), monochlorosilane (SiClH), dichlorosilane (SiHCl), trichlorosilane (SiHCl), hexachlorodisilane (SiCl), diethylsilane (EtSiH), and alkylaminosilane compounds. Examples of alkylaminosilane compounds include diisopropylaminosilane (HSi(NPr)), bis(tert-butylamino)silane (C4H9(H)N)SiH), tetrakis(dimethylamino)silane (Si(NMe)), tetrakis(ethylmethylamino)silane (Si(NEtMe)), tetrakis(diethylamino)silane (Si(NEt)), tris(dimethylamino)silane (HSi(NMe)), tris(ethylmethylamino)silane (Si(NMe)). The silanes used in the present invention include, but are not limited to, bis(diethylamino)silane (HSi(NEtMe)), tris(diethylamino)silane (HSi(NEt)), and tris(dimethylhydrazino)silane (HSi(N(H)NMe)), bis(diethylamino)silane (HSi(NEt)), bis(diisopropylamino)silane (HSi(NPr)), tris(isopropylamino)silane (HSi(NPr)), and (diisopropylamino)silane (HSi(NPr).

[0021] Examples of Sr precursors include bis(tert-butylacetamidinato)strontium (TBAASr), Sr-C, Sr-D, Sr(N(SiMe3)2), Sr(THD)2, Sr(THD)2 (tetraglyme), Sr(iPr4Cp)2, Sr(iPr3Cp)2, and Sr(Me5Cp)2.

[0022] Examples of Y precursors include Y(N(SiMe3)2)3, Y(N(iPr)2)3, ((iPr)Cp)3Y, Cp3Y, Y(THD)3, Y[OOCCH(C2H5)C4H9]3, Y(O(iPr))3, Y(acac)3, (C5Me5)2Y, Y(hfac)3, and Y(FOD)3.

[0023] The following common abbreviations are used for the precursors mentioned above, as well as those mentioned below: Si: silicon; Me: methyl; Et: ethyl; iPr: isopropyl; nPr: n-propyl; Bu: butyl; nBu: n-butyl; sBu: sec-butyl; iBu: iso-butyl; tBu: tert-butyl; Cp: cyclopentadienyl; THD: 2,2,6,6-tetramethyl-3,5-heptanedionate; TMPD: 2,2,6,6-tetramethylpiperidide; acac: acetylacetonate; hfac: hexafluoroacetylacetonate; and FOD: 6,6,7,7,8,8,8-heptafluoro-2,2-dimethyl-3,5-octanedionate.

[0024] Following deposition of the first film 220 on the substrate 200, a thermal treatment process is performed on the first film 220 using a predetermined substrate temperature and duration to form a thermally treated first film 221. This is shown schematically in FIG. 2C. The thermal treatment organizes atomic elements in the first film 220, reduces film stress, and fixes the crystallographic orientation of the first dielectric material. The thermal treatment for the first film 220 may be performed at a substrate temperature of about 500°C or less, about 200°C to about 500°C, about 200°C to about 300°C, about 300°C to about 400°C, or about 400°C to about 500°C. In one embodiment, the thermal treatment may be performed in the same process chamber as the deposition of the first film 220. In another example, the thermal treatment may be performed in a different process chamber from the deposition of the first film 220. The thermal treatment may be performed under vacuum conditions in the presence of an inert gas, such as argon (Ar) or nitrogen (N).

[0025] According to one embodiment of the present invention, the thickness of the heat-treated first film 221 can be approximately 1.5 nm or less. For first dielectric materials comprising metal oxides, this thickness corresponds to a few monoatomic layers of the metal oxide, which is below the threshold thickness required for spontaneous polarization in metal oxides. This results in a metal oxide film capable of linear polarization in the presence of an external electric field. In one example, the heat-treated first film 221 comprises textured tetragonal ZrO2 with a (111) crystallographic orientation.

[0026] According to one embodiment, additional heat-treated films of dielectric material may be formed on the heat-treated first film 221 by repeating the deposition and heat-treating steps at least once. This is shown schematically in Figure 3, where additional heat-treated films 223, 225 are formed on the first film 221 on the heat-treated substrate 200 by repeating the deposition and heat-treating steps twice. In general, any number of additional heat-treated films may be formed. The heat-treated first film 221 and the additional heat-treated films 223, 225 collectively form a linearly polarizable dielectric material 230.

[0027] Referring again to FIG. 1 , the method further includes, at 120, forming a second film 240 of a second dielectric material on the substrate 200 by performing a second plurality of cycles of ALD. This is shown schematically in FIG. 2D . According to embodiments of the invention, the thickness of the second film 240 is greater than the thickness of the first thermally treated first film 221. The second film 240 may include a high-k material. According to some embodiments, the second film 240 may include ZrO, HfO, or a stack or mixture thereof. The HfO may be doped with a dopant of Al, Gd, La, Si, Sr, or Y. In one example, the thermally treated first film 220 and the second film 240 may include the same metal oxide.

[0028] Following deposition of the second film 240, a heat treatment process is performed using a predetermined substrate temperature and duration to form a heat treated second film 241. This is shown schematically in FIG. 2E. The heat treatment organizes the atomic elements in the second film 240, reduces film stress, and fixes the crystallographic orientation of the second dielectric material. The heat treated second film 241 and the heat treated first film 221 can have different crystallographic orientations.

[0029] The heat treatment for the second film 240 may be performed at a substrate temperature of about 500° C. or less, about 200° C. to about 500° C., about 200° C. to about 300° C., about 300° C. to about 400° C., or about 400° C. to about 500° C. According to one embodiment, a capping layer (not shown) may be deposited on the second film 240 prior to the heat treatment. In one example, the capping layer may include titanium nitride (TiN).

[0030] In one example, the heat treatment of the second film 240 may be performed in the same process chamber as the deposition of the second film 240. In another example, the heat treatment may be performed in a different process chamber than the deposition of the second film 240. The heat treatment may be performed under vacuum conditions in the presence of an inert gas, such as Ar or N.

[0031] Typically, the thickness of the heat-treated second film 241 is greater than the thickness of the heat-treated first film 221, and the heat-treated second film 241 is a ferroelectric or antiferroelectric material. In some embodiments, the thickness of the heat-treated second film 241 is about 5 nm or greater.

[0032] According to another embodiment of the present invention, a heat-treated second film 241 is formed on a substrate 200, and then a heat-treated first film 221 is formed on the heat-treated second film 241. This is shown schematically in FIG.

[0033] According to one embodiment, additional heat-treated dielectric materials may be formed on the heat-treated first film 221 by repeating the deposition and heat-treating steps at least once. This is shown schematically in Figure 5, where additional heat-treated films 223, 225 are formed on the heat-treated first film 221. In general, any number of additional heat-treated films may be formed. The heat-treated first film 221 and the additional heat-treated films 223, 225 collectively form a linearly polarizable dielectric material 231.

[0034] Embodiments described herein provide methods for forming dielectric materials on substrates, which may be utilized to form negative capacitance (NC) gate stacks for CMOS-related applications, such as field effect transistor (FET) devices or dynamic random access memory (DRAM) devices. The dielectric materials may be formed with selected and tailored polarizations, for example, for use in metal oxide semiconductor field effect transistors (MOSFETs) with extremely short channel lengths for ultra-low power computing.

[0035] FIG. 6A schematically illustrates a cross-sectional view of a film structure 60 for a semiconductor device. The film structure 60 includes a first conductive layer 600, a first film 602 including a first dielectric material, a second film 604 including a second dielectric material, and a second conductive layer 606 on the second film 604. The first and second conductive layers 600, 606 may include a metal-containing material, such as aluminum (Al), copper (Cu), tungsten (W), nickel (Ni), platinum (Pt), alloys thereof, or metal compounds such as titanium nitride (TiN) or tantalum nitride (TaN). The first and second conductive layers 600, 606 may also include a metal suicide or doped silicon. In one embodiment, the first and second conductive layers 600, 606 may be selected to be compatible with n-type and p-type FETs. The first film 602 may be formed as described above for the heat-treated first film 221. The first film 602 can have a thickness less than the threshold thickness required for spontaneous polarization in the first dielectric material. Thus, the first film 602 can be capable of linear polarization in the presence of an external electric field. The second film 604 can be formed as described above with respect to the heat-treated second film 241. The second film 604 can have a thickness greater than that of the first film 602, and the second dielectric material has spontaneous polarization. The spontaneous polarization can be ferroelectric or antiferroelectric. The capacitance C of the semiconductor structure 60 is comprised of the capacitances of the films and layers shown in FIG. 6A.

[0036] The first film 602 can include ZrO2, HfO2, or a stack or mixture thereof. The HfO2 may be doped with a dopant of Al, Gd, La, Si, Sr, or Y. An exemplary method for forming the first film 602 and the second film 604 is illustrated in FIGS.

[0037] The film structure 61 in FIG. 6B is similar to the film structure 60 and includes a first conductive layer 600, a second film 604 including a second dielectric material, a first film 602 including a first dielectric material, and a second conductive layer 606 on the first film 602.

[0038] The film structures 60, 61 may undergo further CMOS or MOS technology processing to form various features and regions known in the art. For example, subsequent processing may form multi-level interconnects, including vertical interconnects such as conventional vias or contacts, and horizontal interconnects such as metal lines. The various interconnect features may implement various conductive materials, including copper, tungsten, and / or silicides, to provide electrical wiring for coupling various devices in the substrate to input / output power and signals.

[0039] Several embodiments have been described for forming dielectric materials having selected polarizations by thin film vapor deposition. The foregoing description of embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. This specification and the following claims include terms that are used for descriptive purposes only and should not be construed as limiting. Those skilled in the relevant art will recognize that many modifications and variations are possible in light of the above teachings. Those skilled in the art will recognize various equivalent combinations and substitutions of the various components shown in the figures. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.

Claims

1. forming a first film of a first dielectric material on a substrate by performing first multiple cycles of atomic layer deposition, and then heat-treating the first film, wherein a thickness of the first film is less than a threshold thickness required for spontaneous polarization in the first dielectric material, and the heat-treated first film does not spontaneously polarize and exhibits linear polarization in the presence of an external electric field; performing second multiple cycles of atomic layer deposition to form a second film of a second dielectric material on the substrate, and then heat-treating the second film, wherein a thickness of the second film is greater than the thickness of the first film, and the heat-treated second film is a ferroelectric or antiferroelectric material; Including, A method of processing a substrate, wherein forming the first film is performed before forming the second film, or forming the second film is performed before forming the first film.

2. The method of claim 1 , wherein the second film is formed on the first film.

3. The method of claim 1 , wherein the first film is formed on the second film.

4. The method of claim 1 , wherein the first dielectric material and the second dielectric material comprise at least one metal oxide.

5. The method of claim 4 , wherein the at least one metal oxide comprises zirconium oxide, hafnium oxide, or a laminate or mixture thereof.

6. The method of claim 1 , wherein the thickness of the first film is 1.5 nm or less.

7. 10. The method of claim 1, further comprising repeating forming the first film to form an additional film on the first film, the additional film lacking spontaneous polarization.

8. forming the first film before forming the second film; The method of claim 1 , further comprising depositing a cap layer on the second film before heat treating the second dielectric material.

9. 10. The method of claim 1, wherein heat treating the first film and heat treating the second film are carried out at a substrate temperature between 650° C. and 900° C. in the presence of an inert gas.

10. forming a first film of a first zirconium oxide material on a substrate by performing first multiple cycles of atomic layer deposition, and then heat-treating the first film, wherein a thickness of the first film is less than a threshold thickness required for spontaneous polarization in the first zirconium oxide material, and the heat-treated first film does not spontaneously polarize and exhibits linear polarization in the presence of an external electric field; performing second multiple cycles of atomic layer deposition to form a second film of a second zirconium oxide material on the substrate, and then heat-treating the second film, wherein a thickness of the second film is greater than the thickness of the first film, and the heat-treated second film is a ferroelectric or antiferroelectric material; Including, A method of processing a substrate, wherein forming the first film is performed before forming the second film, or forming the second film is performed before forming the first film.

11. forming a first film of a first dielectric material on a substrate by performing first multiple cycles of atomic layer deposition, and then heat-treating the first film to fix a crystalline phase of the first film, the thickness of the first film being less than a threshold thickness required for spontaneous polarization in the first dielectric material, and the heat-treated first film exhibiting no spontaneous polarization and a linear polarization in the presence of an external electric field; forming a second film of a second dielectric material on the substrate by performing second multiple cycles of atomic layer deposition, and then heat-treating the second film to fix a crystalline phase of the second film, the thickness of the second film being greater than the thickness of the first film, and the heat-treated second film being a ferroelectric or antiferroelectric; Including, A method of processing a substrate, wherein forming the first film is performed before forming the second film, or forming the second film is performed before forming the first film.

12. The method of claim 11 , wherein the second film is formed on the first film.

13. The method of claim 11 , wherein the first film is formed on the second film.

14. The method of claim 11 , wherein the first dielectric material and the second dielectric material comprise at least one metal oxide.

15. 15. The method of claim 14, wherein the at least one metal oxide comprises zirconium oxide, hafnium oxide, or a laminate or mixture thereof.

16. The method of claim 11 , wherein the thickness of the first film is less than or equal to 1.5 nm.

17. 12. The method of claim 11, further comprising repeating forming the first film to form an additional film on the first film, the additional film lacking spontaneous polarization.

18. forming the first film before forming the second film; The method of claim 11 , further comprising depositing a cap layer on the second film before heat treating the second dielectric material.

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