semiconductor memory device

Abstract

To provide a semiconductor memory device that lowers the level of difficulty of a manufacturing process and reduces a manufacturing cost and by forming a dummy vertical structure and a word line and thereafter forming a sub-cutting line to overlap the dummy vertical structure in a vertical direction.SOLUTION: A semiconductor memory device comprises: a lower stacked structure extending in a first direction on a substrate, the lower stacked structure including a plurality of lower metal lines stacked in a vertical direction; an upper stacked structure on the lower stacked structure, the upper stacked structure including an upper metal line; a vertical structure penetrating the upper and lower stacked structures in the vertical direction, the vertical structure including a channel layer; a first cutting line cutting the upper and lower stacked structures; a first upper supporter on the first cutting line; a second upper supporter on the first cutting line, the second upper supporter being separated from the first upper supporter in a second direction; and a sub-cutting line cutting the upper stacked structure while at least partially overlapping the vertical structure in the vertical direction, the sub-cutting line being separated from the first cutting line in the first direction, where a top surface of the first upper supporter is coplanar with a top surface of the sub-cutting line.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that can reduce manufacturing costs by reducing the difficulty of the manufacturing process. [Background technology]

[0002] 2. Description of the Related Art In order to meet consumer demands for superior performance and lower prices, there is a demand for increased integration density of semiconductor devices. In the case of semiconductor devices, the degree of integration is an important factor in determining the price of the product, so increased integration is particularly desired. In the case of two-dimensional or planar semiconductor devices, the degree of integration is mainly determined by the area occupied by a unit memory cell, and is therefore greatly affected by the level of fine pattern formation technology.

[0003] However, the need for extremely expensive equipment to achieve finer patterns still limits the integration density of two-dimensional semiconductor devices, even though it is increasing. For this reason, a three-dimensional semiconductor memory device having memory cells arranged three-dimensionally has been proposed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-186868 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in consideration of the above-mentioned problems in conventional semiconductor memory devices, and an object of the present invention is to provide a semiconductor memory device that can reduce the difficulty of the manufacturing process and reduce manufacturing costs by forming sub-cutting lines to vertically overlap the dummy vertical structures after forming dummy vertical structures and word lines. When manufacturing a semiconductor memory device through this process, the upper surfaces of the sub-cutting lines can be formed flush with the upper surfaces of the upper supporters formed on the cutting lines. [Means for solving the problem]

[0006] a first interlayer insulating film surrounding a sidewall of the upper supporter and a sidewall of the at least one sub-cut line; a second interlayer insulating film surrounding a sidewall of the upper supporter and the lower supporter; a second interlayer insulating film surrounding a sidewall of the upper supporter and the lower supporter; a second interlayer insulating film surrounding a sidewall of the upper supporter and the lower supporter; a second interlayer insulating film surrounding a sidewall of the upper supporter and the lower supporter; a second interlayer insulating film surrounding a sidewall of the upper supporter and the lower supporter; a second interlayer insulating film surrounding a sidewall of the upper supporter and the lower supporter; a second interlayer insulating film surrounding a sidewall of the upper supporter and the lower supporter; a second interlayer insulating film surrounding a sidewall of the upper supporter and the lower supporter; a second interlayer insulating film surrounding a sidewall of the upper supporter and the lower supporter; a second interlayer insulating film surrounding a sidewall of the upper supporter and the lower supporter; a second interlayer insulating film surrounding a sidewall of the upper supporter and the lower supporter; a second interlayer insulating film surrounding a sidewall of the at least one sub-cut line; and a second interlayer insulating film disposed between an uppermost surface of the at least one vertical structure and a lower surface of the first interlayer insulating film, The upper surface of the upper supporter is formed on the same plane as the upper surface of the at least one sub-cutting line. The second interlayer insulating film surrounds the sidewalls of the first cutting line, the sidewalls of the second cutting line, and the sidewalls of the at least one sub-cutting line, and at least a portion of the lower surface of the upper supporter contacts the upper surface of the second interlayer insulating film. It is characterized by:

[0007] In order to achieve the above object, a semiconductor memory device according to the present invention includes a lower stacked structure extending in a first direction on a substrate and including a plurality of lower metal lines stacked in a vertical direction; an upper stacked structure disposed on the lower stacked structure and including at least one upper metal line; at least one vertical structure penetrating the upper stacked structure and the lower stacked structure in the vertical direction and including a channel film; a first cutting line cutting the upper stacked structure and the lower stacked structure; a first upper supporter disposed on the first cutting line; a second upper supporter disposed on the first cutting line and spaced apart from the first upper supporter in a second direction different from the first direction; and at least one sub-cutting line cutting the upper stacked structure, at least a portion of which vertically overlaps with the at least one vertical structure and spaced apart from the first cutting line in the first direction. a first interlayer insulating film surrounding a sidewall of the first upper supporter and a sidewall of the at least one sub-cutting line; and a second interlayer insulating film disposed between a top surface of the at least one vertical structure and a lower surface of the first interlayer insulating film. and an upper surface of the first upper supporter is formed on the same plane as an upper surface of the at least one sub-cutting line. The second interlayer insulating film surrounds a sidewall of the first cutting line and a sidewall of the at least one sub-cutting line, and at least a portion of a lower surface of the first upper supporter contacts an upper surface of the second interlayer insulating film. It is characterized by:

[0008] a first cutting line for cutting the upper and lower stacked structure and having a first width in the first direction; a first upper supporter disposed on the first cutting line and having a second width in the first direction greater than the first width; and a second upper supporter disposed on the first cutting line and having the second width in the first direction, the second width being spaced apart from the first upper supporter in a second direction different from the first direction. and a bit line extending in the first direction on the second interlayer insulating film, wherein an upper surface of the first upper supporter is formed on the same plane as an upper surface of the sub-cut line, and at least a portion of a lower surface of the first upper supporter is in contact with an upper surface of the first interlayer insulating film. [Effects of the Invention]

[0009] According to the semiconductor memory device of the present invention, after forming the dummy vertical structures and word lines, sub-cutting lines are formed to overlap the dummy vertical structures in the vertical direction, thereby reducing the difficulty of the manufacturing process and reducing manufacturing costs. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is an exemplary circuit diagram illustrating a semiconductor memory device according to an embodiment of the inventive concept; [Figure 2] 1 is a layout plan view illustrating a semiconductor memory device according to an embodiment of the present invention; [Figure 3] FIG. 3 is a cross-sectional view taken along line AA' in FIG. 2. [Figure 4] FIG. 4 is an enlarged view of region C in FIG. 3. [Figure 5] FIG. 4 is an enlarged view of region D in FIG. 3. [Figure 6] FIG. 4 is an enlarged view of region D in FIG. 3. [Figure 7] FIG. 3 is a cross-sectional view taken along line BB' in FIG. 2. [Figure 8] 10 is a layout diagram illustrating a semiconductor memory device according to another embodiment of the present invention; [Figure 9] 10 is a layout diagram illustrating a semiconductor memory device according to another embodiment of the present invention; [Figure 10] 10 is a layout diagram illustrating a semiconductor memory device according to another embodiment of the present invention; [Figure 11] 10 is a cross-sectional view illustrating a semiconductor memory device according to another embodiment of the present invention; [Figure 12] 10 is a cross-sectional view illustrating a semiconductor memory device according to another embodiment of the present invention; [Figure 13] 10 is a cross-sectional view illustrating a semiconductor memory device according to another embodiment of the present invention; [Figure 14] 10 is a cross-sectional view illustrating a semiconductor memory device according to another embodiment of the present invention; [Figure 15] 10 is a cross-sectional view illustrating a semiconductor memory device according to another embodiment of the present invention; [Figure 16] 10 is a cross-sectional view illustrating a semiconductor memory device according to another embodiment of the present invention; [Figure 17] 10 is a cross-sectional view illustrating a semiconductor memory device according to another embodiment of the present invention; [Figure 18] 10 is a cross-sectional view illustrating a semiconductor memory device according to another embodiment of the present invention; [Figure 19] 10 is a cross-sectional view illustrating a semiconductor memory device according to another embodiment of the present invention; [Figure 20] 1A to 1C are diagrams illustrating intermediate steps for describing a method of manufacturing a semiconductor memory device according to an embodiment of the present invention; [Figure 21] 1A to 1C are diagrams illustrating intermediate steps for describing a method of manufacturing a semiconductor memory device according to an embodiment of the present invention; [Figure 22] 1A to 1C are diagrams illustrating intermediate steps for describing a method of manufacturing a semiconductor memory device according to an embodiment of the present invention; [Figure 23] 1A to 1C are diagrams illustrating intermediate steps for describing a method of manufacturing a semiconductor memory device according to an embodiment of the present invention; [Figure 24] 1A to 1C are diagrams illustrating intermediate steps for describing a method of manufacturing a semiconductor memory device according to an embodiment of the present invention; [Figure 25] 1A to 1C are diagrams illustrating intermediate steps for describing a method of manufacturing a semiconductor memory device according to an embodiment of the present invention; [Figure 26] 1A to 1C are diagrams illustrating intermediate steps for describing a method of manufacturing a semiconductor memory device according to an embodiment of the present invention; [Figure 27] 1A to 1C are diagrams illustrating intermediate steps for describing a method of manufacturing a semiconductor memory device according to an embodiment of the present invention; [Figure 28] 1A to 1C are diagrams illustrating intermediate steps for describing a method of manufacturing a semiconductor memory device according to an embodiment of the present invention; [Figure 29] 1A to 1C are diagrams illustrating intermediate steps for describing a method of manufacturing a semiconductor memory device according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0011] Next, a specific example of an embodiment of a semiconductor memory device according to the present invention will be described with reference to the drawings.

[0012] FIG. 1 is an exemplary circuit diagram illustrating a semiconductor memory device according to an embodiment. Referring to FIG. 1, a memory cell array of a semiconductor memory device according to an embodiment of the present invention includes a common source line CSL, a plurality of bit lines (BL0 to BL2), and a plurality of cell strings CSTR arranged between the common source line CSL and the bit lines (BL0 to BL2).

[0013] A plurality of cell strings CSTR are connected in parallel to each of the bit lines (BL0 to BL2). The plurality of cell strings CSTR are commonly connected to a common source line CSL. That is, a plurality of cell strings CSTR are arranged between a plurality of bit lines (BL0 to BL2) and one common source line CSL. A plurality of common source lines CSL are arranged two-dimensionally. Here, the same voltage may be electrically applied to the common source lines CSL, or each common source line CSL may be electrically controlled.

[0014] For example, each cell string CSTR is composed of an erase control transistor ET, a string selection transistor SST, memory cells MCT connected in series, and a ground selection transistor GST. Each of the memory cells MCT also includes a data storage element. As an example, each cell string CSTR includes an erase control transistor ET and a string selection transistor SST connected in series. The erase control transistor ET is connected to the bit lines (BL0 to BL2). The ground selection transistor GST is connected to a common source line CSL. The memory cells MCT are connected in series between the string selection transistor SST and the ground selection transistor GST.

[0015] Furthermore, each cell string CSTR further includes a dummy cell DMCT connected between the string selection transistor SST and the memory cell MCT. Although not shown in the figure, the dummy cell DMCT can be connected between the ground selection transistor GST and the memory cell MCT. As another example, the ground selection transistor GST in each cell string CSTR may be configured with a plurality of MOS transistors connected in series. As another example, each cell string CSTR may include a plurality of string selection transistors connected in series.

[0016] According to an embodiment, the erase control transistor ET is controlled by an erase control line EL, and the string select transistor SST is controlled by a string select line SSL. The memory cells MCT are connected to a plurality of word lines (WL0 to WL n ), and the dummy cells DMCT are controlled by the dummy word lines DWL. The ground selection transistor GST is also controlled by a ground selection line GSL. A common source line CSL is commonly connected to the sources of the ground selection transistors GST. One cell string CSTR may be composed of a plurality of memory cells MCT having different distances from the common source line CSL.

[0017] A plurality of word lines (WL0 to WL2) are provided between the common source line CSL and the bit lines (BL0 to BL2). n , DWL) are placed. The gate electrodes of the memory cells MCT, which are arranged at substantially the same distance from the common source line CSL, are connected to the word lines (WL0 to WL n, DWL) and are in equipotential condition. In contrast to this, even if the gate electrodes of the memory cells MCT are arranged at substantially the same level from the common source line CSL, the gate electrodes arranged in different rows or columns are controlled independently. The ground selection lines (GSL0 to GSL2) and the string selection lines SSL are connected to, for example, the word lines (WL0 to WL n , DWL). The ground selection lines (GSL0 to GSL2) and the string selection lines SSL, which are arranged at substantially the same level from the common source line CSL, are electrically isolated from each other.

[0018] Moreover, the erase control lines EL, which are arranged at substantially the same level as the common source line CSL, are electrically isolated from each other. In contrast to this, although not shown in the figure, the erase control transistors ET of different cell strings CTSR are controlled by a common erase control line EL. The erase control transistor ET generates a gate induced drain leakage (GIDL) during an erase operation of the memory cell array. That is, the erase control transistor ET can be a GIDL transistor.

[0019] Hereinafter, semiconductor memory devices according to some embodiments of the present invention will be described with reference to FIGS. FIG. 2 is a layout plan view illustrating a semiconductor memory device according to an embodiment of the present invention, FIG. 3 is a cross-sectional view taken along line A-A' in FIG. 2, FIG. 4 is an enlarged view of region C in FIG. 3, FIGS. 5 and 6 are enlarged views of region D in FIG. 3, and FIG. 7 is a cross-sectional view taken along line B-B' in FIG. 2.

[0020] 2 to 7, the semiconductor memory device according to an embodiment of the present invention includes a substrate 100, a horizontal conductive substrate 150, a vertical structure support film 110, a lower stack structure BST, an inter-structure insulating film 126, an upper stack structure UST, first to fourth interlayer insulating films (141, 142, 143, 144), a first cutting line WLC1, a second cutting line WLC2, a first sub-cutting line SLC1, a second sub-cutting line SLC2, a vertical structure VS, first to sixth upper supporters (TS1, TS2, TS3, TS4, TS5, TS6), bit line plugs BLPG, and bit lines BL.

[0021] The substrate 100 may include one of a silicon substrate, a silicon germanium substrate, a germanium substrate, a silicon germanium on insulator (SGOI), a silicon-on-insulator (SOI), and a germanium-on-insulator (GOI). Alternatively, the substrate 100 may comprise a semiconductor material such as, but not limited to, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. A horizontal conductive substrate 150 is disposed on the substrate 100 . The horizontal conductive substrate 150 may be a common source plate. That is, the horizontal conductive substrate 150 can function as the common source line CSL in FIG.

[0022] The horizontal conductive substrate 150 may include at least one of a conductive semiconductor film, a metal silicide film, and a metal film. When the horizontal conductive substrate 150 includes a conductive semiconductor film, the horizontal conductive substrate 150 may include, for example, at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or a combination thereof. The horizontal conductive substrate 150 may have a crystalline structure including at least one selected from single crystal, amorphous, and polycrystalline. The horizontal conductive substrate 150 may include at least one of p-type impurities, n-type impurities, and carbon contained in a semiconductor film.

[0023] The lower stack structure BST extends on the substrate 100 in a first direction DR1. The lower stack structure BST is disposed on a horizontal conductive substrate 150 . The lower stack structure BST includes a plurality of lower metal lines (GSL, WL0 to WL1) stacked in a vertical direction DR3. n , DWL) and a plurality of inter-electrode insulating films (120, 125). The first and second inter-electrode insulating layers 120 and 125 are formed by lower metal lines (GSL, WL0 to WL1) spaced apart in a vertical direction DR3. n , DWL). Multiple bottom metal lines (GSL, WL0 to WL n , DWL) are connected to a ground selection line GSL, a plurality of word lines (WL0 to WL n ), including the dummy word line DWL. A ground selection line GSL, a plurality of word lines (WL0 to WL n ), and dummy word lines DWL are sequentially stacked on the substrate 100 .

[0024] In FIG. 3, six word lines (WL0 to WL n ) are shown for the convenience of explanation, but the technical idea of ​​the present invention is not limited thereto. Also, although the lower metal line disposed on the top of the lower stack structure BST is shown as a dummy word line DWL, the technical idea of ​​the present invention is not limited thereto. The lower metal line disposed on top of the lower stack structure BST is the word line WL n Of course, it is possible.

[0025] The lower laminate structure BST includes a first sub-lower laminate structure (BST_1) and a second sub-lower laminate structure (BST_2) on the first sub-lower laminate structure (BST_1). The first sub-lower stack structure (BST_1) includes a ground selection line GSL and some word lines (WL0 to WL k ) is included. The second sub-lower stack structure (BST_2) is connected to the remaining word lines (WL k+1 ~WL n ) and dummy word lines DWL. Here, n is a natural number greater than k. The word line WL located at the top of the first sub-lower stack structure BST_1 k and the word line WL located at the bottom of the second sub-lower stack structure (BST_2). k+1 A second inter-electrode insulating film 125 is disposed between them. The second inter-electrode insulating film 125 is formed to be thicker than the first inter-electrode insulating film 120 in the first sub-lower stack structure BST_1 and the second sub-lower stack structure BST_2.

[0026] The upper laminate structure UST is disposed on the lower laminate structure BST. The upper stack structure UST includes a first upper metal line SSL and a second upper metal line EL stacked in a vertical direction DR3. The first upper metal line SSL is disposed closer to the substrate 100 than the second upper metal line EL. The upper stack structure UST includes a first inter-electrode insulating film 120 disposed between the first upper metal line SSL and the second upper metal line EL. The first upper metal line SSL includes a first sub-upper metal line SSL1 and a second sub-upper metal line SSL2 disposed on the first sub-upper metal line SSL1.

[0027] The first inter-electrode insulating film 120 is disposed between the first sub-upper metal line SSL1 and the second sub-upper metal line SSL2. The second upper metal line EL includes a third sub-upper metal line EL1 and a fourth sub-upper metal line EL2 disposed on the third sub-upper metal line EL1. The first inter-electrode insulating film 120 is disposed between the third sub-upper metal line EL1 and the fourth sub-upper metal line EL2. The first upper metal line SSL serves as the string select line in FIG. 1, and the second upper metal line EL serves as the erase control line in FIG. The first upper metal line SSL is included in the string select transistor SST of FIG. 1, and the second upper metal line EL is included in the erase control transistor ET of FIG.

[0028] An inter-structure insulating film 126 is disposed between the lower surface of the first upper metal line SSL and the upper surface of the dummy word line DWL. The inter-structure insulating film 126 is formed to be thicker than the first inter-electrode insulating film 120 in the first lower stacked structure sub-layer (BST_1) and the second lower stacked structure sub-layer (BST_2). Lower Metallic Line (GSL, WL0~WL n , DWL), the first upper metal line SSL, and the second upper metal line EL comprise the same material. For example, the bottom metal line (GSL, WL0 to WL n , DWL), the first upper metal line SSL, and the second upper metal line EL have the same conductive film stack structure. For example, the bottom metal line (GSL, WL0 to WL n , DWL), the first upper metal line SSL, and the second upper metal line EL each include a barrier conductive film and a filling conductive film surrounded by the barrier conductive film.

[0029] The barrier conductive film may include at least one of a metal, a metal nitride, a metal carbonitride, and a two-dimensional (2D) material. For example, the two-dimensional material can be a metallic material and / or a semiconductor material. The 2D material may include a 2D allotrope or a 2D compound. The filling conductive film may include metals such as tungsten (W), cobalt (Co), and nickel (Ni), but the technical concept of the present invention is not limited thereto. The first and second inter-electrode insulating films 120 and 125 and the inter-structure insulating film 126 may include, for example, silicon oxide, but the technical concept of the present invention is not limited thereto.

[0030] The first cutting line WLC1 and the second cutting line WLC2 are disposed in the upper laminate structure UST and the lower laminate structure BST, respectively. The first cutting line WLC1 and the second cutting line WLC2 pass through the upper laminate structure UST and the lower laminate structure BST, respectively. The first cutting lines WLC1 and the second cutting lines WLC2 extend in a second direction DR2 different from the first direction DR1 to cut the upper laminate structure UST and the lower laminate structure BST. The second cutting line WLC2 is spaced apart from the first cutting line WLC1 in the first direction DR1. The first cutting line WLC1 and the second cutting line WLC2 are connected to the lower conductive lines (GSL, WL0 to WL n , DWL), the first upper conductive line SSL and the second upper conductive line EL are cut.

[0031] Each of the first cutting line WLC1 and the second cutting line WLC2 includes an insulating material. Each of the first cutting line WLC1 and the second cutting line WLC2 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material.

[0032] Examples of low dielectric constant materials include Fluorinated TetraEthylOrthoSilicate (FTEOS), Hydrogen SilsesQuioxane(HSQ), Bis-benzoCycloButene(BCB), TetraMethylOrthoSilicate(TMOS), OctaMethyleyCloTetraSiloxane(OMCTS), HexaMethylDiSiloxane(HMDS), TriMethylSilyl Borate(TMSB), DiAcetoxyDitertiaryButoSiloxane(DADBS), TriMethylSilil Polyimide nanofoams like Phosphate (TMSP), PolyTetraFluoroEthylene (PTFE), TOSZ (Tonen SilaZen), FSG (Fluoride Silicate Glass), polypropylene oxide, CDO (Carbon Doped silicon Oxide), OSG (Organo Silicate Glass), SiLK, Amorphous Fluorinated The material may include carbon, silica aerogels, silica xerogels, mesoporous silica, or a combination thereof, but the technical idea of ​​the present invention is not limited thereto.

[0033] The vertical structures VS are disposed between the first cutting line WLC1 and the second cutting line WLC2. The vertical structure VS extends in a vertical direction DR3. The vertical structure VS passes through the upper laminate structure UST and the lower laminate structure BST. At least a portion of the vertical structures VS extends into the horizontal conductive substrate 150 . The vertical structure VS includes a first portion disposed within the upper laminate structure UST and the second sub-lower laminate structure (BST_2) and a second portion disposed within the lower laminate structure BST. The width in the first direction DR1 of the lower surface of the first portion of the vertical structure VS may be smaller than the width in the first direction DR1 of the upper surface of the second portion of the vertical structure VS.

[0034] The vertical structures VS include a first vertical structure VS1 and a second vertical structure VS2. The first vertical structure VS1 is connected to the bit line BL through a bit line plug BLPG. The second vertical structure VS2 is not connected to the bit line BL. That is, the second vertical structure VS2 is a dummy vertical structure. The second vertical structure VS2 overlaps one of the first sub-cutting line SLC1 and the second sub-cutting line SLC2 in the vertical direction DR3. Seven vertical structures VS are arranged between the first cutting line WLC1 and the second cutting line WLC2, spaced apart from one another in the first direction DR1.

[0035] For example, two first vertical structures VS1 aligned in the first direction DR1 are disposed between the first cutting line WLC1 and the first sub-cutting line SLC1. A second vertical structure VS2 is disposed so as to overlap the first sub-cutting line SLC1 in the vertical direction DR3. Two first vertical structures VS1 aligned in the first direction DR1 are disposed between the first sub-cutting line SLC1 and the second sub-cutting line SLC2. Two first vertical structures VS1 aligned in the first direction DR1 are disposed between the second sub-cutting line SLC2 and the second cutting line WLC2.

[0036] As shown in FIG. 5, the vertical structure VS includes a channel film 130, a channel insulating film 132, and an insulating pattern 134 that extend in a vertical direction DR3. The channel film 130 is disposed along the sidewalls and bottom surface of the vertical structure VS. The channel film 130 is electrically connected to a horizontal conductive substrate 150 which serves as a common source line. The channel film 130 may include a semiconductor material such as, for example, silicon (Si), germanium (Ge), or a mixture thereof. Alternatively, the channel film 130 may include semiconductor materials such as metal oxide semiconductor materials, organic semiconductor materials, and carbon nanostructures. In some embodiments of the semiconductor memory device, the channel layer 130 may include polycrystalline silicon.

[0037] The insulating pattern 134 is disposed on the channel film 130 . The insulating pattern 134 may include, for example, at least one of silicon oxide, silicon oxynitride, and a low-k material, but the technical concept of the present invention is not limited thereto.

[0038] The channel insulating film 132 is disposed between the channel film 130 and the upper stacked structure UST, between the channel film 130 and the lower stacked structure BST, and between the channel film 130 and the horizontal conductive substrate 150. The channel insulating layer 132 includes, for example, a tunnel insulating layer 132 a, a charge storage layer 132 b, and a blocking insulating layer 132 c, which are sequentially disposed on the channel layer 130 . The tunnel insulating layer 132a, the charge storage layer 132b, and the blocking insulating layer 132c are merely examples, and the technical concept of the present invention is not limited thereto.

[0039] The tunnel insulating film 132a may include, for example, silicon oxide or a high-dielectric-constant material (eg, aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 )). The charge storage film 132b may include, for example, silicon nitride. The blocking insulating film 132c may include, for example, silicon oxide or a high-dielectric-constant material (eg, aluminum oxide (Al2O3), hafnium oxide (HfO2)). In some other embodiments, the tunnel insulating layer 132a and the blocking insulating layer 132c may include silicon oxide. The tunnel insulating layer 132 a , the charge storage layer 132 b , and the blocking insulating layer 132 c are separated below the channel layer 130 . The separated tunnel insulating layer 132 a, charge storage layer 132 b, and blocking insulating layer 132 c expose a portion of the channel layer 130 .

[0040] The vertical structure support layer 110 is disposed between the separated tunnel insulating layer 132a, charge storage layer 132b, and blocking insulating layer 132c. The vertical structure support film 110 electrically connects the horizontal conductive substrate 150 and the channel film 130 . The vertical structure support film 110 may include a semiconductor material such as, for example, silicon (Si), germanium (Ge), or a mixture thereof. In other embodiments, as shown in FIG. 6, the vertical structure support film 110 may not be disposed between the horizontal conductive substrate 150 and the lower stack structure BST. In this case, the sidewalls of the channel film 130 are not exposed, but the bottom of the channel film 130 is exposed. The tunnel insulating layer 132a, the charge storage layer 132b, and the blocking insulating layer 132c between the bottom of the channel layer 130 and the horizontal conductive substrate 150 are removed. The channel film 130 is electrically connected to the horizontal conductive substrate 150 via the bottom of the channel film 130 .

[0041] The bit line pads (BL_PAD) are disposed on the vertical structures VS. The bit line pad (BL_PAD) contacts the channel film 130, the channel insulating film 132, and the insulating pattern 134, respectively. The bit line pad (BL_PAD) includes a conductive material. For example, the bit line pad (BL_PAD) includes a semiconductor material doped with n-type impurities.

[0042] The first to fourth interlayer insulating films (141, 142, 143, 144) are sequentially disposed on the upper stacked structure UST. The bit line pad (BL_PAD) is disposed in the first interlayer insulating film 141 . The first cutting line WLC1 and the second cutting line WLC2 penetrate the first interlayer insulating film 141 and the second interlayer insulating film 142, respectively. The second interlayer insulating film 142 surrounds the side walls of the first cutting lines WLC1, the side walls of the second cutting lines WLC2, the side walls of the first sub-cutting lines SLC1, and the side walls of the first sub-cutting lines SLC2.

[0043] The third interlayer insulating film 143 surrounds the sidewalls of the upper supporters (TS1, TS2, TS3, TS4, TS5, and TS6), the sidewalls of the first sub-cutting lines SLC1, and the sidewalls of the first sub-cutting lines SLC2. The fourth interlayer insulating film 144 is disposed between each of the upper supporters TS1, TS2, TS3, TS4, TS5, and TS6 and the bit line BL. Each of the first to fourth interlayer insulating films (141, 142, 143, 144) may include at least one of silicon oxide, silicon oxynitride, and a low dielectric constant material, but the technical concept of the present invention is not limited thereto.

[0044] The bit line plug BLPG is disposed on the first vertical structure VS1. The bit line plugs BLPG are not disposed on the second vertical structures VS2. The bit line plugs BLPG penetrate the second to fourth interlayer insulating films (142, 143, 144). The bit lines BL are disposed on the upper stack structure UST. The bit lines BL extend in a first direction DR1. The bit line BL is electrically connected to at least one of the channel films 130 . The bit line BL is disposed on the fourth interlayer insulating film 144 . The bit line BL is electrically connected to a bit line pad (BL_PAD) via a bit line plug BLPG. Each of the bit lines BL and the bit line plugs BLPG includes a conductive material.

[0045] The two bit lines BL overlap in a third direction DR3 with the vertical structures VS spaced apart from each other in the first direction DR1, respectively. In this case, two bit lines BL disposed on a plurality of vertical structures VS spaced apart from each other in the first direction DR1 are spaced apart from each other in the second direction DR2. One of two bit lines BL arranged on the plurality of vertical structures VS spaced apart from each other in the first direction DR1 is connected to a part of the plurality of first vertical structures VS1 through a bit line plug BLPG. One of the remaining two bit lines BL arranged on the plurality of vertical structures VS spaced apart from each other in the first direction DR1 is connected to a portion of the remaining plurality of first vertical structures VS1 via a bit line plug BLPG.

[0046] A plurality of upper supporters (TS1, TS2, TS3, TS4, TS5, and TS6) are disposed on the first cutting line WLC1 and the second cutting line WLC2. Each of the upper supporters (TS1, TS2, TS3, TS4, TS5, and TS6) is disposed inside a recess R formed on the first cutting line WLC1 and the second cutting line WLC2. Each of the plurality of upper supporters (TS1, TS2, TS3, TS4, TS5, and TS6) is disposed in the third interlayer insulating film 143. That is, the recess R is formed inside the third interlayer insulating film 143.

[0047] For example, the first to third upper supporters (TS1, TS2, TS3) are disposed on the first cutting line WLC1. The first to third upper supporters (TS1, TS2, TS3) are spaced apart from each other in the second direction DR2. Although FIG. 2 shows that the first to third upper supporters TS1, TS2, and TS3 overlap the bit lines BL in the vertical direction DR3, the technical idea of ​​the present invention is not limited thereto.

[0048] The fourth to sixth upper supporters (TS4, TS5, TS6) are disposed on the second cutting line WLC2. The fourth to sixth upper supporters (TS4, TS5, TS6) are spaced apart from one another in the second direction DR2. Although FIG. 2 shows that the fourth to sixth upper supporters (TS4, TS5, TS6) overlap the bit lines BL in the vertical direction DR3, the technical idea of ​​the present invention is not limited thereto. Although Figure 2 shows that the planar shape of each of the multiple upper supporters (TS1, TS2, TS3, TS4, TS5, TS6) is circular, the shape of each of the multiple upper supporters (TS1, TS2, TS3, TS4, TS5, TS6) is not limited.

[0049] The upper surface TSa of the first upper supporter TS1 is formed on the same plane as the upper surface of the third interlayer insulating film 143. A first width W1 in the first direction DR1 of an upper surface WLC1a of the first cutting line WLC1 is smaller than a second width W2 in the first direction DR1 of a lower surface TSb of the first upper supporter TS1. At least a part of the lower surface TSb of the first upper supporter TS1 can be in contact with the upper surface 142a of the second interlayer insulating film 142. The first upper supporter TS1 may include an insulating material. The first upper supporter TS1 may contain the same material as the first cutting line WLC1. However, the technical idea of ​​the present invention is not limited to this. The first upper supporter TS1 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material.

[0050] The second to sixth upper supporters (TS2, TS3, TS4, TS5, and TS6) have a structure similar to that of the first upper supporter TS1. The first sub-cutting line SLC1 and the second sub-cutting line SLC2 are disposed between the first cutting line WLC1 and the second cutting line WLC2. The first cutting line WLC1, the first sub-cutting line SLC1, the second sub-cutting line SLC2, and the second cutting line WLC2 are spaced apart sequentially in the first direction DR1. The first sub-cutting line SLC1 and the second sub-cutting line SLC2 each extend in the second direction DR2. Two first vertical structures VS1 are arranged between the first cutting line WLC1, the first sub-cutting line SLC1, the second sub-cutting line SLC2, and the second cutting line WLC2, respectively, spaced apart from each other in the first direction DR1. However, the technical idea of ​​the present invention is not limited to this.

[0051] The first sub-cutting line SLC1 and the second sub-cutting line SLC2 cut the upper stacked structure UST and the first to third interlayer insulating films (141, 142, 143), respectively. At least a portion of the first sub-cutting line SLC1 extends inside the second vertical structure VS2. That is, at least a portion of the first sub-cutting line SLC1 overlaps with the second vertical structure VS2 in the vertical direction DR3. At least a portion of the second sub-cutting line SLC2 extends inside the second vertical structure VS2. That is, at least a portion of the second sub-cutting line SLC2 overlaps with the second vertical structure VS2 in the vertical direction DR3. The second vertical structures VS2 overlapping the first sub-cutting line SLC1 in the vertical direction DR3 are different vertical structures from the second vertical structures VS2 overlapping the second sub-cutting line SLC2 in the vertical direction DR3. The lower surface of the first sub-cutting line SLC1 is formed between the lower laminate structure BST and the upper laminate structure UST. That is, the lower surface of the first sub-cutting line SLC1 is formed inside the inter-structure insulating film 126. However, the technical idea of ​​the present invention is not limited to this.

[0052] The upper surface of the first sub-cutting line SLC1 is formed on the same plane as the upper surface TSa of the first upper supporter TS1. That is, the upper surfaces of the first sub-cutting lines SLC1, the upper surface TSa of the first upper supporter TS1, and the upper surface of the third interlayer insulating film 143 are formed on the same plane. The third width W31 in the first direction DR1 of the upper surface of the first sub-cutting line SLC1 is smaller than the fourth width W4 in the first direction DR1 of the uppermost surface of the second vertical structure VS2. The first sub-cutting line SLC1 is spaced apart from the channel film 130, for example. However, the technical idea of ​​the present invention is not limited to this. The height (h) of the first sub-cutting line SLC1 in the vertical direction DR3 may be, for example, 5000 Å to 10000 Å. The height (h) of the first sub-cutting line SLC1 in the vertical direction DR3 is set to a height (h) that completely separates the upper laminate structure UST in the vertical direction DR3.

[0053] In the semiconductor memory device according to an embodiment of the present invention, after forming the dummy vertical structure VS2 and the word line, the sub-cutting lines (SLC1, SLC2) are formed to overlap the dummy vertical structure VS2 in the vertical direction DR3, thereby reducing the process difficulty and manufacturing costs. When a semiconductor memory device is manufactured through this process, the upper surfaces of the sub cutting lines SLC1 and SLC2 are formed flush with the upper surfaces of the upper supporters TS1 formed on the cutting line WLC1.

[0054] Hereinafter, a semiconductor memory device according to another embodiment of the present invention will be described with reference to FIG. The following description will focus on the differences from the semiconductor memory device shown in FIGS. FIG. 8 is a layout diagram illustrating a semiconductor memory device according to another embodiment of the present invention. Referring to FIG. 8, in a semiconductor memory device according to another embodiment of the present invention, first to third sub-cutting lines SLC1, SLC2, and SLC3 are arranged between adjacent first and second cut lines WLC1 and WLC2. The first cutting line WLC1, the first sub-cutting line SLC1, the second sub-cutting line SLC2, the third sub-cutting line SLC3, and the second cutting line WLC2 are spaced apart sequentially in the first direction DR1. The first to third sub-cutting lines (SLC1, SLC2, SLC3) extend in the second direction DR2. Ten vertical structures VS are arranged between the first cutting line WLC1 and the second cutting line WLC2, spaced apart from one another in the first direction DR1.

[0055] For example, two first vertical structures VS1 aligned in the first direction DR1 are disposed between the first cutting line WLC1 and the first sub-cutting line SLC1. A second vertical structure VS2 is disposed so as to overlap the first sub-cutting line SLC1 in the vertical direction DR3. Two first vertical structures VS1 aligned in the first direction DR1 are disposed between the first sub-cutting line SLC1 and the second sub-cutting line SLC2. Two first vertical structures VS1 aligned in the first direction DR1 are disposed between the second sub-cutting line SLC2 and the third sub-cutting line SLC3. A second vertical structure VS2 is disposed so as to overlap the third sub-cutting line SLC3 in the vertical direction DR3. Two first vertical structures VS1 aligned in the first direction DR1 are disposed between the third sub-cutting line SLC3 and the second cutting line WLC2.

[0056] Hereinafter, a semiconductor memory device according to another embodiment of the present invention will be described with reference to FIG. The following description will focus on differences from the semiconductor memory device shown in FIGS. FIG. 9 is a layout diagram illustrating a semiconductor memory device according to another embodiment of the present invention. Referring to FIG. 9, in a semiconductor memory device according to another embodiment of the present invention, first to fourth sub-cutting lines (SLC1, SLC2, SLC3, SLC4) are arranged between adjacent first and second cut lines WLC1 and WLC2. The first cutting line WLC1, the first sub-cutting line SLC1, the second sub-cutting line SLC2, the third sub-cutting line SLC3, the fourth sub-cutting line SLC4, and the second cutting line WLC2 are spaced apart sequentially in the first direction DR1. The first to fourth sub-cutting lines (SLC1, SLC2, SLC3, SLC4) extend in the second direction DR2. Twelve vertical structures VS are arranged between the first cutting line WLC1 and the second cutting line WLC2, spaced apart from one another in the first direction DR1.

[0057] For example, two first vertical structures VS1 aligned in the first direction DR1 are disposed between the first cutting line WLC1 and the first sub-cutting line SLC1. A second vertical structure VS2 is disposed so as to overlap the first sub-cutting line SLC1 in the vertical direction DR3. Two first vertical structures VS1 aligned in the first direction DR1 are disposed between the first sub-cutting line SLC1 and the second sub-cutting line SLC2. Two first vertical structures VS1 aligned in the first direction DR1 are disposed between the second sub-cutting line SLC2 and the third sub-cutting line SLC3. A second vertical structure VS2 is disposed so as to overlap the third sub-cutting line SLC3 in the vertical direction DR3. Two first vertical structures VS1 aligned in the first direction DR1 are disposed between the third sub-cutting line SLC3 and the fourth sub-cutting line SLC4. Two first vertical structures VS1 aligned in the first direction DR1 are disposed between the fourth sub-cutting line SLC4 and the second cutting line WLC2.

[0058] Hereinafter, a semiconductor memory device according to another embodiment of the present invention will be described with reference to FIG. The following description will focus on the differences from the semiconductor memory device shown in FIGS. FIG. 10 is a layout diagram illustrating a semiconductor memory device according to another embodiment of the present invention. Referring to FIG. 10, in a semiconductor memory device according to another embodiment of the present invention, three bit lines BL overlap in a third direction DR3 with a plurality of vertical structures VS spaced apart from each other in a first direction DR1.

[0059] One of three bit lines BL arranged on the plurality of vertical structures VS spaced apart from each other in the first direction DR1 is connected to a part of the plurality of first vertical structures VS1 through a bit line plug BLPG. Another one of the three bit lines BL arranged on the plurality of vertical structures VS spaced apart from each other in the first direction DR1 is connected to another part of the plurality of first vertical structures VS1 through a bit line plug BLPG. One of the remaining three bit lines BL arranged on the plurality of vertical structures VS spaced apart from each other in the first direction DR1 is connected to a remaining part of the plurality of first vertical structures VS1 through a bit line plug BLPG.

[0060] Hereinafter, a semiconductor memory device according to another embodiment of the present invention will be described with reference to FIG. The following description will focus on the differences from the semiconductor memory device shown in FIGS. FIG. 11 is a cross-sectional view illustrating a semiconductor memory device according to another embodiment of the present invention. Referring to FIG. 11, in a semiconductor memory device according to another embodiment of the present invention, the sub-cut lines SLC21 and SLC22 are misaligned with the second vertical structures VS2. For example, the center of the first sub-cutting line SLC21 does not coincide with the second vertical structure VS2. The first sub-cutting line SLC21 overlaps the channel film 130 of the second vertical structure VS2 in the vertical direction DR3. For example, at least a portion of the lower surface of the first sub-cutting line SLC21 that contacts the second vertical structure VS2 in the first direction DR1 contacts the inter-structure insulating film 126. However, the technical idea of ​​the present invention is not limited to this.

[0061] Hereinafter, a semiconductor memory device according to another embodiment of the present invention will be described with reference to FIG. The following description will focus on the differences from the semiconductor memory device shown in FIGS. FIG. 12 is a cross-sectional view illustrating a semiconductor memory device according to another embodiment of the present invention. Referring to FIG. 12, in a semiconductor memory device according to another embodiment of the present invention, the sub-cutting lines SLC31 and SLC32 contact the channel layer 130 formed on both sidewalls of the second vertical structure VS2. The first sub-cutting line SLC31 overlaps the channel film 130 formed on both side walls of the second vertical structure VS2 in the vertical direction DR3. For example, the width of the upper surface of the first sub-cutting line SLC31 in the first direction DR1 is substantially the same as the width (W4 in FIG. 3) of the top surface of the second vertical structure VS2. However, the technical idea of ​​the present invention is not limited to this.

[0062] Hereinafter, a semiconductor memory device according to another embodiment of the present invention will be described with reference to FIG. The following description will focus on the differences from the semiconductor memory device shown in FIGS. FIG. 13 is a cross-sectional view illustrating a semiconductor memory device according to another embodiment of the present invention. Referring to FIG. 13, in a semiconductor memory device according to another embodiment of the present invention, the width of the sub-cutting lines SLC41 and SLC42 in the first direction DR1 is greater than the width of the second vertical structures VS2. For example, the width W32 in the first direction DR1 of the upper surface of the first sub-cutting line SLC41 is greater than the width (W4 in FIG. 3) of the top surface of the second vertical structure VS2. The first sub-cutting line SLC41 overlaps the channel film 130 formed on both side walls of the second vertical structure VS2 in the vertical direction DR3. At least a portion of the lower surface of the first sub-cutting line SLC41 that contacts the second vertical structure VS2 in the first direction DR1 contacts the inter-structure insulating film 126.

[0063] Hereinafter, a semiconductor memory device according to another embodiment of the present invention will be described with reference to FIG. The following description will focus on the differences from the semiconductor memory device shown in FIGS. FIG. 14 is a cross-sectional view illustrating a semiconductor memory device according to another embodiment of the present invention. Referring to FIG. 14, in a semiconductor memory device according to another embodiment of the present invention, the first cutting line WLC71, the second cutting line WLC72, and the upper supporters TS71 and TS74 are each formed of a double film.

[0064] For example, the first cutting line WLC71, the second cutting line WLC72, the first upper supporter TS71, and the fourth upper supporter TS74 each include a spacer 761 and a plug pattern 762. The plug pattern 762 passes through the upper stack structure UST and the lower stack structure BST to connect to the impurity region 750 disposed inside the substrate 700 . The plug pattern 762 may include, for example, a conductive material. The impurity region 750 extends, for example, in the second direction DR2. The spacers 761 extend along the sidewalls of the plug pattern 762 .

[0065] The spacer 761 may include an insulating material. Therefore, the plug pattern 762 is formed by the lower metal lines (GSL, WL0 to WL1) of the upper stack structure UST and the lower stack structure BST. n , DWL), the first upper metal line SSL, and the second upper metal line EL. For example, the spacer 761 disposed on the first cutting line WLC71 and the first upper supporter TS71 may be integrally formed. In addition, the first cutting line WLC71 and the plug pattern 762 disposed on the first upper supporter TS71 may be integrally formed.

[0066] Hereinafter, a semiconductor memory device according to another embodiment of the present invention will be described with reference to FIG. The following description will focus on the differences from the semiconductor memory device shown in FIGS. FIG. 15 is a cross-sectional view illustrating a semiconductor memory device according to another embodiment of the present invention. Referring to FIG. 15, in a semiconductor memory device according to another embodiment of the present invention, an upper stack structure UST8 includes one first upper metal line SSL8 and one second upper metal line EL8. The first upper metal line SSL8 is disposed on the inter-structure dielectric film 126. A second upper metal line EL8 is disposed on the first upper metal line SSL8. The first inter-electrode insulating film 120 is disposed between the first upper metal line SSL8 and the second upper metal line EL8. The first sub-cutting line SLC81 and the second sub-cutting line SLC82 each cut the upper laminated structure UST8. The lower surfaces of the first sub-cutting lines SLC81 and the second sub-cutting lines SLC82 are formed inside the inter-structure insulating film 126.

[0067] Hereinafter, a semiconductor memory device according to another embodiment of the present invention will be described with reference to FIG. The following description will focus on the differences from the semiconductor memory device shown in FIGS. FIG. 16 is a cross-sectional view illustrating a semiconductor memory device according to another embodiment of the present invention. Referring to FIG. 16, in a semiconductor memory device according to another embodiment of the present invention, an upper stack structure UST9 includes one first upper metal line SSL9. The first upper metal line SSL9 is disposed on the inter-structure insulating film 126. For example, the first thickness t1 in the vertical direction DR3 of the first upper metal line SSL9 is greater than the second thickness t2 in the vertical direction DR3 of the lower metal line. The first sub-cutting line SLC91 and the second sub-cutting line SLC92 each cut the upper laminated structure UST9. The lower surfaces of the first sub-cutting lines SLC91 and the second sub-cutting lines SLC92 are formed inside the inter-structure insulating film 126.

[0068] Hereinafter, a semiconductor memory device according to another embodiment of the present invention will be described with reference to FIG. The following description will focus on the differences from the semiconductor memory device shown in FIGS. FIG. 17 is a cross-sectional view illustrating a semiconductor memory device according to another embodiment of the present invention. Referring to FIG. 17, in a semiconductor memory device according to another embodiment of the present invention, a peripheral circuit region is disposed below a substrate 100. Specifically, a semiconductor device according to another embodiment of the present invention includes a peripheral circuit substrate 1000 , a transistor 1001 , a plurality of wirings 1002 , and a fifth interlayer insulating film 1005 . The peripheral circuit board 1000 is disposed below the substrate 100 . The transistor 1001 is disposed on a peripheral circuit board 1000 . The fifth interlayer insulating film 1005 is disposed between the peripheral circuit board 1000 and the substrate 100 . A plurality of wirings 1002 are disposed inside a fifth interlayer insulating film 1005 and are electrically connected to the transistor 1001 .

[0069] Hereinafter, a semiconductor memory device according to another embodiment of the present invention will be described with reference to FIG. The following description will focus on the differences from the semiconductor memory device shown in FIGS. FIG. 18 is a cross-sectional view illustrating a semiconductor memory device according to another embodiment of the present invention. Referring to FIG. 18, in a semiconductor memory device according to another embodiment of the present invention, a peripheral circuit region is disposed on a bit line BL. The peripheral circuit region shown in FIG. 18 has a structure obtained by inverting the peripheral circuit region shown in FIG. Specifically, the semiconductor device according to another embodiment of the present invention includes a peripheral circuit substrate 1100, a transistor 1101, a plurality of wirings 1102, a fifth interlayer insulating film 1105, and a connecting line 1180.

[0070] The peripheral circuit board 1100 is disposed above the bit lines BL. The transistor 1101 is disposed on a peripheral circuit board 1100 . A fifth interlayer insulating film 1105 is disposed between the peripheral circuit substrate 1100 and the bit line BL. A plurality of wirings 1102 are disposed inside a fifth interlayer insulating film 1105 and are electrically connected to the transistor 1101 . The connection line 1180 is disposed between the bit line BL and the fifth interlayer insulating film 1105 . The connecting line 1180 may provide electrical connection between the bit line BL and the plurality of wirings 1102 .

[0071] Hereinafter, a semiconductor memory device according to another embodiment of the present invention will be described with reference to FIG. The following description will focus on the differences from the semiconductor memory device shown in FIGS. FIG. 19 is a cross-sectional view illustrating a semiconductor memory device according to another embodiment of the present invention. Referring to FIG. 19, a semiconductor memory device according to another embodiment of the present invention includes a lower stack structure BST12 having a plurality of lower metal lines (GSL, WL0 to WL12) stacked in a vertical direction DR3. n , DWL) and a plurality of first inter-electrode insulating films 120. The first inter-electrode insulating film 120 includes lower metal lines (GSL, WL0 to WL1) spaced apart in a vertical direction DR3. n , DWL). For example, the sidewalls of the first vertical structure VS1 have a constant slope profile. That is, the width of the first vertical structure VS1 in the first direction DR1 gradually decreases as it moves away from the bit line pad BL_PAD. The sidewalls of the second vertical structure VS2 have a similar structure to the sidewalls of the first vertical structure VS1.

[0072] Hereinafter, a method for manufacturing a semiconductor memory device according to an embodiment of the present invention will be described with reference to FIGS. 20 to 29 are views illustrating intermediate steps for explaining a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. 20 and 21, a horizontal conductive layer 150 and a replacement insulating layer RP are sequentially formed on a substrate 100. As shown in FIG.

[0073] Subsequently, a part of the lower mold film (MS_B) including the first inter-electrode insulating film 120, the second inter-electrode insulating film 125, and the lower sacrificial film SC1 is formed on the alternative insulating film RP. Specifically, the first inter-electrode insulating film 120 and the lower sacrificial film SC1 are alternately stacked on the alternative insulating film RP. A part of the second inter-electrode insulating film 125 is formed on the lower sacrificial film SC1. Subsequently, a part of the channel hole CH penetrating a part of the lower mold film (MS_B) in the vertical direction DR3 is formed. The sacrificial pattern can fill the inside of a part of the channel hole CH. Subsequently, the remaining part of the second inter-electrode insulating film 125 is formed on a part of the lower mold film (MS_B). The remaining part of the lower mold film (MS_B) is formed on the second inter-electrode insulating film 125 . The remaining portion of the lower mold layer (MS_B) includes a lower sacrificial layer SC1 and a first inter-electrode insulating layer 120 that are alternately stacked.

[0074] Subsequently, an inter-structure insulating film 126, an upper mold film (MS_U), and a first interlayer insulating film 141 are sequentially formed on the lower mold film (MS_B). The upper mold layer (MS_U) includes upper sacrificial layers SC2 and first inter-electrode insulating layers 120 that are alternately stacked. Subsequently, the remaining part of the channel hole CH is formed, which penetrates the first interlayer insulating film 141, the upper mold film (MS_U), the inter-structure insulating film 126, and the remaining part of the lower mold film (MS_B) in the vertical direction DR3. The remaining part of the channel hole CH overlaps in the vertical direction DR3 with the part of the channel hole CH formed inside the lower mold film (MS_B). Subsequently, the sacrificial pattern formed in a part of the channel hole CH is removed to form the channel hole CH.

[0075] Referring to FIG. 22, a first vertical structure VS1, a second vertical structure VS2, and a bit line pad BL_PAD are formed inside the channel hole CH. Specifically, a channel insulating film (reference numeral 132 in FIG. 5), a channel film 130, and an insulating pattern 134 are formed inside the channel hole CH. Subsequently, a bit line pad (BL_PAD) is formed on the channel insulating film (132 in FIG. 5), the channel film 130, and the insulating pattern 134 inside the channel hole CH.

[0076] Referring to FIGS. 23 and 24, a second interlayer insulating film 142 is formed on a first interlayer insulating film 141. Subsequently, a first cutting line trench (WLC_H1) and a second cutting line trench (WLC_H2) are formed. The second cutting line trench WLC_H2 is spaced apart from the first cutting line trench WLC_H1 in the first direction DR1. The first cutting line trench WLC_H1 and the second cutting line trench WLC_H2 each extend in a second direction DR2.

[0077] Subsequently, a third interlayer insulating film 143 is formed on the second interlayer insulating film 142 . In another embodiment, the first cutting line trench (WLC_H1) and the second cutting line trench (WLC_H2) may be formed after the second interlayer insulating film 142 and the third interlayer insulating film 143 are formed. Subsequently, a plurality of recesses R are formed inside the third interlayer insulating film 143 . The recesses R overlap the first cutting line trench (WLC_H1) and the second cutting line trench (WLC_H2) in the vertical direction DR3. For example, the width of the recess R in the first direction DR1 is greater than the width of the first cutting line trench WLC_H1 in the first direction DR1.

[0078] Referring to FIG. 25, the lower sacrificial layer SC1 and the upper sacrificial layer SC2 are removed. In the space where the lower sacrificial film SC1 is removed, lower metal lines (GSL, WL0 to WL n , DWL). In addition, a first upper metal line SSL and a second upper metal line EL are formed in the space where the upper sacrificial layer SC2 has been removed. In other words, the lower sacrificial film SC1 and the upper sacrificial film SC2 are formed as lower metal lines (GSL, WL0 to WL1) by the replacement metal gate process. n , DWL), a first upper metal line SSL, and a second upper metal line EL. The alternative insulating film RP is removed. In the space where the alternative insulating film RP has been removed, a vertical structure supporting film 110 is formed.

[0079] Referring to FIGS. 26 and 27, a first cutting line WLC1 is formed inside the first cutting line trench WLC_H1. In addition, a second cutting line WLC2 is formed inside the second cutting line trench WLC_H2. For example, the first upper supporter TS1 is formed inside the recess R formed on the first cutting line trench WLC_H1. Also, a fourth upper supporter TS4 is formed inside the recess R formed on the second cutting line trench WLC_H2. The first cutting lines WLC1, the second cutting lines WLC2, and the upper supporters (TS1, TS4) are formed, for example, by the same process. However, the technical idea of ​​the present invention is not limited to this.

[0080] Referring to Figures 28 and 29, a first sub-cutting line SLC1 and a second sub-cutting line SLC2 are formed through the third interlayer insulating film 143, the second interlayer insulating film 142, the first interlayer insulating film 141, and the upper stack structure UST in the vertical direction DR3. The first and second sub-cutting lines SLC1 and SLC2 extend into the inter-structure insulating film 126, respectively. The first sub-cutting line SLC1 and the second sub-cutting line SLC2 are formed between the first cut line WLC1 and the second cut line WLC2. The first sub-cutting line SLC1 and the second sub-cutting line SLC2 each extend in the second direction DR2. The second sub-cutting line SLC2 and the first sub-cutting line SLC1 are spaced apart in the first direction DR1. The first sub-cutting line SLC1 and the second sub-cutting line SLC2 each overlap the second vertical structure VS2 in the vertical direction DR3.

[0081] Referring to FIG. 3, a fourth interlayer insulating film 144 is formed on the third interlayer insulating film 143 . A bit line plug BLPG connected to the first vertical structure VS1 is formed. The bit lines BL extending in the first direction DR1 are formed on the fourth interlayer insulating layer 144, thereby completing the semiconductor memory device shown in FIG.

[0082] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0083] 100 boards 110 Vertical Structure Support Membrane 120, 125 (first, second) inter-electrode insulating film 126 Inter-structure insulating film 130 Channel Membrane 132 Channel insulating film 132a Tunnel insulating film 132b Charge storage film 132c Blocking insulating film 134 Insulation Pattern 141, 142, 143, 144 (1st to 4th) interlayer insulating films 150 horizontal conductive substrate BST lower laminate structure BL Bit Line BL_PAD Bit Line Pad BLPG bit line plug BST lower laminate structure BST_1, BST_2 (1st, 2nd) sub-lower laminated structure DWL Dummy Word Line EL Second upper metallic line EL1, EL2 (3rd, 4th) sub-upper metallic lines GSL Ground Select Line UST upper laminate structure VS vertical structure VS1, VS2 (1st, 2nd) vertical structure SLC1, SLC2 (1st, 2nd) sub-cutting lines SSL 1st upper metallic line SSL1, SSL2 (1st, 2nd) sub-upper metallic lines TS1, TS2, TS3, TS4, TS5, TS6 (1st to 6th) upper supporters WLC1, WLC2 (1st, 2nd) cutting lines WL0~WL k Word Line

Claims

1. a lower stack structure including a plurality of vertically stacked lower metal lines extending in a first direction on the substrate; an upper laminate structure disposed on the lower laminate structure and including at least one upper metal line; at least one vertical structure including a channel film extending through the upper stacked structure and the lower stacked structure in the vertical direction; a first cutting line for cutting the upper laminated structure and the lower laminated structure; a recess formed on the first cutting line; an upper supporter disposed inside the recess on the first cutting line; a second cutting line that cuts the upper laminated structure and the lower laminated structure and is spaced apart from the first cutting line in the first direction; at least one sub-cutting line that cuts the upper laminate structure and at least a portion of which overlaps with the at least one vertical structure in the vertical direction and is disposed between the first cutting line and the second cutting line; a first interlayer insulating film surrounding a sidewall of the upper supporter and a sidewall of the at least one sub-cutting line; a second interlayer insulating film disposed between an uppermost surface of the at least one vertical structure and a lower surface of the first interlayer insulating film; an upper surface of the upper supporter is formed on the same plane as an upper surface of the at least one sub-cutting line; the second interlayer insulating film surrounds a sidewall of the first cutting line, a sidewall of the second cutting line, and a sidewall of the at least one sub-cutting line; a second interlayer insulating film formed on the second supporter and having a first insulating film formed on the second interlayer insulating film;

2. a third interlayer insulating film disposed on the first interlayer insulating film and the upper surface of the upper supporter; 2. The semiconductor memory device of claim 1, further comprising a bit line extending in the first direction on the third interlayer insulating film and spaced apart from the upper supporter in the vertical direction.

3. The at least one vertical structure includes a first vertical structure connected to the bit line; 3. The semiconductor memory device of claim 2, further comprising: a second vertical structure not connected to the bit line and vertically overlapping the at least one sub-disconnect line.

4. the at least one vertical structure includes a plurality of vertical structures; The at least one sub-cutting line includes a first sub-cutting line spaced apart from the first cutting line in the first direction; a second sub-cutting line spaced apart from the first sub-cutting line in the first direction; 2. The semiconductor memory device of claim 1, wherein at least two of the plurality of vertical structures are disposed between the first sub-cutting line and the second sub-cutting line and spaced apart from each other in the first direction.

5. the at least one sub-cutting line further includes a third sub-cutting line spaced apart from the second sub-cutting line in the first direction; 5. The semiconductor memory device of claim 4, wherein at least two of the plurality of vertical structures are disposed between the second sub-cutting line and the third sub-cutting line and spaced apart from each other in the first direction.

6. 2. The semiconductor memory device of claim 1, wherein a lower surface of the at least one sub-cut line is formed between the lower stack structure and the upper stack structure.

7. 2. The semiconductor memory device of claim 1, wherein the vertical height of the at least one sub-cut line is between 5,000 Å and 10,000 Å.

8. 2. The semiconductor memory device of claim 1, wherein the at least one sub-cut line overlaps the channel layer in the vertical direction.

9. 2. The semiconductor memory device of claim 1, wherein a first width in the first direction of an upper surface of the first cutting line is smaller than a second width in the first direction of a lower surface of the upper supporter.

10. 2. The semiconductor memory device of claim 1, wherein a third width in the first direction of an upper surface of the at least one sub-cut line is greater than a fourth width in the first direction of an uppermost surface of the at least one vertical structure.

11. 2. The semiconductor memory device of claim 1, wherein the at least one upper metal line comprises a first upper metal line and a second upper metal line disposed on the first upper metal line.

12. the first upper metal line includes a first sub-upper metal line and a second sub-upper metal line disposed on the first sub-upper metal line; 12. The semiconductor memory device of claim 11, wherein the second upper metal line includes a third sub-upper metal line and a fourth sub-upper metal line disposed on the third sub-upper metal line.

13. a lower stack structure including a plurality of vertically stacked lower metal lines extending in a first direction on the substrate; an upper laminate structure disposed on the lower laminate structure and including at least one upper metal line; at least one vertical structure including a channel film extending through the upper stacked structure and the lower stacked structure in the vertical direction; a first cutting line for cutting the upper laminated structure and the lower laminated structure; a first upper supporter disposed on the first cutting line; a second upper supporter disposed on the first cutting line and spaced apart from the first upper supporter in a second direction different from the first direction; cutting the upper laminated structure, at least one sub-cutting line at least partially overlapping with the at least one vertical structure in the vertical direction and spaced apart from the first cutting line in the first direction; a first interlayer insulating film surrounding a sidewall of the first upper supporter and a sidewall of the at least one sub-cutting line; a second interlayer insulating film disposed between a top surface of the at least one vertical structure and a bottom surface of the first interlayer insulating film; an upper surface of the first upper supporter is formed on the same plane as an upper surface of the at least one sub-cutting line; the second interlayer insulating film surrounds a sidewall of the first cutting line and a sidewall of the at least one sub-cutting line; a first upper supporter having a lower surface that is in contact with an upper surface of the second interlayer insulating film;

14. a third interlayer insulating film disposed on an upper surface of the first upper supporter; a bit line extending in the first direction on the third interlayer insulating film and spaced apart from the first upper supporter in the vertical direction; The at least one vertical structure includes a first vertical structure connected to the bit line; 14. The semiconductor memory device of claim 13, further comprising: a second vertical structure not connected to the bit line and vertically overlapping the at least one sub-disconnect line.

15. the at least one vertical structure includes a plurality of vertical structures; The at least one sub-cutting line includes a first sub-cutting line spaced apart from the first cutting line in the first direction; a second sub-cutting line spaced apart from the first sub-cutting line in the first direction; 14. The semiconductor memory device of claim 13, wherein at least two of the plurality of vertical structures are disposed between the first sub-cutting line and the second sub-cutting line and spaced apart from each other in the first direction.

16. 14. The semiconductor memory device of claim 13, wherein a lower surface of the at least one sub-cut line is formed between the lower stack structure and the upper stack structure.

17. 14. The semiconductor memory device of claim 13, wherein a first width in the first direction of an upper surface of the first cutting line is smaller than a second width in the first direction of a lower surface of the first upper supporter.

18. 14. The semiconductor memory device of claim 13, wherein the first vertical thickness of the at least one upper metal line is greater than the second vertical thickness of the lower metal line.

19. A substrate; a horizontal conductive substrate disposed on the substrate; a lower stack structure including a plurality of lower metal lines extending in a first direction on the horizontal conductive substrate and stacked vertically; an upper laminate structure disposed on the lower laminate structure and including at least one upper metal line; a vertical structure including a channel film extending through the upper stacked structure and the lower stacked structure in the vertical direction and electrically connected to the horizontal conductive substrate; a first cutting line that cuts the upper laminate structure and the lower laminate structure and has a first width in the first direction; a first upper supporter disposed on the first cutting line and having a second width in the first direction greater than the first width; a second upper supporter disposed on the first cutting line, having the second width in the first direction, and spaced apart from the first upper supporter in a second direction different from the first direction; a second cutting line that cuts the upper laminated structure and the lower laminated structure and is spaced apart from the first cutting line in the first direction; a sub-cutting line for cutting the upper laminated structure, the sub-cutting line at least partially overlapping the vertical structure in the vertical direction, and being disposed between the first cutting line and the second cutting line; a first interlayer insulating film disposed on the vertical structure and surrounding each of the sidewalls of the first cutting line, the sidewalls of the second cutting line, and the sidewalls of the sub-cutting line; a second interlayer insulating film disposed on the first interlayer insulating film and surrounding a sidewall of the first upper supporter and a sidewall of the sub cutting line; a bit line extending in the first direction on the second interlayer insulating film, an upper surface of the first upper supporter is formed on the same plane as an upper surface of the sub-cutting line; At least a portion of a lower surface of the first upper supporter contacts an upper surface of the first interlayer insulating film.

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