Silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device that has high dielectric breakdown resistance and superior switching characteristics and can be prevented from increasing in cost.SOLUTION: In an intermediate region 3 rectangularly surrounding a circumference of an active region 1, a gate polysilicon wiring layer 62 is provided on a gate insulation film 38 on a top surface of a semiconductor substrate 10 with a field oxide film 61 interposed. An inside part 62b of the gate polysilicon wiring layer 62 faces a p-type region in a front surface region on the top surface of the semiconductor substrate 10 via only the gate insulation film 38. At a part of the intermediate region 3 which faces a corner 1a of the active region 1, a low carrier lifetime region 71 formed by introducing a carrier lifetime killer is provided in a manner to overlap with the p-type region and face the gate polysilicon wiring layer 62 in a depth direction, so that the minority carrier lifetime of the corner part of the intermediate region 3 is shorter than the minority carrier lifetime of a linear part of the intermediate region 3.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a silicon carbide semiconductor device. [Background technology]

[0002] Conventionally, a well-known silicon carbide semiconductor device using silicon carbide (SiC) as a semiconductor material is a SiC-MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS-type field effect transistor with an insulated gate having a three-layer structure of metal-oxide-semiconductor). In a SiC-MOSFET, a gate insulating film extends from the active region onto the front surface of a semiconductor substrate in an intermediate region between the active region and the edge termination region, and a gate runner is provided on this gate insulating film via a field oxide film.

[0003] The active region is where the SiC-MOSFET unit cells (the constituent elements of the device) are located and where the main current (drift current) flows. The intermediate region surrounds the periphery of the active region. Gate runners, gate pads, sense pads, etc. are located in the intermediate region, but no SiC-MOSFET unit cells are located there. The gate runners have the function of transmitting potential changes on the gate pads (electrode pads) to the gate electrodes of each unit cell in the active region. The sense pads are electrode pads for circuits such as current sensing, temperature sensing, and overvoltage protection, which protect and control the unit cells in the active region.

[0004] The structure of a conventional silicon carbide semiconductor device will be described. Fig. 11 is a plan view showing a portion of the layout of a conventional silicon carbide semiconductor device as viewed from the front surface side of the semiconductor substrate. Fig. 11 shows the vicinity of a corner (vertex) 201a of an active region 201. Figs. 12 and 13 are cross-sectional views showing cross-sectional structures taken along line AA-AA' and line BB-BB' in Fig. 11, respectively. A conventional silicon carbide semiconductor device 230 shown in Figs. 11 to 13 is a vertical SiC-MOSFET with a trench gate structure, which includes a semiconductor substrate (semiconductor chip) 210 made of SiC, an active region 201, and an edge termination region 202 surrounding the periphery of the active region 201.

[0005] The semiconductor substrate 210 is made of SiC. + On the starting substrate 211 - The epitaxial layers 212, 213 that become the p-type drift region 232 and the p-type base region 234 are epitaxially grown in this order. The semiconductor substrate 210 has a main surface on the side of the p-type epitaxial layer 213 as the front surface, and an n-type + The main surface on the mold starting substrate 211 side is referred to as the backside. The active region 201 is the region through which the main current (drift current) flows when the MOSFET is on, and multiple unit cells of the MOSFET, each with the same structure, are arranged adjacent to one another. The active region 201 has a roughly rectangular planar shape and is located approximately in the center of the semiconductor substrate 210 (chip center).

[0006] A typical trench gate structure is provided on the front surface side of the semiconductor substrate 210 in the active region 201. The trench gate structure includes a p-type base region 234, an n-type + Type source region 235, p ++ The intermediate region 203 is composed of a contact region 236, a gate trench 237, a gate insulating film 238, and a gate electrode 239. The gate trench 237 extends linearly in a first direction X (longitudinal direction) parallel to the front surface of the semiconductor substrate 210 and terminates in the intermediate region 203. A plurality of the gate trenches 237 are arranged in stripes adjacent to each other in a second direction Y (transverse direction) parallel to the front surface of the semiconductor substrate 210 and perpendicular to the first direction X.

[0007] The gate trenches 237 are arranged adjacent to each other in the second direction Y, so that a plurality of unit cells having the same structure are arranged adjacent to each other in the second direction Y. The gate insulating film 238 is provided along the inner wall of the gate trench 237 and extends from the inner wall of the gate trench 237 onto the front surface of the semiconductor substrate 210. The gate insulating film 238 reaches on the front surface of the semiconductor substrate 210 from the active region 201 to the chip edge. The gate electrode 239 is provided inside the gate trench 237 on the gate insulating film 238 so as to fill the inside of the gate trench 237.

[0008] The gate electrode 239 is connected to a gate polysilicon (poly-Si) wiring layer 262 (described later) at a longitudinal end of the gate trench 237. The interlayer insulating film 240 is provided on a gate insulating film 238 on the front surface of the semiconductor substrate 210 over the entire front surface of the semiconductor substrate 210 so as to cover the gate electrode 239, the gate polysilicon wiring layer 262, and the field oxide film 261. The active region 201 is provided with contact holes 240a and 240b that penetrate the interlayer insulating film 240 and the gate insulating film 238 in the depth direction Z and reach the front surface of the semiconductor substrate 210.

[0009] The contact holes 240a and 240b in the active region 201 extend in a stripe shape in the first direction X. The outermost contact hole 240b in the active region 201 is provided further outward in the second direction Y than the outermost gate trench 237, and the entire area thereof is covered with a p ++ The other contact holes 240a in the active region 201 are provided between adjacent gate trenches 237, exposing the n-type contact extensions 236a. + type source region 235 and p ++ The contact region 236 is exposed, and the end portion in the first direction X (longitudinal direction) is p ++ The mold contact extension 236a is exposed.

[0010] The intermediate region 203 between the active region 201 and the edge termination region 202 is adjacent to the active region 201 and surrounds the periphery of the active region 201 in a substantially rectangular shape. In the intermediate region 203, a p ++ A contact extension 236a is provided. ++ The contact extension 236a is p ++ The portion of the contact region 236 that extends to the intermediate region 203. ++ The p-type contact extension 236a is provided over the entire area between the front surface of the semiconductor substrate 210 and the p-type base extension 234a.

[0011] p ++ The p-type contact extension 236a is exposed throughout the entire area of ​​the outermost contact hole 240b of the active region 201. The p-type base extension 234a is a portion of the p-type base region 234 that extends to the intermediate region 203. The p-type base extension 234a and the n - Between the p-type drift region 232 + A mold extension 252a is provided. + The p-type base extension 252a, the p-type base extension 234a, and the p-type ++ The mold contact extension 236a surrounds the periphery of the active region 201, is provided over the entire area of ​​the intermediate region 203, and extends from the intermediate region 203 inward (toward the center of the chip) to the gate trench 237.

[0012] Gate insulating film 238 on the front surface of semiconductor substrate 210 is provided across the entire intermediate region 203 and edge termination region 202. In intermediate region 203, a gate polysilicon wiring layer 262 and a gate metal wiring layer 263, which serve as gate runners, are stacked in this order on gate insulating film 238 on the front surface of semiconductor substrate 210, with field oxide film 261 interposed therebetween. Inner end 261a of field oxide film 261 is located outward from the boundary between active region 201 and intermediate region 203 (the longitudinal ends of contact holes 240a and 240b and the outer sidewall of contact hole 240b) around the entire outer periphery of active region 201.

[0013] The gate polysilicon wiring layer 262 is provided on the field oxide film 261 and surrounds the active region 201. The gate polysilicon wiring layer 262 extends inward beyond an inner end 261a of the field oxide film 261 and terminates on a gate insulating film 238 on the front surface of the semiconductor substrate 210 in the intermediate region 203. Therefore, an inner portion 262b of the gate polysilicon wiring layer 262 faces the semiconductor substrate 210 in the depth direction Z, interposed only by the gate insulating film 238, which is thinner than the field oxide film 261. The field oxide film 261 and the gate polysilicon wiring layer 262 are covered with an interlayer insulating film 240.

[0014] Reference numerals 241, 242, and 222 denote a source electrode, a passivation film, and an n + The reference numeral 233 denotes an n-type channel stopper region. The reference numerals 251 and 252 denote p-type current diffusion regions for alleviating the electric field in the gate insulating film 238 at the bottom of the gate trench 237. + is a type domain. + The mold extension portion 252a is a p-type extension portion between adjacent gate trenches 237. + The reference numeral 262a denotes an inner end portion of the gate polysilicon wiring layer 262. The reference numeral 221 denotes a p-type wiring layer 221 that constitutes the breakdown voltage withstanding structure 220 of the edge termination region 202. - It is a type domain.

[0015] In the conventional silicon carbide semiconductor device 230 (SiC-MOSFET), there are a plurality of parasitic capacitances (gate-source capacitance Cgs, gate-drain capacitance Cgd, drain hmm· sauce between The electrons and holes accumulated inside the semiconductor substrate along the parasitic capacitance when the SiC-MOSFET is on or off are discharged to the outside through the drain electrode 243 and the source electrode 241, respectively, during the switching transition from on to off or from off to on of the SiC-MOSFET or during reverse recovery of the parasitic diode formed at the main junction (pn junction) of the SiC-MOSFET.

[0016] Conventional vertical SiC-MOSFETs have p-type base regions with higher impurity concentrations than the p-type base region at the corners of the active region. + By providing a type region, the displacement current generated in the edge termination region during the switching transition from ON to OFF is + A device has been proposed in which the device is pulled out from the gate region to the source electrode (see, for example, Patent Document 1 below). In Patent Document 1 below, a displacement current generated in the edge termination region during the switching transition from on to off is transferred to the p-type gate of the corner of the active region. + By using a structure that draws the source electrode from the active region, high electric fields are prevented from being applied to the gate insulating film and field oxide film near the corners of the active region.

[0017] Another conventional vertical SiC-MOSFET has been proposed, in which a low carrier lifetime region, where the lifetime of minority carriers is short, is provided in the main invalid region, where the main current of the main MOSFET does not flow, excluding the sense region where the current sense (sense MOSFET) is located (see, for example, Patent Document 2 below). In Patent Document 2 below, the low carrier lifetime region prevents displacement current from flowing from the main invalid region to the sense region, thereby locating the p-type base region of the main MOSFET throughout the entire main invalid region excluding the sense region, thereby suppressing localized electric field concentration in the field oxide film. [Prior art documents] [Patent documents]

[0018] [Patent Document 1] Japanese Patent Application Publication No. 2018-206873 [Patent Document 2] Japanese Patent Publication No. 2020-191420 Summary of the Invention [Problem to be solved by the invention]

[0019] The above-described conventional silicon carbide semiconductor device 230 (SiC-MOSFET: see FIGS. 11 to 13) has a structure in which an inner portion 262b of the gate polysilicon wiring layer 262 faces the semiconductor substrate 210 in the depth direction Z via only a gate insulating film 238 that is thinner than the field oxide film 261, in order to connect the gate polysilicon wiring layer 262 and the gate electrode 239. As a result, a parasitic capacitance is formed directly below the inner portion 262b of the gate polysilicon wiring layer 262, in which the capacitance of the gate insulating film 238 and the space charge capacitance of the SiC portion (semiconductor substrate 210) are connected in series.

[0020] The SiC portion directly below the inner portion 262b of the gate polysilicon wiring layer 262 is a p-type region (p ++ p-type contact extension 236a, p-type base extension 234a and p-type + Therefore, just as electrons and holes are accumulated inside p-type base region 234 along the parasitic capacitance due to the capacitance of gate insulating film 238 on the sidewall of gate trench 237 when the SiC-MOSFET is turned on and off, electrons and holes are also accumulated inside the p-type region immediately below inner portion 262b of gate polysilicon wiring layer 262 along the parasitic capacitance due to the capacitance of gate insulating film 238 on the front surface of semiconductor substrate 210.

[0021] Electrons accumulated inside the p-type region along the parasitic capacitance immediately below the inner portion 262b of the gate polysilicon wiring layer 262 are discharged to the drain electrode 243 during a switching transition from on to off of the SiC-MOSFET or during reverse recovery of the parasitic diode of the SiC-MOSFET. Holes accumulated inside the p-type region along the parasitic capacitance immediately below the inner portion 262b of the gate polysilicon wiring layer 262 flow toward the active region 201 during a switching transition from off to on of the SiC-MOSFET, and are extracted to the source electrode 241 through the contact holes 240a and 240b of the active region 201.

[0022] In addition, the steep dV / dt (drain-source voltage change per unit time) that occurs during the on-to-off switching transition of the SiC-MOSFET causes the n - A displacement current (hole current) is generated in the n-type drift region 232 and flows toward the active region 201. This displacement current flows through the n-type drift region 232. - p of the intermediate region 203 from the drift region 232 + The p-type base extension 252a and the p-type base extension 234a are connected to the p-type ++ The electrons flow into the mold contact extension 236 a and are drawn out to the source electrode 241 through the contact holes 240 a and 240 b in the active region 201 .

[0023] However, aluminum (Al) is used as an acceptor (p-type impurity) in the p-type region of the SiC part, and the energy level of Al is as deep as 200 meV (i.e., the ionization energy is large). Furthermore, the activation rate of Al in SiC is low, making it difficult to form a low-resistance p-type region. ++ the p-type contact region 236, the p-type base region 234, and the p + The parasitic resistance components of the type regions 251 and 252 and the p ++ p-type contact extension 236a, p-type base extension 234a and p-type + The parasitic resistance of the mold extension 252a becomes extremely large. This phenomenon becomes more pronounced at low temperatures where Al, which has a large ionization energy, no longer functions as an acceptor.

[0024] The holes accumulated in the intermediate region 203 and the holes generated in the edge termination region 202 are highly resistive p + The p-type base extension 252a, the p-type base extension 234a, and the p-type ++The voltage drop in the path of these holes increases because the holes are drawn to the source electrode 241 through the contact extension 236a. The voltage generated by this voltage drop is applied to the parasitic capacitance directly below the inner portion 262b of the gate polysilicon wiring layer 262, causing a gate leakage current to pass through the gate insulating film 238 and flow toward the gate polysilicon wiring layer 262. If the gate leakage current exceeds the breakdown voltage of the gate insulating film 238 at the point where it concentrates, the gate insulating film 238 will break down.

[0025] The amount of hole current (amount of gate leakage current) that leads to dielectric breakdown of the gate insulating film 238 is calculated by multiplying the steep dV / dt that occurs during the switching transition from on to off or from off to on of the SiC-MOSFET and during reverse recovery of the parasitic diode of the SiC-MOSFET by the parasitic capacitance adjacent to the p-type region that serves as the path for holes. The parasitic capacitance formed directly below the inner portion 262b of the gate polysilicon wiring layer 262 when a negative voltage is applied to the gate polysilicon wiring layer 262 is approximately equal to the capacitance of the gate insulating film 238 because holes accumulate in the SiC portion (p-type region) and are not depleted.

[0026] One way to suppress breakdown of the gate insulating film 238 is to increase the gate resistance Rg to reduce dV / dt, which occurs during the switching transition of the SiC-MOSFET or during reverse recovery of the SiC-MOSFET's parasitic diode, thereby reducing the amount of hole current in the hole path. However, increasing the gate resistance Rg increases switching loss, which does not fully utilize the advantages of SiC. Furthermore, if the chip size is increased to reduce forward loss and compensate for the increased switching loss in order to maintain the total conduction loss of the SiC-MOSFET, this will result in increased costs.

[0027] The inventors have confirmed that dielectric breakdown of the gate insulating film 238 occurs particularly at a location (near an inner end 261a of the field oxide film 261) on the starting point side of the hole current flowing toward the active region 201 in the gate insulating film 238 (a thin portion of the insulating layer immediately below the gate polysilicon wiring layer 262) immediately below an inner portion 262b of the gate polysilicon wiring layer 262. The inventors have also confirmed that dielectric breakdown of the gate insulating film 238 occurs only at the corners (vertices) 201a of the active region 201 having a substantially rectangular planar shape, and that the corners 201a have a lower dV / dt resistance than the straight portions (sides) of the active region 201.

[0028] Furthermore, the inventors have confirmed from an emission image taken with an EMS (Emission Microscope) that hole current concentrates (emits light) in areas where the gate polysilicon wiring layer forms an angle of approximately 90 degrees, such as near the corner 201 a of the active region 201 of the gate polysilicon wiring layer 262 (the area indicated by the black dot 200 in FIG. 11), at the connection between the gate polysilicon wiring layer 262 and the gate polysilicon wiring layer (not shown) of the gate pad, and at the connection between the gate polysilicon wiring layers of the gate pad and the electrode pad (not shown) for measuring gate resistance, and that the gate insulating film 238 undergoes dielectric breakdown at the areas where this hole current concentrates.

[0029] In order to solve the above-mentioned problems associated with the conventional technology, an object of the present invention is to provide a silicon carbide semiconductor device that has high dielectric breakdown resistance even at low temperatures, excellent switching characteristics, and can suppress increases in cost. [Means for solving the problem]

[0030] In order to solve the above-mentioned problems and achieve the object of the present invention, a silicon carbide semiconductor device according to the present invention has the following features: An active region, through which a main current flows, is provided in a semiconductor substrate made of silicon carbide, in a rectangular planar shape. An termination region surrounds the periphery of the active region. An intermediate region is provided between the active region and the termination region. A first semiconductor region of a first conductivity type is provided within the semiconductor substrate. A second semiconductor region of a second conductivity type is provided between the first main surface of the semiconductor substrate and the first semiconductor region, extending from the active region to the intermediate region. A third semiconductor region of a first conductivity type is selectively provided in the active region between the first main surface of the semiconductor substrate and the second semiconductor region. A gate insulating film is provided in contact with a region of the second semiconductor region between the first semiconductor region and the third semiconductor region, and covers the first main surface of the semiconductor substrate. A gate electrode is provided on a region of the second semiconductor region between the first semiconductor region and the third semiconductor region, with the gate insulating film interposed therebetween. A fourth semiconductor region of a second conductivity type is provided in the intermediate region between the first main surface of the semiconductor substrate and the second semiconductor region, The fourth semiconductor region has a higher impurity concentration than the second semiconductor region.

[0031] In the intermediate region, a field oxide film is provided on the gate insulating film on the first main surface of the semiconductor substrate. A gate polysilicon wiring layer is provided on the field oxide film. The gate polysilicon wiring layer surrounds the active region, is connected to the gate electrode at its inner end, and faces the fourth semiconductor region in the depth direction via the field oxide film and the gate insulating film. An interlayer insulating film covers the gate electrode and the gate polysilicon wiring layer. A first contact hole penetrates the interlayer insulating film in the depth direction to expose the first main surface of the semiconductor substrate. A first electrode is electrically connected to the second semiconductor region, the third semiconductor region, and the fourth semiconductor region via the first contact hole. A second electrode is provided on the second main surface of the semiconductor substrate. The gate polysilicon wiring layer extends inward beyond the inner end of the field oxide film, and faces the fourth semiconductor region in the depth direction at its inner portion via only the gate insulating film. In the intermediate region, a first low carrier lifetime region having a first carrier lifetime killer introduced therein is provided in a portion adjacent to a corner of the active region, facing the gate polysilicon wiring layer in the depth direction and overlapping the fourth semiconductor region.

[0032] Moreover, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the first low carrier lifetime region is provided apart from the third semiconductor region.

[0033] Moreover, in the silicon carbide semiconductor device according to the present invention, the first low carrier lifetime region reaches an outer edge of the fourth semiconductor region.

[0034] In addition, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the first low carrier lifetime region is provided to overlap the fourth semiconductor region and the second semiconductor region in the depth direction.

[0035] Furthermore, the silicon carbide semiconductor device according to the present invention is the above-described one, further comprising a trench extending in a depth direction from the first main surface of the semiconductor substrate through the third semiconductor region and the second semiconductor region to reach the first semiconductor region, and extending linearly in a direction parallel to the first main surface of the semiconductor substrate from the active region to the intermediate region. The gate electrode is provided within the trench via the gate insulating film and is connected to the gate polysilicon wiring layer at a longitudinal end of the trench. The first low carrier lifetime region is provided away from the trench.

[0036] The silicon carbide semiconductor device according to the present invention is the above-described invention, further comprising a first high concentration region of a second conductivity type, a second high concentration region of the second conductivity type, and a third high concentration region of the second conductivity type. The first high concentration region is selectively provided at a position deeper than a bottom surface of the trench, separated from the second semiconductor region and in contact with the first semiconductor region, and faces the bottom surface of the trench in the depth direction. The second high concentration region is selectively provided in the active region between the second semiconductor region and the first semiconductor region, separated from the first high concentration region and the trench, and in contact with the second semiconductor region and the first semiconductor region, and reaches a position deeper than the bottom surface of the trench. The first high concentration region, the second high concentration region, and the third high concentration region have impurity concentrations higher than those of the second semiconductor region. The third high concentration region is provided in the intermediate region between the second semiconductor region and the first semiconductor region, in contact with the second semiconductor region and the first semiconductor region, and reaches a position deeper than the bottom surface of the trench. The first low carrier lifetime region is provided so as to overlap the fourth semiconductor region, the second semiconductor region, and the third high concentration region in the depth direction.

[0037] Moreover, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the first carrier lifetime killer is helium, proton or vanadium.

[0038] Further, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the first low carrier lifetime region is 11 / cm 2 More than 1×10 12 / cm 2 At the following doses The first It is characterized by the introduction of a career lifetime killer.

[0039] Furthermore, the silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, a second low carrier lifetime region, into which a second carrier lifetime killer is introduced, is provided between the first high concentration region, the second high concentration region and the third high concentration region and the first semiconductor region, respectively.

[0040] Further, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the first low carrier lifetime region and the second low carrier lifetime region are formed in the first low carrier lifetime region and the second low carrier lifetime region. The dose of the second carrier lifetime killer introduced into At a higher dose than The first It is characterized by the introduction of a career lifetime killer.

[0041] Moreover, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the second carrier lifetime killer is helium, proton or vanadium.

[0042] In the silicon carbide semiconductor device according to the present invention, in the above-described invention, the first electrode extends over the interlayer insulating film to the intermediate region, and the first low carrier lifetime region faces the first electrode in a depth direction with the interlayer insulating film interposed therebetween.

[0043] According to the above-described invention, the average time until minority carriers generated in the intermediate region and termination region and flowing through the p-type region of the intermediate region (third high-concentration region, second semiconductor region, and fourth semiconductor region) toward the active region disappear can be made shorter in the portion of the intermediate region adjacent to the corner of the active region (corner portion) than in other portions of the intermediate region (straight portion). This makes it possible to set the hole density in the portion where the path of minority carriers is relatively narrow (corner portion of the intermediate region) to be approximately the same as the hole density in other portions of the intermediate region, thereby suppressing hole current concentration at the corner of the active region.

[0044] This suppresses the potential rise at the corners of the p-type region, which serves as a path for minority carriers in the intermediate region, and prevents dielectric breakdown at the corners of the intermediate region in the relatively thin portion of the insulating layer (gate insulating film) between the semiconductor substrate and the gate polysilicon wiring layer. Furthermore, there is no need to increase gate resistance to reduce the hole density in the hole path, which suppresses degradation of switching characteristics. Furthermore, the dV / dt tolerance of the active region corners, where hole current tends to concentrate, can be improved. Furthermore, there is no need to increase the chip size to reduce forward loss in order to maintain the total conduction loss. [Effects of the Invention]

[0045] The silicon carbide semiconductor device according to the present invention has the effect of providing a semiconductor device that has high dielectric breakdown resistance, excellent switching characteristics (high-speed switching, low switching loss), and can suppress increases in cost. [Brief explanation of the drawings]

[0046] [Figure 1] 1 is a plan view showing a layout of a silicon carbide semiconductor device according to a first embodiment, as viewed from the front surface side of a semiconductor substrate. [Figure 2] 2 is an enlarged plan view showing the vicinity of a corner portion of the semiconductor substrate of FIG. 1. [Figure 3]3 is a cross-sectional view showing a cross-sectional structure taken along line AA' in FIG. 2. [Figure 4] 3 is a cross-sectional view showing the cross-sectional structure taken along the line BB' in FIG. 2. [Figure 5] 3 is a cross-sectional view showing a cross-sectional structure taken along the line CC' in FIG. 2. FIG. [Figure 6] 3 is a cross-sectional view showing the cross-sectional structure taken along the line DD' in FIG. 2. FIG. [Figure 7] FIG. 10 is a cross-sectional view showing a structure of a silicon carbide semiconductor device according to a second embodiment. [Figure 8] FIG. 10 is a cross-sectional view showing a structure of a silicon carbide semiconductor device according to a second embodiment. [Figure 9] FIG. 10 is a cross-sectional view showing a structure of a silicon carbide semiconductor device according to a second embodiment. [Figure 10] FIG. 10 is a cross-sectional view showing a structure of a silicon carbide semiconductor device according to a second embodiment. [Figure 11] FIG. 1 is a plan view showing a part of a layout of a conventional silicon carbide semiconductor device as viewed from the front surface side of a semiconductor substrate. [Figure 12] 12 is a cross-sectional view showing the cross-sectional structure taken along the line AA-AA' in FIG. [Figure 13] 12 is a cross-sectional view showing the cross-sectional structure taken along the line BB-BB' in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0047] Preferred embodiments of a silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - prefixed with n or p indicate that the impurity concentration is higher or lower than that of layers or regions not prefixed with that prefix, respectively. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference numerals, and redundant explanations will be omitted.

[0048] (Embodiment 1) The structure of a silicon carbide semiconductor device according to a first embodiment will be described. Fig. 1 is a plan view showing the layout of the silicon carbide semiconductor device according to the first embodiment as viewed from the front surface side of the semiconductor substrate. In Fig. 1, coarse dashed lines indicate the boundary between the active region 1 and the intermediate region 3, and the boundary between the intermediate region 3 and the edge termination region 2, and fine dashed lines indicate n-type regions provided along the periphery of the semiconductor substrate (semiconductor chip) 10 having a substantially rectangular planar shape. + The inner periphery of the channel stopper region 22. + The outer periphery of the type channel stopper region 22 is the outer periphery of the semiconductor substrate 10. Fig. 2 is an enlarged plan view showing the vicinity of a corner portion of the semiconductor substrate in Fig. 1 (a portion including the vertex (chip corner) of the semiconductor substrate having a substantially rectangular planar shape).

[0049] In FIG. 2, the gate trench 37, gate insulating film 38, and gate electrode 39 are collectively indicated by a single thick line, and contact holes 40a and 40b in the active region 1 are indicated by hatching. The inner periphery (inner end 61a) of the field oxide film 61 is indicated by a coarse dashed line, and the inner periphery (inner end 62a) and outer periphery of the gate polysilicon (poly-Si) wiring layer 62 are indicated by fine dashed lines. The outer periphery of the field oxide film 61 is the outer periphery of the semiconductor substrate 10. Reference numeral 41a denotes the outer periphery of the source electrode 41, and reference numerals 63a and 63b denote the inner periphery and outer periphery, respectively, of the gate metal wiring layer 63. FIGS. 3 to 6 are cross-sectional views showing cross-sectional structures along the cut lines A-A', B-B', C-C', and D-D' in FIG. 2, respectively.

[0050] 1 to 6, a silicon carbide semiconductor device 30 according to a first embodiment is a vertical SiC-MOSFET with a trench gate structure, including an active region 1 and an edge termination region 2 on a semiconductor substrate (semiconductor chip) 10 made of silicon carbide (SiC). The active region 1 is a region through which a main current (drift current) flows when the MOSFET is on, and multiple unit cells (element constituent units) of the MOSFET having the same structure are arranged adjacent to one another. The active region 1 has a substantially rectangular planar shape and is arranged approximately at the center of the semiconductor substrate 10 (chip center). At a corner (vertex) 1a of the active region 1, the corners of the source electrode 41, gate polysilicon wiring layer 62, and gate metal wiring layer 63 may be chamfered to form a substantially arc shape.

[0051] The active region 1 is a region located inside (toward the center of the chip) the longitudinal ends of contact holes 40a and 40b (described later) in a first direction X (longitudinal direction of the gate trench 37) (described later). The active region 1 is a region located inside the side surfaces of the insulating layers (interlayer insulating film 40 and gate insulating film 38) that form the outer sidewalls of the outermost contact hole 40b (toward the end (chip end) of the semiconductor substrate 10) in a second direction Y (transverse direction of the gate trench 37) (described later). The longitudinal ends of the contact holes 40a and 40b in the active region 1 refer to the side surfaces of the insulating layers (interlayer insulating film 40 and gate insulating film 38) that form the sidewalls of the contact holes 40a and 40b.

[0052] In the active region 1, a source electrode (first electrode) 41 having substantially the same planar shape and surface area as the active region 1 is provided on the front surface of the semiconductor substrate 10. The portion of the source electrode 41 exposed in an opening in the passivation film 42 (see FIGS. 3 to 6) functions as a source pad (electrode pad). A gate pad (electrode pad) 64 is disposed in the active region 1 or the intermediate region 3. In FIG. 1, the gate pad 64 having a substantially rectangular planar shape with chamfered corners is disposed in the intermediate region 3, and the active region 1 and the source electrode 41 are shown as having a substantially rectangular planar shape with recesses recessed toward the center of the chip surrounding three sides of the gate pad 64, but the planar shapes of these parts may be set as appropriate.

[0053] The intermediate region 3 between the active region 1 and the edge termination region 2 is adjacent to the active region 1 and surrounds the periphery of the active region 1 in a substantially rectangular shape. The boundary between the intermediate region 3 and the edge termination region 2 is defined by a p + The intermediate region 3 is an outer end of the mold extension 52a. A gate pad 64, a gate polysilicon wiring layer 62 and a gate metal wiring layer 63 that serve as gate runners are provided in the intermediate region 3. The gate pad 64, like the gate runner, is formed by laminating a gate polysilicon wiring layer and a gate metal wiring layer (not shown) in this order. The gate electrode 39 of each unit cell of the SiC-MOSFET is electrically connected to the gate pad 64 via the gate runner. The gate runner surrounds the periphery of the active region 1 in a substantially rectangular shape.

[0054] The intermediate region 3 has a low carrier lifetime region 71 (hatched portion: first low carrier lifetime region) formed only in a portion adjacent to the corner 1a of the active region 1 (hereinafter referred to as the corner portion of the intermediate region 3) where carrier lifetime killers (crystal defects that serve as capture centers for minority carriers) are introduced, thereby shortening the lifetime of minority carriers (holes) compared to other portions of the semiconductor substrate 10 (see FIG. 2). The low carrier lifetime region 71 has a planar shape, such as a substantially rectangular, fan-shaped, or arc-shaped shape, connecting mutually orthogonal straight line portions of the intermediate region 3 that surround the active region 1 in a substantially rectangular shape. The low carrier lifetime region 71 does not face the active region 1 in either the first or second direction X or Y. The low carrier lifetime region 71 is not provided in the straight line portions of the intermediate region 3, the active region 1, or the edge termination region 2.

[0055] When holes generated in the intermediate region 3 and the edge termination region 2 are extracted to the source electrode 41, holes passing through the straight portions of the intermediate region 3 pass through the entire area of ​​the outermost contact hole 40b in the active region 1 or through the longitudinal ends of all contact holes 40a, 40b in the active region 1 to reach the source electrode 41. The straight portions of the intermediate region 3 correspond to the four sides of the intermediate region 3 and face the active region 1 in either the first or second direction X or Y. On the other hand, holes passing through the corner portions of the intermediate region 3 pass through, for example, only the longitudinal ends of the outermost contact hole 40b in the active region 1 to reach the source electrode 41. For this reason, the hole path is narrower through the path passing through the corner portions of the intermediate region 3 than through the path passing through the straight portions of the intermediate region 3. As a result, even though the number of holes is greater in the corner portions of the semiconductor substrate 10 than in the straight portions (sides) of the semiconductor substrate 10, hole current is concentrated in the narrow path, making it easier for the potential to rise.

[0056] Therefore, in the first embodiment, as described above, low carrier lifetime regions 71 are disposed in the corners of intermediate region 3. Low carrier lifetime regions 71 have the function of shortening the average time until holes flowing toward corners 1 a of active region 1 disappear, in the path of holes generated in intermediate region 3 and edge termination region 2 being extracted to source electrode 41, compared to the average time until holes flowing toward straight portions (sides) of active region 1 disappear. By disposing low carrier lifetime regions 71 in the corners of intermediate region 3, the hole density in the path of holes flowing from intermediate region 3 and edge termination region 2 toward active region 1 and extracted to source electrode 41 is adjusted to be approximately equal throughout intermediate region 3.

[0057] The low carrier lifetime region 71 is disposed at least directly below the gate polysilicon wiring layer 62. This is because holes generated in the intermediate region 3 and the edge termination region 2 flow toward the active region 1 through the SiC portion (semiconductor substrate 10) directly below the gate polysilicon wiring layer 62, which tends to increase the potential in the SiC portion directly below the gate polysilicon wiring layer 62. Furthermore, it is preferable that the low carrier lifetime region 71 extend outward to a third surface 10c (described later) on the front surface of the semiconductor substrate 10 (the outer edge of a p-type region (described later) overlapping with the low carrier lifetime region 71). This allows the carrier lifetime killer in the low carrier lifetime region 71 to capture and eliminate holes generated in the intermediate region 3 and the edge termination region 2 and flowing toward the active region 1 as far outward as possible, thereby reducing the hole density near the corner 1a of the active region 1.

[0058] As the impurity to be introduced into the low carrier lifetime region 71 as a carrier lifetime killer, an impurity generally used as a carrier lifetime killer in an IGBT (Insulated Gate Bipolar Transistor), a diode, etc. can be used. Specifically, for example, helium (He), protons (H + ) or vanadium (V), etc. can be used. The low carrier lifetime region 71 is set to, for example, 1×10 11 / cm 2 More than 1×10 12 / cm 2 The carrier lifetime killer is introduced at a dose of about: The low carrier lifetime region 71 has the highest carrier lifetime killer concentration (impurity concentration) inside the semiconductor substrate 10.

[0059] The edge termination region 2 is a region between the active region 1 and the edge of the chip. It surrounds the active region 1 via the intermediate region 3 and maintains a breakdown voltage by mitigating the electric field on the front surface side of the semiconductor substrate 10. The breakdown voltage is the limit voltage at which an avalanche breakdown occurs at the pn junction and the source-drain voltage does not increase further even if the source-drain current increases. The edge termination region 2 is equipped with a breakdown voltage structure such as a junction termination extension (JTE) structure or a field limiting ring (FLR) structure 20. This breakdown voltage structure mitigates or disperses the electric field in the edge termination region 2.

[0060] The semiconductor substrate 10 is made of silicon carbide. + On the front surface of the starting substrate 11, - The semiconductor substrate 10 is formed by epitaxially growing epitaxial layers 12, 13, which become the p-type drift region (first semiconductor region) 32 and the p-type base region (second semiconductor region) 34, in this order. The main surface of the semiconductor substrate 10 facing the p-type epitaxial layer 13 is the front surface (first main surface), and the n-type base region (second semiconductor region) 34 is the n-type base region (second semiconductor region) 34. + The main surface on the mold starting substrate 11 side is referred to as the back surface (second main surface). + The starting substrate 11 is n + The p-type epitaxial layer 13 is a p-type drain region 31. A portion of the edge termination region 2 of the p-type epitaxial layer 13 is removed, and a step 14 is formed on the front surface of the semiconductor substrate 10.

[0061] The front surface of the semiconductor substrate 10 is such that the edge termination region 2 portion (hereinafter referred to as the second surface) 10b is closer to the active region 1 and the intermediate region 3 portion (hereinafter referred to as the first surface) 10a, with the step 14 as the boundary. + The second surface 10b of the front surface of the semiconductor substrate 10 is recessed toward the n-type drain region 31. The n-type epitaxial layer 13 is exposed by removing the p-type epitaxial layer 13. - The third surface 10c (the mesa edge of the step 14) of the semiconductor substrate 10 is the exposed surface of the p-type epitaxial layer 12. The third surface 10c (the mesa edge of the step 14) of the semiconductor substrate 10 is the exposed side surface of the p-type epitaxial layer 13 that is exposed by removing the p-type epitaxial layer 13.

[0062] In the active region 1, a p-type base region 34 and an n-type base region 35 are formed on the first surface 10a side of the front surface of the semiconductor substrate 10. + p-type source region (third semiconductor region) 35 ++ A trench gate structure is provided, which is composed of a contact region 36, a gate trench 37, a gate insulating film 38, and a gate electrode 39. The gate trench 37 extends linearly to the intermediate region 3 in a first direction X (longitudinal direction) parallel to the front surface of the semiconductor substrate 10. A plurality of gate trenches 37 are arranged in stripes adjacent to each other in a second direction Y (transverse direction) parallel to the front surface of the semiconductor substrate 10 and perpendicular to the first direction X.

[0063] The gate trenches 37 are arranged adjacent to each other in the second direction Y, so that a plurality of unit cells of the same structure are arranged adjacent to each other in the second direction Y. The ends of adjacent gate trenches 37 may be connected to each other in a circular arc-like planar shape, for example, to form the gate trenches 37 in a ring-shaped planar shape surrounding the portion between the adjacent gate trenches 37 (see FIG. 2). The gate trench 37 extends from the first surface 10a of the front surface of the semiconductor substrate 10 through the p-type epitaxial layer 13 to form an n-type - The gate insulating film 38 extends into the silicon epitaxial layer 12. The gate insulating film 38 is provided along the inner wall of the gate trench 37.

[0064] The gate insulating film 38 extends from the inner wall of the gate trench 37 onto the front surface of the semiconductor substrate 10, reaching on the front surface of the semiconductor substrate 10 from the active region 1 to the edge of the chip. The thickness of the gate insulating film 38 is equal to or greater than a thickness that provides predetermined parasitic capacitances (gate-source capacitance Cgs, gate-drain capacitance Cgd), and is, for example, approximately 100 Å or less. The gate electrode 39 is provided on the gate insulating film 38 inside the gate trench 37 so as to fill the inside of the gate trench 37. The gate electrode 39 is connected to the gate polysilicon wiring layer 62 at the longitudinal end of the gate trench 37.

[0065] p-type base region 34, n +type source region 35 and p ++ The p-type contact regions 36 are selectively provided between adjacent gate trenches 37. The p-type base region 34 is formed by + Type source region 35, p ++ type contact region 36 and p ++ The p-type base region 34 is a portion excluding the p-type contact extension 36a and contacts the gate insulating film 38 on the sidewall of the gate trench 37. The p-type base region 34 extends outward (toward the chip end) from the active region 1 and reaches the third face 10c on the front surface of the semiconductor substrate 10. The p-type base region 34 is provided throughout the active region 1 and intermediate region 3.

[0066] n + type source region 35 and p ++ The n-type contact region 36 is selectively provided between the first surface 10a of the front surface of the semiconductor substrate 10 and the p-type base region 34, in contact with the p-type base region 34, and is exposed to the first surface 10a of the front surface of the semiconductor substrate 10. Exposing to the first surface 10a of the front surface of the semiconductor substrate 10 means that the n-type contact region 36 is in contact with the source electrode 41 at the first surface 10a of the front surface of the semiconductor substrate 10. + The source region 35 contacts the gate insulating film 38 on the sidewall of the gate trench 37. ++ The contact region 36 is an n + The source region 35 is disposed farther from the gate trench 37 than the source region 35 .

[0067] n + type source region 35 and p ++ The mold contact region 36 extends linearly in the first direction X with a length substantially equal to the longitudinal length of the contact hole 40a. "Substantially the same length" means that the length is the same within a range that includes tolerances due to process variations. ++ The contact region 36 has a p ++ The contact extension (fourth semiconductor region) 36a is connected to the contact extension (fourth semiconductor region) 36a. ++ The p-type contact region 36 may not be provided. ++Instead of the p-type contact region 36, the p-type base region 34 reaches the first surface 10a of the front surface of the semiconductor substrate 10 and is exposed.

[0068] The p-type base region 34 and the n + Between the n-type drain region 31 + In contact with the n-type drain region 31 - A type drift region 32 is provided. - The p-type drift region 32 extends from the active region 1 to the edge of the chip. - Between the n-type drift region 32 and the bottom surface of the gate trench 37, + The n-type current diffusion region 33 and the first and second p-type drain region 31 are disposed at a deep position on the side of the n-type drain region 31. + The n-type current diffusion region 33 and the first and second p-type regions (first and second high concentration regions) 51 and 52 may be selectively provided. + The mold regions 51 and 52 extend linearly in the first direction X with a length substantially equal to the length of the gate trench 37 in the longitudinal direction.

[0069] The n-type current diffusion region 33 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. The n-type current diffusion region 33 is arranged in the second direction Y. + The n-type current diffusion region 33 is in contact with the n-type regions 51 and 52 and the gate insulating film 38. + The n-type current diffusion region 33 may not be provided. In this case, instead of the n-type current diffusion region 33, an n - The p-type drift region 32 reaches the p-type base region 34 and extends in the second direction Y. + It contacts the mold regions 51 and 52 and the gate insulating film 38 .

[0070] 1st, 2p + The mold regions 51 and 52 have the function of reducing the electric field applied to the gate insulating film 38 at the bottom of the gate trench 37. + The depth positions of the mold regions 51 and 52 can be set appropriately.+ The n-type regions 51 and 52 are more n-type than the n-type current diffusion region 33. + Alternatively, the first and second p-type current diffusion regions 33 may terminate at a shallow depth on the p-type drain region 31 side and be substantially entirely surrounded by the n-type current diffusion region 33. + The n-type regions 51 and 52 are located at substantially the same depth as the n-type current diffusion region 33 in the depth direction Z, or at a depth lower than the n-type current diffusion region 33. + The n-type drain region 31 is - It may be in contact with the mold drift region 32 .

[0071] 1st, 2p + The mold regions 51 and 52 are formed at the ends in the longitudinal direction (first direction X) by p + It is connected to the mold extension 52a. + The first p-type region 51 is provided apart from the p-type base region 34 and faces the bottom surface of the gate trench 37 in the depth direction Z. + The mold region 51 may reach the bottom surface of the gate trench 37. + The mold region 51 is the first and second p + Another p is placed at a predetermined position between the mold regions 51 and 52. + A mold area (not shown) is placed or the first p + A part of the mold region 51 is + The second p + It may be electrically connected to the mold region 52 at a predetermined location.

[0072] 2nd p. + The first p region 52 is formed between the adjacent gate trenches 37. + The second p + The upper surface of the n-type region 52 contacts the p-type base region 34. - The n-type epitaxial layer 12 includes the n-type current diffusion region 33, the first and second p-type epitaxial layers 12, and the n-type current diffusion region 33. + Type region 51,52, p + The mold extension portion 52a, which will be described later, - The mold region 21 and the n + The portion excluding the channel stopper region 22 is n - n-type drift region 32.- The n-type drift region 32 is + The gate electrode 32 is provided between the gate electrode 32 and the drain region 31 in contact with these regions.

[0073] The interlayer insulating film 40 is provided on the gate insulating film 38 on the front surface of the semiconductor substrate 10 over the entire front surface of the semiconductor substrate 10, and covers the gate electrode 39, the field oxide film 61, and the gate polysilicon wiring layer 62. The contact holes 40a, 40b in the active region 1 penetrate the interlayer insulating film 40 and the gate insulating film 38 in the depth direction Z to reach the front surface of the semiconductor substrate 10. The contact holes 40a, 40b in the active region 1 extend in a stripe shape in the first direction X over the entire active region 1. The contact hole 40c in the intermediate region 3 penetrates the interlayer insulating film 40 in the depth direction Z to reach the gate metal wiring layer 63.

[0074] The outermost contact hole 40b of the active region 1 is provided on the outer side of the outermost gate trench 37 in the second direction Y, and the entire area is covered with a p ++ The n-type contact extension 36a is exposed. + The n-type source region 35 is not provided. The other contact holes 40a in the active region 1 are provided between the adjacent gate trenches 37. + type source region 35 and p ++ The other contact holes 40a in the active region 1 are p-type contact regions 36 exposed at their ends in the longitudinal direction (first direction X). ++ The mold contact extensions 36a may be exposed.

[0075] In the intermediate region 3, a surface region of the first surface 10a of the front surface of the semiconductor substrate 10 is provided with p ++ A contact extension 36a is provided. ++ The contact extension 36a is p ++The p-type contact region 36 extends into the intermediate region 3, and is provided over the entire area between the first surface 10a of the front surface of the semiconductor substrate 10 and the p-type base extension 34a. ++ The mold contact extension 36a is exposed to the first and third faces 10a and 10c of the front surface of the semiconductor substrate 10, and is exposed to the entire outermost contact hole 40b of the active region 1.

[0076] The p-type base extension 34a is a portion of the p-type base region 34 that extends into the intermediate region 3, is provided over the entire intermediate region 3, and is exposed to the third face 10c of the front surface of the semiconductor substrate 10. In the intermediate region 3 and the edge termination region 2, the exposure to the first to third faces 10a to 10c of the front surface of the semiconductor substrate 10 means that the p-type base extension 34a is in contact with the gate insulating film 38 on the first to third faces 10a to 10c. ++ The type contact extension 36a may not be provided. ++ Instead of the p-type contact extension 36a, the p-type base extension 34a reaches the first surface 10a of the front surface of the semiconductor substrate 10 and is exposed. - Between the p-type drift region 32 + A mold extension portion (third high concentration region) 52a may be provided. + The mold extension part 52a is the second p + This is the portion of the mold region 52 that extends into the intermediate region 3 .

[0077] Also, p + The mold extension 52a extends outward from the step 14 to a position where it is exposed on the second surface 10b of the front surface of the semiconductor substrate 10. + The p-type base extension 52a may be exposed on the third surface 10c of the semiconductor substrate 10. ++ Type contact extensions 36a and p + The mold extension 52a surrounds the periphery of the active region 1 and extends inward from the intermediate region 3 to the gate trench 37. ++ p-type contact extension 36a, p-type base extension 34a and p-type +The type extension 52a serves as a path for holes generated in the intermediate region 3 and the edge termination region 2 to be extracted to the source electrode 41. ++ p-type contact extension 36a, p-type base extension 34a and p-type + The lowest resistance p ++ The hole current density is highest in the contact extension 36a.

[0078] In the intermediate region 3, a surface region of the first surface 10a of the front surface of the semiconductor substrate 10 is provided with p ++ A low carrier lifetime region 71 is provided so as to overlap the n-type contact extension 36a. The low carrier lifetime region 71 is provided between the gate trench 37 and the n-type contact extension 36a. + The low carrier lifetime region 71 is located outside the contact holes 40a and 40b of the active region 1 and is not in contact with the source electrode 41. This is because the low carrier lifetime region 71 is located outside the contact holes 40a and 40b of the active region 1 and is not in contact with the source electrode 41. + This is because if the insulating film 38 is in contact with the source region 35 and the inner wall of the gate trench 37, it will adversely affect the electrical characteristics of the active region 1.

[0079] The low carrier lifetime region 71 is formed so as to overlap the p-type base extension 34a or to further overlap the p-type base extension 34a. + n so as to overlap the mold extension portion 52a + The low carrier lifetime region 71 may extend to a deep position on the side of the gate trench 37, the n-type drain region 31. + Away from the p-type source region 35 and the source electrode 41 ++ p-type contact extension 36a, p-type base extension 34a and p-type + It is preferable that the low carrier lifetime region 71 overlaps substantially the entirety of the n-type extension portion 52a. -The low carrier lifetime region 71 may be in contact with the type drift region 32. The low carrier lifetime region 71 may face the source electrode 41 in the depth direction Z via the interlayer insulating film 40. The low carrier lifetime region 71 may be exposed to the first and third faces 10a and 10c of the front surface of the semiconductor substrate 10.

[0080] In the intermediate region 3 and the edge termination region 2, the entire front surface of the semiconductor substrate 10 is covered with an insulating layer formed by stacking a gate insulating film 38, a field oxide film 61, and an interlayer insulating film 40 in this order. The entire front surface of the semiconductor substrate 10 in the intermediate region 3 and the edge termination region 2 is in contact with the gate insulating film 38. In the intermediate region 3, a gate polysilicon wiring layer 62 and a gate metal wiring layer 63, which serve as gate runners, are stacked in this order on the gate insulating film 38 on the front surface of the semiconductor substrate 10, with the field oxide film 61 interposed between them. The gate polysilicon wiring layer 62 and the gate metal wiring layer 63 surround the periphery of the active region 1.

[0081] The field oxide film 61 and the gate polysilicon wiring layer 62 are provided between the gate insulating film 38 and the interlayer insulating film 40. An inner end 61a of the field oxide film 61 is located outwardly away from the sidewalls of the contact holes 40a, 40b in the active region 1 (i.e., the boundary between the active region 1 and the intermediate region 3). The inner end 61a of the field oxide film 61 is located outwardly of an inner end 62a of the gate polysilicon wiring layer 62. The inner end 61a of the field oxide film 61 may form an obtuse angle (inclined surface) or a substantially right angle (vertical surface) with respect to the first surface 10a of the front surface of the semiconductor substrate 10.

[0082] An inner end 61a of the field oxide film 61 is located outward from the boundary between the active region 1 and the intermediate region 3 (the longitudinal ends of the contact holes 40a and 40b and the outer sidewall of the contact hole 40b) around the entire periphery of the active region 1. The field oxide film 61 extends from the intermediate region 3 to the edge of the chip. A gate polysilicon wiring layer 62 is provided on the field oxide film 61 and surrounds the periphery of the active region 1. The gate polysilicon wiring layer 62 extends inward from the inner end 61a of the field oxide film 61 and terminates on the gate insulating film 38 on the front surface of the semiconductor substrate 10 in the intermediate region 3.

[0083] An inner portion 62b of the gate polysilicon wiring layer 62 is located inside an inner end portion 61a of the field oxide film 61 and faces the semiconductor substrate 10 in the depth direction Z with only the gate insulating film 38 interposed therebetween. The field oxide film 61 and the gate polysilicon wiring layer 62 are covered with the interlayer insulating film 40. Therefore, between the first surface 10a of the front surface of the semiconductor substrate 10 and the gate polysilicon wiring layer 62, there exists a relatively thick insulating layer formed by laminating the gate insulating film 38 and the field oxide film 61 in this order, and a relatively thin insulating layer formed only of the gate insulating film 38 located inside this portion.

[0084] The gate polysilicon wiring layer 62 faces the longitudinal end of the gate trench 37 in the depth direction Z, and is connected to the gate electrode 39 at the longitudinal end of the gate trench 37. The gate metal wiring layer 63 contacts the gate polysilicon wiring layer 62 through a contact hole 40c in the interlayer insulating film 40. The gate electrode 39 and a gate pad 64 are electrically connected via a gate runner constituted by the gate polysilicon wiring layer 62 and the gate metal wiring layer 63. The gate pad 64 has a stacked structure similar to that of the gate runner, and is provided on the field oxide film 61.

[0085] The second surface 10b of the front surface of the semiconductor substrate 10 is formed in the edge termination region 2. - The surface region of the epitaxial layer 12 is provided with a plurality of p- The second surface 10b of the semiconductor substrate 10 is entirely covered with an insulating layer formed by laminating a gate insulating film 38, a field oxide film 61, and an interlayer insulating film 40 in this order. - On the type region 21, - A field plate (FP) which is a metal electrode at a floating potential may be provided in contact with the mold region 21.

[0086] The second surface 10b of the front surface of the semiconductor substrate 10 is formed in the edge termination region 2. - In the surface region of the type epitaxial layer 12, outside the FLR structure 20, apart from the FLR structure 20, + A channel stopper region 22 may be provided. + The channel stopper region 22 is exposed at the edge of the semiconductor substrate 10. + The n-type channel stopper region 22 is formed when the SiC-MOSFET is turned off. - It has the function of suppressing the extension of the depletion layer that spreads outward from the active region 1 within the n-type drift region 32. + On the type channel stopper region 22, + A channel stopper electrode (not shown) may be provided in contact with the channel stopper region 22 .

[0087] The source electrode 41 is in ohmic contact with the front surface of the semiconductor substrate 10 inside the contact holes 40a and 40b, and is connected to the p-type base region 34, the n-type + Type source region 35, p ++ The p-type contact region 36, the p-type base extension 34a and the p ++ The source electrode 41 is electrically connected to the gate contact extension 36a. The source electrode 41 may extend outward on the interlayer insulating film 40 to such an extent that it does not face the gate polysilicon wiring layer 62 in the depth direction Z. A barrier metal (not shown) may be provided between the source electrode 41 and the interlayer insulating film 40 in the active region 1 to prevent mutual reaction between the source electrode 41 and the interlayer insulating film 40 and its underlying layers.

[0088] The passivation film 42 covers the entire front surface of the semiconductor substrate 10. The source electrode 41 and the gate pad 64 are exposed through different openings in the passivation film 42. The passivation film 42 is, for example, a polyimide film. In the edge termination region 2, the front surface of the semiconductor substrate 10 is provided with an n-type GaN film. - The front surface of the semiconductor substrate 10 may be a flat surface that is continuous from the active region 1 to the chip edge without providing the step 14, as long as the n-type epitaxial layer is exposed. + The mold is in ohmic contact with the entire back surface of the starting substrate 11.

[0089] The operation of the silicon carbide semiconductor device 30 (SiC-MOSFET) according to the first embodiment will be described. When a voltage equal to or greater than the gate threshold voltage is applied to the gate electrode 39 while a positive voltage (forward voltage) relative to the source electrode 41 is applied to the drain electrode 43, electrons are accumulated in the p-type base region 34 along the parasitic capacitance due to the capacitance of the gate insulating film 38 on the sidewall of the gate trench 37, and a channel (n-type inversion layer) is formed. As a result, + The n-type drain region 31 passes through the channel. + A main current (drift current) flows toward the type source region 35, and the SiC-MOSFET turns on.

[0090] On the other hand, when a voltage less than the gate threshold voltage is applied to the gate electrode 39 while a forward voltage is applied between the source and drain, + The p-type regions 51 and 52 and the p-type base region 34, and the n-type current diffusion region 33 and the n - When the pn junction (main junction) between the p-type drift region 32 and the SiC-MOSFET is reverse-biased, electrons are discharged from the portion of the p-type base region 34 along the gate trench 37, causing depletion and preventing the main current from flowing, so that the SiC-MOSFET remains in the off state. At this time, the main junction (pn junction) of the active region 1 is reverse-biased, causing a depletion layer to expand from the pn junction, ensuring a predetermined breakdown voltage of the active region 1.

[0091] When the SiC-MOSFET is turned off, the depletion layer that spreads from the main junction in the active region 1 flows through the p - Type region 21 and n - The pn junction with the silicon drift region 32 causes the depletion layer to extend outward (toward the chip edge) in the normal direction through the edge termination region 2. The depletion layer extends outward through the edge termination region 2, ensuring a predetermined breakdown voltage for the edge termination region 2 based on the SiC breakdown field strength and depletion layer width. Furthermore, the FLR structure 20 distributes the electric field in the edge termination region 2, thereby improving the breakdown voltage of the edge termination region 2.

[0092] The electrons and holes accumulated inside the semiconductor substrate 10 along the parasitic capacitance when the SiC-MOSFET is turned on and off are discharged to the outside through the drain electrode 43 and the source electrode 41, respectively, during the switching transition from on to off or from off to on of the SiC-MOSFET and during reverse recovery of the parasitic diode formed at the main junction of the SiC-MOSFET. In addition, the steep dV / dt (drain-source voltage change per unit time) that occurs during the switching transition from on to off of the SiC-MOSFET causes the n - A displacement current (hole current) is generated in the type drift region 32 and flows toward the active region 1 .

[0093] The holes generated in the intermediate region 3 and the edge termination region 2 are p + The p-type base extension 52a, the p-type base extension 34a, and the p-type ++ The holes pass through the contact extension 36a and are drawn out from the contact holes 40a, 40b in the active region 1 to the source electrode 41. At this time, the holes are captured by the carrier lifetime killers in the low carrier lifetime region 71 and disappear, promoting the recombination of electrons and holes in the corner portions of the intermediate region 3. Therefore, the hole density in the corner portions of the intermediate region 3, where the hole path is narrower than in the straight portions of the intermediate region 3, can be reduced to the same level as the hole density in the straight portions of the intermediate region 3.

[0094] This makes it possible to suppress the concentration of hole current at the corner 1a of the active region 1, and therefore the p-type region (p ++ p-type contact extension 36a, p-type base extension 34a and p-type + Therefore, it is possible to prevent dielectric breakdown at the corners of the intermediate region 3 in the relatively thin portion of the insulating layer between the front surface of the semiconductor substrate 10 and the gate polysilicon wiring layer 62 (the insulating layer immediately below the inner portion 62b of the gate polysilicon wiring layer 62 where only the gate insulating film 38 is disposed).

[0095] Next, a method for manufacturing the silicon carbide semiconductor device 30 according to the first embodiment will be described. + A mold starting substrate (starting wafer) 11 is prepared. Next, + On the front surface of the starting mold substrate 11, n - n-type drift region 32 - Next, an n-type epitaxial layer 12 is epitaxially grown in the active region 1 by photolithography and ion implantation of p-type impurities. - The surface region of the first p-type epitaxial layer 12 + The mold region 51 and the second p + The lower part of the mold region 52 (n + The portion on the side of the gate electrode 31 and the portion on the side of the drain region 31 are selectively formed.

[0096] At this time, the second p + At the same time as the lower part of the mold region 52, the intermediate region 3 + The lower part of the n-type extension 52a is formed. Also, by photolithography and ion implantation of n-type impurities, n-type impurities are formed in the active region 1. - The lower part of the n-type current spreading region 33 is formed in the surface region of the n-type epitaxial layer 12. - The first and second p-type epitaxial layers 12 + Type region 51,52, p + The n-type extension 52a and the n-type current diffusion region 33 +The portion of the starting substrate 11 that is not ion-implanted and remains at the same impurity concentration is n - This becomes the type drift region 32.

[0097] Next, further epitaxial growth is performed to - The n-type epitaxial layer 12 is then grown to a predetermined thickness. Then, the n-type epitaxial layer 12 is grown by photolithography and ion implantation of p-type impurities. - The second p-type epitaxial layer 12 is formed in the thickened portion in the depth direction Z. + The second p is disposed adjacent to the lower portion of the mold region 52. + The upper part of the mold region 52 (n + The n-type source region 35 side portion is selectively formed by photolithography and ion implantation of n-type impurities. - The upper part of the n-type current diffusion region 33 is formed in the thickened portion of the n-type epitaxial layer 12 so as to be adjacent to the lower part of the n-type current diffusion region 33 in the depth direction Z.

[0098] At this time, the second p + At the same time as the upper part of the mold region 52, p + The mold extension 52a is adjacent to the lower part of the mold extension 52a. + Forms the upper part of the mold extension 52a. - The upper and lower portions adjacent to each other in the depth direction Z inside the epitaxial layer 12 are connected to each other to form a second p + the n-type region 52, the n-type current spreading region 33 and the p + The mold extensions 52a are formed respectively. - The order of ion implantation into the first epitaxially grown portion of the n-type epitaxial layer 12 can be reversed. - The order of ion implantation into the thickened portion of the type epitaxial layer 12 can be reversed.

[0099] Next, n - A p-type epitaxial layer 13 is epitaxially grown on the n-type epitaxial layer 12. +A semiconductor substrate (semiconductor wafer) 10 is completed by laminating epitaxial layers 12 and 13 in this order on a p-type starting substrate 11. Next, the portion of p-type epitaxial layer 13 on the edge termination region 2 side is removed by etching to form a step 14 on the front surface of semiconductor substrate 10, with the edge termination region 2 portion (second surface 10b) lower than the active region 1 and intermediate region 3 portion (first surface 10a). On second surface 10b, which now becomes the front surface of semiconductor substrate 10, an n - The epitaxial layer 12 is exposed.

[0100] The third surface 10c connecting the first surface 10a and the second surface 10b of the front surface of the semiconductor substrate 10 may be, for example, at an obtuse angle (inclined surface) to the first and second surfaces 10a and 10b, or at a substantially right angle (vertical surface) to the first and second surfaces 10a and 10b. The side surface of the p-type epitaxial layer 13 is exposed on the third surface 10c of the front surface of the semiconductor substrate 10. The portion of this p-type epitaxial layer 13 on the edge termination region 2 side is removed, and the n-type epitaxial layer 13 is exposed on the second surface 10b, which has become the new front surface of the semiconductor substrate 10. - By etching to expose the p-type epitaxial layer 12, the n-type epitaxial layer 13 is - A small surface region of the type epitaxial layer 12 may be removed.

[0101] Next, photolithography and ion implantation under predetermined conditions are repeatedly performed to form n + type source region 35 and p ++ The p-type contact regions 36 are selectively formed. ++ The p-type contact region 36 ++ The n-type contact extension 36a is formed in the p-type epitaxial layer 13. + Type source region 35, p ++ type contact region 36 and p ++ n than the type contact extension 36a + The portions of the starting substrate 11 that are not ion-implanted and remain with the same impurity concentration become the p-type base region 34 and the p-type base extension 34a.

[0102] In addition, photolithography and ion implantation under predetermined conditions are repeatedly performed to form n-type silicon nitride (nN) oxides exposed on second surface 10b of the front surface of semiconductor substrate 10 in edge termination region 2. - The surface region of the epitaxial layer 12 is provided with a plurality of p - Type region 21 and n + The n-type channel stopper region 22 is selectively formed in the edge termination region 2. - The p-type epitaxial layer 12 - Type regions 21 and n + n type channel stopper region 22 + The portion of the starting substrate 11 that is not ion-implanted and remains at the same impurity concentration is n - This becomes the type drift region 32.

[0103] For the ion implantation of the n-type impurities (donors) described above, dopants such as phosphorus (P), nitrogen (N), and arsenic (As) can be used. For the ion implantation of the p-type impurities (acceptors) described above, dopants such as aluminum can be used. Next, a heat treatment (activation annealing) is performed to activate the impurities ion-implanted into the semiconductor substrate 10 (epitaxial layers 12 and 13). This activation annealing may be performed once after all of the ion implantations described above have been performed, or may be performed after each ion implantation.

[0104] Next, impurities that act as carrier lifetime killers are introduced only into the corners of the intermediate region 3 by photolithography and ion implantation or irradiation, thereby forming low carrier lifetime regions 71 in the surface region of the front surface of the semiconductor substrate 10 at the corners of the intermediate region 3. The low carrier lifetime regions 71 may be formed at any timing between the deposition of the p-type epitaxial layer 13 and the formation of the gate trench 37, which will be described later. + The portion overlapping the p-type extension 52a is formed as an n-type epitaxial layer before the deposition of the p-type epitaxial layer 13. - Alternatively, the semiconductor layer 12 may be formed inside the semiconductor layer 12 .

[0105] Next, by photolithography and etching, n-type semiconductor substrate 10 is formed on the front surface thereof. + The first p-type source region 35 and the p-type base region 34 are formed in the n-type current diffusion region 33 and terminate inside the n-type current diffusion region 33. + A gate trench 37 is formed facing the mold region 51. A plurality of gate trenches 37 are formed in a stripe pattern extending in the first direction X. The longitudinal ends of the gate trenches 37 are terminated inside the intermediate region 3. Next, a gate insulating film 38 is formed over the entire front surface of the semiconductor substrate 10 and along the inner walls (side walls and bottom surfaces) of the gate trenches 37.

[0106] Next, a field oxide film 61 is deposited on the gate insulating film 38 on the front surface of the semiconductor substrate 10. Next, the portion of the field oxide film 61 in the active region 1 is removed by photolithography and, for example, wet etching, leaving only the intermediate region 3 and the edge termination region 2. In addition, the position of the inner end 61a of the field oxide film 61 is set so that the field oxide film 61 does not cover at least a portion of the end of the gate trench 37. Next, a polysilicon layer is deposited over the entire front surface of the semiconductor substrate 10 so as to fill the gate trench 37.

[0107] Next, the polysilicon layer is selectively removed by photolithography and etching, leaving a portion of the polysilicon layer that will become the gate electrode 39 inside the gate trench 37, and leaving a portion that will become the gate polysilicon wiring layer 62 and a portion that will become the gate polysilicon wiring layer that constitutes the gate pad 64 on the outermost surface of the front surface of the semiconductor substrate 10. At this time, the polysilicon layer is left so as to cover the longitudinal ends of the gate trench 37, so that the gate polysilicon wiring layer 62 and the gate electrode 39 are connected.

[0108] Next, an interlayer insulating film 40 is formed over the entire front surface of the semiconductor substrate 10, covering the gate electrode 39, the gate polysilicon wiring layer 62, and the gate polysilicon wiring layer that constitutes the gate pad 64. Next, photolithography and etching are used to form contact holes 40a and 40b in the active region 1, penetrating the interlayer insulating film 40 and the gate insulating film 38 in the depth direction Z to reach the front surface of the semiconductor substrate 10. The contact hole 40a contains n + type source region 35 and p ++ The outermost contact hole 40b is filled with p ++ The mold contact extensions 36a are exposed.

[0109] Furthermore, photolithography and etching are used to form a contact hole 40c in the intermediate region 3, penetrating the interlayer insulating film 40 in the depth direction Z to reach the gate polysilicon wiring layer 62, and a contact hole (not shown) reaching the gate polysilicon wiring layer constituting the gate pad 64. Next, the interlayer insulating film 40 is planarized (reflowed) by heat treatment. Next, a metal layer is formed over the entire front surface of the semiconductor substrate 10 so as to fill the contact holes. Next, the metal layer is patterned to leave portions that will become the source electrode 41, the gate metal wiring layer 63, and the gate metal wiring layer that constitutes the gate pad 64.

[0110] The source electrode 41 is in ohmic contact with the front surface of the semiconductor substrate 10 inside the contact holes 40a and 40b. The source electrode 41 is disposed apart from the gate metal wiring layer 63 and the gate metal wiring layer that constitutes the gate pad 64. The gate metal wiring layer 63 contacts the gate polysilicon wiring layer 62 at the contact hole 40c. The gate metal wiring layer that constitutes the gate pad 64 contacts the gate polysilicon wiring layer that constitutes the gate pad 64 at a contact hole (not shown). The gate metal wiring layer 63 and the gate metal wiring layer that constitutes the gate pad 64 are connected to each other.

[0111] Furthermore, a drain electrode 43 is formed on the back surface of the semiconductor substrate 10. Next, a passivation film 42 is formed over the entire front surface of the semiconductor substrate 10, and the passivation film 42 covers the gate metal wiring layer that constitutes the source electrode 41, the gate metal wiring layer 63, and the gate pad 64. Next, the passivation film 42 is selectively removed to form different openings, which expose the source electrode 41 (source pad) and the gate pad 64, respectively. Thereafter, the semiconductor substrate 10 (semiconductor wafer) is diced (cut) into individual chips, thereby completing the MOSFETs (silicon carbide semiconductor devices 30) shown in FIGS. 1 to 6.

[0112] As described above, according to the first embodiment, a low carrier lifetime region is provided facing the gate polysilicon wiring layer in the depth direction so as to overlap the p-type region in the surface region of the front surface of the semiconductor substrate at the corner portion of the intermediate region between the active region and the edge termination region. No low carrier lifetime region is provided in the linear portion of the intermediate region. As a result, the p-type region (p + p-type extension, p-type base extension and p-type ++ The average time until holes flowing through the mold contact extension toward the active region disappear can be made shorter at the corner portions of the intermediate region than at the straight portion of the intermediate region.

[0113] By providing a low-carrier lifetime region at the corner of the intermediate region, the hole density at the corner of the intermediate region, where the hole path is narrower than the linear portion of the intermediate region, can be set to be approximately the same as the hole density at the linear portion of the intermediate region, thereby suppressing hole current concentration at the corner of the active region. This suppresses the potential rise at the corner of the intermediate region in the p-type region, which serves as a hole path in the intermediate region. This prevents dielectric breakdown at the corner of the intermediate region in the relatively thin portion (gate insulating film) of the insulating layer between the front surface of the semiconductor substrate and the gate polysilicon wiring layer.

[0114] For example, if the gate resistance Rg is adjusted high as in the past, not only does the amount of hole current decrease along the path of holes extracted to the source electrode through the SiC portion directly below the gate runner in the intermediate region, but also the amount of hole current decreases along the path of holes discharged to the source electrode through the portion along the gate trench in the active region. This results in degradation of the switching characteristics of the SiC-MOSFET (decreased switching speed and increased switching loss). Specifically, the gate resistance Rg was adjusted so that the steep dV / dt that occurs during the switching transition from on to off or off to on of the SiC-MOSFET and during reverse recovery of the SiC-MOSFET's parasitic diode is, for example, 20 kV / μsec.

[0115] The inventors have confirmed that with the conventional structure (see Figures 11 to 13), high-speed switching with dV / dt exceeding 20 kV / μsec causes dielectric breakdown of the gate insulating film at the corners of the active region. Furthermore, the inventors have confirmed that when the internal inductance of a semiconductor package is 10 nH or more, high-speed switching with dV / dt exceeding 20 kV / μsec occurs in a SiC-MOSFET chip (semiconductor chip) mounted in the semiconductor package, the voltage and current waveforms in the various components of the semiconductor package oscillate, the various components of the semiconductor package turn on (malfunction) at unintended times, and operational problems with the semiconductor package occur.

[0116] In contrast, according to the first embodiment, by providing a low carrier lifetime region in the corner of the intermediate region, it is possible to reduce the hole density in the hole path in the corner of the intermediate region. Therefore, it is not necessary to increase the gate resistance Rg in order to reduce the hole density in the hole path, and it is possible to suppress deterioration of the switching characteristics. It is also possible to improve the dV / dt tolerance of the corner of the active region where hole current tends to concentrate. It is also not necessary to increase the chip size to reduce forward loss, and it is possible to suppress an increase in cost. Therefore, it is possible to provide a SiC-MOSFET that has high dielectric breakdown tolerance, excellent switching characteristics, and suppresses an increase in cost.

[0117] (Embodiment 2) The structure of a silicon carbide semiconductor device according to the second embodiment will be described. Figures 7 to 10 are cross-sectional views showing the structure of a silicon carbide semiconductor device according to the second embodiment. The layout of a silicon carbide semiconductor device 70 according to the second embodiment, as viewed from the front surface side of a semiconductor substrate 10 (see Figures 1 and 2), and the configuration of a low carrier lifetime region (hereinafter referred to as a first low carrier lifetime region) 71 are the same as those of the first embodiment. Figures 7 to 10 show cross-sectional structures taken along the cutting lines A-A', B-B', C-C', and D-D' in Figure 2, respectively.

[0118] The silicon carbide semiconductor device 70 according to the second embodiment differs from the silicon carbide semiconductor device 30 according to the first embodiment (see FIGS. 3 to 6) in that a second low carrier lifetime region 72 (hatched portion) is further provided. The second low carrier lifetime region 72 is a region between the main junction (first and second p + The p-type regions 51 and 52 and the p-type base region 34, and the n-type current diffusion region 33 and the n - The pn junction between the pn junction and the pn drift region 32 functions to suppress deterioration of the parasitic diode formed.

[0119] The second low carrier lifetime region 72 is formed by disposing all of the first and second p-type carriers in the active region 1. + Type regions 51, 52 and n - The second low carrier lifetime region 72 is provided between the first and second p-type drift regions 32 and in contact with these regions. + The JFET (Junction FET) region between the n-type regions 51 and 52 - The second low carrier lifetime region 72 is not provided between the p-type drift region 32 and the intermediate region 3. + Mold extensions 52a and n - The metal layer 34 is provided in contact with the mold drift region 32 over the entire area between the metal layer 34 and the mold drift region 32 .

[0120] That is, the second low carrier lifetime region 72 is provided so as not to face the JFET region in the depth direction Z, and + Type regions 51, 52 and p + Mold extensions 52a and n - The first low carrier lifetime region 71 is in contact with the entire pn junction surface with the n-type drift region 32. + n-type drain region 31 side - When the second low carrier lifetime region 72 is provided at a depth that reaches the type drift region 32, the second low carrier lifetime region 72 contacts the first low carrier lifetime region 71 in the depth direction.

[0121] The second low carrier lifetime region 72 is a region into which an impurity that acts as a carrier lifetime killer is introduced. The carrier lifetime killer introduced to form the second low carrier lifetime region 72 can be an impurity that is used as a carrier lifetime killer in IGBTs, diodes, etc., such as helium, protons, or vanadium. The carrier lifetime killers introduced into the first and second low carrier lifetime regions 71 and 72 may be the same ion species.

[0122] The second low carrier lifetime region 72 is doped with a carrier lifetime killer at a dose that is smaller than the dose of the carrier lifetime killer doped in the first low carrier lifetime region 71. For example, the dose of the second low carrier lifetime region 72 is smaller than the dose of the carrier lifetime killer doped in the first low carrier lifetime region 71. 71 The width of the second low carrier lifetime region 72 is, for example, 5% or more and 50% or less of the first and second p regions adjacent to each other in the depth direction Z. + Type regions 51, 52 and p + The width may be substantially the same as that of the mold extension portion 52a. "Substantially the same width" means that the width is the same within a range including tolerances due to process variations.

[0123] The method for manufacturing silicon carbide semiconductor device 70 according to the second embodiment is the method for manufacturing silicon carbide semiconductor device 30 according to the first embodiment, plus the step of forming second low carrier lifetime region 72. Second low carrier lifetime region 72 may be formed immediately after, before, or after the formation of first low carrier lifetime region 71, or may be formed at a different timing from the formation of first low carrier lifetime region 71. Furthermore, first and second low carrier lifetime regions 71 and 72 may be formed under the same ion implantation conditions (irradiation conditions).

[0124] When the same ion implantation conditions (irradiation conditions) are used, the dose of each carrier lifetime killer introduced into the first and second low carrier lifetime regions 71 and 72 can be adjusted by, for example, increasing the number of ion implantations (irradiations) when forming the first low carrier lifetime region 71 compared to when forming the second low carrier lifetime region 72, or by covering the formation region of the second low carrier lifetime region 72 with a mask so that the amount of ion implantation (irradiation) in the second low carrier lifetime region 72 is less than when forming the first low carrier lifetime region 71.

[0125] As described above, according to the second embodiment, it is possible to obtain the same effects as those of the first embodiment. Furthermore, according to the second embodiment, when the parasitic diode formed at the main junction of the SiC-MOSFET operates, holes are captured by the carrier lifetime killer in the second low carrier lifetime region and disappear, so that n - This promotes the recombination of electrons and holes in the type drift region, which reduces the forward current of the SiC-MOSFET's parasitic diode and suppresses the expansion of stacking faults in the epitaxial layer, resulting in a highly reliable SiC-MOSFET with minimal fluctuation in characteristics over time.

[0126] The present invention is not limited to the above-described embodiments, and various modifications are possible without departing from the spirit of the present invention. For example, a current sensor may be disposed on the same semiconductor substrate as a SiC-MOSFET, which serves as a main semiconductor element. The current sensor is a SiC-MOSFET with the same structure as the main semiconductor element, and is connected in parallel to the main semiconductor element to detect overcurrent (OC) flowing through the main semiconductor element. The current sensor may be disposed, for example, in a linear portion of the intermediate region, or in an ineffective region in which part of the active region is not used as the main semiconductor element. The present invention is also applicable when a planar gate structure is used instead of a trench gate structure. The present invention is also applicable when the conductivity type (n-type, p-type) is reversed. [Industrial Applicability]

[0127] As described above, the silicon carbide semiconductor device according to the present invention is useful as a power semiconductor device for controlling high voltages and large currents. [Explanation of symbols]

[0128] 1 active area 2 Edge Termination Area 3 Intermediate area 10. Semiconductor substrate 10a to 10c: first to third surfaces of the front surface of the semiconductor substrate 11n + Starting substrate 12n - Type epitaxial layer 13 p-type epitaxial layer 14 Steps on the front surface of the semiconductor substrate 20 FLR structure 21 p that constitutes the FLR structure - type area 22n + Type channel stopper region 30,70 Silicon carbide semiconductor device 31n + Type drain region 32n - Type Drift Region 33 n-type current diffusion region 34 p-type base region 34a p type base extension 35n + Type Source Area 36 pages ++ Mold contact area 36a p ++ Type contact extension 37 Gate Trench 38 Gate insulating film 39 Gate electrode 40 Interlayer insulating film 40a, 40b, 40c: contact holes in interlayer insulating film 41 Source electrode 42 Passivation film 43 Drain electrode 51,52 The p-type gate insulating film at the bottom of the gate trench is used to reduce the electric field. + type area 52a p + Mold extension 61 Field oxide 61a Inner edge of field oxide 62 Gate polysilicon wiring layer 62a Inner end of gate polysilicon wiring layer 62b Inner portion of gate polysilicon wiring layer 63 Gate metal wiring layer 64 Gate Pad 71,72 Low carrier lifetime region X: the first direction parallel to the front surface of the semiconductor substrate Y: A second direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction Z depth direction

Claims

1. an active region through which a main current flows, the active region being provided in a rectangular planar shape on a semiconductor substrate made of silicon carbide; a termination region surrounding the active region; an intermediate region between the active region and the termination region; a first semiconductor region of a first conductivity type provided inside the semiconductor substrate; a second semiconductor region of a second conductivity type provided between the first main surface of the semiconductor substrate and the first semiconductor region, spanning from the active region to the intermediate region; a third semiconductor region of the first conductivity type selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region in the active region; a gate insulating film provided in contact with a region of the second semiconductor region between the first semiconductor region and the third semiconductor region and covering the first main surface of the semiconductor substrate; a gate electrode provided on a region of the second semiconductor region between the first semiconductor region and the third semiconductor region via the gate insulating film; a fourth semiconductor region of a second conductivity type provided in the intermediate region between the first main surface of the semiconductor substrate and the second semiconductor region and having a higher impurity concentration than the second semiconductor region; a field oxide film provided on the gate insulating film of the first main surface of the semiconductor substrate in the intermediate region; a gate polysilicon wiring layer provided on the field oxide film, surrounding the active region, connected to the gate electrode at an inner end thereof, and facing the fourth semiconductor region via the field oxide film and the gate insulating film in a depth direction; an interlayer insulating film covering the gate electrode and the gate polysilicon wiring layer; a contact hole that penetrates the interlayer insulating film in a depth direction and exposes the first main surface of the semiconductor substrate; a first electrode electrically connected to the second semiconductor region, the third semiconductor region, and the fourth semiconductor region via the contact hole; a second electrode provided on a second main surface of the semiconductor substrate; Equipped with the gate polysilicon wiring layer extends inward beyond an inner end of the field oxide film, and faces the fourth semiconductor region in the depth direction at an inner portion thereof, with only the gate insulating film interposed therebetween; a first low carrier lifetime region, into which a first carrier lifetime killer is introduced, provided in the intermediate region at a portion adjacent to a corner of the active region, the first low carrier lifetime region facing the gate polysilicon wiring layer in the depth direction and overlapping the fourth semiconductor region.

2. 2 . The silicon carbide semiconductor device according to claim 1 , wherein the first low carrier lifetime region is provided apart from the third semiconductor region.

3. 3 . The silicon carbide semiconductor device according to claim 1 , wherein the first low carrier lifetime region reaches an outer edge of the fourth semiconductor region. 4 .

4. 4. The silicon carbide semiconductor device according to claim 1, wherein the first low carrier lifetime region is provided to overlap the fourth semiconductor region and the second semiconductor region in a depth direction.

5. a trench extending in a depth direction from the first main surface of the semiconductor substrate through the third semiconductor region and the second semiconductor region to reach the first semiconductor region, and extending linearly in a direction parallel to the first main surface of the semiconductor substrate from the active region to the intermediate region; the gate electrode is provided in the trench via the gate insulating film and is connected to the gate polysilicon wiring layer at an end of the trench in a longitudinal direction; 5. The silicon carbide semiconductor device according to claim 1, wherein the first low carrier lifetime region is provided away from the trench.

6. a first high concentration region of a second conductivity type having an impurity concentration higher than that of the second semiconductor region, the first high concentration region being selectively provided at a position deeper than a bottom surface of the trench, spaced apart from the second semiconductor region and in contact with the first semiconductor region, and facing the bottom surface of the trench in a depth direction; a second heavily doped region of a second conductivity type having an impurity concentration higher than that of the second semiconductor region, the second heavily doped region being selectively provided in the active region between the second semiconductor region and the first semiconductor region, away from the first heavily doped region and the trench and in contact with the second semiconductor region and the first semiconductor region, the second heavily doped region reaching a position deeper than a bottom surface of the trench; a third heavily doped region of a second conductivity type having an impurity concentration higher than that of the second semiconductor region, the third heavily doped region being provided in contact with the second semiconductor region and the first semiconductor region in the intermediate region and reaching a position deeper than a bottom surface of the trench; Furthermore, 6. The silicon carbide semiconductor device according to claim 5, wherein the first low carrier lifetime region is provided to overlap the fourth semiconductor region, the second semiconductor region, and the third high concentration region in the depth direction.

7. 7. The silicon carbide semiconductor device according to claim 1, wherein the first carrier lifetime killer is helium, proton or vanadium.

8. 1×10 11 / cm 2 1x10 or more 12 / cm 2 8. The silicon carbide semiconductor device according to claim 1, wherein the first carrier lifetime killer is introduced at a dose of:

9. 7. The silicon carbide semiconductor device according to claim 6, wherein second low carrier lifetime regions into which a second carrier lifetime killer is introduced are provided between the first high concentration region, the second high concentration region, and the third high concentration region and the first semiconductor region, respectively.

10. 10. The silicon carbide semiconductor device according to claim 9, wherein the first carrier lifetime killer is introduced into the first low carrier lifetime region at a dose higher than a dose of the second carrier lifetime killer introduced into the second low carrier lifetime region.

11. 11. The silicon carbide semiconductor device according to claim 9, wherein the second carrier lifetime killer is helium, proton or vanadium.

12. the first electrode extends over the interlayer insulating film to the intermediate region; 12. The silicon carbide semiconductor device according to claim 1, wherein the first low carrier lifetime region faces the first electrode in a depth direction via the interlayer insulating film.

Images