Semiconductor device manufacturing method

Abstract

To suppress a characteristic change of a semiconductor device, in the manufacture of the semiconductor device.SOLUTION: Provided is a manufacturing method of a semiconductor device including a semiconductor substrate having an upper surface. The manufacturing method includes: a trench formation step of forming a trench on the upper surface of the semiconductor substrate; a material arrangement step of arranging a surface treatment material on the upper surface of the semiconductor substrate and the surface of the trench; a resist application step of applying a resist to an interior of the trench; and a patterning step of exposing the resist using a mask to leave the resist in the interior of the trench predetermined. Surface free energy of solids of the surface treatment material is less than surface free energy of liquids of the resist.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] BACKGROUND ART Conventionally, in the manufacturing method of a semiconductor device, there is known a technique relating to a method for filling a trench groove having a high aspect ratio, such as forming a trench isolation region in a semiconductor substrate (see, for example, Patent Document 1). Patent Document 1: Japanese Patent Application Laid-Open No. 2004-363615 Summary of the Invention [Problem to be solved by the invention]

[0003] In the manufacture of semiconductor devices, it is preferable to suppress fluctuations in the characteristics of the semiconductor devices. [Means for solving the problem]

[0004] In order to solve the above-mentioned problems, one aspect of the present invention provides a method for manufacturing a semiconductor device. The semiconductor device may include a semiconductor substrate having an upper surface. The method for manufacturing a semiconductor device may include a trench formation step. In the trench formation step, a trench may be formed in the upper surface of the semiconductor substrate. The method for manufacturing a semiconductor device may include a material disposing step. In the material disposing step, a surface treatment material may be disposed on the upper surface of the semiconductor substrate and the surface of the trench. The method for manufacturing a semiconductor device may include a resist application step. In the resist application step, resist may be applied inside the trench. The method for manufacturing a semiconductor device may include a patterning step. In the patterning step, the resist may be exposed using a mask to leave the resist inside a predetermined trench. The solid surface free energy of the surface treatment material may be lower than the liquid surface free energy of the resist.

[0005] The solid surface free energy of the surface treatment material may be 20 mN / m or less.

[0006] The viscosity of the surface treatment material may be 10 cP or less.

[0007] The thickness of the surface treatment material may be 0.1 μm or more and 0.3 μm or less.

[0008] The thickness of the resist may be 25% or more of the depth of the trench.

[0009] In the material disposing step, the surface treatment material may be applied and solidified. In the material disposing step, the surface treatment material may be vapor-deposited.

[0010] The method for manufacturing a semiconductor device may include an ion implantation step. In the ion implantation step, ions may be implanted into an upper surface of a semiconductor substrate. The method for manufacturing a semiconductor device may include a resist removal step. In the resist removal step, the resist may be removed. The method for manufacturing a semiconductor device may include a material removal step. In the material removal step, the surface treatment material may be removed. Each step from the material placement step to the material removal step may be performed at a temperature of 200°C or less.

[0011] The method for manufacturing a semiconductor device may include a heat treatment step after the resist removal step and the material removal step, in which the semiconductor substrate is heat treated at 500° C. or higher.

[0012] The resist may be a negative resist.

[0013] The trench may have a tapered shape.

[0014] The trench may have an extension portion extending in a predetermined direction and a connection portion connecting the extension portions. During the trench formation step, the connection portion may be formed deeper than the extension portion.

[0015] In the trench formation step, a dummy trench may be formed outside the trench in the semiconductor substrate.

[0016] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions. [Brief explanation of the drawings]

[0017] [Figure 1] 10 is a diagram illustrating a comparative example of a flowchart of a method for manufacturing the semiconductor device 100. FIG. [Figure 2] 10A to 10C are diagrams illustrating a comparative example of a method for manufacturing the semiconductor device 100. [Figure 3] 10A to 10C are diagrams illustrating a comparative example of a method for manufacturing the semiconductor device 100. [Figure 4] 1 is a diagram illustrating an example of a flowchart of a method for manufacturing the semiconductor device 100. FIG. [Figure 5] 2A to 2C are diagrams illustrating an embodiment of a method for manufacturing the semiconductor device 100. [Figure 6] 2A to 2C are diagrams illustrating an embodiment of a method for manufacturing the semiconductor device 100. [Figure 7] 1 is a diagram illustrating the solid surface free energy of a surface treatment material 80 and the liquid surface free energy of a resist 130. FIG. [Figure 8] 10A to 10C are diagrams illustrating another example of the method for manufacturing the semiconductor device 100. [Figure 9] FIG. 10 is a diagram showing an example of the arrangement of trenches 45. [Figure 10] FIG. 10 is a cross-sectional view of FIG. 9 . [Figure 11] FIG. 10 is a view showing a cross section bb of FIG. 9. [Figure 12] FIG. 10 is a diagram showing another example of the arrangement of trenches 45. [Figure 13] FIG. 13 is a view showing the cc cross section of FIG. [Figure 14] FIG. 13 is a view showing a cross section dd of FIG. [Figure 15] 10A and 10B are diagrams illustrating trenches 45 and dummy trenches 35. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0018] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention. In this specification and drawings, elements having substantially the same function and configuration are designated by the same reference numerals to avoid redundant description, and elements not directly related to the present invention are not shown. Furthermore, in a single drawing, elements having the same function and configuration may be designated by the same reference numeral, and the reference numerals may be omitted for other elements.

[0019] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor module is mounted.

[0020] In this specification, technical matters may be described using orthogonal coordinate axes, i.e., the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. The +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is referred to without specifying positive or negative, it means a direction parallel to the +Z-axis and the -Z-axis. In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, the axis perpendicular to the top and bottom surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0021] In this specification, when we say "same" or "equal," it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0022] 1 is a diagram illustrating a comparative example of a flowchart of a method for manufacturing a semiconductor device 100 (see FIG. 2). The method for manufacturing the semiconductor device 100 includes a trench formation step S101, a resist application step S102, a resist exposure step S103, a resist development step S104, an ion implantation step S105, a resist removal step S106, an oxide film removal step S107, and a heat treatment step S108.

[0023] 2 and 3 are diagrams illustrating a comparative example of a manufacturing method for semiconductor device 100. Fig. 2 illustrates trench formation step S101, resist application step S102, resist exposure step S103, and resist development step S104. Fig. 3 illustrates ion implantation step S105, resist removal step S106, oxide film removal step S107, and heat treatment step S108.

[0024] The semiconductor device 100 functions as a power conversion device such as an inverter, for example. The semiconductor device 100 may include an insulated gate bipolar transistor (IGBT), a diode such as an FWD (Free Wheel Diode), a combination of these such as an RC (Reverse Conducting)-IGBT, and a MOS transistor. The semiconductor device 100 is not limited to these examples.

[0025] The semiconductor device 100 is provided on a semiconductor substrate 10. Therefore, the semiconductor device 100 includes the semiconductor substrate 10. In this example, the semiconductor substrate 10 is a wafer that is approximately circular in shape when viewed from above. The semiconductor substrate 10 is a substrate made of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate, but the material of the semiconductor substrate 10 is not limited to silicon. The semiconductor substrate 10 also has an upper surface 21 and a lower surface (not shown). FIG. 2 shows a portion of the upper surface 21 of the semiconductor substrate 10.

[0026] The upper surface 21 of the semiconductor substrate 10 may be a surface on which a gate structure such as an IGBT or a MOS transistor is formed. The gate structure includes at least one of a gate electrode, a gate insulating film, a source region, an emitter region, and a channel region. The upper surface 21 of the semiconductor substrate 10 may be a so-called device surface.

[0027] In the trench formation step S101, trenches 45 are formed in the upper surface 21 of the semiconductor substrate 10. The trenches 45 are, for example, grooves in which gate electrodes of a gate structure are formed. The trenches 45 may be formed by etching. The trenches 45 may be etched by a known method. For example, the trenches 45 are formed by dry etching. A mesa portion 60 is provided between adjacent trenches 45. For example, the width W1 of the trenches 45 is 1 μm or less.

[0028] Also, in the trench formation step S101, an oxide film 30 is formed. In this example, the oxide film 30 is formed on the upper surface 21 of the semiconductor substrate 10 and the surface of the trench 45. In this specification, the surface of the trench 45 includes the sidewalls and bottom of the trench 45. The oxide film 30 may be a thermal oxide film. The oxide film 30 may be formed by a known method. By forming the oxide film 30 on the upper surface 21 of the semiconductor substrate 10 and the surface of the trench 45, metal contamination and channeling due to ion implantation can be prevented.

[0029] In the resist application step S102, a resist 130 is applied to the upper surface 21 of the semiconductor substrate 10 and the inside of the trench 45. In this example, the resist 130 is a negative resist. The resist 130 may include a photosensitive material.

[0030] In the resist exposure step S103, the resist 130 is exposed. In this example, the resist 130 is exposed to ultraviolet light. In addition, in the resist exposure step S103, the resist 130 is exposed using a mask 160. Because the resist 130 is a negative resist, it is possible to reduce the solubility of the exposed portions in a developer.

[0031] In the resist developing step S104, the resist 130 is developed. For example, the resist 130 is developed using a developer. The developer is, for example, an alkaline chemical. The developer may also be an organic solvent. Since the solubility of the exposed portions is reduced, the resist 130 can be patterned. In the resist developing step S104, the resist is left inside the predetermined trenches 45. The resist exposure step S103 and the resist developing step S104 are examples of patterning steps.

[0032] The thickness of the resist 130 provided on the mesa portion 60 is about 1 μm, while the thickness of the resist 130 provided on the trench 45 is about 5 μm or more. Therefore, there is a risk of resist cracking due to the difference in the thickness of the provided resist. In this example, to prevent cracking of the resist 130, it is preferable that the resist 130 is not provided on the mesa portion 60-1 and the mesa portion 60-2.

[0033] In this example, the resist 130 is patterned so as to be provided in the trenches 45-1 and 45-2. The resist 130 has a positional error of 0.1 μm to 0.3 μm, and variation must be ensured. To ensure variation, in this example, the resist 130 is provided on the mesa portion 60-1 near the trench 45-1 and the mesa portion 60-1 near the trench 45-2. Furthermore, the resist 130 is provided on the mesa portion 60-2 near the trench 45-1.

[0034] In the ion implantation step S105, ions are implanted into the upper surface 21 of the semiconductor substrate 10. In this example, a P-type dopant such as boron is implanted into the upper surface 21 of the semiconductor substrate 10. The acceleration energy of the ion implantation is, for example, about 150 keV. The dose of the ion implantation is, for example, 3×10 -13 atoms / cm 2 By implanting a P-type dopant, the P-type region 50 can be formed. The ion implantation may be performed by an ion implanter.

[0035] In the resist removal step S106, the resist 130 is removed. The resist 130 may be removed by oxygen plasma or by a chemical solution.

[0036] In the oxide film removing step S107, the oxide film 30 formed in the trench forming step S101 is removed. The oxide film 30 may be removed using a chemical solution such as hydrofluoric acid.

[0037] In the heat treatment step S108, the semiconductor substrate 10 is heat treated. In this example, the semiconductor substrate 10 is heat treated at 500°C or higher (for example, 1000°C). By heat treating the semiconductor substrate 10, it is possible to diffuse the ion species in the P-type region 50. By providing the P-type region 50 at the bottom of the trench 45, it is possible to improve characteristics such as turn-on loss.

[0038] In this example, an undiffused region 70 is formed in the mesa portion 60-1 and the mesa portion 60-2. The undiffused region 70 is a region in which the P-type region 50 is not formed. The undiffused region 70 is formed because a resist 130 is provided on a portion of the mesa portion 60-1 and the mesa portion 60-2 during the patterning stage. If the undiffused region 70 is formed on the upper surface 21 of the semiconductor substrate 10, there is a risk that the characteristics of the semiconductor device 100 will fluctuate. In order to prevent the characteristics of the semiconductor device 100 from fluctuating, it is preferable that the undiffused region 70 is not formed on the upper surface 21 of the semiconductor substrate 10.

[0039] 4 is a diagram illustrating an example of a flowchart of a method for manufacturing the semiconductor device 100. The method for manufacturing the semiconductor device 100 includes a trench formation step S201, a material placement step S209, a resist application step S202, a resist exposure step S203, a resist development step S204, an ion implantation step S205, a resist removal step S206, a material removal step S210, an oxide film removal step S207, and a heat treatment step S208.

[0040] 5 and 6 are diagrams illustrating an embodiment of a method for manufacturing semiconductor device 100. In FIG. 5, trench formation step S201, material placement step S209, resist application step S202, resist exposure step S203, and resist development step S204 are illustrated. In FIG. 6, ion implantation step S205, resist removal step S206, material removal step S210, oxide film removal step S207, and heat treatment step S208 are illustrated. Trench formation step S201 may be the same as trench formation step S101 in FIG. 2.

[0041] In material disposing step S209, a surface treatment material 80 is disposed on the upper surface 21 of the semiconductor substrate 10 and the surface of the trench 45. The surface treatment material 80 is a material that lowers the solid surface free energy of the surface of the semiconductor substrate 10. In this example, the solid surface free energy of the surface treatment material 80 is lower than the liquid surface free energy of the resist 130. The solid surface free energy of the surface treatment material 80 may be lower than the solid surface free energy of the upper surface 21 of the semiconductor substrate 10. The solid surface free energy of the surface treatment material 80 may be lower than the solid surface free energy of the oxide film 30. In order to lower the solid surface free energy of the surface treatment material 80, the surface treatment material 80 is preferably a material with a high carbon-fluorine bond content.

[0042] The solid surface free energy of the surface treatment material 80 may be 20 mN / m or less. The solid surface free energy of the surface treatment material 80 may be 10 mN / m or less. By setting the solid surface free energy of the surface treatment material 80 to 20 mN / m or less, the solid surface free energy of the surface treatment material 80 can be made lower than the liquid surface free energy of the resist 130. The liquid surface free energy of the resist 130 may be 40 mN / m or less.

[0043] The viscosity of the surface treatment material 80 may be 10 cP or less. The viscosity of the surface treatment material 80 may be 5 cP or less. By making the viscosity of the surface treatment material 80 10 cP or less, the thickness T1 at which the surface treatment material 80 is applied can be reduced. By reducing the thickness T1 at which the surface treatment material 80 is applied, the surface treatment material 80 can be easily removed in the material removal step S210. The viscosity of the surface treatment material 80 is adjusted by adding an organic solvent to the surface treatment material 80.

[0044] The thickness T1 of the surface treatment material 80 may be 0.1 μm or more and 0.3 μm or less. By setting the thickness T1 of the surface treatment material 80 to 0.1 μm or more and 0.3 μm or less, fluctuations in the characteristics of the semiconductor device 100 can be suppressed and the surface treatment material 80 can be easily removed in the material removal step S210.

[0045] The surface treatment material 80 may be deposited by spin coating. The surface treatment material 80 may also be deposited by a common application method such as bar coating, slit coating, dispensing, or screen printing. In material deposition step S209, the surface treatment material 80 may be applied and solidified. In material deposition step S209, the surface treatment material 80 may be vapor deposited. Alternatively, the surface treatment material 80 may be deposited by vapor deposition.

[0046] In resist application step S202, resist 130 is applied inside trench 45. In this example, since surface treatment material 80 is disposed on upper surface 21 of semiconductor substrate 10 and the surface of trench 45, resist 130 on upper surface 21 of semiconductor substrate 10 flows. Therefore, unlike resist application step S102 in FIG. 2, resist 130 is not provided on mesa portion 60. Furthermore, resist 130 may be provided at a position higher than upper surface 21 of semiconductor substrate 10. Note that, since resist 130 on upper surface 21 of semiconductor substrate 10 flows, it is preferable to keep semiconductor substrate 10 still for 10 minutes or more.

[0047] The thickness T2 of the resist 130 may be 25% or more of the depth D5 of the trench 45. The thickness T2 of the resist 130 may be the maximum thickness of the resist 130. The depth D5 of the trench 45 may be the maximum depth of the trench 45. In this example, the thickness T2 of the resist 130 is equal to or greater than the depth D5 of the trench 45. That is, at least a portion of the resist 130 is provided at a position higher in the height direction than the upper surface 21 of the semiconductor substrate 10.

[0048] In the resist exposure step S203, the resist 130 is exposed. In this example, the resist 130 is exposed to ultraviolet light. In the resist exposure step S203, the resist 130 is exposed using a mask 160. Because the resist 130 is a negative resist, the solubility of the exposed portions in a developer can be reduced.

[0049] In the resist development step S204, the resist 130 is developed. For example, the resist 130 is developed using a developer. The developer is, for example, an alkaline chemical. The developer may also be an organic solvent. Since the solubility of the exposed portions is reduced, the resist 130 can be patterned. In the resist development step S204, the resist is left inside the predetermined trenches 45. The resist exposure step S203 and the resist development step S204 are examples of patterning steps.

[0050] In the ion implantation step S205, ions are implanted into the upper surface 21 of the semiconductor substrate 10. In this example, a P-type dopant such as boron is implanted into the upper surface 21 of the semiconductor substrate 10. The acceleration energy of the ion implantation is, for example, about 150 keV. The dose of the ion implantation is, for example, 3×10 -13 atoms / cm 2 By implanting a P-type dopant, the P-type region 50 can be formed. The ion implantation may be performed by an ion implanter.

[0051] In the resist removal step S206, the resist 130 is removed. The resist 130 may be removed by oxygen plasma or by a chemical solution.

[0052] In the material removal step S210, the surface treatment material 80 is removed. The surface treatment material 80 is removed by, for example, plasma containing CF4 and about 10% nitrogen. The surface treatment material 80 may also be removed by a chemical solution.

[0053] If heat treatment is performed at a temperature higher than 200°C while the surface treatment material 80 is in place, there is a risk that the surface treatment material 80 may be altered or deformed. Therefore, it is preferable that each step from the material placement step S209 to the material removal step S210 be performed at a temperature of 200°C or less.

[0054] In the oxide film removing step S207, the oxide film 30 formed in the trench forming step S201 is removed. The oxide film 30 may be removed using a chemical solution such as hydrofluoric acid.

[0055] In the heat treatment step S208, the semiconductor substrate 10 is heat treated. In this example, the semiconductor substrate 10 is heat treated at 500°C or higher (e.g., 1000°C). By heat treating the semiconductor substrate 10, it is possible to diffuse ion species in the P-type region 50. Furthermore, by performing the heat treatment step S208 after the resist removal step S206 and the material removal step S210, it is possible to prevent deformation of the resist 130 and the surface treatment material 80.

[0056] 3, no undiffused region is formed in the mesa portion 60. Therefore, by providing the surface treatment material 80, it is possible to prevent the characteristics of the semiconductor device 100 from fluctuating.

[0057] 7 is a diagram illustrating the solid surface free energy of the surface treatment material 80 and the liquid surface free energy of the resist 130. In FIG. 7, the solid surface free energy of the surface treatment material 80 is expressed as γ sThe solid surface free energy may be the surface tension of a solid. The liquid surface free energy of the resist 130 is expressed as γ L The liquid surface free energy of the resist 130 may be the liquid surface free energy of the resist 130 at the time of application. The liquid surface free energy may be the surface tension of the liquid. In addition, the interfacial tension between the surface treatment material 80 and the resist 130 is set as γ sL The contact angle of the resist 130 with the surface treatment material 80 is set to θ1. The relationship between the solid surface free energy of the surface treatment material 80 and the liquid surface free energy of the resist 130 is expressed by the following equation 1.

number

[0058] Solid surface free energy γ of surface treatment material 80 s is the liquid surface free energy γ of the resist 130 L Therefore, the solid surface free energy γ of the surface treatment material 80 is s is the liquid surface free energy γ of the resist 130 L 7, the contact angle θ1 is 90° or more. Therefore, the surface of the semiconductor substrate 10 on which the surface treatment material 80 is provided has low wettability, and the resist 130 is more likely to flow.

[0059] 8 is a diagram illustrating another example of the manufacturing method of the semiconductor device 100. FIG. 8 shows another example of the resist application step S202. This example differs from the resist application step S202 in FIG. 5 in that the trench 45 has a tapered shape. Other configurations in FIG. 8 may be the same as those in the resist application step S202 in FIG. 5.

[0060] The tapered shape may be a shape in which the opening of the trench 45 is larger than the bottom of the trench 45. Because the trench 45 has a tapered shape, the resist 130 can easily flow into the trench 45. The angle θ2 formed between the sidewall of the trench 45 and the bottom of the trench 45 may be 70° or more. The angle θ2 formed between the sidewall of the trench 45 and the bottom of the trench 45 may be 80° or more. The trench 45 may have a predetermined shoulder.

[0061] Fig. 9 is a diagram showing an example of the arrangement of trenches 45. Fig. 9 shows the trenches 45 in a top view.

[0062] In this example, trench 45 has extension portions 39 and connection portions 41. Extension portions 39 extend in a predetermined direction. In FIG. 9, extension portions 39 extend in the Y-axis direction. Connection portions 41 connect extension portions 39. In FIG. 9, connection portions 41 connect extension portions 39 in the X-axis direction.

[0063] Fig. 10 is a diagram showing the aa cross section of Fig. 9. Fig. 10 is an XZ cross section passing through the extension 39 of the trench 45. Note that Fig. 10 shows only the vicinity of the upper surface 21 of the semiconductor substrate 10, and omits the vicinity of the lower surface of the semiconductor substrate 10.

[0064] In this example, the depth of the extension 39 of the trench 45 is D1. The depth D1 of the extension 39 of the trench 45 may be the maximum depth of the extension 39 of the trench 45.

[0065] Fig. 11 is a diagram showing the bb cross section of Fig. 9. Fig. 11 is a YZ cross section passing through the connection portion 41 of the trench 45. Note that Fig. 11 shows only the vicinity of the upper surface 21 of the semiconductor substrate 10, and omits the vicinity of the lower surface of the semiconductor substrate 10.

[0066] In this example, the depth of the connection portion 41 of the trench 45 is D2. The depth D2 of the connection portion 41 of the trench 45 may be the maximum depth of the connection portion 41 of the trench 45.

[0067] The depth D2 of the connection portion 41 of the trench 45 is greater than the depth D1 of the extension portion 39 of the trench 45. That is, the connection portion 41 of the trench 45 is formed deeper than the extension portion 39 of the trench 45. By making the connection portion 41 of the trench 45 deeper than the extension portion 39 of the trench 45, the resist 130 can more easily flow into the connection portion 41 of the trench 45 in the resist application step S202. Furthermore, even if the shape of the connection portion 41 of the trench 45 is changed, the characteristics of the semiconductor device 100 are less likely to fluctuate.

[0068] In the trench formation step S201, the connection portion 41 of the trench 45 is formed deeper than the extension portion 39 of the trench 45. The connection portion 41 of the trench 45 may be formed shallower as it approaches the extension portion 39 of the trench 45. The depth D2 of the connection portion 41 of the trench 45 may vary continuously.

[0069] Fig. 12 is a diagram showing another example of the arrangement of trenches 45. Fig. 12 shows the trenches 45 as viewed from above. In this example, the trenches 45 also have extension portions 39 and connection portions 41. This example also shows the arrangement of dummy trenches 35 and gate wiring 46.

[0070] The gate wiring 46 is a wiring connected to the gate electrode. The gate wiring 46 may also be connected to a gate pad. The gate wiring 46 outputs a gate potential applied to the gate pad to the gate electrode. In FIG. 12, the gate wiring 46 extends in the Y-axis direction. The gate wiring 46 may surround the active portion of the semiconductor device 100 in a top view. The gate wiring 46 may be a metal wiring containing aluminum or the like.

[0071] The dummy trench 35 is a trench in which no gate electrode is formed. An insulating film may be provided inside the dummy trench 35. The dummy trench 35 extends in a predetermined direction. In FIG. 12, the dummy trench 35 extends in the Y-axis direction.

[0072] In this example, the dummy trench 35 is provided on the outer side of the semiconductor substrate 10 than the trench 45. The outer side of the semiconductor substrate 10 is the gate wiring 46 side. In other words, the dummy trench 35 is provided on the gate wiring 46 side of the trench 45. The outer side of the semiconductor substrate 10 may also be the opposite side of the active portion of the semiconductor device 100. In trench formation step S201, the dummy trench 35 is formed on the outer side of the semiconductor substrate 10 than the trench 45.

[0073] Fig. 13 is a view showing the cc cross section of Fig. 12. Fig. 12 is an XZ cross section passing through the extension 39 of the trench 45. Note that Fig. 13 shows only the vicinity of the upper surface 21 of the semiconductor substrate 10, and omits the vicinity of the lower surface of the semiconductor substrate 10.

[0074] In this example, the depth of the extension 39 of the trench 45 is D3. The depth D3 of the extension 39 of the trench 45 may be the maximum depth of the extension 39 of the trench 45.

[0075] Fig. 14 is a view showing the dd cross section of Fig. 12. Fig. 14 is an XZ cross section passing through the dummy trench 35. Note that Fig. 14 shows only the vicinity of the upper surface 21 of the semiconductor substrate 10, and omits the vicinity of the lower surface of the semiconductor substrate 10.

[0076] In this example, the depth of the dummy trench 35 is D4. The depth D4 of the dummy trench 35 may be the maximum depth of the dummy trench 35.

[0077] The depth D4 of the dummy trench 35 is greater than the depth D3 of the extension 39 of the trench 45. That is, the dummy trench 35 is formed deeper than the extension 39 of the trench 45. The dummy trench 35 may also be formed deeper than the connection portion 41 of the trench 45. By making the dummy trench 35 deeper than the trench 45, the resist 130 can more easily flow into the dummy trench 35 in the resist application step S202. Furthermore, because the dummy trench 35 is a trench in which no gate electrode is formed, even if the depth D4 of the dummy trench 35 is increased, fluctuations in the characteristics of the semiconductor device 100 are unlikely to occur. The depth D4 of the dummy trench 35 may be approximately the same as the depth D3 of the extension 39 of the trench 45.

[0078] 15 is a diagram illustrating trenches 45 and dummy trenches 35. This cross section is an XZ plane passing through the emitter region 12. In this cross section, the semiconductor device 100 of this example has a semiconductor substrate 10 and an interlayer insulating film 38. Note that in FIG. 15, only the vicinity of the upper surface 21 of the semiconductor substrate 10 is shown, and the vicinity of the lower surface of the semiconductor substrate 10 is omitted.

[0079] The interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films. A contact hole 54 is provided in the interlayer insulating film 38.

[0080] Each mesa portion 60 is provided with a base region 14. The mesa portion 60 has an emitter region 12 exposed on the upper surface 21 of the semiconductor substrate 10. The emitter region 12 is provided in contact with the trench 45. Furthermore, the mesa portion 60 in contact with the trench 45 may be provided with a contact region exposed on the upper surface 21 of the semiconductor substrate 10.

[0081] Bottom region 15 is provided at the bottom of trench 45. Bottom region 15 does not have to be provided at the bottom of dummy trench 35. Base region 14 and bottom region 15 are an example of the aforementioned P-type region.

[0082] The trench 45 has a gate insulating film 42 and a gate electrode 44 inside. The gate insulating film 42 is provided to cover the inner wall of the trench 45. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the trench 45. The gate electrode 44 is provided inside the trench 45, more inward than the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate electrode 44 from the semiconductor substrate 10. The gate electrode 44 is formed of a conductive material such as polysilicon.

[0083] The gate electrode 44 may be provided to be longer than the base region 14 in the depth direction. The trench 45 in this cross section is covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate electrode 44 is electrically connected by a gate runner or the like. The gate electrode 44 may be connected to a gate pad. When a predetermined gate voltage is applied to the gate electrode 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the trench 45.

[0084] An interlayer insulating film 38 may be provided inside the dummy trench 35. The interlayer insulating film 38 may also be provided above the dummy trench 35. Because the interlayer insulating film 38 is provided inside the dummy trench 35, no channel is formed in the surface layer of the interface of the base region 14 that contacts the dummy trench 35.

[0085] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention. [Explanation of symbols]

[0086] 10 semiconductor substrate, 12 emitter region, 14 base region, 15 bottom region, 21 upper surface, 30 oxide film, 35 dummy trench, 38 interlayer insulating film, 39 extension portion, 41 connection portion, 42 gate insulating film, 44 gate electrode, 45 trench, 46 gate wiring, 50 p-type region, 54 contact hole, 60 mesa portion, 70 undiffused region, 80 surface treatment material, 100 semiconductor device, 130 resist, 160 mask

Claims

1. 1. A method of manufacturing a semiconductor device including a semiconductor substrate having an upper surface, the method comprising: forming a trench in the upper surface of the semiconductor substrate; a material disposing step of disposing a surface treatment material on the top surface of the semiconductor substrate and on a surface of the trench; a resist coating step of coating a resist inside the trench, and then flowing the resist from the upper surface of the semiconductor substrate into the trench, and removing the resist from the upper surface of the semiconductor substrate; patterning the resist by exposing the resist using a mask to leave the resist within the predetermined trenches; an ion implantation step of implanting ions into the upper surface of the semiconductor substrate; a heat treatment step of heat-treating the semiconductor substrate; Equipped with The solid surface free energy of the surface treatment material is lower than the liquid surface free energy of the resist. A method for manufacturing a semiconductor device.

2. The solid surface free energy of the surface treatment material is 20 mN / m or less. The method for manufacturing a semiconductor device according to claim 1 .

3. The viscosity of the surface treatment material is 10 cP or less.

3. The method for manufacturing a semiconductor device according to claim 1.

4. The thickness of the surface treatment material is 0.1 μm or more and 0.3 μm or less. The method for manufacturing a semiconductor device according to claim 1 .

5. The thickness of the resist is 25% or more of the depth of the trench. The method for manufacturing a semiconductor device according to claim 1 .

6. In the material placement step, the surface treatment material is applied and solidified. The method for manufacturing a semiconductor device according to claim 1 .

7. In the material disposing step, the surface treatment material is vapor-deposited. The method for manufacturing a semiconductor device according to claim 1 .

8. After the ion implantation step, a resist removal step of removing the resist; a material removal step of removing the surface treatment material; Further provided with The method for manufacturing a semiconductor device according to claim 1 .

9. Each step from the material placement step to the material removal step is carried out at a temperature of 200°C or less. The method for manufacturing a semiconductor device according to claim 8 .

10. The heat treatment step is performed after the resist removal step and the material removal step. The method for manufacturing a semiconductor device according to claim 8 .

11. The heat treatment step is carried out at 500°C or higher. The method for manufacturing a semiconductor device according to claim 10.

12. The resist is a negative resist. The method for manufacturing a semiconductor device according to claim 1 .

13. The trench has a tapered shape. The method for manufacturing a semiconductor device according to claim 1 .

14. the trench has an extension portion extending in a predetermined direction and a connection portion connecting the extension portions, In the trench forming step, the connection portion is formed deeper than the extension portion. The method for manufacturing a semiconductor device according to claim 1 .

15. In the trench forming step, a dummy trench is formed outside the trench on the semiconductor substrate. The method for manufacturing a semiconductor device according to claim 1 .

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