Array substrate, display panel and display device

Abstract

This application discloses an array substrate, a display panel, and a display device, in which a thin film transistor (T) and a gate driving circuit (G) are provided on the array substrate, a trigger signal input terminal of the gate driving circuit (G) corresponds to an output terminal of the thin film transistor (T), a first insulating layer (30) is provided between a first metal layer (10) corresponding to the output terminal of the thin film transistor (T) and a second metal layer (20) corresponding to the trigger signal input terminal of the gate driving circuit (G), and a projection area of ​​the first metal layer (10) on the first insulating layer (30) partially overlaps with a projection area of ​​the second metal layer (20) on the first insulating layer (30), thereby reducing the facing area between the first metal layer (10) of the thin film transistor (T) and the second metal layer (20) of the gate driving circuit (G), and effectively improving the current leakage situation of the thin film transistor.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority from a Chinese patent application filed on December 2, 2021, bearing application number 202111456673.4, the entire contents of which are incorporated herein by reference.

[0002] The present application relates to the technical field of displays, and in particular to array substrates, display panels and display devices. [Background technology]

[0003] Cut-out displays are designed to allow panels to be cut to any size, but the gate drive circuit trigger signal is scanned from top to bottom, and once cut, the gate drive circuit cannot be triggered. Therefore, a frame start signal line is usually added to the output side of each gate drive circuit, and a thin-film transistor is designed between the frame start signal line and each stage of the gate drive circuit structure, with one side connected to the frame start signal line and the other side connected to the gate drive circuit structure. Once a cut-out display is cut, the first stage of the gate drive circuit after cutting can only be triggered by the newly added frame start signal line.

[0004] After the display is cut into cut displays of any size, the thin film transistors can be laser welded to turn them on. The signal on the frame start signal line is then transmitted to the first-stage gate driver circuit after the cut, allowing the first-stage gate driver circuit to start up normally. However, this type of thin film transistor is particularly prone to leakage current because the connections between the thin film transistor, the frame start signal line, and the gate driver circuit have a parallel-plate capacitor structure. If cutting is not required, leakage current is likely to occur at the connections between the thin film transistor and other components, resulting in abnormalities on the display screen of the cut display.

[0005] The above content is used to aid in understanding the technical solution of the present application, and is not an admission that the above content is prior art. Summary of the Invention [Problem to be solved by the invention]

[0006] The main purpose of this application is to provide an array substrate, a display panel, and a display device, which solves the technical problem in the prior art that the first metal layer of the output terminal of the thin film transistor on the array substrate and the second metal layer of the input terminal of the gate driving circuit are configured so that the projection areas on the first insulating layer partially overlap, which makes it easy for leakage current to occur in the thin film transistor and causes abnormalities in the display screen of the disconnected display. [Means for solving the problem]

[0007] In order to achieve the above object, the array substrate is provided with a thin film transistor and a gate drive circuit, a trigger signal input terminal of the gate drive circuit is disposed corresponding to an output terminal of the thin film transistor, and a first insulating layer is provided between a first metal layer corresponding to the output terminal of the thin film transistor and a second metal layer corresponding to the trigger signal input terminal of the gate drive circuit; A projection area of ​​the first metal layer on the first insulating layer partially overlaps a projection area of ​​the second metal layer on the first insulating layer.

[0008] In one embodiment, the first metal layer comprises at least two first metal electrodes; the second metal layer includes the same number of second metal electrodes as the number of first metal electrodes; the first metal electrodes are spaced apart from one another on a lower surface of the first insulating layer, and the second metal electrodes are spaced apart from one another on an upper surface of the first insulating layer; In the first insulating layer, the projected area of ​​the first metal electrode has an overlapping area with both of the projected areas of the two second metal electrodes adjacent to each other at corresponding positions.

[0009] In one embodiment, the first metal electrodes are arranged on the lower surface of the first insulating layer at a predetermined distance from each other, and the second metal electrodes are arranged on the upper surface of the first insulating layer at the predetermined distance from each other.

[0010] In one embodiment, the array substrate further includes a frame start signal line, the frame start signal line is provided corresponding to the input terminal of the thin film transistor, and a second insulating layer is provided between the third metal layer corresponding to the input terminal of the thin film transistor and the fourth metal layer corresponding to the frame start signal line; A projection area of ​​the third metal layer on the second insulating layer partially overlaps a projection area of ​​the fourth metal layer on the second insulating layer.

[0011] In one embodiment, the third metal layer comprises at least two third metal electrodes; the fourth metal layer includes the same number of fourth metal electrodes as the number of third metal electrodes; the third metal electrodes are disposed on a lower surface of the second insulating layer at intervals from one another, and the fourth metal electrodes are disposed on an upper surface of the second insulating layer at intervals from one another; In the second insulating layer, the projected area of ​​the third metal electrode has an overlapping area with both of the projected areas of the two fourth metal electrodes adjacent to each other at corresponding positions.

[0012] In one embodiment, the third metal electrodes are arranged on the lower surface of the second insulating layer at a predetermined interval, and the fourth metal electrodes are arranged on the upper surface of the second insulating layer at the predetermined interval.

[0013] In one embodiment, the first metal layer comprises at least two first metal electrodes; the second metal layer includes the same number of second metal electrodes as the number of first metal electrodes; the first metal electrodes are disposed on a lower surface of the first insulating layer at intervals, and the second metal electrodes are disposed on an upper surface of the first insulating layer at intervals; In the first insulating layer, a projected area of ​​the first metal electrode has an overlapping area with projected areas of two adjacent second metal electrodes at corresponding positions; a second insulating layer is provided between the third metal layer and the fourth metal layer; A projection area of ​​the third metal layer on the second insulating layer partially overlaps a projection area of ​​the fourth metal layer on the second insulating layer.

[0014] In one embodiment, the array substrate is provided with a plurality of the thin film transistors; Here, the output terminals of the thin film transistors are provided so as to correspond to the trigger signal input terminals of the gate drive circuits at the corresponding positions.

[0015] To achieve the above object, the present application further provides a display panel, which includes a color film substrate, a liquid crystal layer, and the above-mentioned array substrate, and the liquid crystal layer is located between the color film substrate and the array substrate.

[0016] Furthermore, to achieve the above object, the present application further provides a display device, which includes a backlight module and the display panel, the backlight module being installed on a rear surface of the display panel to provide a backlight source for the display panel. Beneficial effects

[0017] The present application provides an array substrate, a display panel, and a display device, the array substrate including thin film transistors and gate driving circuits, a trigger signal input terminal of the gate driving circuit corresponding to an output terminal of the thin film transistor, a first insulating layer disposed between a first metal layer corresponding to the output terminal of the thin film transistor and a second metal layer corresponding to the trigger signal input terminal of the gate driving circuit, and a projection area of ​​the first metal layer on the first insulating layer partially overlapping a projection area of ​​the second metal layer on the first insulating layer, whereby the projection area of ​​the first metal layer on the first insulating layer partially overlaps with the projection area of ​​the second metal layer on the first insulating layer, thereby reducing the facing area between the first metal layer of the thin film transistor and the second metal layer of the gate driving circuit and effectively improving the current leakage of the thin film transistor.

[0018] In order to more clearly explain the technical solutions of the embodiments of the present application and the prior art, the accompanying drawings necessary for the description of the embodiments or the prior art are briefly introduced below. It is clear that the accompanying drawings in the following description are only drawings corresponding to the first, second, and third embodiments of the array substrate, the display panel, and the display device of the present application, and those skilled in the art can obtain the other accompanying drawings from the structures shown in these accompanying drawings without any creative work. [Brief explanation of the drawings]

[0019] [Figure 1] FIG. 1 is a plan view of an array substrate according to the present invention. [Figure 2] 1 is a structural schematic diagram of a thin film transistor and a gate driving circuit according to a first embodiment of an array substrate of the present application; [Figure 3] 3 is a structural schematic diagram of a connection portion between a thin film transistor and a gate drive circuit according to a first embodiment of the array substrate of the present application. FIG. [Figure 4] 1 is a cross-sectional view of a connection portion between a thin film transistor and a gate drive circuit according to a first embodiment of the array substrate of the present application. [Figure 5]FIG. 2 is a schematic diagram of a frame start signal line according to a first embodiment of the array substrate of the present application. [Figure 6] 10 is a structural schematic diagram of a thin film transistor and a gate driving circuit according to a second embodiment of the array substrate of the present invention; FIG. [Figure 7] 10 is a cross-sectional view of the structure of a connection portion between a thin film transistor and a gate drive circuit according to a second embodiment of the array substrate of the present application. FIG. [Figure 8] FIG. 10 is a schematic diagram of a connection between a first metal electrode and a second metal electrode when a connection portion between a thin film transistor and a gate drive circuit is conductive according to a second embodiment of the array substrate of the present application. [Figure 9] FIG. 10 is a structural schematic diagram of a connection portion between a thin film transistor and an STV line according to a second embodiment of the array substrate of the present application. [Figure 10] FIG. 10 is a cross-sectional view of the structure of a connection portion between a thin film transistor and an STV line according to a second embodiment of the array substrate of the present application. [Figure 11] FIG. 10 is a schematic diagram of a first type of structure of a thin film transistor, a gate driving circuit, and a frame start signal line according to a third embodiment of the array substrate of the present application; [Figure 12] FIG. 10 is a schematic diagram of a second type of structure of a thin film transistor, a gate driving circuit, and a frame start signal line according to a third embodiment of the array substrate of the present application; [Figure 13] FIG. 10 is a schematic diagram of a third type of structure of thin film transistors, gate driving circuits, and frame start signal lines according to a third embodiment of the array substrate of the present application; [Figure 14] FIG. 10 is a structural diagram showing a configuration of an array substrate according to a third embodiment of the present invention, in which a plurality of thin film transistors are disposed. [Figure 15] 1 is a structural schematic diagram of an embodiment of a display panel according to the present invention; [Figure 16] 1 is a structural schematic diagram of an embodiment of a display device according to the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0020] The realization of the object, function features and advantages of the present invention will be further explained in conjunction with the accompanying drawings.

[0021] It should be understood that the specific examples described herein are used only to interpret the present application, and are not used to limit the present application.

[0022] In the following, the technical solutions in the embodiments of the present application will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present application. First Example

[0023] 1, 2 and 3, Fig. 1 is a plan view of an array substrate of the present application, Fig. 2 is a structural diagram of a thin film transistor and a gate drive circuit of a first embodiment of the array substrate of the present application, and Fig. 3 is a structural diagram of a connection portion between the thin film transistor and the gate drive circuit of the first embodiment of the array substrate of the present application. As shown in Fig. 1, 2 and 3, in this embodiment, the array substrate is provided with a thin film transistor T and a gate drive circuit G, a trigger signal input terminal of the gate drive circuit G is arranged corresponding to the output terminal of the thin film transistor T, and a first insulating layer 30 is provided between a first metal layer 10 corresponding to the output terminal of the thin film transistor T and a second metal layer 20 corresponding to the trigger signal input terminal of the gate drive circuit G, Referring to FIGS. 2 and 3, the projection area of ​​the first metal layer 10 on the first insulating layer 30 partially overlaps with the projection area of ​​the second metal layer 20 on the first insulating layer 30 .

[0024] In this embodiment, the gate driving circuit G is a circuit that drives the GOA to operate normally. In this embodiment, the gate driving circuit can light up each row of pixels in response to a trigger signal transmitted from the frame start signal line STV2 or the output terminal of a previous gate driving circuit. The first metal layer 10 and the second metal layer 20 are both metal electrode layers, and this specification does not limit the specific materials used for the metal electrode layers. The first metal layer 10 is a metal layer disposed at a position corresponding to the output terminal of the thin-film transistor T. The output terminal may be the source or drain of the thin-film transistor T. The first insulating layer 30 may be constructed of a zinc-plated material Gi, or of course, may be constructed using other insulating materials. In prior art, the first metal layer 10 and the second metal layer 20 are typically arranged directly opposite each other to maximize their facing area. The metal portions of the first metal layer 10 connected inside the thin-film transistor T and the metal portions of the second metal layer 20 inside the gate driving circuit G are excluded.

[0025] Referring to FIG. 4 , in a specific implementation, the first metal layer 10 and the second metal layer 20 are arranged to correspond to each other but offset from each other. However, an overlapping area must be provided between their corresponding projections on the first insulating layer 30 to ensure that the first metal layer 10 and the second metal layer 20 can be laser welded together through the first insulating layer 30 and that the thin film transistor T can operate normally. That is, as long as there is an overlapping area of ​​more than 0 micrometers between the projections of the first metal layer 10 and the second metal layer 20 on the first insulating layer, the first metal layer 10 and the second metal layer 20 can be welded together and the thin film transistor T can normally transmit the start signal of the gate driving circuit G. In addition, to solve the problem of leakage current at the connection between the thin film transistor T and the gate driving circuit G, the offset arrangement of the first metal layer 10 and the second metal layer 20 can reduce the facing area between the first metal layer 10 and the second metal layer 20. By reducing the opposing area of ​​the first metal layer 10 and the second metal layer 20, the leakage current at the connection portion between the thin film transistor T and the gate drive circuit G can be effectively reduced.

[0026] In a display panel, the normal operation of the gate driver circuit G is to receive a trigger signal CLK to activate the scanning unit and sequentially scan the RGB array on the display panel. Referring to Figure 5, the start signal input terminal IN supplies a trigger signal to the input terminal INPUT on the left or right side of the first row of the RGB array via the frame start signal line STV1, turning on the transistor and initiating the scanning process. Similarly, the gate driver circuit signal input terminal Q can be set to a high level to turn on the subsequent transistor of the thin-film transistor T. After scanning the first row of the RGB array is completed, the clock signal input terminal CLK supplies a trigger signal to the gate driver circuit of the next row via the output terminal OUT of the gate driver circuit G, thereby initiating scanning of the second row of the RGB array. After scanning the second row of the RGB array is completed, the clock signal input terminal CLK also supplies a trigger signal to the scanning unit of the subsequent gate driver circuit. The above process is repeated until scanning of the entire display panel is completed.

[0027] A cut display is a display that can be cut into display panels of the required size. However, because the entire display panel is scanned sequentially from top to bottom, the trigger signal CLK is supplied to the gate drive circuit corresponding to the first row of RGB arrays via the frame start signal line STV1. When the display is cut, the connection between the two rows of RGB arrays at the cut position is severed, and the trigger signal CLK corresponding to the gate drive circuit of the RGB array that will be connected after the cut cannot be supplied. Referring to Figure 5, a frame start signal line STV2 is added to the two output terminals of the first row of arrays, and a thin-film transistor T is designed between the frame start signal line STV2 and the gate drive circuit signal input terminal Q of the trigger structure of each row of RGB arrays. The input terminal of the thin-film transistor T is connected to the frame start signal line STV2 and the output terminal is connected to the gate drive circuit signal input terminal Q. When the display is cut, the gate drive circuit G corresponding to the first row of RGB arrays after the cut can be triggered by the trigger signal CLK supplied via the newly added frame start signal line STV2.

[0028] In this embodiment, when one end of the thin film transistor T is connected to the gate driving circuit of the RGB array of the corresponding row, this is mainly achieved by interconnecting the first metal layer 10 of the thin film transistor T with the second metal layer 20 of the gate driving circuit. However, if there is no need to disconnect the display, there is no need to connect the first metal layer 10 of the thin film transistor T with the second metal layer 20 of the gate driving circuit, and they form a parallel plate capacitor structure, which is prone to leakage current.

[0029] In this embodiment, an array substrate is provided, the array substrate comprising thin film transistors (TFTs) and gate driving circuits, a trigger signal input terminal of the gate driving circuit corresponding to an output terminal of the TFT, a first insulating layer disposed between a first metal layer corresponding to the output terminal of the TFT and a second metal layer corresponding to the trigger signal input terminal of the gate driving circuit, and a projection area of ​​the first metal layer on the first insulating layer partially overlapping a projection area of ​​the second metal layer on the first insulating layer. In this application, the projection area of ​​the first metal layer on the first insulating layer partially overlapping the projection area of ​​the second metal layer on the first insulating layer reduces the facing area between the first metal layer of the TFTs and the second metal layer of the gate driving circuit, thereby effectively improving the current leakage of the TFTs. Second Example

[0030] Referring to FIG. 6, FIG. 6 is a structural schematic diagram of a thin film transistor and a gate driving circuit of a second embodiment of the array substrate of the present invention, and the second embodiment of the array substrate of the present invention is proposed based on FIG.

[0031] In this embodiment, the first metal layer 10 includes at least two first metal electrodes 101; the second metal layer 20 includes second metal electrodes 201 in the same number as the first metal electrodes 101; the first metal electrodes 101 are arranged at intervals on the lower surface of the first insulating layer 30, and the second metal electrodes 201 are arranged at intervals on the upper surface of the first insulating layer 30; In the first insulating layer 30, the projected area of ​​the first metal electrode 101 has an overlapping area with both of the projected areas of the two second metal electrodes 201 adjacent to each other at the corresponding positions.

[0032] Note that when the first metal electrode 101 and the second metal electrode 201 are properly welded by the laser, the trigger signal CLK can be properly transmitted. The first metal electrode 101 has the same function as the first metal layer 10. The first metal layer 10 may include multiple first metal electrodes 101. The specific number of first metal electrodes 101 can be determined depending on the size of the first metal layer 10. For example, the larger the size of the first metal layer 10, the more first metal electrodes 101 can be arranged. Referring to FIG. 7 and FIG. 4, an example in which the first metal layer 10 includes three first metal electrodes 101 has been described. However, in this embodiment, the specific number of metal electrodes included in the metal layer is not limited, and one metal layer may include two, three, four, or the like. In this embodiment, the specific size of the metal electrodes is not limited, and the size of the metal electrodes may be larger than the precision of the exposure machine. For example, if the accuracy of the exposure machine is 2 micrometers, the dimensions of the metal electrode, such as its length and width, must be larger than 2 micrometers, which is the accuracy compatible with the exposure machine.

[0033] In this embodiment, the first metal electrode 101 may be disposed on the upper surface of the first insulating layer 30, and the second metal electrode 201 may be disposed on the lower surface of the first insulating layer 30. In this specification, the positions of the first metal electrode 101 and the second metal electrode 201 relative to the first insulating layer 30 may be interchanged. Of course, all of the first metal electrodes 101 are located on one surface of the first insulating layer 30, and all of the second metal electrodes 201 are located on the other surface of the first insulating layer 30. There is an overlapping area between the projections of the first metal electrode 101 and the second metal electrode 201 on the first insulating layer 30, and the smaller this overlapping area is, the greater the effect of reducing current leakage. Therefore, it is necessary to minimize the area of ​​the overlapping area between the projections of the first metal electrode 101 and the second metal electrode 201 on the first insulating layer 30 while ensuring normal transmission of the start signal.

[0034] Specifically, referring to FIG. 8, if a leakage current occurs at the connection between the thin film transistor T and the gate driver circuit G, the leakage current must pass through the first first metal electrode 101, the first second metal electrode 201, the second first metal electrode 101, the second second metal electrode 201, the third first metal electrode 101, and the third second metal electrode 201. This current leakage path requires that the welding point F on the first insulating layer 30 between the first metal electrode 101 and the second metal electrode 201 be in a welded state. The above-described method of arranging the first metal electrode 101 and the second metal electrode 201 effectively increases the number of leakage current paths, preventing current leakage when one of the first metal electrodes 201 is not welded to the corresponding second metal electrode 201. Of course, since there are multiple first metal electrodes 101 and a corresponding number of second metal electrodes 201, multiple welding processes are required between the first metal electrodes 101 and the second metal electrodes 201 to properly connect the thin film transistor T and the gate driving circuit G. Referring to FIG. 8, in FIG. 8, to properly connect the thin film transistor T and the gate driving circuit G and properly transmit the trigger signal CLK, the first metal electrode 101 under the first insulating layer 30 must be welded to two second metal electrodes 201 at corresponding positions. In this embodiment, the more first metal electrodes 101 and second metal electrodes 201 are provided, the smaller the leakage current. For example, if one first metal electrode 101 and one second metal electrode 201 are provided, the leakage current may be on the order of 10^-12, and if two first metal electrodes 101 and two second metal electrodes 201 are provided, the leakage current may be on the order of 10^-24. Thus, the more first metal electrodes 101 and second metal electrodes 201 that are installed, the lower the possibility of leakage current occurring.

[0035] In this embodiment, the first metal electrodes 101 are arranged on the lower surface of the first insulating layer 30 at a predetermined interval, and the second metal electrodes 201 are arranged on the upper surface of the first insulating layer 30 at the predetermined interval.

[0036] In this embodiment, the length and width of the multiple first metal electrodes 101 and second metal electrodes 201, which are independent and not connected to each other, are not specifically limited. Meanwhile, to avoid display abnormalities during exposure, the spacing between adjacent first metal electrodes 101 needs to be greater than the unit precision of the exposure machine. Meanwhile, a certain overlapping area needs to be provided between the corresponding projected areas of the first metal electrodes 101 and the second metal electrodes 201 on the first insulating layer 30, but the size of the overlapping area is not specifically limited. The "predetermined spacing" refers to the distance between adjacent first metal electrodes 101 and adjacent second metal electrodes 201. The predetermined spacing may be greater than the unit precision of the exposure machine. For example, if the unit precision of the exposure machine is 2 μm, the predetermined spacing may be greater than 2 μm.

[0037] In this embodiment, a frame start signal line STV2 is further provided on the array substrate, and the frame start signal line is provided corresponding to the input terminal of the thin film transistor T; a second insulating layer 60 is provided between the third metal layer 40 corresponding to the input terminal of the thin film transistor T and the fourth metal layer 50 corresponding to the frame start signal line; The projection area of ​​the third metal layer 40 on the second insulating layer 60 partially overlaps with the projection area of ​​the fourth metal layer 50 on the second insulating layer 60 .

[0038] The third metal layer 40 is a metal layer provided corresponding to the input terminal of the thin-film transistor T, and the input terminal may be the drain or source of the thin-film transistor T. Here, the third metal layer 40 faces the first metal layer 10. If the first metal layer 10 is a metal layer provided on the source of the thin-film transistor T, the third metal layer 40 is a metal layer provided on the drain of the thin-film transistor T. Similarly, if the first metal layer 10 is a metal layer provided on the drain of the thin-film transistor T, the third metal layer 40 is a metal layer provided on the source of the thin-film transistor T. When the trigger signal CLK needs to be transmitted, the third metal layer 40 is connected to the fourth metal layer 50 provided on the frame start signal line STV2. When it is not necessary to disconnect the display, a parallel-plate capacitor is also formed between the third metal layer 40 and the fourth metal layer 50. Referring to FIG. 9, the first connection region S1 is the connection portion between the thin-film transistor T and the frame start signal line STV2. The second connection region S2 is a connection portion between the thin film transistor T and the gate drive circuit G.

[0039] 9, in this specific embodiment, the third metal layer 40 and the fourth metal layer 50 may be similarly arranged with a gap therebetween. An overlapping area exists between the projected area of ​​the third metal layer 40 on the second insulating layer 60 and the projected area of ​​the fourth metal layer 50 on the second insulating layer 60, and the area where the third metal layer 40 and the fourth metal layer 50 directly face each other is the smallest possible area. The arrangement of the third metal layer 40 may be performed with reference to the arrangement method of the first metal layer 10 in the first embodiment, and the arrangement of the fourth metal layer 50 may be performed with reference to the arrangement method of the second metal layer 20, and description thereof will be omitted here.

[0040] In this embodiment, the third metal layer 40 includes at least two third metal electrodes 401; the fourth metal layer 50 includes the same number of fourth metal electrodes 501 as the number of third metal electrodes 401; The third metal electrodes 401 are arranged at intervals on the lower surface of the second insulating layer 60, and the fourth metal electrodes 501 are arranged at intervals on the upper surface of the second insulating layer 60, In the second insulating layer 60, the projected area of ​​the third metal electrode 401 has an overlapping area with both of the projected areas of the two fourth metal electrodes 501 adjacent to each other at the corresponding positions.

[0041] In addition, by providing at least two third metal electrodes 401 on the third metal layer 40 and the same number of fourth metal electrodes 501 on the fourth metal layer 50, the transmission paths of leakage current between the thin film transistor T and the frame start signal line STV2 can be increased, and the leakage current between the thin film transistor T and the frame start signal line STV2 can be effectively reduced. Only when all the third metal electrodes 401 and the corresponding fourth metal electrodes 401 are welded together can a complete current leakage circuit be formed, and the current leakage phenomenon may occur.

[0042] 10 , in a specific embodiment, the third metal electrode 401 and the fourth metal electrode 501 can be sequentially arranged on the second insulating layer 60 such that the projection area of ​​the third metal electrode 401 overlaps with the projection areas of the two adjacent fourth metal electrodes 501 at corresponding positions. When a leakage current occurs at the connection between the thin film transistor T and the frame start signal line STV2, the leakage current must pass through the first third metal electrode 401, the first fourth metal electrode 501, the second third metal electrode 401, the second fourth metal electrode 501, the third third metal electrode 401, and the third fourth metal electrode 501 to generate the current leakage.

[0043] In this embodiment, referring to the above arrangement method, the third metal electrodes 401 should also be arranged at a predetermined interval on the underside of the second insulating layer 60, and the fourth metal electrodes 501 should also be arranged at the predetermined interval on the upper surface of the second insulating layer 60. In a specific arrangement process, the positions of the third metal layer 40 and the fourth metal layer 50 on the second insulating layer may be interchanged. However, the intervals between the third metal electrodes 401 and the fourth metal electrodes 501 should also satisfy the unit accuracy requirements of the exposure machine to avoid abnormalities in the exposed image.

[0044] In this embodiment, an array substrate is provided, which includes thin film transistors (TFTs) and gate driving circuits, a trigger signal input terminal of the gate driving circuit corresponding to an output terminal of the TFT, a first insulating layer disposed between a first metal layer corresponding to the output terminal of the TFT and a second metal layer corresponding to the trigger signal input terminal of the gate driving circuit, and a projection area of ​​the first metal layer on the first insulating layer partially overlaps a projection area of ​​the second metal layer on the first insulating layer. In this embodiment, the corresponding positions of the first metal electrode in the first metal layer and the second metal electrode in the second metal layer are offset, so that the projection area of ​​the first metal electrode on the first insulating layer overlaps with the projection areas of two adjacent second metal electrodes at corresponding positions, thereby reducing the facing area between the first metal layer of the TFTs and the second metal layer of the gate driving circuit and increasing the transmission path of leakage current, thereby more accurately improving the current leakage of the TFTs. Third Example

[0045] Based on the above first and second embodiments, a third embodiment of the array substrate of the present invention is proposed.

[0046] In addition, the specific process by which the gate drive circuit receives the drive signal is to first establish electrical continuity between the fourth metal electrode 501 of the fourth metal layer 50 and the third metal electrode 401 of the third metal layer 40, then establish electrical continuity between the second metal electrode 201 of the second metal layer 20 and the first metal electrode 101 of the first metal layer 10, and then input the drive signal from the frame start signal line STV2 to the gate drive circuit G via the thin film transistor T.

[0047] In this embodiment, the array substrate is provided with a first connection region S1 between the thin film transistor T and the frame start signal line STV2, and a second connection region S2 between the thin film transistor T and the gate drive circuit G. In the first connection region S1, the first metal layer 10 and the second metal layer 20 can be arranged such that a projected region of the first metal layer 10 on the first insulating layer 30 partially overlaps a projected region of the second metal layer 20 on the first insulating layer 30, and also in the second connection region S2, the first metal layer 10 and the second metal layer 20 can be arranged such that a projected region of the third metal layer on the second insulating layer partially overlaps a projected region of the fourth metal layer on the second insulating layer. At least two first metal electrodes 101 and at least two second metal electrodes 201 are arranged in the first connection region S1, and are arranged in the first insulating layer so that the projection area of ​​the first metal electrode 101 has an overlapping area with both of the projection areas of the two adjacent second metal electrodes 201 at corresponding positions; and at least two third metal electrodes 401 and at least two fourth metal electrodes 501 are arranged in the first connection region S1, and are arranged in the second insulating layer 60 so that the projection area of ​​the third metal electrode 401 has an overlapping area with both of the projection areas of the two adjacent fourth metal electrodes 501 at corresponding positions.

[0048] In addition to the above-mentioned method of arranging two types of electrode layers or electrodes in the first connection region S1 and the second connection region S2, the first metal layer 10 in the second connection region S2 may be provided as at least two first metal electrodes 101, and the second metal layer 20 may be provided as at least two second metal electrodes 201, the first metal electrodes 101 may be arranged at intervals on the lower surface of the first insulating layer 30, and the second metal electrodes 201 may be arranged at intervals on the upper surface of the first insulating layer 30, and the first metal electrodes 101 may be arranged so that the projection area of ​​the first metal electrode 101 overlaps with the projection areas of two adjacent second metal electrodes 201 at corresponding positions on the first insulating layer 30. In this case, a second insulating layer 60 is provided between the third metal layer 40 and the fourth metal layer 50 included in the first connection region S1, and a projected area of ​​the third metal layer 40 on the second insulating layer 60 partially overlaps a projected area of ​​the fourth metal layer 50 on the second insulating layer 60. Similarly, the projected area of ​​the first metal layer 10 on the first insulating layer 30 in the second connection region S2 may be arranged to partially overlap a projected area of ​​the second metal layer 20 on the first insulating layer 30, and the projected area of ​​the third metal layer 40 on the second insulating layer 60 in the first connection region S1 may be arranged to partially overlap a projected area of ​​the fourth metal layer 50 on the second insulating layer 60.

[0049] In this embodiment, in the first connection region S1 and the second connection region S2, the corresponding first metal layer 10, second metal layer 20, third metal layer 40 and fourth metal layer 50 can all be provided as a multiple metal electrode structure. Referring to Figures 11, 12 and 13, in Figure 11, two metal electrodes are provided on each of the first metal layer 10 and the second metal layer 20 in the first connection region S1 and the third metal layer 40 and the fourth metal layer 50 in the second connection region S2, in Figure 12, three metal electrodes are provided on each of the first metal layer 10 and the second metal layer 20 in the first connection region S1 and the third metal layer 40 and the fourth metal layer 50 in the second connection region S2, and in Figure 13, four metal electrodes are provided on each of the first metal layer 10 and the second metal layer 20 in the first connection region S1 and the third metal layer 40 and the fourth metal layer 50 in the second connection region S2.

[0050] In this embodiment, the metal layers in the first connection region S1 and the second connection region S2 may be provided with different numbers of metal electrodes. For example, two metal electrodes may be provided on the first metal layer 10 and the second metal layer 20 in the first connection region S1, and three metal electrodes may be provided on the third metal layer 40 and the fourth metal layer 50 in the second connection region S2. In this specification, the combination of the numbers of metal electrodes provided on the metal layers in the first connection region S1 and the second connection region S2 will not be described.

[0051] Referring to FIG. 14, in this embodiment, a plurality of thin film transistors T are provided on the array substrate, and the output terminals of the thin film transistors T are provided corresponding to the trigger signal input terminals of the gate driving circuits G at the corresponding positions.

[0052] Referring to FIG. 14, when determining the position where the display is to be disconnected, the thin film transistor T may be provided at the position where the display is to be disconnected, and then the frame start signal line STV2 may be connected to one end of the thin film transistor T, and the gate drive circuit corresponding to the disconnection position may be connected to the other end of the thin film transistor T. Of course, the specific number of thin film transistors may be determined depending on the specific number of times the display needs to be disconnected. For example, if the display needs to be disconnected two times, two thin film transistors may be provided, and if the display needs to be disconnected three times, three thin film transistors may be provided. Of course, the number of thin film transistors may be the same as the number of RGB array layers, allowing for disconnection from any position on the display. Here, the structure of the connection between each thin film transistor and the gate drive circuit and the connection between each thin film transistor and the STV line can be referenced from the above structures, and therefore will not be described here.

[0053] In this embodiment, an array substrate is provided, and both ends of the thin film transistors on the array substrate are all formed with the above-mentioned electrode layer structure or electrode structure, thereby effectively preventing current leakage from the thin film transistors from two areas: a first connection area S1 between the thin film transistors and the frame start signal line, and a second connection area S2 between the thin film transistors and the gate driving circuit.

[0054] Furthermore, an embodiment of the present invention further proposes a display panel. Referring to FIG. 15, FIG. 15 is a structural schematic diagram of an embodiment of the display panel of the present invention. The display panel includes the array substrate 70, a color film substrate 90 disposed opposite the array substrate 70, and a liquid crystal layer 80 sandwiched between the array substrate 70 and the color film substrate 90.

[0055] In addition, an embodiment of the present application further proposes a display device. Please refer to Fig. 16, which is a structural schematic diagram of the display device embodiment of the present application. The display device includes the above-mentioned display panel 100 and a backlight module 110, and the backlight module 110 is installed on the rear surface of the display panel 100 to provide a backlight source for the display panel 100.

[0056] Since the present display employs all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, and therefore the description thereof will be omitted here.

[0057] The above is merely a preferred embodiment of the present application, and does not limit the scope of protection of the present application. Any equivalent structure or equivalent process transformation made by utilizing the contents of the specification and drawings of the present application, or direct or indirect application to other related technical fields, shall also be included in the scope of protection of the present application for the same reason.

[0058] It is clear that the described embodiments are only some of the embodiments of the present application, and not all of the embodiments of the present application. Based on the embodiments of the present application, all other embodiments that can be obtained by a person skilled in the art without performing creative work fall within the scope of protection of the present application.

[0059] It should be noted that all directional indications (e.g., up, down, left, right, front, back, etc.) in the embodiments of the present application are used only to describe the relative positional relationships, movement status, etc. between each part in a specific posture (as shown in the attached drawings), and if the specific posture changes, the directional indications will also change accordingly.

[0060] Furthermore, the terms "first," "second," etc., used in the embodiments of the present application are for illustrative purposes only and should not be understood as indicating or implying the relative importance of the features or implicitly specifying the number of technical features presented. Thus, features defined as "first" or "second" may explicitly or implicitly include at least one of the features. Furthermore, the technical solutions in each embodiment may be combined with each other, provided that such combination is feasible by a person skilled in the art. If a combination of technical solutions contradicts or is not feasible, it should be understood that such combination of technical solutions does not exist and is not within the scope of protection claimed by the present application. [Explanation of symbols]

[0061] 10 First Metal Layer 20 Second Metal Layer 30 First insulating layer 101 First metal electrode 201 Second metal electrode S1 First connection area S2 Second connection area Gate drive circuit L scan line A noise reduction chip IN Start signal input terminal T thin film transistor P pixel unit Q Gate drive circuit signal input terminal STV1, STV2 Frame start signal lines 40 Third Metal Layer 50 Fourth Metal Layer 60 Second insulating layer 401 Third metal electrode 501 Fourth metal electrode 70 Array board 80 Liquid Crystal Layer 90 Color film substrate 100 Display Panel 110 Backlight Module F welding point CLK Clock signal input terminal

Claims

1. An array substrate provided with a thin film transistor (T) and a gate drive circuit (G), wherein a trigger signal input terminal of the gate drive circuit (G) is arranged corresponding to an output terminal of the thin film transistor (T), and a first insulating layer (30) is provided between a first metal layer (10) corresponding to the output terminal of the thin film transistor (T) and a second metal layer (20) corresponding to the trigger signal input terminal of the gate drive circuit (G), a projection area of ​​the first metal layer (10) on the first insulating layer (30) partially overlaps a projection area of ​​the second metal layer (20) on the first insulating layer (30); The first metal layer (10) comprises at least two first metal electrodes (101); The second metal layer (20) includes the same number of second metal electrodes (201) as the number of first metal electrodes (101), The first metal electrodes (101) are arranged at intervals on the lower surface of the first insulating layer (30), The second metal electrodes (201) are arranged on the upper surface of the first insulating layer (30) at intervals from each other, In the first insulating layer (30), the projection area of ​​the first metal electrode (101) has an overlap area with both of the projection areas of the two adjacent second metal electrodes (201) at corresponding positions. Array board.

2. The first metal layer (10) is a metal layer provided at a position corresponding to the output terminal of the thin film transistor (T), and the output terminal is the source or drain of the thin film transistor (T). The array substrate according to claim 1 .

3. The first metal layer (10) and the second metal layer (20) are arranged in a shifted manner, and an overlapping region exists between the projected region of the first metal layer (10) and the projected region of the second metal layer (20) in the first insulating layer (30). The array substrate according to claim 1 .

4. The first metal electrodes (101) are arranged at predetermined intervals on the lower surface of the first insulating layer (30), and the second metal electrodes (201) are arranged at the predetermined intervals on the upper surface of the first insulating layer (30). The array substrate according to claim 1 .

5. a frame start signal line (STV2) is further provided on the array substrate, the frame start signal line (STV2) is provided corresponding to an input terminal of the thin film transistor (T), and a second insulating layer (60) is provided between a third metal layer (40) corresponding to the input terminal of the thin film transistor (T) and a fourth metal layer (50) corresponding to the frame start signal line; The projection area of ​​the third metal layer (40) on the second insulating layer (60) partially overlaps with the projection area of ​​the fourth metal layer (50) on the second insulating layer (60).

5. The array substrate according to claim 4.

6. The third metal layer (40) is a metal layer provided corresponding to the input terminal of the thin film transistor (T), the input terminal being the drain or source of the thin film transistor (T), and the third metal layer (40) is provided opposite the first metal layer (10).

6. The array substrate according to claim 5.

7. When the first metal layer (10) is a metal layer provided on the source of the thin film transistor (T), the third metal layer (40) is a metal layer provided on the drain of the thin film transistor (T), or When the first metal layer (10) is a metal layer provided on the drain of the thin film transistor (T), the third metal layer (40) is a metal layer provided on the source of the thin film transistor T.

7. The array substrate according to claim 6.

8. The third metal layer (40) and the fourth metal layer (50) are arranged at an offset interval from each other.

6. The array substrate according to claim 5.

9. The third metal layer (40) comprises at least two third metal electrodes (401); the fourth metal layer (50) includes the same number of fourth metal electrodes (501) as the number of third metal electrodes (401); The third metal electrodes (401) are arranged on the lower surface of the second insulating layer (60) at intervals from each other, The fourth metal electrodes (501) are arranged on the upper surface of the second insulating layer (60) at intervals from each other, In the second insulating layer (60), the projection area of ​​the third metal electrode (401) has an overlapping area with both of the projection areas of the two adjacent fourth metal electrodes (501) at corresponding positions.

6. The array substrate according to claim 5.

10. The third metal electrodes (401) are arranged at predetermined intervals on the lower surface of the second insulating layer (60), and the fourth metal electrodes (501) are arranged at the predetermined intervals on the upper surface of the second insulating layer (60). The array substrate according to claim 9 .

11. The first metal layer (10) comprises at least two first metal electrodes (101); The second metal layer (20) includes the same number of second metal electrodes (201) as the number of first metal electrodes (101), The first metal electrode (101) is disposed on the lower surface of the first insulating layer (30) at a distance from the lower surface, The second metal electrode (201) is disposed on the upper surface of the first insulating layer (30) at a distance from the upper surface; In the first insulating layer (30), the projection area of ​​the first metal electrode (101) has an overlapping area with both projection areas of two adjacent second metal electrodes (201) at corresponding positions; a second insulating layer (60) is provided between the third metal layer (40) and the fourth metal layer (50); The projection area of ​​the third metal layer (40) on the second insulating layer (60) partially overlaps with the projection area of ​​the fourth metal layer (50) on the second insulating layer (60).

6. The array substrate according to claim 5.

12. A plurality of the thin film transistors (T) are provided on the array substrate, The output terminals of the thin film transistors (T) are provided to correspond to the trigger signal input terminals of the gate drive circuits (G) at the corresponding positions. The array substrate according to claim 10 .

13. A display panel, The display panel includes a color film substrate (90), a liquid crystal layer (80), and the array substrate (70) according to any one of claims 1 to 12, and the liquid crystal layer (80) is located between the color film substrate (90) and the array substrate (70). Display panel.

14. A display device, The display device includes a backlight module (110) and a display panel (100) according to claim 13, wherein the backlight module (110) is installed on the rear surface of the display panel (100) to provide a backlight source for the display panel (100). Display device.

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