Plasma processing apparatus and plasma processing method

Abstract

To provide a technology for improving etching shape and suppressing abnormal discharge in a plasma processing device.SOLUTION: A plasma processing device is provided. The plasma processing device includes a first RF signal generator and a second RF signal generator coupled to a lower electrode, and a DC signal generator coupled to an upper electrode. The first RF signal has a first power level during a first state within a repetition period, a second power level smaller than the first power level during a second state within the repetition period, and the second power level during a third state within the repetition period. The second RF signal has a third power level during the first state, a fourth power level larger than the third power level during the second state, and the third power level during the third state. The DC signal has a first voltage level during the first state and a second voltage level during the second state, and the absolute value of the first voltage level is larger than the absolute value of the second voltage level.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] SUMMARY OF THE INVENTION Exemplary embodiments of the present disclosure relate to a plasma processing apparatus and a plasma processing method. [Background technology]

[0002] 2. Description of the Related Art Patent Document 1 discloses a technique for effectively preventing deposits from adhering to chamber inner walls and chamber internal members such as insulators in a plasma processing apparatus. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-5755 Summary of the Invention [Problem to be solved by the invention]

[0004] The present disclosure provides a technique for improving etching shapes and suppressing abnormal discharge in a plasma processing apparatus. [Means for solving the problem]

[0005] In one exemplary embodiment of the present disclosure, a plasma processing apparatus includes: a plasma processing chamber; a substrate support disposed within the plasma processing chamber and including a lower electrode; an upper electrode disposed above the substrate support; a first RF signal generator coupled to the lower electrode and configured to generate a first RF signal, the first RF signal having a first power level during a first state within a repeating period, a second power level less than the first power level during a second state within the repeating period, and the second power level during a third state within the repeating period; and a first RF signal generator coupled to the lower electrode and configured to generate a second RF signal. wherein the second RF signal has a third power level during the first state, a fourth power level during the second state that is greater than the third power level, and has the third power level during the third state; and a DC signal generator coupled to the upper electrode and configured to generate a DC signal, the DC signal having a first voltage level during the first state and a second voltage level during the second state, the absolute value of the first voltage level being greater than the absolute value of the second voltage level. [Effects of the Invention]

[0006] According to one exemplary embodiment of the present disclosure, it is possible to provide a technique for improving an etching profile and suppressing abnormal discharge in a plasma processing apparatus. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram illustrating an example of the configuration of a capacitively coupled plasma processing apparatus. [Figure 2] 1 is a flowchart illustrating an example of the present processing method. [Figure 3] 1 is a diagram showing an example of a cross-sectional structure of a substrate W provided in step ST1. FIG. [Figure 4] FIG. 10 is a diagram showing an example of the cross-sectional structure of the substrate W being processed at step ST3. [Figure 5] 10 is a diagram showing an example of the power or voltage of each signal during a period T. FIG. [Figure 6] 6 is a diagram for explaining the potential difference between the plasma and the upper electrode during a period T in FIG. 5. FIG. [Figure 7] 10 is a diagram showing another example of the power or voltage of each signal during the period T. FIG. [Figure 8] 10 is a diagram showing another example of the power or voltage of each signal during the period T. FIG. [Figure 9] 10 is a diagram showing another example of the power or voltage of each signal during the period T. FIG. [Figure 10] 10 is a diagram showing another example of the power or voltage of each signal during the period T. FIG. [Figure 11] 10 is a diagram showing another example of the power or voltage of each signal during the period T. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, each embodiment of the present disclosure will be described.

[0009] In one exemplary embodiment, a plasma processing system includes a plasma processing chamber, a substrate support disposed within the plasma processing chamber and including a lower electrode, an upper electrode disposed above the substrate support, a first RF signal generator coupled to the lower electrode and configured to generate a first RF signal, the first RF signal having a first power level during a first state within the repeating period, a second power level less than the first power level during a second state within the repeating period, and a third power level during a third state within the repeating period, and a second RF signal generator coupled to the lower electrode and configured to generate a second RF signal. a second RF signal generator coupled to the upper electrode and configured to generate a DC signal, the DC signal having a first voltage level during the first state and a second voltage level during the second state, the DC signal having a first voltage level greater than an absolute value of the second voltage level.

[0010] In one exemplary embodiment, the first voltage level has a negative polarity.

[0011] In one exemplary embodiment, the DC signal has a first voltage level during the third state.

[0012] In one exemplary embodiment, the second power level is a zero power level.

[0013] In one exemplary embodiment, the third power level is a zero power level.

[0014] In one exemplary embodiment, the second voltage level is a zero voltage level.

[0015] In one exemplary embodiment, the frequency of the first RF signal is greater than the frequency of the second RF signal.

[0016] In one exemplary embodiment, the repetition period is within the range of 20 μs to 800 μs.

[0017] In one exemplary embodiment, the first state occupies at least 10% and at most 80% of the repeat period.

[0018] In one exemplary embodiment, the second state occupies at least 10% and at most 80% of the repeat period.

[0019] In one exemplary embodiment, the third state occupies at least 10% and at most 80% of the repeat period.

[0020] In one exemplary embodiment, the first voltage level is in the range of -500V to -2500V.

[0021] In one exemplary embodiment, a plasma processing system includes a plasma processing chamber, a substrate support disposed within the plasma processing chamber and including a lower electrode, an upper electrode disposed above the substrate support, an RF signal generator coupled to the lower electrode and configured to generate an RF signal, the RF signal having a first power level during a first state within the repeating period, a second power level during a second state within the repeating period that is less than the first power level, and a third power level during a third state within the repeating period, and a first DC signal generator coupled to the lower electrode and configured to generate a first DC signal, the first DC signal generator having a first DC voltage. A plasma processing apparatus is provided, comprising: a first DC signal generator, wherein the C signal has a sequence of voltage pulses having a first voltage level during a first state, a second voltage level during a second state, and the first voltage level during a third state, wherein the absolute value of the first voltage level is less than the absolute value of the second voltage level; and a second DC signal generator, coupled to the upper electrode and configured to generate a second DC signal, wherein the second DC signal has a third voltage level during the first state and a fourth voltage level during the second state, wherein the absolute value of the third voltage level is greater than the absolute value of the fourth voltage level.

[0022] In one exemplary embodiment, the second voltage level has a negative polarity.

[0023] In one exemplary embodiment, the sequence of voltage pulses has a pulse frequency in the range of 100 kHz to 500 kHz.

[0024] In one exemplary embodiment, the first voltage level is a zero voltage level.

[0025] In one exemplary embodiment, the second voltage level is in the range of -5 kV to -30 kV.

[0026] In one exemplary embodiment, the third voltage level has a negative polarity.

[0027] In one exemplary embodiment, the second DC signal has a third voltage level during the third state.

[0028] In one exemplary embodiment, the fourth voltage level is a zero power level.

[0029] Hereinafter, each embodiment of the present disclosure will be described in detail with reference to the drawings. In each drawing, the same or similar elements are designated by the same reference numerals, and redundant explanations will be omitted. Unless otherwise specified, the positional relationships, such as up, down, left, and right, will be described based on the positional relationships shown in the drawings. The dimensional ratios in the drawings do not represent actual ratios, and the actual ratios are not limited to the ratios shown in the drawings.

[0030] <Configuration example of plasma processing apparatus> FIG. 1 is a diagram illustrating an example of the configuration of a capacitively coupled plasma processing apparatus.

[0031] The capacitively coupled plasma processing apparatus 1 includes a controller 2, a plasma processing chamber 10, a gas supply 20, a power supply 30, and an exhaust system 40. The plasma processing apparatus 1 also includes a substrate support 11 and a gas inlet. The gas inlet is configured to introduce at least one process gas into the plasma processing chamber 10. The gas inlet includes a showerhead 13. The substrate support 11 is disposed within the plasma processing chamber 10. The showerhead 13 is disposed above the substrate support 11. In one embodiment, the showerhead 13 forms at least a portion of the ceiling of the plasma processing chamber 10. The plasma processing chamber 10 has a plasma processing space 10s defined by the showerhead 13, a sidewall 10a of the plasma processing chamber 10, and the substrate support 11. The plasma processing chamber 10 has at least one gas inlet for supplying at least one process gas to the plasma processing space 10s and at least one gas outlet for exhausting gas from the plasma processing space 10s. The plasma processing chamber 10 is grounded. The showerhead 13 and the substrate support 11 are electrically isolated from the enclosure of the plasma processing chamber 10 .

[0032] The substrate support 11 includes a main body 111 and a ring assembly 112. The main body 111 has a central region 111a for supporting a substrate W and an annular region 111b for supporting the ring assembly 112. A wafer is an example of a substrate W. The annular region 111b of the main body 111 surrounds the central region 111a of the main body 111 in a plan view. The substrate W is disposed on the central region 111a of the main body 111, and the ring assembly 112 is disposed on the annular region 111b of the main body 111 so as to surround the substrate W on the central region 111a of the main body 111. Therefore, the central region 111a is also called a substrate support surface for supporting the substrate W, and the annular region 111b is also called a ring support surface for supporting the ring assembly 112.

[0033] In one embodiment, the main body 111 includes a base 1110 and an electrostatic chuck 1111. The base 1110 includes a conductive member. The conductive member of the base 1110 can function as a lower electrode. The electrostatic chuck 1111 is disposed on the base 1110. The electrostatic chuck 1111 includes a ceramic member 1111a and an electrostatic electrode 1111b disposed within the ceramic member 1111a. The ceramic member 1111a has a central region 111a. In one embodiment, the ceramic member 1111a also has an annular region 111b. Note that the annular region 111b may also be provided by another member surrounding the electrostatic chuck 1111, such as an annular electrostatic chuck or an annular insulating member. In this case, the ring assembly 112 may be disposed on the annular electrostatic chuck or the annular insulating member, or may be disposed on both the electrostatic chuck 1111 and the annular insulating member. Furthermore, at least one RF / DC electrode coupled to an RF (Radio Frequency) power supply 31 and / or a DC (Direct Current) power supply 32 (described later) may be disposed within the ceramic member 1111a. In this case, the at least one RF / DC electrode functions as a lower electrode. When a bias RF signal and / or a DC signal (described later) is supplied to the at least one RF / DC electrode, the RF / DC electrode is also called a bias electrode. Note that the conductive member of the base 1110 and the at least one RF / DC electrode may function as multiple lower electrodes. Alternatively, the electrostatic electrode 1111b may function as the lower electrode. Therefore, the substrate support 11 includes at least one lower electrode.

[0034] The ring assembly 112 includes one or more annular members. In one embodiment, the one or more annular members include one or more edge rings and at least one cover ring. The edge rings are formed of a conductive or insulating material, and the cover rings are formed of an insulating material.

[0035] The substrate support 11 may also include a temperature adjustment module configured to adjust at least one of the electrostatic chuck 1111, the ring assembly 112, and the substrate to a target temperature. The temperature adjustment module may include a heater, a heat transfer medium, a flow passage 1110a, or a combination thereof. A heat transfer fluid such as brine or a gas flows through the flow passage 1110a. In one embodiment, the flow passage 1110a is formed in the base 1110, and one or more heaters are disposed in the ceramic member 1111a of the electrostatic chuck 1111. The substrate support 11 may also include a heat transfer gas supply configured to supply a heat transfer gas to a gap between the backside of the substrate W and the central region 111a.

[0036] The showerhead 13 is configured to introduce at least one processing gas from the gas supply unit 20 into the plasma processing space 10s. The showerhead 13 has at least one gas supply port 13a, at least one gas diffusion chamber 13b, and multiple gas inlets 13c. The processing gas supplied to the gas supply port 13a passes through the gas diffusion chamber 13b and is introduced into the plasma processing space 10s from the multiple gas inlets 13c. The showerhead 13 also includes at least one upper electrode. In addition to the showerhead 13, the gas introduction unit may also include one or more side gas injectors (SGIs) attached to one or more openings formed in the sidewall 10a.

[0037] The gas supply unit 20 may include at least one gas source 21 and at least one flow controller 22. In one embodiment, the gas supply unit 20 is configured to supply at least one process gas from a corresponding gas source 21 to the showerhead 13 via a corresponding flow controller 22. Each flow controller 22 may include, for example, a mass flow controller or a pressure-controlled flow controller. Additionally, the gas supply unit 20 may include one or more flow modulation devices to modulate or pulse the flow rate of the at least one process gas.

[0038] The power supply 30 includes an RF power supply 31 coupled to the plasma processing chamber 10 via at least one impedance matching circuit. The RF power supply 31 is configured to supply at least one RF signal (RF power) to at least one lower electrode. This generates a plasma from at least one processing gas supplied to the plasma processing space 10s. Therefore, the RF power supply 31 can function as at least a part of a plasma generating unit configured to generate a plasma from one or more processing gases in the plasma processing chamber 10. In addition, by supplying a bias RF signal to the at least one lower electrode, a bias potential is generated on the substrate W, thereby attracting ion components in the formed plasma to the substrate W.

[0039] In one embodiment, the RF power supply 31 includes a first RF generating unit 31a and a second RF generating unit 31b. The first RF generating unit 31a is coupled to at least one lower electrode via at least one impedance matching circuit and is configured to generate a source RF signal (source RF power) for plasma generation. In one embodiment, the source RF signal has a frequency in the range of 10 MHz to 150 MHz. In one embodiment, the first RF generating unit 31a may be configured to generate multiple source RF signals having different frequencies. The generated one or more source RF signals are supplied to at least one lower electrode. In one embodiment, the generated one or more source RF signals are supplied to at least one lower electrode.

[0040] The second RF generating unit 31b is coupled to at least one lower electrode via at least one impedance matching circuit and configured to generate a bias RF signal (bias RF power). The frequency of the bias RF signal may be the same as or different from the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency lower than the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency in the range of 100 kHz to 60 MHz. In one embodiment, the second RF generating unit 31b may be configured to generate multiple bias RF signals having different frequencies. The generated one or more bias RF signals are supplied to at least one lower electrode. In various embodiments, at least one of the source RF signal and the bias RF signal may be pulsed.

[0041] The power supply 30 may also include a DC power supply 32 coupled to the plasma processing chamber 10. The DC power supply 32 includes a first DC generator 32a and a second DC generator 32b. In one embodiment, the first DC generator 32a is connected to at least one lower electrode and configured to generate a first DC signal (hereinafter also referred to as a "bias DC signal"). The generated bias DC signal is applied to at least one lower electrode. In one embodiment, the second DC generator 32b is connected to at least one upper electrode and configured to generate a second DC signal (hereinafter also referred to as an "upper DC signal"). The generated upper DC signal is applied to at least one upper electrode. In one embodiment, supplying the upper DC signal to the upper electrode can achieve one or more of the following effects (I) to (V): (I) increasing the self-bias voltage of the upper electrode to increase the sputtering effect on the surface of the upper electrode; (II) expanding the plasma sheath in the upper electrode to reduce the plasma; and (III) irradiating electrons generated in the upper electrode onto the substrate W. (IV) Controlling the plasma potential. (V) Increasing the electron density of the plasma.

[0042] In various embodiments, at least one of the first and second DC signals may be pulsed. In this case, a sequence of voltage pulses is applied to at least one lower electrode and / or at least one upper electrode. The voltage pulses may have a rectangular, trapezoidal, triangular, or combination thereof pulse waveform. In one embodiment, a waveform generator for generating a sequence of voltage pulses from the DC signal is connected between the first DC generator 32a and at least one lower electrode. Thus, the first DC generator 32a and the waveform generator constitute a voltage pulse generator. When the second DC generator 32b and the waveform generator constitute a voltage pulse generator, the voltage pulse generator is connected to at least one upper electrode. The voltage pulses may have either positive or negative polarity. Furthermore, the sequence of voltage pulses may include one or more positive voltage pulses and one or more negative voltage pulses within one period. The first and second DC generating units 32a and 32b may be provided in addition to the RF power supply 31, or the first DC generating unit 32a may be provided instead of the second RF generating unit 31b. In one embodiment, the power supply 30 may be composed of an RF power supply 31 including the first RF generating unit 31a and the second RF generating unit 31b, and a DC power supply 32 including the second DC generating unit 32b. In one embodiment, the power supply 30 may be composed of an RF power supply 31 including the first RF generating unit 31a, and a DC power supply 32 including the first DC generating unit 32a and the second DC generating unit 32b.

[0043] The exhaust system 40 may be connected to, for example, a gas exhaust port 10e provided at the bottom of the plasma processing chamber 10. The exhaust system 40 may include a pressure regulating valve and a vacuum pump. The pressure regulating valve regulates the pressure in the plasma processing space 10s. The vacuum pump may include a turbomolecular pump, a dry pump, or a combination thereof.

[0044] The control unit 2 processes computer-executable instructions that cause the plasma processing apparatus 1 to perform various processes described in this disclosure. The control unit 2 may be configured to control each element of the plasma processing apparatus 1 to perform various processes described herein. In one embodiment, part or all of the control unit 2 may be included in the plasma processing apparatus 1. The control unit 2 may include a processing unit 2a1, a storage unit 2a2, and a communication interface 2a3. The control unit 2 may be implemented by, for example, a computer 2a. The processing unit 2a1 may be configured to read a program from the storage unit 2a2 and execute the read program to perform various control operations. The program may be stored in the storage unit 2a2 in advance or may be acquired via a medium when needed. The acquired program is stored in the storage unit 2a2 and read from the storage unit 2a2 by the processing unit 2a1 for execution. The medium may be various storage media readable by the computer 2a or a communication line connected to the communication interface 2a3. The processing unit 2a1 may be a CPU (Central Processing Unit). The storage unit 2a2 may include a random access memory (RAM), a read only memory (ROM), a hard disk drive (HDD), a solid state drive (SSD), or a combination thereof. The communication interface 2a3 may communicate with the plasma processing apparatus 1 via a communication line such as a local area network (LAN).

[0045] <An example of a plasma processing method> A plasma processing apparatus 1 according to one exemplary embodiment performs a plasma processing method (hereinafter also referred to as "the present processing method") for plasma processing a substrate. The plasma processing can be any of various processes using plasma, such as etching, film formation, trimming, and cleaning.

[0046] Fig. 2 is a flowchart showing an example of the present processing method. Fig. 2 shows an example of a method for etching a substrate. As shown in Fig. 2, the present processing method may include a step (ST1) of providing a substrate, a step (ST2) of supplying a processing gas, and a step (ST3) of generating plasma. In one embodiment, a control unit 2 controls each unit of the plasma processing apparatus 1 to perform the present processing method.

[0047] In step ST1, a substrate W is provided in a plasma processing space 10s of the plasma processing apparatus 1. The substrate W is carried into the chamber 10 by a transfer arm and placed on the central region 111a of the substrate support member 11. The substrate W is attracted and held on the substrate support member 11 by an electrostatic chuck 1111 (see FIG. 1).

[0048] 3 is a diagram showing an example of the cross-sectional structure of the substrate W provided in step ST1. The substrate W has an etching target film EF and a metal-containing film MF stacked in this order on an undercoat film UF. The substrate W may be used in the manufacture of semiconductor devices. Examples of semiconductor devices include semiconductor memory devices such as DRAMs and 3D-NAND flash memories.

[0049] The base film UF is, for example, a silicon wafer, an organic film formed on a silicon wafer, a dielectric film, a metal film, a semiconductor film, etc. The base film UF may be configured by stacking a plurality of films.

[0050] The etching target film EF is a film different from the underlayer film UF. The etching target film EF may be, for example, an organic film, a dielectric film, a semiconductor film, or a metal film. The etching target film EF may be composed of a single film or may be composed of a laminate of multiple films. For example, the etching target film EF may be composed of one or more laminated films, such as a silicon-containing film, a carbon-containing film, a spin-on-glass (SOG) film, or a Si-containing anti-reflective coating (SiARC). In one embodiment, the etching target film is a silicon-containing film. In one example, the silicon-containing film is composed of an alternating laminate of a silicon oxide film and a silicon nitride film. In one example, the silicon-containing film is composed of an alternating laminate of a silicon oxide film and a polycrystalline silicon film. In one example, the silicon-containing film is a laminated film including a silicon nitride film, a silicon oxide film, and a polycrystalline silicon film. In one example, the silicon-containing film includes a silicon carbonitride film.

[0051] The mask MK is formed from a material whose etching rate with respect to the plasma generated in step ST3 is lower than that of the etching target film EF. The mask MK may be a single-layer mask consisting of one layer, or may be a multi-layer mask consisting of two or more layers. As shown in FIG. 3, the mask MK defines at least one opening OP on the mask MK. The opening OP is a space on the mask MK and is surrounded by the sidewall of the mask MK. That is, the upper surface of the etching target film EF has a region covered by the mask MK and a region exposed at the bottom of the opening OP.

[0052] The openings OP may have any shape when viewed from above the substrate W, i.e., when the substrate W is viewed from top to bottom in FIG. 3. The shape may be, for example, a circle, an ellipse, a rectangle, a line, or a combination of one or more of these. The mask MK may have multiple side walls that define multiple openings OP. The multiple openings OP may each have a linear shape and be arranged at regular intervals to form a line-and-space pattern. Alternatively, the multiple openings OP may each have a hole shape and form an array pattern.

[0053] In step ST2, a processing gas is supplied to the shower head 13 by the gas supply unit 20, and then supplied from the shower head 13 to the plasma processing space 10s. The processing gas includes a gas that generates activated species necessary for etching the substrate W. The type of processing gas may be appropriately selected based on the material of the film to be etched, the material of the mask, the material of the base film, the pattern of the mask, the etching depth, etc.

[0054] In step ST3, plasma is generated from the processing gas. In step ST3, a source RF signal and a bias signal are supplied to the lower electrode, and a second DC signal (upper DC signal) is supplied to the upper electrode. In one embodiment, the bias signal is a bias RF signal generated by the second RF generator 31b. In one embodiment, the bias signal is a first DC signal (bias DC signal) generated by the first DC generator 32a. This generates plasma from the processing gas in the plasma processing space 10s. A bias potential is also generated between the plasma and the substrate W. Then, active species such as ions and radicals in the plasma are attracted to the substrate W, thereby etching the etching target film EF.

[0055] 4 is a diagram showing an example of the cross-sectional structure of the substrate W during processing in step ST3. As shown in FIG. 4, as the etching progresses, portions of the etching target film EF that are not covered by the mask MK (portions exposed at the openings OP) are etched in the depth direction. As a result, recesses RC are formed in the etching target film EF based on the shape of the openings OP in the mask MK. Then, when a given stop condition is satisfied, the supply of the source RF signal, the bias signal, and the upper DC signal is stopped, and step ST3 is terminated. The stop condition may be, for example, the etching time or the depth of the recesses RC. The aspect ratio of the recesses RC at the end of etching may be, for example, 20 or more, 30 or more, 40 or more, 50 or more, or 100 or more.

[0056] In one embodiment, the source RF signal, bias signal, and upper DC signal (hereinafter collectively referred to as "each signal") are each pulsed and periodically supplied with a given repetition period T (hereinafter also referred to as "period T"). In one embodiment, period T is a period within a range of 20 μs to 800 μs.

[0057] Fig. 5 is a diagram showing an example of the power or voltage of each signal during a period T. Fig. 5 shows an example in which a source RF signal (RF1) and a bias RF signal (RF2) are supplied to the lower electrode, and an upper DC signal (DC2) is supplied to the upper electrode. In Fig. 5, the horizontal axis represents time, and the vertical axis represents the power (effective value of power, as an example) of the source RF signal (RF1) and bias RF signal (RF2), and the voltage (effective value of voltage, as an example) of the upper DC signal (DC2).

[0058] In the example shown in FIG. 5, the period T has a first state Ta (times t11 to t12), a second state Tb (times t12 to t13), and a third state Tc (times t13 to t14), in this order. In one embodiment, the first state Ta occupies 10% to 80% of the period T. In one embodiment, the second state Tb occupies 10% to 80% of the period T. In one embodiment, the third state Tc occupies 10% to 80% of the period T.

[0059] 5, the source RF signal (RF1) is pulsed and has a rectangular power pulse waveform with a duration T. The source RF signal (RF1) has a first power P1 during a first state Ta and a second power P2 lower than the first power P1 during a second state Tb and a third state Tc. In one embodiment, the second power is 0 W.

[0060] 5, the bias RF signal (RF2) is pulsed and has a rectangular power pulse waveform with a period T. The bias RF signal (RF2) has a third power P3 during the first state Ta and the third state Tc, and a fourth power P4 higher than the third power P3 during the second state Tb. In one embodiment, the third power is 0 W.

[0061] In the example shown in FIG. 5, the upper DC signal (DC2) is pulsed and has a rectangular voltage pulse waveform with a period T. The upper DC signal (DC2) has a negative first voltage V1 during the first state Ta and the third state Tc, and a second voltage V2 during the second state Tb. The absolute value of the first voltage V1 is greater than the absolute value of the second voltage V2. In one embodiment, the first voltage V1 is in the range of −500V to −2500V. The second voltage V2 may be positive or negative, or may be 0V. In one embodiment, the second voltage V2 is 0V.

[0062] In the example shown in FIG. 5, between the first state Ta and the second state Tb, the state in which the power level of the source RF signal is high (power level P1) and the state in which the power level of the bias RF signal is high (power level P4) do not overlap. That is, between the first state Ta and the second state Tb, the pulse of the source RF signal and the pulse of the bias RF signal are offset from each other. Also, in the example shown in FIG. 5, between the first state Ta and the second state Tb, the state in which the absolute value of the voltage level of the upper DC signal is high (voltage level V1) and the state in which the power level of the bias RF signal is high (power level P4) do not overlap. That is, between the first state Ta and the second state Tb, the pulse of the upper DC signal and the pulse of the bias RF signal are offset from each other. As a result, during the second state Tb in which the power level of the bias RF signal is high, the absolute values ​​of the power levels or voltage levels of the source RF signal and the upper DC signal are low, or these signals are not supplied. Therefore, the electron density of the plasma in the second state Tb decreases, and the plasma sheath thickness increases. This makes it possible to increase the supply of activated species in the plasma to the bottom of the recess RC in the second state Tb.

[0063] In one embodiment, when ions in the plasma are attracted to the substrate W and the etching target film EF is etched between the first state Ta and the second state Tb, the bottom of the recess RC may become positively charged. In this regard, in the example shown in FIG. 5, the charging of the substrate W may be eliminated or reduced between the third state Tc.

[0064] That is, during the third state Tc, the power levels of the source RF signal and the bias RF signal are low or these signals are not supplied, so charging of the substrate W is suppressed. Also, during the third state Tc, a negative upper DC signal is supplied to the upper electrode, so ions in the plasma are attracted to the upper electrode and secondary electrons are emitted. The emitted secondary electrons are accelerated by the upper electrode, which is at a negative potential (V1), and reach the substrate W. The secondary electrons that reach the substrate W can eliminate or reduce the charging of positively charged portions of the substrate W (for example, the bottom of the recess RC, etc.). This makes it possible to increase the supply of active species in the plasma to the bottom of the recess RC during the next repetition period T.

[0065] 5, during the third state Tc, the power levels of the source RF signal and the bias RF signal are low or these signals are not supplied. Therefore, during the third state Tc, the progress of etching is suppressed and exhaust of by-products generated by etching can be promoted. This allows the supply of activated species in the plasma to the bottom of the recess RC to be increased during the next repetition period T.

[0066] As described above, in one embodiment, the etching rate of the etching target film EF can be improved, and in one embodiment, shape abnormalities and shape deterioration due to etching can be suppressed.

[0067] In recent years, however, there has been a trend toward increasing RF power. As RF power increases, the potential of the plasma in the chamber increases. This increases the potential difference between the plasma and the surface of the upper electrode, and between the back surface of the upper electrode and a location adjacent to the back surface (for example, the cooling plate), which can lead to abnormal discharge.

[0068] 5, during the second state Tb in which the power level of the bias RF signal is high, the absolute values ​​of the power levels or voltage levels of the source RF signal and the upper DC signal are low or these signals are not supplied, thereby preventing the potential difference between the plasma and the upper electrode from increasing.

[0069] FIG. 6 is a diagram for explaining the potential difference between the plasma and the upper electrode during the period T in FIG. 5. FIG. 6 shows an example in which the second voltage V2 is 0 V. In FIG. 6, the horizontal axis indicates time, and the vertical axis indicates potential (V). In FIG. 6, P PL denotes the plasma potential. W denotes the potential of the substrate W. P CL indicates the potential of the upper electrode (shower head 13 in one example).

[0070] As shown in Figure 6, the plasma potential P PL and the potential P of the substrate W W The magnitude (amplitude) of the potential of the upper electrode is small during the first state Ta and is large during the second state Tb. CL The magnitude of the potential difference is large during the first state Ta and small (0 V in this example) during the second state Tb. Therefore, during the second state Tb, the maximum value of the potential difference between the plasma and the upper electrode (Vd in FIG. 6) is prevented from increasing. According to one embodiment, the occurrence of the abnormal discharge described above can be prevented.

[0071] The source RF signal, bias signal, and upper DC signal supplied during the period T are not limited to the example shown in FIG. 5, but may take various forms.

[0072] 7 to 11 are diagrams showing other examples of the power or voltage of each signal supplied during the period T. In FIGS. 7 to 11, the horizontal axis represents time. The vertical axis represents the power (for example, the effective value of the power) of the source RF signal (RF1) / bias RF signal (RF2) and the voltage (for example, the effective value of the voltage) of the bias DC signal (DC1) / upper DC signal (DC2). The following description will focus on the differences from the example shown in FIG. 5, and will omit a description of the same or similar points as in the example shown in FIG. 5.

[0073] In the example shown in FIG. 7, the third state Tc is provided not only after the second state Ta (time t24 to time t25) but also between the first state Ta and the second state Tb (time t22 to time t23). As shown in FIG. 7, the pulse of the bias RF signal may rise at a time (time t23) when a given period has elapsed since the time (time t22) when the pulse of the source RF signal falls. In the example shown in FIG. 7, the relationships between the signals in the first state Ta, the second state Tb, and the third state Tc are the same as those in FIG. 5. Therefore, even in the example shown in FIG. 7, it is possible to obtain effects such as an improvement in the etching rate, suppression of etching shape abnormalities and shape deterioration, and suppression of abnormal discharge.

[0074] The example shown in FIG. 8 is an example in which a third voltage V3 having a negative polarity different from that of the first voltage V1 is supplied as the upper DC signal (DC2) during the third state Tc. As shown in FIG. 8, the absolute value of the third voltage V3 may be greater than that of the first voltage V1. The absolute value of the third voltage V3 may also be smaller than that of the first voltage V1. In one embodiment, the magnitude of the third voltage V3 may be appropriately adjusted depending on the amount of charge on the substrate W between the first state Ta and the second state Tb to enhance the effect of eliminating or suppressing the charge. In the example shown in FIG. 8, the relationships between the signals between the first state Ta, the second state Tb, and the third state Tc are the same as those in the example described in FIG. 5. Therefore, the example shown in FIG. 8 can also achieve effects such as improving the etching rate, suppressing etching shape abnormalities and shape deterioration, and suppressing abnormal discharge.

[0075] The examples shown in Figures 9 to 11 are examples in which a bias DC signal (DC1) is used as the bias signal instead of the bias RF signal in the examples shown in Figures 5, 7, and 8. In the examples shown in Figures 9 to 11, the bias DC signal (DC1) is pulsed and has a rectangular power pulse waveform during the period T.

[0076] 9-11, the bias DC signal (DC1) has a sequence of negative voltage pulses during the second state Tb. In one embodiment, the sequence of negative voltage pulses has a pulse frequency in the range of 100 kHz to 500 kHz. The negative voltage pulses have a fourth voltage V4 of negative polarity. In one embodiment, the fourth voltage V4 is in the range of -5 kV to -30 kV. The waveform of the negative voltage pulses may have a rectangular, trapezoidal, triangular, or combination thereof.

[0077] 9 to 11, the bias DC signal (DC1) has a fifth voltage V5 between the first state Ta and the third state Tc. The absolute value of the fifth voltage V5 is less than the fourth voltage V4. In one embodiment, the fifth voltage is 0 V. Note that in one embodiment, the bias DC signal (DC1) may have a sequence of negative voltage pulses between the first state Ta and the third state Tc. In this case, the absolute value of the voltage of the negative voltage pulses is less than the absolute value of the negative voltage pulses during the second state Tb.

[0078] 9 to 11, the relationships among the bias RF signal, bias DC signal, and upper DC signal in the first state Ta, the second state Tb, and the third state Tc are the same as the relationships among the bias RF signal, bias RF signal, and upper DC signal described in Fig. 5. Therefore, also in the examples shown in Fig. 9 to 11, it is possible to obtain effects such as improvement of the etching rate, suppression of etching shape abnormalities and shape deterioration, and suppression of abnormal discharge.

[0079] <Example> Next, examples of the present processing method will be described, but the present disclosure is not limited to the following examples.

[0080] Example 1 In Example 1, the present processing method was applied using plasma processing apparatus 1 to etch a substrate having a structure similar to that of substrate W shown in FIG. 3. The silicon-containing film SF was a laminated film of a silicon oxide film and a silicon nitride film. In step ST3, each signal had a repetition period T shown in FIG. 5.

[0081] (Reference example 1) In Reference Example 1, the substrate W was etched under the same conditions as in Example 1, except that a constant negative voltage was continuously applied to the upper electrode in step ST3.

[0082] As a result, the etching rate of the silicon-containing film SF in Example 1 was improved compared to Reference Example 1, and the etching shape was also improved.

[0083] Embodiments of the present disclosure further include the following aspects.

[0084] (Appendix 1) a plasma processing chamber; a substrate support disposed within the plasma processing chamber and including a lower electrode; an upper electrode disposed above the substrate support; a first RF signal generator coupled to the lower electrode and configured to generate a first RF signal, the first RF signal having a first power level during a first state within a repeating period, a second power level less than the first power level during a second state within the repeating period, and the second power level during a third state within the repeating period; a second RF signal generator coupled to the lower electrode and configured to generate a second RF signal, the second RF signal having a third power level during the first state, a fourth power level greater than the third power level during the second state, and the third power level during the third state; a DC signal generator coupled to the upper electrode and configured to generate a DC signal, the DC signal having a first voltage level during the first state and a second voltage level during the second state, the absolute value of the first voltage level being greater than the absolute value of the second voltage level; A plasma processing apparatus comprising:

[0085] (Appendix 2) 2. The plasma processing apparatus of claim 1, wherein the first voltage level has a negative polarity.

[0086] (Appendix 3) 3. The plasma processing apparatus of claim 1, wherein the DC signal has a third voltage level of negative polarity during the third state.

[0087] (Appendix 4) 4. The plasma processing apparatus of claim 1, wherein the second power level is a zero power level.

[0088] (Appendix 5) 5. The plasma processing apparatus of claim 1, wherein the third power level is a zero power level.

[0089] (Appendix 6) 6. The plasma processing apparatus of claim 1, wherein the second voltage level is a zero voltage level.

[0090] (Appendix 7) 7. The plasma processing apparatus according to claim 1, wherein the frequency of the first RF signal is higher than the frequency of the second RF signal.

[0091] (Appendix 8) 8. The plasma processing apparatus according to claim 1, wherein the repeating period is a period in a range of 20 μs to 800 μs.

[0092] (Appendix 9) 9. The plasma processing apparatus according to claim 1, wherein the first state occupies 10% to 80% of the repeating period.

[0093] (Appendix 10) 10. The plasma processing apparatus according to claim 1, wherein the second state occupies 10% to 80% of the repeating period.

[0094] (Appendix 11) 11. The plasma processing apparatus of claim 1, wherein the third state occupies 10% to 80% of the repeating period.

[0095] (Appendix 12) 12. The plasma processing apparatus of claim 1, wherein the first voltage level is in the range of −500V to −2500V.

[0096] (Appendix 13) a plasma processing chamber; a substrate support disposed within the plasma processing chamber and including a lower electrode; an upper electrode disposed above the substrate support; an RF signal generator coupled to the lower electrode and configured to generate an RF signal, the RF signal having a first power level during a first state within a repeating period, a second power level less than the first power level during a second state within the repeating period, and the second power level during a third state within the repeating period; a first DC signal generator coupled to the lower electrode and configured to generate a first DC signal, the first DC signal having a sequence of voltage pulses having a first voltage level during the first state, a second voltage level during the second state, and the first voltage level during the third state, wherein an absolute value of the first voltage level is less than an absolute value of the second voltage level; a second DC signal generator coupled to the upper electrode and configured to generate a second DC signal, the second DC signal having a third voltage level during the first state and a fourth voltage level during the second state, the absolute value of the third voltage level being greater than the absolute value of the fourth voltage level; A plasma processing apparatus comprising:

[0097] (Appendix 14) 14. The plasma processing apparatus of claim 13, wherein the second voltage level has a negative polarity.

[0098] (Appendix 15) 15. The plasma processing apparatus of claim 13 or 14, wherein the sequence of voltage pulses has a pulse frequency in the range of 100 kHz to 500 kHz.

[0099] (Appendix 16) 16. The plasma processing apparatus of claim 13, wherein the first voltage level is a zero voltage level.

[0100] (Appendix 17) 17. The plasma processing apparatus of claim 13, wherein the second voltage level is in a range of −5 kV to −30 kV.

[0101] (Appendix 18) 18. The plasma processing apparatus of claim 13, wherein the third voltage level has a negative polarity.

[0102] (Appendix 19) 19. The plasma processing apparatus of any one of Appendix 13 to Appendix 18, wherein the second DC signal has a fifth voltage level of negative polarity during the third state.

[0103] (Appendix 20) 20. The plasma processing apparatus of claim 13, wherein the fourth voltage level is a zero power level.

[0104] (Appendix 21) A plasma processing method using a plasma processing apparatus, comprising: the plasma processing apparatus includes a plasma processing chamber, a substrate support disposed in the plasma processing chamber and including a lower electrode, an upper electrode disposed above the substrate support, a first RF signal generator, a second RF signal generator, and a DC signal generator; The plasma processing method includes: (a) providing a substrate on the substrate support; (b) supplying a process gas into the plasma processing chamber; and (c) generating a plasma from the process gas; In the step (c), a first RF signal is supplied from the first RF signal generator to the lower electrode, the first RF signal having a first power level during a first state within a repeating period, a second power level less than the first power level during a second state within the repeating period, and the second power level during a third state within the repeating period; a second RF signal is provided from the second RF signal generator to the lower electrode, the second RF signal having a third power level during the first state, a fourth power level greater than the third power level during the second state, and the third power level during the third state; a DC signal is provided from the DC signal generator to the upper electrode, the DC signal having a first voltage level during the first state and a second voltage level during the second state, the absolute value of the first voltage level being greater than the absolute value of the second voltage level; Plasma treatment method.

[0105] (Appendix 22) A plasma processing method using a plasma processing apparatus, comprising: the plasma processing apparatus comprises a plasma processing chamber, a substrate support disposed in the plasma processing chamber and including a lower electrode, an upper electrode disposed above the substrate support, an RF signal generator, a first DC signal generator, and a second DC signal generator; The plasma processing method includes: (a) providing a substrate on the substrate support; (b) supplying a process gas into the plasma processing chamber; and (c) generating a plasma from the process gas; In the step (c), an RF signal is provided from the RF signal generator to the lower electrode, the RF signal having a first power level during a first state within a repeating period, a second power level less than the first power level during a second state within the repeating period, and the second power level during a third state within the repeating period; a first DC signal is supplied to the lower electrode from the first DC signal generator, the first DC signal having a sequence of voltage pulses having a first voltage level during the first state, a second voltage level during the second state, and the first voltage level during the third state, the absolute value of the first voltage level being less than the absolute value of the second voltage level; a second DC signal is supplied to the upper electrode from the second DC signal generator, the second DC signal having a third voltage level during the first state and a fourth voltage level during the second state, the absolute value of the third voltage level being greater than the absolute value of the fourth voltage level; Plasma treatment method.

[0106] The above embodiments are described for the purpose of explanation and are not intended to limit the scope of the present disclosure. Various modifications can be made to the above embodiments without departing from the scope and spirit of the present disclosure. For example, some components in one embodiment can be added to other embodiments. Also, some components in one embodiment can be replaced with corresponding components in other embodiments. [Explanation of symbols]

[0107] REFERENCE SIGNS LIST 1: plasma processing apparatus, 2: control unit, 10: plasma processing chamber, 10s: plasma processing space, 11: substrate support unit, 13: shower head, 20: gas supply unit, 30: power supply, 31: RF power supply, 31a: first RF generation unit, 31b: second RF generation unit, 32: DC power supply, 32a: first DC generation unit, 32b: second DC generation unit, SF: silicon-containing film, MK: mask, OP: opening, RC: recess, UF: base film, W: substrate

Claims

1. a plasma processing chamber; a substrate support disposed within the plasma processing chamber and including a lower electrode; an upper electrode disposed above the substrate support; a first RF signal generator coupled to the lower electrode and configured to generate a first RF signal, the first RF signal having a first power level during a first state within a repeating period, a second power level less than the first power level during a second state within the repeating period, and the second power level during a third state within the repeating period; a second RF signal generator coupled to the lower electrode and configured to generate a second RF signal, the second RF signal having a third power level during the first state, a fourth power level greater than the third power level during the second state, and the third power level during the third state; a DC signal generator coupled to the upper electrode and configured to generate a DC signal, the DC signal having a first voltage level during the first state and a second voltage level during the second state, the absolute value of the first voltage level being greater than the absolute value of the second voltage level; A plasma processing apparatus comprising:

2. The plasma processing apparatus of claim 1 , wherein the first voltage level has a negative polarity.

3. The plasma processing apparatus of claim 2 , wherein the DC signal has the first voltage level during the third state.

4. The plasma processing apparatus of claim 3 , wherein the second power level is a zero power level.

5. The plasma processing apparatus of claim 4 , wherein the third power level is a zero power level.

6. The plasma processing apparatus of claim 5 , wherein the second voltage level is a zero voltage level.

7. The plasma processing apparatus of claim 6 , wherein the frequency of the first RF signal is greater than the frequency of the second RF signal.

8. The plasma processing apparatus of claim 1 , wherein the repeat period is in a range of 20 μs to 800 μs.

9. The plasma processing apparatus of claim 1 , wherein the first state is in a range of 10% to 80% of the repeating period.

10. The plasma processing apparatus of claim 1 , wherein the second state is in a range of 10% to 80% of the repeating period.

11. 8. The plasma processing apparatus of claim 1, wherein the third state is in a range of 10% to 80% of the repeating period.

12. 8. The plasma processing apparatus according to claim 1, wherein the first voltage level is in the range of −500V to −2500V.

13. a plasma processing chamber; a substrate support disposed within the plasma processing chamber and including a lower electrode; an upper electrode disposed above the substrate support; an RF signal generator coupled to the lower electrode and configured to generate an RF signal, the RF signal having a first power level during a first state within a repeating period, a second power level less than the first power level during a second state within the repeating period, and the second power level during a third state within the repeating period; a first DC signal generator coupled to the lower electrode and configured to generate a first DC signal, the first DC signal having a sequence of voltage pulses having a first voltage level during the first state, a second voltage level during the second state, and the first voltage level during the third state, wherein an absolute value of the first voltage level is less than an absolute value of the second voltage level; a second DC signal generator coupled to the upper electrode and configured to generate a second DC signal, the second DC signal having a third voltage level during the first state and a fourth voltage level during the second state, the absolute value of the third voltage level being greater than the absolute value of the fourth voltage level; A plasma processing apparatus comprising:

14. The plasma processing apparatus of claim 13 , wherein the second voltage level has a negative polarity.

15. The plasma processing apparatus of claim 14 , wherein the sequence of voltage pulses has a pulse frequency in the range of 100 kHz to 500 kHz.

16. 16. The plasma processing apparatus of claim 15, wherein the first voltage level is a zero voltage level.

17. 17. The plasma processing apparatus of claim 16, wherein the second voltage level is in the range of -5 kV to -30 kV.

18. 18. The plasma processing apparatus of claim 13, wherein the third voltage level has a negative polarity.

19. 20. The plasma processing apparatus of claim 18, wherein the second DC signal has the third voltage level during the third state.

20. 20. The plasma processing apparatus of claim 19, wherein the fourth voltage level is a zero voltage level.

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