Cache, cache management method, and electronic device

Abstract

This application provides a cache, a cache management method, and an electronic device. The cache includes a plurality of cache lines, a first read request queue, and a second read request queue. The first read request queue is configured to store and send first read requests to a main memory control device, the first read requests requesting data from a main memory and storing the data in the main memory control device. The number of first read requests that can be stored in the first read request queue is greater than the number of cache lines. The second read request queue is configured to store and send second read requests to the main memory control device, the second read requests corresponding to the first read requests one-to-one, and the second read requests are configured to request data corresponding to the first read requests from the main memory control device if the cache line corresponding to the first read request is empty. The cache has relatively high processing efficiency.

Description

[Technical Field]

[0001] The present application is in the field of chips, and specifically relates to caches, cache management methods and electronic devices. [Background technology]

[0002] To improve the processing speed of the processor, a cache is installed between the processor and the main memory. When the processor reads data, it first searches for the data in the cache. If the data is stored in the cache, it returns it directly to the processor for processing. If the data is not stored in the cache, it reads it from the main memory and returns it to the processor for processing, while storing the data in the cache. This eliminates the need to read it from the main memory and allows the data to be obtained directly from the cache.

[0003] Because the memory space of a cache is relatively small, when a processor processes a large amount of data, the data stored in the cache must be frequently updated. During the data update process, the processor requests data from the cache, the cache requests the data from the main memory, the main memory returns the data to the cache, and then the cache returns the data to the processor. Because the physical distance between the cache and the main memory is relatively long, it usually takes several hundred clock cycles to transmit data from the main memory to the cache. During the cache operation process, most of the time is spent waiting for data to be transmitted from the main memory to the cache, which greatly reduces the processing efficiency of the cache. Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the embodiments of the present application is to provide a cache, a cache management method, and an electronic device that improve the processing efficiency of the cache. [Means for solving the problem]

[0005] In a first aspect, the present application provides a cache including a plurality of cache lines, a first read request queue, and a second read request queue, the first read request queue configured to store and send first read requests to a main memory controller, the first read requests requesting data from a main memory and configured to store the data in the main memory controller, a number of first read requests storable in the first read request queue greater than the number of cache lines, the second read request queue configured to store and send second read requests to the main memory controller, the second read requests corresponding to the first read requests in a one-to-one correspondence, and the second read requests configured to request data corresponding to the first read requests from the main memory controller if the cache line corresponding to the first read request is free.

[0006] In an embodiment of the present application, a number of first read requests greater than the number of cache lines is sent to the main memory controller in advance to store data in the main memory controller in advance, and when a cache line is available, data is directly obtained from the main memory controller, thereby shortening the time required for data transmission from the main memory to the cache, and thereby improving the processing efficiency of the cache.

[0007] In an optional embodiment, the cache further includes a third read request queue, the third read request queue configured to store a cache line number corresponding to the first read request and to store data corresponding to the first read request in the cache line corresponding to the first read request based on the cache line number of the first read request.

[0008] In an alternative embodiment, the cache further includes a cache control device and a first buffer, the cache control device configured to allocate a cache line to a request sent by a processor, the request being a request that does not hit the cache, and the first buffer configured to determine whether a read-after-write situation exists on the cache line corresponding to the request, and if a read-after-write situation does not exist on the cache line corresponding to the request, generate a first read request and send it to the first read request queue, and if a read-after-write situation exists on the cache line corresponding to the request, store the request, and determine whether a read-after-write situation exists on the cache line corresponding to a request following the first request.

[0009] In an embodiment of the present application, when a read-after-write situation occurs for a request, the request is stored in a first buffer, and the first read request is not generated by the request; the cache can continue to process subsequent requests of the request, and there is no need to wait for the read-after-write situation to be resolved before processing subsequent requests. This reduces the impact of the read-after-write situation on the processing efficiency of the cache, and further improves the processing efficiency of the cache.

[0010] In an alternative embodiment, the first buffer is further configured to generate a first read request corresponding to a request stored in the first buffer when a read-after-write condition corresponding to the request is lifted.

[0011] In an embodiment of the present application, when a read-after-write condition occurs for a request, the request is stored in a first buffer, and subsequent requests for the request are processed by the cache. After the read-after-write condition for the request is cleared, a first read request corresponding to the request is generated, so that the request for which the read-after-write condition occurred is subsequently processed by the cache.

[0012] In an alternative embodiment, the first buffer includes trigger groups whose number is the same as the number of cache lines, each trigger corresponding to one cache line, the triggers configured to store requests for which a read-after-write condition exists, and the cache line corresponding to the request is the same as the cache line corresponding to the trigger that stores the request.

[0013] In an alternative embodiment, the cache control device is specifically configured to select a cache line other than a cache line corresponding to a target request and allocate the cache line to the request sent by the processor, the target request being a request stored in the first buffer.

[0014] In an embodiment of the present application, when the cache control device determines a cache line for a request, it selects a cache line that does not have a read-after-write situation and assigns the cache line to the request sent by the processor, thereby preventing the occurrence of a new read-after-write situation and further improving the processing efficiency of the cache.

[0015] In an alternative embodiment, the cache further includes a second buffer and a send queue, the second buffer configured to store write requests, the number of pending requests, and the number of processed requests for each cache line, and when the number of pending requests corresponding to a cache line is the same as the number of processed requests corresponding to the cache line, the write request corresponding to the cache line is sent to the send queue.

[0016] In an embodiment of the present application, a determination is made on the number of pending requests and the number of processed requests for the cache line, and if both are the same, a write request corresponding to the cache line is sent to a send queue, thereby writing the data in the cache line back to the main memory.

[0017] In an alternative embodiment, the second buffer includes trigger groups whose number is equal to the number of cache lines, each trigger corresponding to one cache line, and configured to store write requests, the number of pending requests, and the number of processed requests for the corresponding cache line.

[0018] In an alternative embodiment, the cache further includes a determination module configured to determine which cache lines to process based on a state of each cache line and predetermined rules; and / or The cache further includes a multi-thread queue, the multi-thread queue including multiple threads, each thread corresponding to a cache line, and configured to store pending requests for the corresponding cache line.

[0019] In a second aspect, the present application provides a cache management method, which is applied to the cache according to the first aspect, the cache including a plurality of cache lines, a first read request queue, and a second read request queue, the cache management method including the steps of: the first read request queue sending a first read request to a main memory control device; and the second read request queue sending a second read request to the main memory control device if a cache line corresponding to the first read request is free, the first read request being for requesting data from a main memory and storing the data in the main memory control device; and the second read request being for requesting the data corresponding to the first read request from the main memory control device.

[0020] In an alternative embodiment, the cache further includes a third read request queue, and the method further includes the step of the third read request queue storing data corresponding to the first read request in a cache line corresponding to the first read request based on a cache line number of the first read request.

[0021] In an alternative embodiment, the cache further includes a cache controller and a first buffer. The method further includes the following steps: the cache controller allocates a cache line to a request sent by a processor, the request is a request that does not hit the cache, and the first buffer determines whether a read-after-write condition exists on the cache line corresponding to the request, generates a first read request if a read-after-write condition does not exist on the cache line corresponding to the request, stores the request in the first buffer if a read-after-write condition exists on the cache line corresponding to the request, and determines whether a read-after-write condition exists on the cache line corresponding to a request following the first request.

[0022] In an optional embodiment, the method further includes a step in which the first buffer generates a first read request corresponding to a request stored in the first buffer when a read-after-write condition corresponding to the request is cleared.

[0023] In an alternative embodiment, the first buffer includes trigger groups whose number is the same as the number of cache lines, each trigger corresponding to one cache line, the triggers configured to store requests for which a read-after-write condition exists, and the cache line corresponding to the request is the same as the cache line corresponding to the trigger that stores the request.

[0024] In an alternative embodiment, allocating a cache line to a request sent by a processor includes the cache control device selecting a cache line other than a cache line corresponding to a target request and allocating the cache line to the request sent by the processor, the target request being a request stored in the first buffer.

[0025] In an alternative embodiment, the cache further includes a second buffer and a transmit queue. The method further includes the steps of: storing a write request, a number of pending requests, and a number of processed requests for each cache line in the second buffer; when the number of pending requests corresponding to a cache line is the same as the number of processed requests corresponding to the cache line, transmitting the write request corresponding to the cache line to a transmit queue; and transmitting the write request to the main memory control device via the transmit queue.

[0026] In an alternative embodiment, the second buffer includes trigger groups whose number is equal to the number of cache lines, each trigger corresponding to one cache line, and configured to store write requests, the number of pending requests, and the number of processed requests for the corresponding cache line.

[0027] In an alternative embodiment, the cache further comprises a determination module. The method further comprises the steps of:

[0028] The determination module determines the cache line to be processed based on the state of each cache line and a predetermined rule; and / or The cache further includes a multi-thread queue, the multi-thread queue including multiple threads, each thread corresponding to one cache line, and the method further includes a step in which each thread stores pending requests for its corresponding cache line.

[0029] In a third aspect, the present application provides an electronic device, the electronic device comprising a processor and the cache according to any one of the first aspects above. [Brief explanation of the drawings]

[0030] In order to more clearly explain the technical solutions of the embodiments of the present application, the drawings used in the embodiments of the present application will be briefly described below. The drawings described are only for illustrating some embodiments of the present application and are not intended to limit the scope. Those skilled in the art can obtain other related drawings based on these drawings without using inventive abilities. [Figure 1] 1 is a block diagram showing a configuration of an electronic device according to an embodiment of the present application. [Figure 2] FIG. 2 is a schematic configuration diagram of a cache according to an embodiment of the present application. [Figure 3] FIG. 2 is a schematic configuration diagram of a first buffer according to an embodiment of the present application; [Figure 4] 4 is a flowchart of the operation of a cache according to an embodiment of the present application. [Figure 5] 1 is a flowchart of a cache management method according to an embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0031] Hereinafter, the technical solutions of the embodiments of the present application will be described with reference to the drawings in the embodiments of the present application.

[0032] To improve the processing efficiency of the cache, the present application provides a cache, a cache management method and an electronic device.

[0033] Referring to FIG. 1, FIG. 1 is a block diagram showing the configuration of an electronic device according to an embodiment of the present application. The electronic device 100 includes a processor 101, a cache 102, a main memory control device 103, and a main memory 104. The main memory control device 103 is installed between the cache 102 and the main memory 104. The processor 101 can access the cache 102, and the cache 102 stores data currently being processed by the processor 101. If the cache 102 does not store data to be processed by the processor 101, the cache 102 sends a read request to the main memory control device 103, and the main memory control device 103 retrieves the data to be processed by the processor 101 from the main memory 104 based on the read request. After the processor 101 has finished processing the data, the cache 102 sends a write request to the main memory control device 103, and the main memory control device 103 updates the data in the main memory 104 based on the write request.

[0034] The processor 101 has signal processing capabilities and may be a central processing unit (CPU), a graphics processing unit (GPU), a pixel processor (PP), a vertex processor (VP), or the like.

[0035] The cache 102 includes multiple cache lines, each of which is the smallest unit of data transmission between the cache 102 and the main memory controller 103. Each cache line has attributes such as a tag, an idx, and a validity. The tag indicates the address of the data in the cache line in the main memory 104, the idx indicates the location of the cache line in the cache 102, and the valid indicates whether the data currently stored in the cache line is valid. Only data in a cache line with a valid value is output by the cache 102. After the cache 102 receives a request from the processor 101, the cache controller generates a tag based on the address of the request and compares it with the tag of each cache line. If a cache line with an equal tag exists, it is called a cache hit, and the cache 102 returns the data in the corresponding cache line directly to the processor 101. If no cache line with an equal tag exists, it is called a cache miss. The cache 102 first requests the corresponding data from the main memory controller 103, stores the data in a cache line, and then returns the data to the processor 101. After the cache 102 is initialized, the default valid attribute of all cache lines is invalid, and each cache line is set to valid after receiving the data returned by the main memory controller 103.

[0036] The electronic device 100 may be a physical device such as, but not limited to, a desktop computer, a laptop, a smartphone, a smart wearable device, an in-vehicle device, etc. Also, the electronic device is not necessarily a single device, but may be a combination of multiple devices, such as a server cluster.

[0037] 2, which is a schematic diagram of a cache according to an embodiment of the present application. The cache 102 includes a first read request queue 201 and a second read request queue 202.

[0038] The first read request queue 201 is configured to store first read requests. The first read requests are configured to request data from the main memory 104 and store the data in the main memory controller 103. The number of first read requests that can be stored in the first read request queue 201 is greater than the number of cache lines in the cache.

[0039] The second read request queue 202 is configured to store second read requests. The second read requests correspond one-to-one to the first read requests, and are configured to request data corresponding to the first read request from the main memory control device 103 if the cache line corresponding to the first read request is available.

[0040] In some embodiments, the first read request queue 201 and the second read request queue 202 are first-in, first-out queues. In this application, the first read request queue 201 and the second read request queue 202 are not limited to a specific implementation form and can be any hardware having a data storage function.

[0041] In the process of data processing, the processor 101 generates a large number of requests, which are sent to the cache 102. After a request arrives at the cache 102, if the request does not hit a cache line in the cache 102, a cache line is allocated to the request, a first read request and a second read request are generated, the first read request is stored in the first read request queue 201, and the second read request is stored in the second read request queue 202. When the main memory control device 103 is able to receive the first read requests, the first read request queue 201 sequentially sends the stored first read requests to the main memory control device 103, and after receiving the first read requests, the main memory control device 103 requests the main memory 104 to obtain the corresponding data based on the first read request and stores the obtained data in its own storage unit.

[0042] If a cache line corresponding to a certain first read request is free, a second read request corresponding to the first read request is sent to the main memory control device 103 by the second read request queue 202, and after the main memory control device 103 receives the second read request, it sends the data corresponding to the first read request stored in its own storage unit to the cache 102, thereby obtaining the data requested by the processor 101 from the main memory 104 and storing the data in the allocated cache line.

[0043] A cache line being free means that the cache line is in an initialized state or that the data currently stored therein has been processed by the processor 101 and updated to the main memory 104, and the data currently stored in the cache line can be overwritten by other data.

[0044] When a large number of requests are generated from the processor 101 and none of these requests hit a cache line in the cache 102, one cache line is allocated to each request. Because there is a limit to the number of cache lines in the cache 102, if the number of requests that do not hit the cache 102 is greater than the number of cache lines, one cache line will handle multiple requests.

[0045] For example, suppose 16 cache lines (cache line 1 to cache line 16) are installed in cache 102, and processor 101 sends 32 requests with different tags to cache 102. None of these 32 requests hit a cache line in cache 102. Cache 102 assigns requests 1 to 16 in order to cache lines 1 to 16, and requests 17 to 32 in order to cache lines 1 to 16. Cache line 1 processes the first request and the 17th request. Each request generates a first read request and a second read request, respectively. For simplicity, the first read request generated by the first request is referred to as first read request 1, the second read request generated by the first request is referred to as second read request 1, the first read request generated by the second request is referred to as first read request 2, the second read request generated by the second request is referred to as second read request 2, and so on. The first read request queue 201 stores the first read requests 1 to 32. When the main memory control device 103 is able to receive the first read requests, the first read request queue 201 transmits the first read requests 1 to 32 to the main memory control device 103, and the main memory control device 103 requests data corresponding to the first to 32nd requests from the main memory and stores this data in the memory space of the main memory control device 103.

[0046] Assume that all cache lines are free in the initial state. A first request corresponds to cache line 1, and cache line 1 is free. In this case, second read request queue 202 sends second read request 1 to main memory controller 103, and main memory controller 103 returns the data obtained based on first read request 1 to the cache, and cache line 1 stores the data corresponding to the first request. Later, processor 101 accesses cache line 1 to perform data processing related to the data corresponding to the first request. During this process, cache line 1 is in use.

[0047] Since the 17th request corresponds to cache line 1 and cache line 1 is processing the first request, cache line 1 is not free, so the second read request queue 202 does not send the second read request 17 to the main memory control device 103, and the main memory control device 103 does not return the data corresponding to the 17th request, thereby preventing the data corresponding to the first request stored in cache line 1 from being overwritten by the data corresponding to the 17th request.

[0048] After the data corresponding to the first request is processed by the processor 101, the 17th request needs to use cache line 1, so the second buffer 206 sends a write request to the main memory controller 103 to update the cache line data where the data corresponding to the first request is located in the main memory 104, after which cache line 1 becomes free, the second read request queue 202 sends a second read request 17 to the main memory controller 103, and the main memory controller 103 returns the data corresponding to the 17th request, overwriting the data corresponding to the first request originally stored in cache line 1 with the data corresponding to the 17th request. Later, the processor 101 accesses cache line 1 to perform related data processing on the data corresponding to the 17th request.

[0049] The cache 102 and the main memory 104 are physically far apart, resulting in a relatively large data transmission delay, typically several hundred clock cycles. The main memory controller 103 and the cache 102 are physically close, resulting in a relatively small data transmission delay, typically only several dozen clock cycles. In an embodiment of the present application, a first read request, the number of which is greater than the number of cache lines, is sent to the main memory controller 103 in advance to store data in the main memory controller 103 in advance. When a cache line is available, data is directly obtained from the main memory controller 103, thereby shortening the time required for data transmission from the main memory 104 to the cache 102 and improving the cache processing efficiency.

[0050] In one alternative embodiment, the cache 102 further includes a third read request queue 203 .

[0051] The third read request queue 203 is configured to store a cache line number corresponding to the first read request. After the second read request queue 202 sends the second read request, it stores the corresponding cache line number (i.e., cache line idx) in the third read request queue 203, so that after returning the data corresponding to the first read request by the MC, the third read request queue 203 stores the returned data in the cache line corresponding to the first read request based on the cache line number corresponding to the first read request.

[0052] In some embodiments, the first read request queue 201 is further configured to store a cache line idx that stores the read request data in the cache. After sending the first read request to the main memory controller 103, the first read request queue 201 sends a cache line idx that stores the data in the cache 102 to the third read request queue 203.

[0053] In some other embodiments, the second read request queue 202 is further configured to store a cache line idx that stores the read request data in the cache. After sending the second read request to the main memory controller 103, the second read request queue 202 sends a cache line idx that stores the data in the cache 102 to the third read request queue 203.

[0054] Additionally, in one alternative embodiment, cache 102 further includes a cache controller 204 and a first buffer 205 .

[0055] Cache controller 204 is configured to allocate cache lines to requests sent by processor 101 .

[0056] The first buffer 205 is configured to determine whether a read-after-write condition exists on a cache line corresponding to a request. If a read-after-write condition does not exist on a cache line corresponding to the request, the first buffer 205 generates a first read request and sends it to the first read request queue 201. If a read-after-write condition exists on a cache line corresponding to the request, the first buffer 205 stores the request and determines whether a read-after-write condition exists on a cache line corresponding to a request following the first request.

[0057] In the present embodiment, after the processor 101 sends a request to the cache 102, the cache controller 204 generates a tag based on the address of the request and compares it with the respective tags of each cache line. In the case of a cache hit, the cache 102 returns the data in the hit cache line to the processor 101, and the processor 101 performs processing on the data.

[0058] If the cache does not hit, it means that the data requested by the processor 101 is not stored in the cache 102, and in this case, the cache 102 requests the main memory 104 to obtain the data. To obtain the data, the cache controller 204 allocates one cache line to the request based on a predetermined replacement algorithm. When the processor 101 frequently requests the cache 102, if there are no free cache lines in the cache 102, a read-after-write situation occurs.

[0059] A read-after-write state means that only when a new request is assigned to a cache line in the cache 102, the cache 102 sends a write request to the main memory controller 103 and writes the data stored therein back to the main memory 104. To ensure data consistency, the main memory 104 returns a write completion signal to the cache 102 after receiving data lineA from the cache line. If a new request, requestB, requests the cache line containing data lineA before the cache 102 receives the write completion signal for data lineA, the cache 102 sends a first read request corresponding to the new request, requestB, to the main memory controller 103 to request data from the main memory 104 only after receiving the write completion signal for data lineA. This phenomenon is known as read-after-write. Cancellation of read-after-write means that the write completion signal associated with read-after-write reaches the cache 102, allowing the cache 102 to send a first read request corresponding to requestB. Because of the relatively long communication delay between the cache 102 and the main memory 104, when a read-after-write situation occurs, the cache 102 must wait a relatively long time before it can continue operating. Also, because only one cache line in the cache 102 is exchanging data at the same time, when a read-after-write situation occurs, the cache 102 continues to process subsequent requests after the read-after-write situation is cleared, resulting in relatively low cache processing efficiency.

[0060] To solve the above problem, in an embodiment of the present application, a first buffer 205 is provided in the cache. After the cache control device 204 allocates a cache line to a request, the first buffer 205 makes a judgment on the cache line corresponding to the request. If the cache line corresponding to the request does not have a read-after-write status, a first read request is generated and sent to the first read request queue 201, which requests the main memory 104 to obtain the corresponding data. If the cache line corresponding to the request has a read-after-write status, the request is stored in the first buffer 205, and a judgment is made on whether the cache line corresponding to the next request after the first request has a read-after-write status. The processing method for the next request is the same as the above processing method.

[0061] According to the above scheme, if a read-after-write condition occurs for a request, the request is stored in the first buffer 205, and the request does not generate a first read request, and the cache 102 can continue to process subsequent requests of the request, without having to wait for the read-after-write condition to be cleared before processing the subsequent requests, thereby further improving the processing efficiency of the cache.

[0062] Additionally, in one alternative embodiment, the first buffer 205 is further configured to generate a first read request corresponding to a request stored in the first buffer when the read-after-write condition corresponding to the request is lifted.

[0063] In an embodiment of the present application, after the read-after-write status of the request stored in the first buffer 205 is released, the request is released from the first buffer 205, a first read request is generated based on the request, the first read request is sent to the first read request queue 201, and the first read request queue 201 requests the main memory 104 to obtain the data corresponding to the request.

[0064] Further, in some embodiments, the first buffer 205 includes trigger groups whose number is equal to the number of cache lines, each trigger corresponding to one cache line, and the triggers are configured to store requests for which a read-after-write condition exists, and the cache line corresponding to the request is the same as the cache line corresponding to the trigger that stores the request.

[0065] As shown in FIG. 3, skid_buf in FIG. 3 is a trigger group, and one cache line corresponds to one trigger. When the idx of a cache line assigned to a request is 1 and a read-after-write situation occurs in the cache line, the tag corresponding to the request (i.e., the request tag in FIG. 3) is saved in the trigger L1. skid_buf_vld indicates whether data is saved in each trigger in the trigger group, and is used by the determination module to later determine the state of each cache line. RAW released indicates that the trigger group has received information that the read-after-write (RAW) situation of a cache line has been released. release RAW's idx indicates the idx corresponding to the cache line whose read-after-write situation has been released. release tag indicates that after receiving information that the read-after-write situation of a cache line has been released, the tag stored in the trigger corresponding to the cache line is released from the trigger.

[0066] Furthermore, in one alternative embodiment, cache controller 204 allocates cache lines to requests sent from processors in the following manner.

[0067] A cache line other than the cache line corresponding to the target request is selected and allocated to the request sent by the processor. The target request is a request stored in the first buffer.

[0068] In an embodiment of the present application, when a read-after-write situation occurs in one cache line, in order to improve cache processing efficiency, when allocating a cache line to a subsequent request, a cache line other than the cache line in question is selected and allocated to the subsequent request.

[0069] Specifically, a target queue is provided in the cache controller 204, which stores information about cache lines that can be allocated to the target queue. When allocating a cache line, the cache controller 204 selects a cache line from the target queue based on a predetermined replacement algorithm. A set of triggers is provided in the cache controller 204 to store information about cache lines that have a read-after-write condition. When a read-after-write condition occurs for a cache line, the information about the cache line is moved from the target queue to a trigger group, and cache lines in the trigger group are not selected by the replacement algorithm. After the read-after-write condition for the cache line is released, the information about the cache line is moved from the trigger group to the target queue.

[0070] According to the above method, when the cache control device 204 determines a cache line for a request, it selects a cache line that does not have a read-after-write status and assigns the cache line to the request sent by the processor, thereby preventing the occurrence of a new read-after-write status and further improving the cache processing efficiency.

[0071] Additionally, in one alternative embodiment, cache 102 further includes a second buffer 206 and a transmit queue 207 .

[0072] The second buffer 206 is configured to store a write request, the number of pending requests, and the number of processed requests for each cache line. If the number of pending requests corresponding to a cache line is the same as the number of processed requests corresponding to the cache line, the second buffer 206 sends the write request corresponding to the cache line to the send queue 207.

[0073] The send queue 207 is configured to store write requests waiting to be sent and to send the write requests to the main memory controller 103, which writes the data stored in the cache line back to the main memory 104 based on the write requests.

[0074] Furthermore, in an alternative embodiment, the transmit queue 207 is further configured to store write requests that have been sent but have not yet received a write completion signal. The transmit queue 207 includes write requests waiting to be sent and write requests that have been sent but have not yet received a write completion signal. The first buffer 205 determines whether a read-after-write condition exists for a cache line based on all the write requests stored in the transmit queue 207. If the cache line corresponding to a newly generated read request is the same as the cache line corresponding to a write request stored in the transmit queue 207, it is determined that the read-after-write condition exists for the cache line.

[0075] In some embodiments, taking one cache line as an example, during the process in which processor 101 makes a request to cache 102, after each request arrives at cache 102, cache 102 determines whether the request hits. If the cache line is hit, it increments the number of pending requests for that cache line by one. Each time the cache line finishes processing a request, it increments the number of processed requests for that cache line by one. When the number of pending requests and the number of processed requests for the cache line become the same, processor 101 will no longer process the data stored in that cache line, and the current data stored in that cache line needs to be written back to main memory 104. Therefore, second buffer 206 sends a write request corresponding to that cache line to send queue 207.

[0076] In some other embodiments, if the number of pending requests for the cache line is the same as the number of processed requests and there are read requests for the cache line in the first read request queue 201 or the second read request queue 202, it means that the processor 101 has completed processing the data stored in the current cache line and needs to write the current data stored in the cache line back to the main memory 104, so that the cache line can be allocated to the next request. The second buffer 206 sends a write request corresponding to the cache line to the send queue 207.

[0077] Further, in some embodiments, the second buffer 206 includes trigger groups whose number is equal to the number of cache lines, each trigger corresponding to one cache line, and is configured to store the write requests, the number of pending requests, and the number of processed requests for the corresponding cache line.

[0078] For example, 16 cache lines are installed in the cache 102, and the idx of the 16 cache lines is 0 to 15, respectively. 16 triggers are installed in the second buffer 206, and the 16 triggers are numbered L0 to L15, respectively. The idx of the cache line corresponding to trigger L0 is 0, and the idx of the cache line corresponding to trigger L1 is 1, and so on. Trigger L0 is configured to store a write request corresponding to cache line 0, the number of pending requests, and the number of processed requests. When it is confirmed that the number of pending requests and the number of processed requests for cache line 0 are the same, trigger L0 transmits the write request corresponding to cache line 0 to the transmit queue 207.

[0079] Additionally, in one alternative embodiment, cache 102 further includes a determination module 208. Determination module 208 is configured to determine which cache lines to process based on the state of each cache line and predetermined rules.

[0080] In the present application, the state of a cache line is the valid attribute of the cache line.

[0081] By setting up a first read request queue 201 and a second read request queue 202 in the cache 102, data is stored in the main memory control device 103 in advance, and when a cache line is free, the data is directly obtained from the main memory control device 103. After the cache line obtains the data from the main memory control device 103, the valid attribute of the cache line is valid, and the data of the cache line can be output by the cache 102, allowing the cache 102 to process a request corresponding to the cache line. Therefore, at the same time, there are multiple cache lines in the cache 102 with a valid attribute.

[0082] Furthermore, because the first buffer 205 is provided, if a read-after-write state occurs for one request, a first read request is not generated for that request, and the cache 102 processes the request that follows that request. After the read-after-write state is cleared, the request is released from the first buffer 205, a first read request is generated based on that request and sent to the first read request queue 201, and the first read request queue 201 requests the main memory 104 to obtain the data corresponding to that request. According to the above method, it often happens that multiple cache lines with valid attributes are present in the cache 102 at the same time.

[0083] The cache 102 has only one cache line that exchanges data at the same time, and in the embodiment of the present application, a determination module 208 is installed, and predetermined rules are set in the determination module 208, and the cache line to be processed is determined from multiple cache lines whose valid attribute is valid based on the predetermined rules.

[0084] In some embodiments, the predetermined rule may be as follows:

[0085] Priority 1: The valid attribute of the cache line is valid and the idx of the cache line is the same as the first idx to be output in the first read request queue 201.

[0086] Priority 2: The valid attribute of the cache line is valid and the idx of the cache line is the same as the second idx to be output in the first read request queue 201.

[0087] Priority 3: The valid attribute of the cache line is valid and a read-after-write situation exists in the cache line.

[0088] Priority 4: The valid attribute of the cache line is valid and there is a write request waiting to be sent in the cache line (that is, the cache line is allocated to a subsequent request).

[0089] Priority 5: The valid attribute of the cache line is valid.

[0090] If a cache line that satisfies priority 1 exists, the determination module 208 selects that cache line as the cache line to be processed. If a cache line that satisfies priority 1 does not exist but a cache line that satisfies priority 2 exists, the determination module 208 selects that cache line as the cache line to be processed. Processing continues in this manner thereafter.

[0091] According to the above-mentioned predetermined rule, because it takes a relatively long time for the cache 102 to request data from the main memory 104, the cache line that sends the first read request to the main memory 104 is processed preferentially. If the valid attribute of the cache lines corresponding to the first two first read requests output in the first read request queue 201 is invalid, the cache line that has a read-after-write status is processed preferentially, thereby clearing the read-after-write status as quickly as possible. If the valid attribute of a cache line that does not have a read-after-write status or a cache line that has a read-after-write status is invalid, the cache line corresponding to the write request waiting to be sent is processed preferentially. If there is no cache line corresponding to the write request waiting to be sent, the cache line with a valid valid attribute is processed.

[0092] In some other embodiments, the predetermined rule may be as follows:

[0093] Priority 1: The valid attribute of the cache line is valid and the idx of the cache line is the same as the first idx to be output in the first read request queue 201.

[0094] Priority 2: The valid attribute of the cache line is valid and the idx of the cache line is the same as the second idx to be output in the first read request queue 201.

[0095] Priority 3: The valid attribute of the cache line is valid and the idx of the cache line is the same as the third idx to be output in the first read request queue 201.

[0096] Priority 4: The valid attribute of the cache line is valid and a read-after-write situation exists in the cache line.

[0097] Priority 5: The valid attribute of the cache line is valid and there is a write request waiting to be sent in the cache line (that is, the cache line is allocated to a subsequent request).

[0098] Priority 6: The valid attribute of the cache line is valid.

[0099] In the embodiments of the present application, the predetermined rule is not specifically limited, and can be set according to the actual application scenario of the cache 102. For example, if a read-after-write situation occurs frequently in the actual application scenario of the cache 102, the priority of the condition "the valid attribute of the cache line is valid and a read-after-write situation exists in the cache line" is increased. Conversely, if a read-after-write situation rarely occurs in the actual application scenario of the cache 102, the priority of the condition "the valid attribute of the cache line is valid and a read-after-write situation exists in the cache line" is decreased.

[0100] Additionally, in one alternative embodiment, cache 102 further includes a multi-thread queue 209. Multi-thread queue 209 includes multiple threads, each corresponding to a cache line, and is configured to store pending requests for its corresponding cache line.

[0101] The multithread queue 209 further includes a multithread controller and a random access memory, and includes threads whose number is equal to the number of cache lines. After a request from the processor 101 reaches the cache 102, the multithread controller stores the request corresponding to the cache line whose idx is N in thread N, and all threads share the random access memory. Requests between different threads are unordered, but requests from the same thread (i.e., requests corresponding to the same cache line) are strictly ordered.

[0102] After the determination module 208 determines the cache line to be processed, the multi-thread queue 209 outputs a request corresponding to the cache line.

[0103] In one alternative embodiment, cache 102 further includes storage unit 210. Storage unit 210 is organized into multiple cache lines and is configured to store data retrieved from main memory 104.

[0104] Please refer to FIG. 4, which is a flowchart of the operation of a cache according to an embodiment of the present application.

[0105] The cache 102 receives one new request from the processor 101, generates a tag based on the address of the new request, and compares it with each tag of each cache line to determine whether the tag of the new request hits the cache line.

[0106] If a cache line is hit, the data of the cache line is returned to the processor 101. The processor 101 processes the data returned by the cache line and writes the processed data to the cache line. Then, it determines whether all requests for the cache line have been executed, and if not, it returns the data in the cache line to the processor 101 again, and repeats the above process until all requests for the cache line have been executed. If all requests for the cache line have been executed, the send queue 207 writes the data of the cache line back to the main memory 104.

[0107] If there is no cache line hit, a cache line is allocated to the new request, and it is determined whether a read-after-write state exists for the cache line. If a read-after-write state exists, the new request is stored in the first buffer 205 until the read-after-write state is cleared. After the read-after-write state is cleared, a first read request is generated based on the request. If a read-after-write state does not exist, a first read request is generated based on the request. Then, the determination module 208 determines the cache line to be processed. After the determination module 208 determines the cache line to be processed, it processes the cache line to be processed. The processing process is similar to the above processing process after the Tag of the new request hits a cache line, and for the sake of brevity, a description thereof will be omitted here.

[0108] Based on the same inventive idea, an embodiment of the present application further provides a cache management method. Refer to Fig. 5, which is a flowchart of the cache management method according to the embodiment of the present application. The cache management method is applied to the cache 102 according to the above embodiment. The cache management method includes the following contents:

[0109] S501: The first read request queue sends a first read request to the main memory control device.

[0110] S502: If the cache line corresponding to the first read request is empty, the second read request queue sends the second read request to the main memory control device.

[0111] In an embodiment of the present application, a first read request is configured to request data from a main memory and store the data in the main memory controller, and a second read request is configured to request data corresponding to the first read request from the main memory controller.

[0112] In an alternative embodiment, the cache further includes a third read request queue, and the method further includes the step of the third read request queue storing data corresponding to the first read request in a cache line corresponding to the first read request based on a cache line number of the first read request.

[0113] In an alternative embodiment, the cache further includes a cache controller and a first buffer. The method further includes the following steps: the cache controller allocates a cache line to a request sent by a processor, the request is a request that does not hit the cache, and the first buffer determines whether a read-after-write condition exists on the cache line corresponding to the request, generates a first read request if a read-after-write condition does not exist on the cache line corresponding to the request, stores the request in the first buffer if a read-after-write condition exists on the cache line corresponding to the request, and determines whether a read-after-write condition exists on the cache line corresponding to a request following the first request.

[0114] In an optional embodiment, the method further includes a step in which the first buffer generates a first read request corresponding to a request stored in the first buffer when a read-after-write condition corresponding to the request is cleared.

[0115] In an alternative embodiment, the first buffer includes trigger groups whose number is the same as the number of cache lines, each trigger corresponding to one cache line, the triggers configured to store requests for which a read-after-write condition exists, and the cache line corresponding to the request is the same as the cache line corresponding to the trigger that stores the request.

[0116] In an alternative embodiment, allocating a cache line to a request sent by a processor includes the cache control device selecting a cache line other than a cache line corresponding to a target request and allocating the cache line to the request sent by the processor, the target request being a request stored in the first buffer.

[0117] In an alternative embodiment, the cache further includes a second buffer and a transmit queue. The method further includes the steps of: storing a write request, a number of pending requests, and a number of processed requests for each cache line in the second buffer; when the number of pending requests corresponding to a cache line is the same as the number of processed requests corresponding to the cache line, transmitting the write request corresponding to the cache line to a transmit queue; and transmitting the write request to the main memory control device via the transmit queue.

[0118] In an alternative embodiment, the second buffer includes trigger groups whose number is equal to the number of cache lines, each trigger corresponding to one cache line, and configured to store write requests, the number of pending requests, and the number of processed requests for the corresponding cache line.

[0119] In an alternative embodiment, the cache further comprises a determination module. The method further comprises the steps of:

[0120] The determination module determines the cache line to be processed based on the state of each cache line and a predetermined rule; and / or The cache further includes a multi-thread queue, the multi-thread queue including multiple threads, each thread corresponding to one cache line, and the method further includes a step in which each thread stores pending requests for its corresponding cache line.

[0121] The cache management method according to the present application corresponds to the above cache 102 in terms of working principle, and for the sake of brevity, the same or similar parts can be referred to each other, so the description will be omitted here.

[0122] In the embodiments of the present application, the disclosed devices and methods may be realized in other ways. The device embodiments described above are merely illustrative. For example, the division of the above units is merely a logical functional division, and may be differently divided in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be omitted or not implemented. Furthermore, the shown or discussed mutual couplings or direct couplings or communication connections may be indirect couplings or communication connections via several interfaces, devices, or units, and may be electrical, mechanical, or other types of connections.

[0123] Furthermore, units described as separate components may or may not be physically separate. Elements shown as units may or may not be physical units, i.e., they may be located in the same location or distributed across multiple network units. Some or all of the units can be selected according to actual requirements to achieve the purpose of the proposed embodiment.

[0124] Furthermore, each functional module in each embodiment of the present application may be integrated to form a single independent part, each module may exist independently, or two or more modules may be integrated to form a single independent part.

[0125] The functions may be realized in the form of a software functional unit and stored in a computer-readable storage medium when sold or used as an independent product. From this understanding, the technical solution of the present application itself, or a portion of the technical solution that contributes to the prior art, may be realized in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for executing all or part of the steps of the above-described methods in each embodiment of the present application on a computer device (such as a personal computer, a server, or a network device). The storage medium includes various media capable of storing program code, such as a USB disk, a portable hard disk, a read-only memory (ROM), a random-access memory (RAM), a magnetic disk, or an optical disk.

[0126] As used herein, relational terms such as first and second are used solely to distinguish one entity or action from another entity or action and do not necessarily require or imply any actual relationship or order between such entities or actions.

[0127] The above is only an example of the present application and does not limit the scope of protection of the present application. Those skilled in the art may have various modifications and variations in the present application. As long as they do not deviate from the spirit and principle of the present application, any modifications, equivalent substitutions, improvements, etc., will fall within the scope of protection of the present application. [Explanation of symbols]

[0128] 100 Electronic equipment 101 processors 102 Cache 103 Main memory control device 104 main memory 201 First Read Request Queue 202 Second read request queue 203 Third Read Request Queue 204 Cache Control Device 205 First Buffer 206 Second Buffer 207 Send Queue 208 Judgment Module 209 Multi-Threaded Queue 210 Storage Unit

Claims

1. a plurality of cache lines, a first read request queue, and a second read request queue; the first read request queue is configured to store first read requests and send them to a main memory controller, the first read requests being configured to request data from a main memory and store the data in the main memory controller, the number of first read requests that can be stored in the first read request queue being greater than the number of the plurality of cache lines; The second read request queue is configured to store second read requests and send them to a main memory controller, the second read requests having a one-to-one correspondence with the first read requests, and the second read requests are configured to request data corresponding to the first read requests from the main memory controller if a cache line corresponding to the first read request is free. A cache characterized by:

2. the cache further includes a third read request queue; The third read request queue is configured to store a cache line number corresponding to the first read request, and to store data corresponding to the first read request in the cache line corresponding to the first read request based on the cache line number of the first read request. The cache of claim 1 .

3. the cache further includes a cache controller and a first buffer; the cache controller is configured to allocate a cache line to a request sent by a processor, the request being a request that does not hit the cache; The first buffer is configured to determine whether a read-after-write state exists in a cache line corresponding to a request, and if a read-after-write state does not exist in the cache line corresponding to the request, generate a first read request and send it to the first read request queue, and if a read-after-write state exists in the cache line corresponding to the request, store the request and determine whether a read-after-write state exists in a cache line corresponding to a request subsequent to the first request. The cache of claim 1 .

4. The first buffer is further configured to generate a first read request corresponding to a request stored in the first buffer when a read-after-write condition corresponding to the request is lifted.

4. The cache of claim 3.

5. The first buffer includes trigger groups, the number of which is the same as the number of cache lines, each trigger corresponding to one cache line, the triggers configured to store requests for which a read-after-write condition exists, and the cache line corresponding to the request is the same as the cache line corresponding to the trigger that stores the request.

4. The cache of claim 3.

6. The cache control device is specifically configured to select a cache line other than a cache line corresponding to a target request and allocate the cache line to the request sent by the processor, the target request being a request stored in the first buffer.

4. The cache of claim 3.

7. the cache further includes a second buffer and a transmission queue; The second buffer is configured to store a write request, a number of pending requests, and a number of processed requests for each cache line, and when the number of pending requests corresponding to a cache line is equal to the number of processed requests corresponding to the cache line, the second buffer transmits the write request corresponding to the cache line to the transmission queue. The cache of claim 1 .

8. The second buffer includes trigger groups, the number of which is equal to the number of cache lines, each trigger corresponding to one cache line, and is configured to store the write requests, the number of pending requests, and the number of processed requests for the corresponding cache line.

8. The cache of claim 7.

9. the cache further includes a determination module configured to determine which cache lines to process based on a state of each cache line and predetermined rules; and / or The cache further includes a multi-thread queue, the multi-thread queue including a plurality of threads, each thread corresponding to a cache line, and configured to store pending requests for the corresponding cache line. The cache of claim 1 .

10. A cache management method applied to the cache according to any one of claims 1 to 9, the cache includes a plurality of cache lines, a first read request queue, and a second read request queue; The cache management method includes: the first read request queue sending a first read request to a main memory controller; the second read request queue sending a second read request to the main memory control device if the cache line corresponding to the first read request is empty; the first read request is for requesting data from a main memory and storing the data in the main memory control device; The second read request is for requesting data corresponding to the first read request from the main memory control device. A cache management method comprising:

11. A processor and a cache according to any one of claims 1 to 9. An electronic device characterized by:

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